Page 1
INPUT FREQUENCY (MHZ)
0
SNR (dBFS)
200
2249 TAO1b
50
100
150
75
74
73
72
71
70
查询LTC2246供应商
FEATURES
■
Sample Rate: 65Msps/40Msps/25Msps
■
Single 3V Supply (2.7V to 3.4V)
■
Low Power: 205mW/120mW/75mW
■
74dB SNR up to 70MHz Input
■
80dB SFDR up to 140MHz Input
■
No Missing Codes
■
Flexible Input: 1V
■
575MHz Full Power Bandwidth S/H
■
Clock Duty Cycle Stabilizer
■
Shutdown and Nap Modes
■
Pin Compatible Family
P-P
to 2V
P-P
Range
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
■
32-Pin (5mm × 5mm) QFN Package
U
APPLICATIO S
LTC2248/LTC2247/LTC2246
14-Bit, 65/40/25Msps
Low Power 3V ADCs
U
DESCRIPTIO
The LTC®2248/LTC2247/LTC2246 are 14-bit 65Msps/
40Msps/25Msps, low power 3V A/D converters designed
for digitizing high frequency, wide dynamic range signals.
The LTC2248/LTC2247/LTC2246 are perfect for demanding imaging and communications applications with AC
performance that includes 74dB SNR and 80dB SFDR for
signals well beyond the Nyquist frequency.
DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and
no missing codes over temperature. The transition noise
is a low 1LSB
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.3V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
RMS
.
■
Wireless and Wired Broadband Communication
■
Imaging Systems
■
Ultrasound
■
Spectral Analysis
■
Portable Instrumentation
U
TYPICAL APPLICATIO
REFH
REFL
ANALOG
INPUT
FLEXIBLE
REFERENCE
+
INPUT
S/H
–
CLOCK/DUTY
CYCLE
CONTROL
CLK
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
2249 TA01a
OV
DD
D13
•
•
•
D0
OGND
LTC2248: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
224876f
1
Page 2
LTC2248/LTC2247/LTC2246
WW
W
U
ABSOLUTE AXI U RATI GS
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (V
Digital Input Voltage .................... –0.3V to (V
Digital Output Voltage ................– 0.3V to (OV
Power Dissipation............................................ 1500mW
Operating Temperature Range
LTC2248C, LTC2247C, LTC2246C........... 0°C to 70°C
LTC2248I, LTC2247I, LTC2246I .......... –40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
+ 0.3V)
DD
+ 0.3V)
DD
+ 0.3V)
DD
UUW
PACKAGE/ORDER I FOR ATIO
TOP VIEW
VDDVCMSENSE
MODEOFD13
D12
32 31 30 29 28 27 26 25
+
1AIN
–
AIN
2
REFH
3
REFH
4
REFL
5
REFL
6
V
7
DD
GND
8
9 10 11 12
32-LEAD (5mm × 5mm) PLASTIC QFN
T
JMAX
EXPOSED PAD IS GND (PIN 33)
MUST BE SOLDERED TO PCB
33
OED0D1D2D3
CLK
SHDN
UH PACKAGE
= 125°C, θJA = 34°C/W
13 14 15 16
D11
D4
D10
24
D9
23
D8
22
OV
21
DD
OGND
20
D7
19
D6
18
D5
17
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
ORDER PART
NUMBER
LTC2248CUH
LTC2248IUH
LTC2247CUH
LTC2247IUH
LTC2246CUH
LTC2246IUH
QFN PART*
MARKING
2248
2247
2246
U
CO VERTER CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Resolution ● 14 14 14 Bits
(No Missing Codes)
Integral Differential Analog Input ● –4 ±14–4±14–4±1 4 LSB
Linearity Error (Note 5)
Differential Differential Analog Input ● –1 ±0.5 1 –1 ±0.5 1 –1 ±0.5 1 LSB
Linearity Error
Offset Error (Note 6) ● –12 ±212–12±212–12±212 mV
Gain Error External Reference ● –2.5 ±0.5 2.5 – 2.5 ±0.5 2.5 – 2.5 ±0.5 2.5 %FS
Offset Drift ±10 ±10 ±10 µV/°C
Full-Scale Drift Internal Reference ±30 ±30 ±30 ppm/°C
External Reference ±15 ±15 ±15 ppm/°C
Transition Noise SENSE = 1V 1 1 1 LSB
The ● denotes the specifications which apply over the full operating
LTC2248 LTC2247 LTC2246
RMS
2
224876f
Page 3
LTC2248/LTC2247/LTC2246
UU
A ALOG I PUT
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
V
IN,CM
I
IN
I
SENSE
I
MODE
t
AP
t
JITTER
CMRR Analog Input Common Mode Rejection Ratio 80 dB
U
Analog Input Range (A
Analog Input Common Mode Differential Input (Note 7) ● 1 1.5 1.9 V
Analog Input Leakage Current 0V < A
SENSE Input Leakage 0V < SENSE < 1V ● –3 3 µA
MODE Pin Leakage ● –3 3 µA
Sample-and-Hold Acquisition Delay Time 0 ns
Sample-and-Hold Acquisition Delay Time Jitter 0.2 ps
Full Power Bandwidth Figure 8 Test Circuit 575 MHz
W
DY A IC ACCURACY
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input 74.3 74.4 74.5 dB
SFDR 5MHz Input 90 90 90 dB
SFDR 5MHz Input 95 95 95 dB
S/(N+D) 5MHz Input 74.3 74.4 74.5 dB
I
MD
Spurious Free
Dynamic Range
2nd or 3rd
Harmonic
Spurious Free
Dynamic Range
4th Harmonic
or Higher
Signal-to-Noise
Plus Distortion
Ratio
Intermodulation f
Distortion f
The ● denotes the specifications which apply over the full operating temperature range, otherwise
+
–
–A
IN
) 2.7V < V
IN
< 3.4V (Note 7) ● 1V to 2V V
DD
+
–
, A
< V
IN
IN
DD
● –1 1 µA
RMS
The ● denotes the specifications which apply over the full operating temperature range,
LTC2248 LTC2247 LTC2246
12.5MHz Input ● 72.9 74.2 dB
20MHz Input ● 72.9 74.4 dB
30MHz Input ● 72.5 74.3 dB
70MHz Input 74.3 73.9 73.4 dB
140MHz Input 73.9 73.3 73 dB
12.5MHz Input ● 76 90 dB
20MHz Input ● 76 90 dB
30MHz Input ● 76 90 dB
70MHz Input 85 85 85 dB
140MHz Input 80 80 80 dB
12.5MHz Input ● 84 95 dB
20MHz Input ● 84 95 dB
30MHz Input ● 84 95 dB
70MHz Input 95 95 95 dB
140MHz Input 90 90 90 dB
12.5MHz Input ● 72.2 74.2 dB
20MHz Input ● 72.2 74.3 dB
30MHz Input ● 72 74.2 dB
70MHz Input 74.1 73.6 73.4 dB
140MHz Input 71.9 71.9 71.8 dB
= 28.2MHz 90 90 90 dB
IN1
= 26.8MHz
IN2
224876f
3
Page 4
LTC2248/LTC2247/LTC2246
UU U
I TER AL REFERE CE CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage I
VCM Output Tempco ±30 ppm/C
VCM Line Regulation 2.7V < VDD < 3.4V 3 mV/V
VCM Output Resistance –1mA < I
= 0 1.475 1.500 1.525 V
OUT
(Note 4)
< 1mA 4 Ω
OUT
UU
DIGITAL I PUTS A D DIGITAL OUTPUTS
full operating temperature range, otherwise specifications are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LOGIC INPUTS (CLK, OE, SHDN)
V
IH
V
IL
I
IN
C
IN
LOGIC OUTPUTS
OVDD = 3V
C
OZ
I
SOURCE
I
SINK
V
OH
V
OL
OV
= 2.5V
DD
V
OH
V
OL
OVDD = 1.8V
V
OH
V
OL
High Level Input Voltage VDD = 3V ● 2V
Low Level Input Voltage VDD = 3V ● 0.8 V
Input Current VIN = 0V to V
Input Capacitance (Note 7) 3 pF
Hi-Z Output Capacitance OE = High (Note 7) 3 pF
Output Source Current V
Output Sink Current V
High Level Output Voltage IO = –10µA 2.995 V
Low Level Output Voltage IO = 10µA 0.005 V
High Level Output Voltage IO = –200µA 2.49 V
Low Level Output Voltage IO = 1.6mA 0.09 V
High Level Output Voltage IO = –200µA 1.79 V
Low Level Output Voltage IO = 1.6mA 0.09 V
= 25°C. (Note 4)
A
= 0V 50 mA
OUT
= 3V 50 mA
OUT
I
= –200µA ● 2.7 2.99 V
O
I
= 1.6mA ● 0.09 0.4 V
O
The ● denotes the specifications which apply over the
DD
● –10 10 µA
WU
POWER REQUIRE E TS
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
V
DD
OV
IV
P
DISS
P
SHDN
P
NAP
DD
DD
Analog Supply (Note 9) ● 2.7 3 3.4 2.7 3 3.4 2.7 3 3.4 V
Voltage
Output Supply (Note 9) ● 0.5 3 3.6 0.5 3 3.6 0.5 3 3.6 V
Voltage
Supply Current ● 68.3 80 40 48 25 30 mA
Power Dissipation ● 205 240 120 144 75 90 mW
Shutdown Power SHDN = H, 2 2 2 mW
OE = H, No CLK
Nap Mode Power SHDN = H, 15 15 15 mW
OE = L, No CLK
The ● denotes the specifications which apply over the full operating temperature
LTC2248 LTC2247 LTC2246
4
224876f
Page 5
LTC2248/LTC2247/LTC2246
UW
TI I G CHARACTERISTICS
range, otherwise specifications are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
f
s
t
L
t
H
t
AP
t
D
Pipeline 6 6 6 Cycles
Latency
Sampling Frequency (Note 9) ● 165140125MHz
CLK Low Time Duty Cycle Stabilizer Off ● 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns
Duty Cycle Stabilizer On
(Note 7)
CLK High Time Duty Cycle Stabilizer Off ● 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns
Duty Cycle Stabilizer On
(Note 7)
Sample-and-Hold 0 0 0 ns
Aperture Delay
CLK to DATA delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns
Data Access Time CL = 5pF (Note 7) ● 4.3 10 4.3 10 4.3 10 ns
After OE↓
BUS Relinquish Time (Note 7) ● 3.3 8.5 3.3 8.5 3.3 8.5 ns
= 25°C. (Note 4)
A
The ● denotes the specifications which apply over the full operating temperature
LTC2248 LTC2247 LTC2246
● 5 7.7 500 5 12.5 500 5 20 500 ns
● 5 7.7 500 5 12.5 500 5 20 500 ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, f
25MHz (LTC2246), input range = 2V
= 65MHz (LTC2248), 40MHz (LTC2247), or
SAMPLE
with differential drive, unless
P-P
otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: V
= 3V, f
DD
25MHz (LTC2246), input range = 1V
Note 9: Recommended operating conditions.
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2248: Typical INL,
2V Range, 65Msps
2.0
1.5
1.0
0.5
0
–0.5
INL ERROR (LSB)
–1.0
–1.5
–2.0
0
4096 8192 16384
CODE
12288
2248 G01
1.00
0.75
0.50
0.25
0
–0.25
DNL ERROR (LSB)
–0.50
–0.75
–1.00
= 65MHz (LTC2248), 40MHz (LTC2247), or
SAMPLE
P-P
LTC2248: Typical DNL,
2V Range, 65Msps
4096 8192 16384
0
CODE
with differential drive.
12288
2248 G02
224876f
5
Page 6
LTC2248/LTC2247/LTC2246
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2248: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
LTC2248: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
510152025
FREQUENCY (MHz)
510152025
FREQUENCY (MHz)
LTC2248: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
30
2248 G05
–120
0
30
2248 G03
510152025
FREQUENCY (MHz)
LTC2248: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
510152025
FREQUENCY (MHz)
LTC2248: 8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz,
–1dB, 2V Range, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
30
2248 G06
–120
0
30
2248 G04
510152025
FREQUENCY (MHz)
30
2248 G06a
LTC2248: Grounded Input
Histogram, 65Msps
25000
21824
20000
15000
COUNT
10000
5000
2116
172
0
8196 8197 8198 8199 8200 8201 8202 8203
20412
10224
CODE
6
9042
1596
121
2248 G08
LTC2248: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
75
74
73
72
SNR (dBFS)
71
70
0
50
INPUT FREQUENCY (MHz)
100
150
2248 G09
200
LTC2248: SFDR vs Input Frequency,
–1dB, 2V Range, 65Msps
100
95
90
85
80
SFDR (dBFS)
75
70
65
0
50 100 200
INPUT FREQUENCY (MHz)
150
2248 G10
224876f
Page 7
LTC2248/LTC2247/LTC2246
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2248: SNR and SFDR vs
Sample Rate, 2V Range,
f
= 5MHz, –1dB
IN
110
100
90
80
SNR AND SFDR (dBFS)
70
60
40
20 30
SAMPLE RATE (Msps)
50
SFDR
SNR
60
70 80
90010
100
110
2248 G11
LTC2248: SNR and SFDR vs
Clock Duty Cycle, 65Msps
100
SFDR: DCS ON
95
90
85
80
SNR AND SFDR (dBFS)
75
70
SFDR: DCS OFF
SNR: DCS ON
SNR: DCS OFF
30
35 45
40
CLOCK DUTY CYCLE (%)
50
60
55
65
2247 G12
LTC2248: SNR vs Input Level,
fIN = 30MHz, 2V Range, 65Msps
80
70
60
50
40
30
SNR (dBc AND dBFS)
20
10
70
0
–60 –50
dBFS
dBc
–40 –20–30
INPUT LEVEL (dBFS)
–10
0
2248 G13
LTC2248: SFDR vs Input Level,
fIN = 30MHz, 2V Range, 65Msps
120
110
100
90
80
70
60
50
SFDR (dBc AND dBFS)
40
30
20
dBFS
dBc
90dBc SFDR
REFERENCE LINE
–60 – 50 –40 –20–30
INPUT LEVEL (dBFS)
LTC2247: Typical INL,
2V Range, 40Msps
2.0
1.5
1.0
0.5
0
–0.5
INL ERROR (LSB)
–1.0
–1.5
–2.0
4096 8192 16384
0
CODE
12288
–10
2248 G14
2247 G01
0
LTC2248: I
vs Sample Rate,
VDD
5MHz Sine Wave Input, –1dB
80
75
70
(mA)
65
2V RANGE
VDD
I
60
55
50
0
10 30
20
40
SAMPLE RATE (Msps)
LTC2247: Typical DNL,
2V Range, 40Msps
1.00
0.75
0.50
0.25
0
–0.25
DNL ERROR (LSB)
–0.50
–0.75
–1.00
4096 8192 16384
0
CODE
1V RANGE
50
60
12288
70
2248 G15
2247 G02
LTC2248: I
vs Sample Rate,
OVDD
5MHz Sine Wave Input, –1dB,
O
= 1.8V
VDD
6
5
4
(mA)
3
OVDD
I
2
1
80
0
0
10 30
20
SAMPLE RATE (Msps)
70
40
60
50
80
2248 G16
LTC2247: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
40Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
5101520
FREQUENCY (MHz)
2247 G03
224876f
7
Page 8
LTC2248/LTC2247/LTC2246
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2247: 8192 Point FFT,
= 30MHz, –1dB, 2V Range,
f
IN
40Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
5101520
FREQUENCY (MHz)
LTC2247: 8192 Point 2-Tone FFT,
f
= 21.6MHz and 23.6MHz,
IN
–1dB, 2V Range, 40Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
5 101520
FREQUENCY (MHz)
2247 G04
2247 G07
LTC2247: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
40Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
5101520
FREQUENCY (MHz)
LTC2247: Grounded Input
Histogram, 40Msps
30000
4641
14833
24558
15714
CODE
25000
20000
15000
COUNT
10000
5000
640
30
0
8184 81858186 818781888189 8190 81918192
4520
546
2247 G05
36
2247 G08
LTC2247: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
40Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
5101520
FREQUENCY (MHz)
LTC2247: SNR vs Input Frequency,
–1dB, 2V Range, 40Msps
75
74
73
72
SNR (dBFS)
71
70
0
50
INPUT FREQUENCY (MHz)
100
150
2247 G06
200
2247 G09
LTC2247: SFDR vs Input Frequency,
–1dB, 2V Range, 40Msps
100
95
90
85
80
SFDR (dBFS)
75
70
65
0
50 100 200
INPUT FREQUENCY (MHz)
8
150
2247 G10
LTC2247: SNR and SFDR vs
Sample Rate, 2V Range,
fIN = 5MHz, –1dB
110
100
90
80
SNR AND SFDR (dBFS)
70
60
0
SFDR
SNR
20 60
40
SAMPLE RATE (Msps)
2247 G11
LTC2247: SNR vs Input Level,
fIN = 5MHz, 2V Range, 40Msps
80
70
60
50
40
30
SNR (dBc AND dBFS)
20
10
0
80
–60 –50
dBFS
dBc
–40 –20–30
INPUT LEVEL (dBFS)
–10
0
2247 G12
224876f
Page 9
LTC2248/LTC2247/LTC2246
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2247: SFDR vs Input Level,
f
= 5MHz, 2V Range, 40Msps
IN
120
110
100
90
80
70
60
50
SNR (dBc AND dBFS)
40
30
20
dBFS
dBc
–60 – 50 –40 –20–30
INPUT LEVEL (dBFS)
LTC2246: Typical INL,
2V Range, 25Msps
2.0
1.5
1.0
0.5
0
–0.5
INL ERROR (LSB)
–1.0
–1.5
–2.0
0
4096 8192 16384
CODE
LTC2246: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
25Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
246810
FREQUENCY (MHz)
90dBc SFDR
REFERENCE LINE
–10
2247 G13
12288
2246 G01
12
2246 G04
0
LTC2247: I
vs Sample Rate,
VDD
5MHz Sine Wave Input, –1dB
50
45
(mA)
40
VDD
I
35
30
0
2V RANGE
10
20
SAMPLE RATE (Msps)
LTC2246: Typical DNL,
2V Range, 25Msps
1.00
0.75
0.50
0.25
0
–0.25
DNL ERROR (LSB)
–0.50
–0.75
–1.00
4096 8192 16384
0
CODE
LTC2246: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
25Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
246810
FREQUENCY (MHz)
1V RANGE
30
12288
LTC2247: I
vs Sample Rate,
OVDD
5MHz Sine Wave Input, –1dB,
O
= 1.8V
VDD
4
3
(mA)
2
OVDD
I
1
0
40
50
2247 G14
10
0
SAMPLE RATE (Msps)
30
40
20
50
2247 G15
LTC2246: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
25Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
2246 G02
–120
0
246810
FREQUENCY (MHz)
12
2246 G03
LTC2246: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
25Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
12
2246 G05
–120
0
246810
FREQUENCY (MHz)
12
2246 G06
224876f
9
Page 10
LTC2248/LTC2247/LTC2246
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2246: 8192 Point 2-Tone FFT,
fIN = 10.9MHz and 13.8MHz,
–1dB, 2V Range, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
246810
FREQUENCY (MHz)
12
2246 G07
LTC2246: Grounded Input
Histogram, 25Msps
25000
22016
20000
15000
COUNT
10000
5000
43
0
8179 8180 8181 8182 8183 8184 8185 8186
18803
6919
853
CODE
13373
3227
278
2246 G08
LTC2246: SNR vs Input Frequency,
–1dB, 2V Range, 25Msps
75
74
73
72
SNR (dBFS)
71
70
0
50
INPUT FREQUENCY (MHz)
100
150
200
2246 G09
LTC2246: SFDR vs Input
Frequency, –1dB, 2V Range,
25Msps
100
95
90
85
80
SFDR (dBFS)
75
70
65
0
50 100 200
INPUT FREQUENCY (MHz)
LTC2246: SFDR vs Input Level,
fIN = 5MHz, 2V Range, 25Msps
120
110
100
90
80
70
60
50
SFDR (dBc AND dBFS)
40
30
20
–60 – 50 –40 –20–30
dBFS
dBc
INPUT LEVEL (dBFS)
150
2246 G10
90dBc SFDR
REFERENCE LINE
–10
2246 G13
0
LTC2246: SNR and SFDR vs
Sample Rate, 2V Range,
fIN = 5MHz, –1dB
110
100
SFDR
90
80
SNR AND SFDR (dBFS)
70
60
10
0
LTC2246: I
SNR
20 30 40
SAMPLE RATE (Msps)
vs Sample Rate,
VDD
5MHz Sine Wave Input, –1dB
35
30
2V RANGE
(mA)
25
VDD
I
20
15
0
515
1V RANGE
10
SAMPLE RATE (Msps)
LTC2246: SNR vs Input Level,
fIN = 5MHz, 2V Range, 25Msps
80
dBFS
dBc
–30
–40
INPUT LEVEL (dBFS)
OVDD
–20
vs Sample Rate,
–10
0
2246 G12
2246 G11
70
60
50
40
30
SNR (dBc AND dBFS)
20
10
0
–60
50
–50
LTC2246: I
5MHz Sine Wave Input, –1dB,
O
= 1.8V
VDD
3
2
(mA)
OVDD
I
1
0
0
515
20
35
2246 G14
30
25
10
SAMPLE RATE (Msps)
20
30
25
35
2246 G15
10
224876f
Page 11
LTC2248/LTC2247/LTC2246
U
UU
PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input.
AIN- (Pin 2): Negative Differential Analog Input.
REFH (Pins 3, 4): ADC High Reference. Short together and
bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 5, 6 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 3, 4 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF
ceramic chip capacitors.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to V
results in sleep mode with the outputs at high impedance.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
DD
D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24,
25, 26, 27): Digital Outputs. D13 is the MSB.
OGND (Pin 20): Output Driver Ground.
OVDD (Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1µF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
straight binary output format and turns the clock duty
cycle stabilizer off. 1/3 VDD selects straight binary output
format and turns the clock duty cycle stabilizer on. 2/3 V
selects 2’s complement output format and turns the clock
duty cycle stabilizer on. VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
SENSE (Pin 30): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±V
VCM (Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 33): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
. ±1V is the largest valid input range.
SENSE
DD
224876f
11
Page 12
LTC2248/LTC2247/LTC2246
UU
W
FUNCTIONAL BLOCK DIAGRA
+
A
A
V
2.2µF
SENSE
IN
INPUT
S/H
–
IN
CM
1.5V
REFERENCE
RANGE
SELECT
FIRST PIPELINED
ADC STAGE
(4 BITS)
REF
BUF
SECOND PIPELINED
ADC STAGE
(3 BITS)
DIFF
REF
AMP
REFH
0.1µF
2.2µF
THIRD PIPELINED
ADC STAGE
(3 BITS)
INTERNAL CLOCK SIGNALSREFH REFL
REFL
FOURTH PIPELINED
CLOCK/DUTY
CYCLE
CONTROL
CLK
ADC STAGE
(3 BITS)
M0DE
CONTROL
LOGIC
SHDN
FIFTH PIPELINED
ADC STAGE
(3 BITS)
OE
SIXTH PIPELINED
ADC STAGE
(3 BITS)
SHIFT REGISTER
AND CORRECTION
OUTPUT
DRIVERS
OGND
224876 F01
OV
DD
OF
D13
•
•
•
D0
UWW
TI I G DIAGRA
ANALOG
INPUT
CLK
D0-D13, OF
1µF1µF
Figure 1. Functional Block Diagram
Timing Diagram
t
AP
N
t
H
t
D
N – 6
N + 1
t
L
N + 2
N + 3
N – 5 N – 4 N – 3 N – 2
N + 4
N + 5
N – 1
224876 TD01
12
224876f
Page 13
WUUU
APPLICATIO S I FOR ATIO
LTC2248/LTC2247/LTC2246
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log √(V22 + V32 + V42 + . . . Vn2)/V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when CLK reaches mid-supply to the instant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNR
CONVERTER OPERATION
= –20log (2π) • fIN • t
JITTER
JITTER
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
As shown in Figure 1, the LTC2248/LTC2247/LTC2246 is
a CMOS pipelined multistep converter. The converter has
six pipelined ADC stages; a sampled analog input will
result in a digitized value six cycles later (see the Timing
Diagram section). For optimal AC performance the analog
inputs should be driven differentially. For cost sensitive
applications, the analog inputs can be driven single-ended
with slightly worse harmonic distortion. The CLK input is
single-ended. The LTC2248/LTC2247/LTC2246 has two
phases of operation, determined by the state of the CLK
input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
224876f
13
Page 14
LTC2248/LTC2247/LTC2246
V
DD
V
DD
V
DD
15Ω
15Ω
C
PARASITIC
1pF
C
PARASITIC
1pF
C
SAMPLE
4pF
C
SAMPLE
4pF
LTC2248/47/46
A
IN
+
A
IN
–
CLK
224876 F02
U
WUU
APPLICATIO S I FOR ATIO
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
disconnected from the input and the held voltage is passed
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2248/
LTC2247/LTC2246 CMOS differential sample-and-hold.
The analog inputs are connected to the sampling capacitors (C
SAMPLE
shown attached to each input (C
tion of all other capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when CLK is high, the sampling capacitors are
) through NMOS transistors. The capacitors
PARASITIC
) are the summa-
Figure 2. Equivalent Input Circuit
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
should be driven with the input signal and A
–
should be
IN
IN
+
connected to 1.5V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin (Pin
31) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
224876f
14
Page 15
WUUU
APPLICATIO S I FOR ATIO
LTC2248/LTC2247/LTC2246
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2248/LTC2247/LTC2246
can be influenced by the input drive circuitry, particularly
the second and third harmonics. Source impedance and
reactance can influence SFDR. At the falling edge of CLK,
the sample-and-hold circuit will connect the 4pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when CLK rises, holding the
sampled input on the sampling capacitor. Ideally the input
circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F
ENCODE
); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2248/LTC2247/LTC2246 being
driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM,
setting the ADC input signal at its optimum DC level.
Terminating on the transformer secondary is desirable, as
this provides a common mode path for charging glitches
caused by the sample and hold. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedance seen by the ADC does not exceed 100Ω
for each ADC input. A disadvantage of using a transformer
is the loss of low frequency response. Most small RF
transformers have poor performance at frequencies below 1MHz.
Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
V
CM
2.2µF
ANALOG
INPUT
0.1µFT1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
25Ω
25Ω
25Ω
0.1µF
25Ω
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
HIGH SPEED
ANALOG
INPUT
DIFFERENTIAL
AMPLIFIER
+
CM
–
25Ω
+
–
25Ω
Figure 4. Differential Drive with an Amplifier
2.2µF
12pF
ANALOG
INPUT
0.1µF
10k
10k
25Ω
25Ω
0.1µF
V
2.2µF
A
12pF
A
V
A
A
12pF
CM
IN
IN
CM
IN
IN
+
A
IN
LTC2248/47/46
–
A
IN
+
LTC2248/47/46
–
+
LTC2248/47/46
–
224876 F03
224876 F04
224876 F05
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input
frequencies.
Figure 5. Single-Ended Drive
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
224876f
15
Page 16
LTC2248/LTC2247/LTC2246
WUUU
APPLICATIO S I FOR ATIO
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux
coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In
Figure 8, the series inductors are impedance matching
elements that maximize the ADC bandwidth.
V
CM
2.2µF
ANALOG
INPUT
0.1µF
T1
0.1µF
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
25Ω
25Ω
12Ω
0.1µF
12Ω
8pF
A
IN
A
IN
+
LTC2248/47/46
–
224876 F06
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 70MHz and 170MHz
V
CM
2.2µF
ANALOG
INPUT
0.1µF
T1
0.1µF
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
25Ω
25Ω
0.1µF
+
A
IN
LTC2248/47/46
–
A
IN
224876 F07
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 170MHz and 300MHz
V
CM
2.2µF
ANALOG
INPUT
0.1µF
T1
0.1µF
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
25Ω
25Ω
6.8nH
0.1µF
6.8nH
+
A
IN
LTC2248/47/46
–
A
IN
224876 F08
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 300MHz
Reference Operation
Figure 9 shows the LTC2248/LTC2247/LTC2246 reference circuitry consisting of a 1.5V bandgap reference, a
difference amplifier and switching and control circuit. The
internal voltage reference can be configured for two pin
selectable input ranges of 2V (±1V differential) or 1V
(±0.5V differential). Tying the SENSE pin to VDD selects
the 2V range; tying the SENSE pin to V
selects the 1V
CM
range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, V
. This provides a high
CM
frequency low impedance path to ground for internal and
external circuitry.
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9.
LTC2248/47/46
4Ω
V
TIE TO V
TIE TO V
RANGE = 2 • V
1.5V
FOR 2V RANGE;
DD
FOR 1V RANGE;
CM
SENSE
0.5V < V
SENSE
1µF
2.2µF
1µF
FOR
< 1V
CM
2.2µF
SENSE
REFH
0.1µF
REFL
Figure 9. Equivalent Reference Circuit
RANGE
DETECT
AND
CONTROL
1.5V BANDGAP
REFERENCE
1V
INTERNAL ADC
HIGH REFERENCE
DIFF AMP
INTERNAL ADC
LOW REFERENCE
0.5V
BUFFER
224876 F09
224876f
16
Page 17
WUUU
APPLICATIO S I FOR ATIO
LTC2248/LTC2247/LTC2246
Other voltage ranges in-between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
1.5V
12k
0.75V
12k
Figure 10. 1.5V Range ADC
V
CM
2.2µF
SENSE
1µF
LTC2248/47/46
224876 F10
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 5.8dB. See the Typical Performance Characteristics section.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with
a low-jitter squaring circuit before the CLK pin (see
Figure 11).
The noise performance of the LTC2248/LTC2247/LTC2246
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
CLEAN
FERRITE
BEAD
0.1µF
CLK
SUPPLY
LTC2248/47/46
224876 F11
4.7µF
1k
1k
NC7SVU04
SINUSOIDAL
CLOCK
INPUT
Figure 11. Sinusoidal Single-Ended CLK Drive
0.1µF
50Ω
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2248/LTC2247/
LTC2246 is 65Msps (LTC2248), 40Msps (LTC2247), and
25Msps (LTC2246). For the ADC to operate properly, the
CLK signal should have a 50% (±5%) duty cycle. Each half
cycle must have at least 7.3ns (LTC2248), 11.8ns
(LTC2247), and 18.9ns (LTC2246) for the ADC internal
circuitry to have enough settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To use
the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2248/LTC2247/LTC2246 sample
rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on
storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified
minimum operating frequency for the LTC2248/LTC2247/
LTC2246 is 1Msps.
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17
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LTC2248/LTC2247/LTC2246
WUUU
APPLICATIO S I FOR ATIO
DIGITAL OUTPUTS
Digital Output Buffers
Figure 12 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2248/LTC2247/LTC2246 should
drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as
an ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
DATA
FROM
LATCH
OE
V
DD
PREDRIVER
LOGIC
LTC2248/47/46
V
DD
OV
DD
43Ω
OV
DD
OGND
0.5V
TO V
0.1µF
TYPICAL
DATA
OUTPUT
DD
Table 1. MODE Pin Function
Clock Duty
MODE Pin Output Format Cycle Stablizer
0 Straight Binary Off
1/3V
2/3V
V
DD
DD
DD
Straight Binary On
2’s Complement On
2’s Complement Off
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply, then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage from 500mV up to
the VDD of the part. OGND can be powered with any voltage
from GND up to 1V and must be less than OVDD. The logic
outputs will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data access and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long
periods of inactivity.
224876 F12
Figure 12. Digital Output Buffer
Data Format
Using the MODE pin, the LTC2248/LTC2247/LTC2246
parallel digital output can be selected for offset binary or
2’s complement format. Connecting MODE to GND or
1/3VDD selects straight binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 1 shows the logic
states for the MODE pin.
18
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to V
DD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
15mW. In nap mode, the on-chip reference circuit is kept
224876f
Page 19
LTC2248/LTC2247/LTC2246
U
WUU
APPLICATIO S I FOR ATIO
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Grounding and Bypassing
The LTC2248/LTC2247/LTC2246 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of
particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be placed as close
to the device as possible (1.5mm or less). A size 0402
ceramic capacitor is recommended. The large 2.2µF ca-
pacitor between REFH and REFL can be somewhat further
away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as
possible.
The LTC2248/LTC2247/LTC2246 differential inputs should
run parallel and close to each other. The input traces
should be as short as possible to minimize capacitance
and to minimize noise pickup.
Heat Transfer
Most of the heat generated by the LTC2248/LTC2247/
LTC2246 is transferred from the die through the bottomside exposed pad and package leads onto the printed
circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large
grounded pad on the PC board. It is critical that all ground
pins are connected to a ground plane of sufficient area.
PACKAGE DESCRIPTIO
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ±0.05
(4 SIDES)
PACKAGE OUTLINE
RECOMMENDED SOLDER PAD LAYOUT
0.50 BSC
0.25 ± 0.05
U
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
5.00 ± 0.10
(4 SIDES)
PIN 1
TOP MARK
(NOTE 6)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE
DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT,
SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.75 ± 0.05
0.200 REF
0.00 – 0.05
3.45 ± 0.10
(4-SIDES)
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
31
0.25 ± 0.05
0.50 BSC
32
0.23 TYP
(4 SIDES)
(UH) QFN 0603
1
2
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
224876f
19
Page 20
LTC2248/LTC2247/LTC2246
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20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
224876f
LT/TP 0904 1K • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2004
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