Page 1
FEATURES
■
Sample Rate: 105Msps/80Msps
■
68dB SNR up to 140MHz Input
■
80dB SFDR up to 170MHz Input
■
775MHz Full Power Bandwidth S/H
■
Single 3.3V Supply
■
Low Power Dissipation: 475mW/366mW
■
Selectable Input Ranges: ±0.5V or ±1V
■
No Missing Codes
■
Optional Clock Duty Cycle Stabilizer
■
Shutdown and Nap Modes
■
Data Ready Output Clock
■
Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
■
48-Pin QFN Package
U
APPLICATIO S
■
Wireless and Wired Broadband Communication
■
Cable Head-End Systems
■
Power Amplifier Linearization
■
Communications Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTC2222/LTC2223
12-Bit,105Msps/
80Msps ADCs
U
DESCRIPTIO
The LTC®2222 and LTC2223 are 105Msps/80Msps, sampling 12-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2222/
LTC2223 are perfect for demanding communications
applications with AC performance that includes 68dB SNR
and 80dB spurious free dynamic range for signals
up to 170MHz. Ultralow jitter of 0.15ps
undersampling of IF frequencies with excellent noise
performance.
DC specs include ±0.3LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSB
RMS
.
A separate output power supply allows the outputs to drive
0.5V to 3.3V logic.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
RMS
allows
TYPICAL APPLICATIO
REFH
REFL
ANALOG
INPUT
FLEXIBLE
REFERENCE
+
INPUT
S/H
–
CLOCK/DUTY
CYCLE
CONTROL
ENCODE
INPUT
12-BIT
PIPELINED
ADC CORE
U
V
3.3V
DD
CORRECTION
LOGIC
OUTPUT
DRIVERS
22201 TA01
0V
DD
0.5V TO 3.3V
D11
•
•
•
D0
0GND
100
95
90
85
80
SFDR (dBFS)
75
70
65
60
0
SFDR vs Input Frequency
4th OR HIGHER
2nd or 3rd
200 300 400 500 600
100
INPUT FREQUENCY (MHz)
22223 TA01b
22223f
1
Page 2
LTC2222/LTC2223
WW
W
U
ABSOLUTE AXI U RATI GS
OV
= VDD (Notes 1, 2)
DD
Supply Voltage (VDD) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (V
Digital Input Voltage .................... –0.3V to (V
Digital Output Voltage ............... –0.3V to (OV
Power Dissipation............................................ 1500mW
Operating Temperature Range
LTC2222C, LTC2223C ............................. 0°C to 70°C
LTC2222I, LTC2223I ...........................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
+ 0.3V)
DD
+ 0.3V)
DD
+ 0.3V)
DD
UUW
PACKAGE/ORDER I FOR ATIO
TOP VIEW
DD
48 GND
47 VDD46 VDD45 GND
44 VCM43 SENSE
42 MODE
41 OF
40 D11
39 D10
38 OGND
37 OV
23
OV
DD
D1 24
36 D9
35 D8
34 D7
33 OV
DD
32 OGND
31 D6
30 D5
29 D4
28 OV
DD
27 OGND
26 D3
25 D2
A
IN+
–
A
IN
REFHA 3
REFHA 4
REFLB
REFLB
REFHB 7
REFHB 8
REFLA 9
REFLA 10
V
11
DD
V
12
DD
1
2
5
6
14
DD
V
GND 13
48-LEAD (7mm × 7mm) PLASTIC QFN
EXPOSED PAD IS GND (PIN 49),
MUST BE SOLDERED TO PCB
T
JMAX
49
18
16
19
17
+
–
GND 15
OE
ENC
ENC
SHDN
UK PACKAGE
= 125°C, θJA = 29°C/W
20
CLOCKOUT
DO 21
OGND 22
ORDER PART
NUMBER
LTC2222CUK
LTC2223CUK
LTC2222IUK
LTC2223IUK
*The temperature grade is identified by a label on the shipping container. Consult LTC
Marketing for parts specified with wider operating temperature ranges.
UK PART
MARKING*
LTC2222UK
LTC2223UK
LTC2222UK
LTC2223UK
U
CO VERTER CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Resolution (No Missing Codes) ● 12 12 Bits
Integral Linearity Error (Note 5) Differential Analog Input ● –1.3 ±0.3 1.3 –1.1 ±0.3 1.1 LSB
Differential Linearity Error Differential Analog Input ● –1 ±0.2 1 –0.8 ±0.2 0.8 LSB
Integral Linearity Error (Note 5) Single-Ended Analog Input ±1 ±1 LSB
Differential Linearity Error Single-Ended Analog Input ±0.2 ±0.2 LSB
Offset Error (Note 6) ● –30 ±330–30±330 mV
Gain Error External Reference ● –2.5 ±0.5 2.5 –2.5 ±0.5 2.5 %FS
Offset Drift ±10 ±10 µV/C
Full-Scale Drift Internal Reference ±30 ±30 ppm/C
External Reference ±15 ±15 ppm/C
Transition Noise SENSE = 1V 0.5 0.5 LSB
The ● denotes the specifications which apply over the full operating
LTC2222 LTC2223
RMS
22223f
2
Page 3
LTC2222/LTC2223
UU
A ALOG I PUT
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
V
IN, CM
I
IN
I
SENSE
I
MODE
t
AP
t
JITTER
CMRR Analog Input Common Mode Rejection Ratio 80 dB
U
Analog Input Range (A
Analog Input Common Mode Differential Input ● 1 1.6 1.9 V
Analog Input Leakage Current 0 < A
SENSE Input Leakage 0V < SENSE < 1V ● –1 1 µA
MODE Pin Pull-Down Current to GND 10 µA
Full Power Bandwidth Figure 8 Test Circuit 775 MHz
Sample and Hold Acquisition Delay Time 0 ns
Sample and Hold Acquisition Delay Time Jitter 0.15 ps
W
DY A IC ACCURACY
otherwise specifications are at TA = 25°C. A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 30MHz Input (1V Range) 63.5 63.6 dB
SFDR Spurious Free Dynamic Range 30MHz Input (1V Range) 84 84 dB
SFDR Spurious Free Dynamic Range 30MHz Input (1V Range) 90 90 dB
4th Harmonic or Higher 30MHz Input (2V Range) 90 90 dB
S/(N+D) Signal-to-Noise 30MHz Input (1V Range) 63.5 63.6 dB
Plus Distortion Ratio 30MHz Input (2V Range)
IMD Intermodulation Distortion f
The ● denotes the specifications which apply over the full operating temperature range, otherwise
+
–
– A
IN
) 3.1V < VDD < 3.5V ● ±0.5 to ±1V
IN
+
–
, A
< V
IN
IN
DD
● –1 1 µA
RMS
The ● denotes the specifications which apply over the full operating temperature range,
= –1dBFS. (Note 4)
IN
LTC2222 LTC2223
30MHz Input (2V Range)
70MHz Input (1V Range) 63.4 63.5 dB
70MHz Input (2V Range) 68.3 68.4 dB
140MHz Input (1V Range) 63.2 63.5 dB
140MHz Input (2V Range) 67.9 68.0 dB
250MHz Input (1V Range) 62.7 63.0 dB
250MHz Input (2V Range) 67.0 67.3 dB
30MHz Input (2V Range)
70MHz Input (1V Range) 84 84 dB
70MHz Input (2V Range) 84 84 dB
140MHz Input (1V Range) 81 84 dB
140MHz Input (2V Range) 81 81 dB
250MHz Input (1V Range) 77 80 dB
250MHz Input (2V Range) 77 75 dB
70MHz Input (1V Range) 90 90 dB
70MHz Input (2V Range) 90 90 dB
140MHz Input (1V Range) 90 90 dB
140MHz Input (2V Range) 90 90 dB
250MHz Input (1V Range) 90 90 dB
250MHz Input (2V Range) 90 90 dB
70MHz Input (1V Range) 63.5 63.6 dB
70MHz Input (2V Range) 68.2 68.3 dB
= 138MHz, f
IN1
= 140MHz 81 81 dBc
IN2
● 67 68.4 67.5 68.5 dB
● 72 84 73 84 dB
● 66.5 68.4 67 68.5 dB
22223f
3
Page 4
LTC2222/LTC2223
UU U
I TER AL REFERE CE CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage I
VCM Output Tempco ±25 ppm/C
VCM Line Regulation 3.1V < VDD < 3.5V 3 mV/V
V
Output Resistance –1mA < I
CM
= 0 1.575 1.600 1.625 V
OUT
< 1mA 4 Ω
OUT
(Note 4)
UU
DIGITAL I PUTS A D DIGITAL OUTPUTS
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC–)
V
ID
V
ICM
R
IN
C
IN
LOGIC INPUTS (OE, SHDN)
V
IH
V
IL
I
IN
C
IN
LOGIC OUTPUTS
OVDD = 3.3V
C
OZ
I
SOURCE
I
SINK
V
OH
V
OL
OVDD = 2.5V
V
OH
V
OL
OV
= 1.8V
DD
V
OH
V
OL
Differential Input Voltage ● 0.2 V
Common Mode Input Voltage Internally Set 1.6 V
Externally Set (Note 7)
Input Resistance 6kΩ
Input Capacitance (Note 7) 3 pF
High Level Input Voltage VDD = 3.3V ● 2V
Low Level Input Voltage VDD = 3.3V ● 0.8 V
Input Current VIN = 0V to V
Input Capacitance (Note 7) 3 pF
Hi-Z Output Capacitance OE = High (Note 7) 3 pF
Output Source Current V
Output Sink Current V
High Level Output Voltage IO = –10µA 3.295 V
Low Level Output Voltage IO = 10µA 0.005 V
High Level Output Voltage IO = –200µA 2.49 V
Low Level Output Voltage IO = 1.6mA 0.09 V
High Level Output Voltage IO = –200µA 1.79 V
Low Level Output Voltage IO = 1.6mA 0.09 V
OUT
OUT
= –200µA ● 3.1 3.29 V
I
O
= 1.6mA ● 0.09 0.4 V
I
O
DD
= 0V 50 mA
= 3.3V 50 mA
The ● denotes the specifications which apply over the
● 1.1 1.6 2.5 V
● –10 10 µA
4
22223f
Page 5
LTC2222/LTC2223
WU
POWER REQUIRE E TS
range, otherwise specifications are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
V
DD
OV
IV
P
DISS
P
SHDN
P
NAP
DD
DD
Analog Supply Voltage (Note 7) ● 3.1 3.3 3.5 3.1 3.3 3.5 V
Output Supply Voltage (Note 7) ● 0.5 3.3 3.6 0.5 3.3 3.6 V
Analog Supply Current ● 144 162 111 123 mA
Power Dissipation ● 475 535 366 406 mW
Shutdown Power SHDN = H, OE = H, No CLK 2 2 mW
Nap Mode Power SHDN = H, OE = L, No CLK 35 35 mW
= 25°C. (Note 8)
A
The ● denotes the specifications which apply over the full operating temperature
LTC2222 LTC2223
UW
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
f
S
t
L
t
H
t
AP
t
D
t
C
t
OE
Pipeline Latency 5 5 Cycles
Sampling Frequency ● 1 105 1 80 MHz
ENC Low Time Duty Cycle Stabilizer Off ● 4.5 4.76 500 5.9 6.25 500 ns
ENC High Time Duty Cycle Stabilizer Off ● 4.5 4.76 500 5.9 6.25 500 ns
Sample-and-Hold Aperture Delay 0 0 ns
ENC to DATA Delay (Note 7) ● 1.3 2.1 4 1.3 2.1 4 ns
ENC to CLOCKOUT Delay (Note 7) ● 1.3 2.1 4 1.3 2.1 4 ns
DATA to CLOCKOUT Skew (tC - tD) (Note 7) ● –0.6 0 0.6 –0.6 0 0.6 ns
Output Enable Delay (Note 7) ● 510 510 ns
The ● denotes the specifications which apply over the full operating temperature
LTC2222 LTC2223
Duty Cycle Stabilizer On
Duty Cycle Stabilizer On
● 3 4.76 500 3 6.25 500 ns
● 3 4.76 500 3 6.25 500 ns
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V
be clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND or above V
Note 4: V
differential ENC
drive, unless otherwise noted.
= 3.3V, f
DD
SAMPLE
+
/ENC– = 2V
= 105MHz (LTC2222) or 80MHz (LTC2223),
sine wave, input range = 2V
P-P
without latchup.
DD
P-P
, they will
DD
with differential
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve. The
deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when the
output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s
complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: V
differential ENC
drive.
= 3.3V, f
DD
+
SAMPLE
/ENC– = 2V
= 105MHz (LTC2222) or 80MHz (LTC2223),
sine wave, input range = 1V
P-P
with differential
P-P
22223f
5
Page 6
LTC2222/LTC2223
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2222: INL, 2V Range LTC2222: DNL, 2V Range
1.0
0.8
0.6
0.4
0.2
0
–0.2
ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0
1024
2048
OUTPUT CODE
3072
4096
2222 G01
1.0
0.8
0.6
0.4
0.2
0
–0.2
ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0
1024
2048
OUTPUT CODE
3072
2222 G02
4096
LTC2222: SNR vs Input Frequency,
–1dB, 2V Range
70
69
68
67
66
65
64
SNR (dBFS)
63
62
61
60
0
100 200
INPUT FREQUENCY (MHz)
500 600300 400
2222 G03
LTC2222: SNR vs Input Frequency,
–1dB, 1V Range
70
69
68
67
66
65
64
SNR (dBFS)
63
62
61
60
0
100 200 500 600300 400
INPUT FREQUENCY (MHz)
LTC2222: SFDR (HD4+) vs Input
Frequency, –1dB, 2V Range
100
95
90
85
80
75
SFDR (dBFS)
70
65
60
55
0
200 300 400 500 600
100
INPUT FREQUENCY (MHz)
2222 G04
LTC2222: SFDR (HD2 and HD3) vs
Input Frequency, –1dB, 2V Range
100
95
90
85
80
75
SFDR (dBFS)
70
65
60
55
0
200 300 400
100
INPUT FREQUENCY (MHz)
LTC2222: SFDR (HD4+) vs Input
Frequency, –1dB, 1V Range
100
95
90
85
80
75
SFDR (dBFS)
70
65
60
55
0
200 300 400 500 600
100
INPUT FREQUENCY (MHz)
500 600
2222 G05
2222 G082222 G07
LTC2222: SFDR (HD2 and HD3) vs
Input Frequency, –1dB, 1V Range
100
95
90
85
80
75
SFDR (dBFS)
70
65
60
55
0
200 300 400 500 600
100
INPUT FREQUENCY (MHz)
LTC2222: SFDR and SNR vs
Sample Rate, 2V Range,
fIN = 30MHz, –1dB
100
95
90
85
80
75
SFDR AND SNR (dBFS)
70
65
60
20 60 100
0
SFDR
SNR
40 80
SAMPLE RATE (Msps)
2222 G06
120
2222 G09
6
22223f
Page 7
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2222/LTC2223
LTC2222: SFDR and SNR vs
Sample Rate, 1V Range,
f
= 30MHz, –1dB
IN
100
95
90
85
80
75
70
65
SFDR AND SNR (dBFS)
60
55
50
20 60 100
0
SFDR
SNR
40 80
SAMPLE RATE (Msps)
LTC2222: SFDR vs Input Level,
fIN = 70MHz, 2V Range
100
90
80
70
60
50
40
30
SFDR (dBc AND dBFS)
20
10
0
–60
INPUT LEVELS (dBFS)
–40 –30 –20 –10 0–50
dBFS
dBc
LTC2222: IOV
LTC2222: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
130
120
110
100
2V RANGE
90
80
20
0
40
SAMPLE RATE (Msps)
(mA)
DD
IV
2223 G10 2223 G11 2223 G12
1V RANGE
60
80
100
LTC2222: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
2223 G13
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G14
5MHz Sine Wave Input,
–1dB,OV
8
6
(mA)
4
DD
IOV
2
0
20
0
LTC2222: 8192 Point FFT,
fIN = 5MHz, –1dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
vs Sample Rate,
DD
= 1.8V
DD
60
40
SAMPLE RATE (Msps)
FREQUENCY (MHz)
25 30 35 40
80
2223 G15
100
LTC2222: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G16
LTC2222: 8192 Point FFT,
fIN = 30MHz, –1dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G17
LTC2222: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G18
22223f
7
Page 8
LTC2222/LTC2223
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2222: 8192 Point FFT,
fIN = 70MHz, –1dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
LTC2222: 8192 Point FFT,
fIN = 250MHz, –1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G19
2223 G22
LTC2222: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
LTC2222: 8192 Point FFT,
fIN = 250MHz, –1dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G20
2223 G23
LTC2222: 8192 Point FFT,
fIN = 140MHz, –1dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
LTC2222: 8192 Point FFT,
fIN = 500MHz, –6dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G21
2223 G24
LTC2222: 8192 Point 2-Tone FFT,
fIN = 68MHz and 70MHz, –7dB
Each, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
8
2223 G25
LTC2222: 8192 Point 2-Tone FFT,
fIN = 138MHz and 140MHz, –7dB
Each, 1V Range LTC2222: Noise Histogram
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
5
10 15 20
FREQUENCY (MHz)
25 30 35 40
2223 G26
100000
80000
60000
COUNT
40000
20000
96679
16182
42 89
0
2044
2045
2046
CODE
18080
2047
2048
2223 G27
22223f
Page 9
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2223: INL, 2V Range LTC2223: DNL, 2V Range
1.0
0.8
0.6
0.4
0.2
0
–0.2
ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0
1024
2048
OUTPUT CODE
3072
4096
2223 G01
1.0
0.8
0.6
0.4
0.2
0
–0.2
ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0
1024
2048
OUTPUT CODE
3072
2223 G02
LTC2222/LTC2223
LTC2223: SNR vs Input Frequency,
–1dB, 2V Range
70
69
68
67
66
65
64
SNR (dBFS)
63
62
61
60
0
4096
100 200
INPUT FREQUENCY (MHz)
500 600300 400
2223 G03
LTC2223: SNR vs Input Frequency,
–1dB, 1V Range
70
69
68
67
66
65
64
SNR (dBFS)
63
62
61
60
0
100 200 500 600300 400
INPUT FREQUENCY (MHz)
LTC2223: SFDR (HD4+) vs Input
Frequency, –1dB, 2V Range
100
95
90
85
80
SFDR (dBFS)
75
70
65
60
0
200 300 400 500 600
100
INPUT FREQUENCY (MHz)
2223 G04
LTC2223: SFDR (HD2 and HD3) vs
Input Frequency, –1dB, 2V Range
100
95
90
85
80
SFDR (dBFS)
75
70
65
60
0
200 300 400
100
INPUT FREQUENCY (MHz)
LTC2223: SFDR (HD4+) vs Input
Frequency, –1dB, 1V Range
100
95
90
85
80
SFDR (dBFS)
75
70
65
60
0
200 300 400 500 600
100
INPUT FREQUENCY (MHz)
500 600
2223 G05
2223 G082223 G07
LTC2223: SFDR (HD2 and HD3) vs
Input Frequency, –1dB, 1V Range
100
95
90
85
80
SFDR (dBFS)
75
70
65
60
0
200 300 400 500 600
100
INPUT FREQUENCY (MHz)
LTC2223: SFDR and SNR vs
Sample Rate, 2V Range,
fIN = 30MHz, –1dB
100
95
90
85
80
75
70
65
SFDR AND SNR (dBFS)
60
55
50
20 60 100
0
SFDR
SNR
40 80
SAMPLE RATE (Msps)
2223 G06
2223 G09
22223f
9
Page 10
LTC2222/LTC2223
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2223: SFDR and SNR vs
Sample Rate, 1V Range,
= 30MHz, –1dB
f
IN
100
95
90
85
80
75
70
65
SFDR AND SNR (dBFS)
60
55
50
20 60 100
0
SFDR
SNR
40 80
SAMPLE RATE (Msps)
LTC2223: SFDR vs Input Level,
f
= 70MHz, 2V Range
IN
100
90
80
70
60
50
40
30
SFDR (dBc AND dBFS)
20
10
0
–60
INPUT LEVELS (dBFS)
–40 –30 –20 –10 0–50
dBFS
dBc
LTC2223: IOVDD vs Sample Rate,
LTC2223: IV
5MHz Sine Wave Input, –1dB
130
120
110
100
2V RANGE
90
80
20
0
(mA)
DD
IV
2223 G10 2223 G11 2223 G12
LTC2223: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
5
2223 G13
vs Sample Rate,
DD
60
40
SAMPLE RATE (Msps)
10 15 20
FREQUENCY (MHz)
1V RANGE
80
100
25 30 35 40
2223 G14
5MHz Sine Wave Input,
= 1.8V
DD
20
40
SAMPLE RATE (Msps)
(mA)
DD
IOV
–1dB,OV
8
6
4
2
0
0
LTC2223: 8192 Point FFT,
fIN = 5MHz, –1dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
60
80
25 30 35 40
2223 G15
100
LTC2223: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
10
25 30 35 40
2223 G16
LTC2223: 8192 Point FFT,
fIN = 30MHz, –1dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G17
LTC2223: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G18
22223f
Page 11
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2222/LTC2223
LTC2223: 8192 Point FFT,
fIN = 70MHz, –1dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
LTC2223: 8192 Point FFT,
fIN = 250MHz, –1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G19
25 30 35 40
2223 G22
LTC2223: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
LTC2223: 8192 Point FFT,
fIN = 250MHz, –1dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G20
2223 G23
LTC2223: 8192 Point FFT,
fIN = 140MHz, –1dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
LTC2223: 8192 Point FFT,
fIN = 500MHz, –6dB, 1V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G21
2223 G24
LTC2223: 8192 Point 2-Tone FFT,
fIN = 68MHz and 70MHz, –7dB
Each, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
10 15 20
5
FREQUENCY (MHz)
25 30 35 40
2223 G25
LTC2223: 8192 Point 2-Tone FFT,
fIN = 138MHz and 140MHz, –7dB
Each, 1V Range LTC2223: Noise Histogram
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
5
10 15 20
FREQUENCY (MHz)
25 30 35 40
2223 G26
100000
80000
60000
COUNT
40000
20000
96679
16182
42 89
0
2044
2045
2046
CODE
18080
2047
2048
2223 G27
22223f
11
Page 12
LTC2222/LTC2223
U
UU
PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input.
AIN– (Pin 2): Negative Differential Analog Input.
REFHA (Pins 3, 4): ADC High Reference. Bypass to Pins
5, 6 with 0.1µF ceramic chip capacitor, to Pins 9, 10 with
a 2.2µF ceramic capacitor and to ground with a 1µF
ceramic capacitor.
REFLB (Pins 5, 6): ADC Low Reference. Bypass to Pins 3,
4 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 9, 10.
REFHB (Pins 7, 8): ADC High Reference. Bypass to Pins
9, 10 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 3, 4.
REFLA (Pins 9, 10): ADC Low Reference. Bypass to Pins
7, 8 with 0.1µF ceramic chip capacitor, to Pins 3, 4 with a
2.2µF ceramic capacitor and to ground with a 1µF ceramic
capacitor.
VDD (Pins 11, 12, 14, 46, 47): 3.3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors. Adjacent pins
can share a bypass capacitor.
GND (Pins 13, 15, 45, 48): ADC Power Ground.
ENC+ (Pin 16): Encode Input. The input is sampled on the
positive edge.
ENC– (Pin 17): Encode Complement Input. The input is
sampled on the negative edge. Bypass to ground with
0.1µF ceramic for single-ended ENCODE signal.
SHDN (Pin 18): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to V
results in sleep mode with the outputs at high impedance.
DD
OE (Pin 19): Output Enable Pin. Refer to SHDN pin
function.
CLOCKOUT (Pin 20): Data Valid Output. Latch data on the
falling edge of CLKOUT.
D0 – D11 (Pins 21, 24, 25, 26, 29, 30, 31, 34, 35, 36, 39,
40): Digital Outputs. D11 is the MSB.
OGND (Pins 22, 27, 32, 38): Output Driver Ground.
(Pins 23, 28, 33, 37): Positive Supply for the
OV
DD
Output Drivers. Bypass to ground with 0.1µF ceramic chip
capacitors.
OF (Pin 41): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 42): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
straight binary output format and turns the clock duty
cycle stabilizer off. Connecting MODE to 1/3 V
straight binary output format and turns the clock duty
cycle stabilizer on. Connecting MODE to 2/3 VDD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. Connecting MODE to VDD selects 2’s
complement output format and turns the clock duty cycle
stabilizer off.
SENSE (Pin 43): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±V
VCM (Pin 44): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package needs to be soldered to
ground.
. ±1V is the largest valid input range.
SENSE
selects
DD
12
22223f
Page 13
LTC2222/LTC2223
UU
W
FUNCTIONAL BLOCK DIAGRA
+
A
A
V
2.2µF
SENSE
IN
INPUT
S/H
–
IN
CM
1.6V
REFERENCE
RANGE
SELECT
REF
BUF
FIRST PIPELINED
ADC STAGE
(4 BITS)
SECOND PIPELINED
ADC STAGE
(3 BITS)
DIFF
REF
AMP
REFHAREFLB REFLA REFHB
0.1µF0.1µF
2.2µF
1µF
1µF
THIRD PIPELINED
INTERNAL CLOCK SIGNALSREFH REFL
DIFFERENTIAL
LOW JITTER
ENC
ADC STAGE
(3 BITS)
INPUT
CLOCK
DRIVER
+
ENC
FOURTH PIPELINED
ADC STAGE
(3 BITS)
CONTROL
LOGIC
–
SHDN
OEM0DE
FIFTH PIPELINED
ADC STAGE
(3 BITS)
SHIFT REGISTER
AND CORRECTION
OUTPUT
DRIVERS
OGND
22223 F01
•
•
•
OV
DD
OF
D11
D0
CLKOUT
WUW
TI I G DIAGRA S
ANALOG
INPUT
–
ENC
+
ENC
D0-D11, OF
CLOCKOUT
OE
DATA
Figure 1. Functional Block Diagram
Timing Diagram
t
AP
N
t
H
t
OE
N + 1
t
L
t
D
N – 5 N – 4 N – 3 N – 2 N – 1
t
C
N + 2
OF, D0-D11, CLKOUT
N + 3
t
OE
N + 4
22223 TD02
22223f
13
Page 14
LTC2222/LTC2223
WUUU
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log √(V22 + V32 + V42 + . . . Vn2)/V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC+ equals the ENC– voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNR
CONVERTER OPERATION
As shown in Figure 1, the LTC2222/LTC2223 is a CMOS
pipelined multistep converter. The converter has five
pipelined ADC stages; a sampled analog input will result in
a digitized value five cycles later (see the Timing Diagram
section). For optimal AC performance the analog inputs
should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with
slightly worse harmonic distortion. The encode input is
differential for improved common mode noise immunity.
The LTC2222/LTC2223 has two phases of operation,
determined by the state of the differential ENC+/ENC– input
pins. For brevity, the text will refer to ENC+ greater than
ENC– as ENC high and ENC+ less than ENC– as ENC low.
= –20log (2pi) • fIN • t
JITTER
JITTER
22223f
14
Page 15
LTC2222/LTC2223
U
WUU
APPLICATIO S I FOR ATIO
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth
stage residue that is sent to the fifth stage ADC for final
evaluation.
they charge to, and track the differential input voltage.
When ENC transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when ENC is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
LTC2222/LTC2223
V
DD
15Ω
+
A
IN
V
DD
15Ω
–
A
IN
V
C
PARASITIC
1pF
C
PARASITIC
1pF
DD
C
SAMPLE
1.6pF
C
SAMPLE
1.6pF
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2222/
LTC2223 CMOS differential sample-and-hold. The analog
inputs are connected to the sampling capacitors (C
SAMPLE
)
through NMOS transistors. The capacitors shown attached to each input (C
PARASITIC
) are the summation of all
other capacitance associated with each input.
During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
1.6V
6k
+
ENC
–
ENC
6k
1.6V
22223 F02
Figure 2. Equivalent Input Circuit
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
should be driven with the input signal and A
–
should be
IN
IN
+
connected to 1.6V or VCM.
22223f
15
Page 16
LTC2222/LTC2223
WUUU
APPLICATIO S I FOR ATIO
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.6V. The VCM output pin (Pin
60) may be used to provide the common mode bias level.
can be tied directly to the center tap of a transformer
V
CM
to set the DC input level or as a reference level to an op amp
differential driver circuit. The V
pin must be bypassed to
CM
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2222/LTC2223 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and input
reactance can influence SFDR. At the falling edge of ENC,
the sample-and-hold circuit will connect the 1.6pF sampling capacitor to the input pin and start the sampling
period. The sampling period ends when ENC rises, holding
the sampled input on the sampling capacitor. Ideally the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F
ENCODE
); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2222/LTC2223 being driven by an
RF transformer with a center tapped secondary. The
secondary center tap is DC biased with VCM, setting the
ADC input signal at its optimum DC level. Figure 3 shows
a 1:1 turns ratio transformer. Other turns ratios can be
used if the source impedance seen by the ADC does not
exceed 100Ω for each ADC input. A disadvantage of using
a transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequencies below 1MHz.
V
CM
2.2µF
ANALOG
INPUT
0.1µFT1
1:1
25Ω
25Ω
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
25Ω
0.1µF
25Ω
12pF
A
A
A
A
IN
IN
IN
IN
+
+
–
–
LTC2222/23
22223 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input
frequencies.
Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
V
CM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
ANALOG
INPUT
+
CM
–
AMPLIFIER = LTC6600-20, AD8138, ETC.
25Ω
+
–
25Ω
2.2µF
A
A
12pF
A
A
+
IN
+
IN
–
IN
–
IN
LTC2222/23
22223 F04
Figure 4. Differential Drive with an Amplifier
V
CM
ANALOG
INPUT
0.1µF
10k
10k
25Ω
25Ω
0.1µF
2.2µF
12pF
A
IN
A
IN
A
IN
A
IN
+
LTC2222/23
+
–
–
22223 F05
Figure 5. Single-Ended Drive
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
22223f
16
Page 17
WUUU
APPLICATIO S I FOR ATIO
LTC2222/LTC2223
wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be
decreased to prevent excessive signal loss.
IN
+
and A
The A
package inductance. The two A
–
inputs each have two pins to reduce
IN
+
and the two A
IN
IN
–
pins
should be shorted together.
For input frequencies above 100MHz the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux
coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.6V. In
Figure 8 the series inductors are impedance matching
elements that maximize the ADC bandwidth.
V
CM
2.2µF
8pF
2.2µF
V
2.2µF
2pF
A
A
A
A
A
A
A
A
IN
IN
IN
IN
V
CM
A
IN
A
IN
A
IN
A
IN
CM
+
IN
+
IN
–
IN
–
IN
+
LTC2222/23
+
–
–
+
+
–
–
LTC2222/23
22223 F06
LTC2222/23
22223 F07
22223 F08
ANALOG
INPUT
0.1µF
T1
0.1µF
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
25Ω
25Ω
12Ω
0.1µF
12Ω
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 100MHz and 250MHz
0.1µF
ANALOG
INPUT
T1
0.1µF
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
25Ω
25Ω
0.1µF
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 250MHz and 500MHz
ANALOG
INPUT
0.1µF
T1
0.1µF
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
25Ω
25Ω
4.7nH
0.1µF
4.7nH
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 500MHz
Reference Operation
Figure 9 shows the LTC2222/LTC2223 reference circuitry
consisting of a 1.6V bandgap reference, a difference
amplifier and switching and control circuit. The internal
voltage reference can be configured for two pin selectable
input ranges of 2V (±1V differential) or 1V (±0.5V differ-
ential). Tying the SENSE pin to V
typing the SENSE pin to V
CM
selects the 2V range;
DD
selects the 1V range.
The 1.6V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.6V reference output, V
. This provides a high
CM
frequency low impedance path to ground for internal and
external circuitry.
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has four pins: two each of REFHA
and REFHB for the high reference and two each of REFLA
and REFLB for the low reference. The multiple output pins
are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9.
LTC2222/LTC2223
4Ω
V
TIE TO V
TIE TO V
RANGE = 2 • V
CM
2.2µF
SENSE
REFLB
0.1µF
REFHA
2.2µF
REFLA
0.1µF
REFHB
FOR 2V RANGE;
DD
FOR 1V RANGE;
CM
SENSE
0.5V < V
SENSE
1.6V
1µF
1µF
FOR
< 1V
Figure 9. Equivalent Reference Circuit
RANGE
DETECT
AND
CONTROL
1.6V BANDGAP
REFERENCE
1V
INTERNAL ADC
HIGH REFERENCE
DIFF AMP
INTERNAL ADC
LOW REFERENCE
0.5V
BUFFER
22223 F09
22223f
17
Page 18
LTC2222/LTC2223
WUUU
APPLICATIO S I FOR ATIO
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
1.6V
12k
0.8V
12k
Figure 10. 1.6V Range ADC
V
CM
2.2µF
SENSE
1µF
LTC2222/
LTC2223
22223 F10
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 5dB. See the Typical Performance Characteristics section.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at both
inputs as common mode noise. The encode inputs have a
common mode range of 1.1V to 2.5V. Each input may be
driven from ground to VDD for single-ended drive.
V
DD
TO INTERNAL
ADC CIRCUITS
6k
6k
22223 F11
–
CLOCK
INPUT
LTC2222/LTC2223
1.6V BIAS
V
DD
+
ENC
0.1µF
1:4
1.6V BIAS
ENC
V
DD
–
50Ω
Figure 11. Transformer Driven ENC+/ENC
Driving the Encode Inputs
The noise performance of the LTC2222/LTC2223 can
depend on the encode signal quality as much as on the
analog input. The ENC+/ENC– inputs are intended to be
driven differentially, primarily for noise immunity from
common mode noise sources. Each input is biased through
a 6k resistor to a 1.6V bias. The bias resistors set the DC
operating point for transformer coupled drive circuits and
can set the logic threshold for single-ended drive circuits.
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequencies) take the following into consideration:
1. Differential drive should be used.
18
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2222/LTC2223 is
105Msps (LTC2222) and 80Msps (LTC2223). For the ADC
to operate properly, the encode signal should have a 50%
(±5%) duty cycle. Each half cycle must have at least 4.5ns
(LTC2222) or 5.9ns (LTC2223) for the ADC internal circuitry to have enough settling time for proper operation.
Achieving a precise 50% duty cycle is easy with differential
sinusoidal drive using a transformer or using symmetric
differential logic such as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the ENC+ pin to sample the analog
input. The falling edge of ENC+ is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 20% to 80% and the clock
22223f
Page 19
WUUU
APPLICATIO S I FOR ATIO
LTC2222/LTC2223
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To use
the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3V
or 2/3VDD using external resistors.
DD
The lower limit of the LTC2222/LTC2223 sample rate is
determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operating frequency for the LTC2222/LTC2223 is 1Msps.
+
1.6V
ENC
ENC
–
LTC2222/
LTC2223
22223 F09a
V
THRESHOLD
= 1.6V
0.1µF
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
3.3V
MC100LVELT22
3.3V
130Ω
Q0
D0
Q0
130Ω
ENC
ENC
83Ω83Ω
+
–
LTC2222/
LTC2223
22223 F09b
Figure 12b. ENC Drive Using a CMOS to PECL Translator
DIGITAL OUTPUTS
Digital Output Buffers
Figure 13 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2222/LTC2223 should drive a
minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The
output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OV
voltages will also help reduce interference
DD
from the digital outputs.
DATA
FROM
LATCH
OE
V
DD
PREDRIVER
LOGIC
V
DD
Figure 13. Digital Output Buffer
LTC2222/LTC2223
OV
DD
43Ω
22223 F10
OV
OGND
DD
0.5V
TO V
0.1µF
TYPICAL
DATA
OUTPUT
DD
Data Format
The LTC2222/LTC2223 parallel digital output can be selected for offset binary or 2’s complement format. The
format is selected with the MODE pin. Connecting MODE
to GND or 1/3VDD selects straight binary output format.
Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be
used to set the 1/3VDD or 2/3VDD logic values. Table 1
shows the logic states for the MODE pin.
Table 1. MODE Pin Function
Clock Duty
MODE Pin Output Format Cycle Stablizer
0 Straight Binary Off
1/3V
2/3V
V
DD
DD
DD
Straight Binary On
2’s Complement On
2’s Complement Off
22223f
19
Page 20
LTC2222/LTC2223
U
WUU
APPLICATIO S I FOR ATIO
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Clock
The ADC has a delayed version of the ENC+ input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system. This
is necessary when using a sinusoidal encode. Data will be
updated just after CLKOUT rises and can be latched on the
falling edge of CLKOUT.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage up to the VDD of the
part. OGND can be powered with any voltage from GND up
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF and CLKOUT.
The data access and bus relinquish times are too slow to
allow the outputs to be enabled and disabled during full
speed operation. The output Hi-Z state is intended for use
during long periods of inactivity.
to GND results in nap mode, which typically dissipates
35mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap mode all digital outputs are disabled and enter the
Hi-Z state.
GROUNDING AND BYPASSING
The LTC2222/LTC2223 requires a printed circuit board with
a clean unbroken ground plane. A multilayer board with an
internal ground plane is recommended. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB pins
as shown in the block diagram on the front page of this data
sheet. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recommended. The 2.2µF capacitor between REFHA and
REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and
should be made as wide as possible.
The LTC2222/LTC2223 differential inputs should run parallel and close to each other. The input traces should be as
short as possible to minimize capacitance and to minimize
noise pickup.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to V
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to VDD and OE
DD
20
HEAT TRANSFER
Most of the heat generated by the LTC2222/LTC2223 is
transferred from the die through the bottom-side exposed
pad and package leads onto the printed circuit board. For
good electrical and thermal performance, the exposed pad
should be soldered to a large grounded pad on the PC board.
It is critical that all ground pins are connected to a ground
plane of sufficient area.
22223f
Page 21
WUUU
APPLICATIO S I FOR ATIO
Evaluation Circuit Schematic of the LTC2222
ANALOG
INPUT
V
C27
10µF
6.3V
R19
C1
OPT
0.1µF
T1*
J1
C3
0.1µF
CM
V
DD
V
DD
V
CM
EXT
REF
C7
2.2µF
C10
0.1µF
R17
105k
R18
100k
V
V
DD
JP3
SENSE
V
V
EXT
REF
CC
C12
0.1µF
DD
CM
0.1µF
R5
1k
C22
(2.5V)
C28
0.01µF
SHDN
GND
C5
1µF
C8
1µF
V
DD
C13
0.1µF
R12
1k
R13
1k
R14
1k
U6
1
2
3
4
V
LT1763
OUT
ADJ
GND
BYP
R1*
R2
24.9
R4
24.9
C4
0.1µF
CLK
CLK
JP2
JP4
MODE
DD
V
2/3V
1/3V
GND
IN
GND
GND
SHDN
C2*
C24
0.1µF
ENCODE
INPUT
C34
1µF
U1
LTC2222*
1
+
A
CLKOUT
IN
2
–
A
IN
3
REFHA
4
REFHA
13
GND
15
GND
5
REFLB
6
REFLB
7
REFHB
8
REFHB
9
REFLA
10
REFLA
46
V
DD
47
V
DD
11
V
DD
12
V
DD
14
V
DD
16
+
ENC
17
–
ENC
18
SHDN
19
OEL
44
V
CM
43
SENSE
42
MODE
C23
0.1µF
J3
GND
49
OV
OV
OV
OV
OGND
OGND
OGND
OGND
R16
100Ω
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
OF
DD
DD
DD
DD
GND
GND
ETC1-1T
R6*
C6
0.1µF
C9
0.1µF
C11
33pF
C15
2.2µF
DD
DD
DD
V
DD
8
7
6
5
20
21
24
25
26
29
30
31
34
35
36
39
40
41
37
33
28
23
38
32
27
22
48
45
C21
0.1µF
C20
0.1µF
C19
0.1µF
C18
0.1µF
T2
V
C26
0.1µF
CC
V
R15
100Ω
LTC2222/LTC2223
C33
V
WP
SCL
SDA
C29
0.1µF
C17
0.1µF
CC
V
CC
U2
5
NC7SV865X
1
4
2
8
7
6
5
3
R10
10k
C30
0.1µF
R3
33Ω
R9
10kR810k
C31
0.1µF
V
CC
U3
34
GND
45
GND
39
GND
42
V
CC
25
2LE
48
1LE
24
2OE
1
1OE
47
1D1
46
1D2
44
1D3
43
1D4
41
1D5
40
1D6
38
1D7
37
1D8
36
2D1
35
2D2
33
2D3
32
2D4
30
2D5
29
2D6
27
2D7
26
2D8
PI74VCX16373A
NC7SV865X
CC
28
GND
31
V
CC
21
GND
15
GND
18
V
CC
10
GND
4
GND
7
V
CC
2
1Q1
3
1Q2
RN1D 33Ω
5
1Q3
RN1C 33Ω
6
1Q4
RN1B 33Ω
8
1Q5
RN1A 33Ω
9
1Q6
RN2D 33Ω
11
1Q7
RN2C 33Ω
12
1Q8
RN2B 33Ω
13
2Q1
RN2A 33Ω
14
2Q2
RN3D 33Ω
16
2Q3
RN3C 33Ω
17
2Q4
RN3B 33Ω
19
2Q5
RN3A 33Ω
20
2Q6
22
2Q7
23
2Q8
V
CC
5
U5
1
4
2
C16
3
0.1µF
V
DD
GND
JP1
CLKOUT CLKOUT
0.1µF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
U4
1
A0
2
A1
3
A2
4
A3
24LC025
V
CC
V
DD
3.3V
C25
4.7µF
PWR
GND
Assembly Type U1 R1, R6 C2 T1
DC751A-A LTC2222 24.9Ω 12pF ETC1-1T
DC751A-B LTC2223 24.9Ω 12pF ETC1-1T
DC751A-C LTC2232 24.9Ω 12pF ETC1-1T
DC751A-D LTC2233 24.9Ω 12pF ETC1-1T
CLK
DC751A-E LTC2222 12.4Ω 8.2pF ETC1-1-13
DC751A-F LTC2223 12.4Ω 8.2pF ETC1-1-13
DC751A-G LTC2232 12.4Ω 8.2pF ETC1-1-13
CLK
DC751A-H LTC2233 12.4Ω 8.2pF ETC1-1-13
*Version Type
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
3201S-40G1
C32
0.1µF
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
22223f
21
Page 22
LTC2222/LTC2223
WUUU
APPLICATIO S I FOR ATIO
Layer 1 Component Side Layer 2 GND Plane
Silkscreen Top
22
Layer 3 Power Plane Layer 4 Bottom Side
22223f
Page 23
PACKAGE DESCRIPTIO
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
7.00 ± 0.10
(4 SIDES)
PIN 1 TOP MARK
(SEE NOTE 5)
U
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704)
0.70 ±0.05
5.15 ±0.05
6.10 ±0.05 7.50 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
0.75 ± 0.05
LTC2222/LTC2223
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE MO-220 VARIATION (WKKD-2)
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM
OF PACKAGE DO NOT INCLUDE MOLD FLASH.
MOLD FLASH, IF PRESENT, SHALL NOT EXCEED
0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1
LOCATION ON THE TOP AND BOTTOM OF PACKAGE
R = 0.115
TYP
CHAMFER
4847
PIN 1
0.40 ± 0.10
1
2
5.15 ± 0.10
(4-SIDES)
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
0.25 ± 0.05
0.50 BSC
(UK48) QFN 0903
22223f
23
Page 24
LTC2222/LTC2223
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1741 12-Bit, 65Msps ADC 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
LTC1742 14-Bit, 65Msps ADC 76.5dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1743 12-Bit, 50Msps ADC 72.5dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1744 14-Bit, 50Msps ADC 77dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1745 12-Bit, 25Msps ADC 72.5dB SNR, 380mW, 48-Pin TSSOP Package
LTC1746 14-Bit, 25Msps ADC 77.5dB SNR, 390mW, 48-Pin TSSOP Package
LTC1747 12-Bit, 80Msps ADC 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
LTC1748 14-Bit, 80Msps ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1749 12-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 87dB SFDR
LTC1750 14-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR
LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm x 9mm QFN Package
LTC2221 12-Bit, 135Msps ADC 660mW, 67.5dB SNR, 9mm x 9mm QFN Package
LTC2224 12-Bit, 135Msps ADC 660mW, 67.5dB SNR, 7mm x 7mm QFN Package
LTC2230 10-Bit, 170Msps ADC 890mW, 61dB SNR, 9mm x 9mm QFN Package
LTC2231 10-Bit, 135Msps ADC 660mW, 61dB SNR, 9mm x 9mm QFN Package
LTC2232 10-Bit, 105Msps ADC 475mW, 61dB SNR, 7mm x 7mm QFN Package
LTC2233 10-Bit, 80Msps ADC 366mW, 61dB SNR, 7mm x 7mm QFN Package
LTC2234 10-Bit, 135Msps ADC 660mW, 61dB SNR, 7mm x 7mm QFN Package
LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514 Ultralow Distortion IF Amplifier/ADC Driver with 450MHz 1dB BW, 47dB OIP3, Digital Gain Control
Digitally Controlled Gain 10.5dB to 33dB in 1.5dB/Step
LT5515 1.5GHz to 2.5GHz Direct Conversion 20dBm IIP3, Integrated LO Quadrature Generator
Quadrature Demodulator
LT5516 0.8GHz to 1.5GHz Direct Conversion 21.5dBm IIP3, Integrated LO Quadrature Generator
Quadrature Demodulator
LT5517 40MHz to 900MHz Direct Conversion 21dBm IIP3, Integrated LO Quadrature Generator
Quadrature Demodulator
LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 500Ω Single-Ended RF and LO Ports
24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
22223f
LT/TP 0804 1K • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2004
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