Datasheet LTC2208UP, LTC2208 Datasheet (Linear Technology)

FEATURES

■

Sample Rate: 130Msps

■

78dBFS Noise Floor

■

100dB SFDR

■

SFDR >83dB at 250MHz (1.5V

■

PGA Front End (2.25V

■

700MHz Full Power Bandwidth S/H

■

Optional Internal Dither

■

Optional Data Output Randomizer

■

LVDS or CMOS Outputs

■

Single 3.3V Supply

■

Power Dissipation: 1.25W

■

Clock Duty Cycle Stabilizer

■

Pin Compatible 14-Bit Version

or 1.5V

P-P

Input Range)

P-P

Input Range)

P-P

130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit)

■

64-Pin (9mm × 9mm) QFN Package

U

APPLICATIO S

■

Telecommunications

■

Receivers

■

Cellular Base Stations

■

Spectrum Analysis

■

Imaging Systems

■

ATE

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

LTC2208

16-Bit, 130Msps ADC

U

DESCRIPTIO

The LTC®2208 is a 130Msps, sampling 16-bit A/D con­verter designed for digitizing high frequency, wide dynamic
range signals with input frequencies up to 700MHz. The
input range of the ADC can be optimized with the PGA
front end.

The LTC2208 is perfect for demanding communications
applications, with AC performance that includes 78dBFS
Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low jitter of 70fs

of high input frequencies with excellent noise performance.
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
missing codes).

The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.

+

The ENC

and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al­lows high performance at full speed with a wide range of
clock duty cycles.

allows undersampling

RMS

TYPICAL APPLICATIO

3.3V

SENSE

–

INTERNAL ADC

REFERENCE

GENERATOR

16-BIT
PIPELINED
ADC CORE

PGA SHDN DITH MODE LVDS RAND

ANALOG

INPUT

V

CM

2.2µF

AIN

AIN

COMMON MODE

+

–

1.25V

BIAS VOLTAGE

+

S/H

AMP

–

CLOCK/DUTY

CYCLE

CONTROL

+

ENC

ENC

U

CORRECTION

LOGIC AND

SHIFT REGISTER

ADC CONTROL INPUTS

OUTPUT

DRIVERS

OV

DD

OGND

V

GND

64k Point FFT, FIN = 15.1MHz,

0.5V TO 3.6V

1µF

OF
CLKOUT
D15

DD

CMOS
OR

•
LVDS

•

•

D0

1µF 1µF 1µF

3.3V

2208 TA01

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0

–1dB, PGA = 0

20

10

FREQUENCY (MHz)

50

40

30

60

2208 G03

2208fb

1

LTC2208

WW

W

U

ABSOLUTE AXI U RATI GS

OV

= VDD (Notes 1 and 2)

DD

Supply Voltage (VDD) ...................................–0.3V to 4V

Digital Output Ground Voltage (OGND) ........–0.3V to 1V

Analog Input Voltage (Note 3) ..... –0.3V to (V

Digital Input Voltage .................... –0.3V to (V

Digital Output Voltage ................ –0.3V to (OV

Power Dissipation ............................................ 2000mW

Operating Temperature Range

LTC2208C ................................................0°C to 70°C

LTC2208I .............................................– 40°C to 85°C

Storage Temperature Range ..................–65°C to 150°C

Digital Output Supply Voltage (OV

) .......... –0.3V to 4V

DD

+ 0.3V)

DD

+ 0.3V)

DD

+ 0.3V)

DD

SENSE 1

GND 2

V

CM

GND 4

V

DD

V

DD

GND 7
AIN

AIN
GND 10
GND 11

+

ENC

–

ENC

GND 14

V

DD

V

DD

TOP VIEW

/DA14

+

/OFA

/DA15

+

–

59 OF

64 PGA

63 RAND

3

5
6

+

8

–

9

12
13

15
16

17

DD

V

GND 18

EXPOSED PAD IS GND (PIN 65)

MUST BE SOLDERED TO PCB BOARD

T

58 D15

62 MODE

61 LVDS

60 OF

19

20

/DB0 21

/DB1 22

/DB2 23

DITH

SHDN

–

+

–

D0

D1

DO

= 125°C, θJA = 20°C/W**

JMAX

+

–

57 D15 /DA13

65

/DB3 24

+

–

D1

/DA12

/DA11

–

56 D14

55 D14

/DB4 25

/DB5 26

+

D2

D2

/DA10

+

–

54 D13

/DB6 27

–

+

D3

/DA9

53 D13

/DB7 28

D3

UUW

FOR ATIOPACKAGE/ORDER I

/DA8

–

+

DD

52 D12

51 D12 /DA7

50 OGND

49 OV

48 D11
47 D11
46 D10
45 D10

+

44 D9

–

43 D9

+

42 D8

–

41 D8
40 CLKOUT
39 CLKOUT

+

38 D7

–

37 D7

+

36 D6

–

35 D6

+

34 D5

–

33 D5

32

DD

/DB8 29

/DB9 30

–

+

OV

OGND 31

D4

D4

+

/DA6

–

/DA5

+

/DA4

–

/DA3
/DA2
/DA1
/DA0
/CLKOUTA

+

/CLKOUTB

–

/OFB
/DB15
/DB14
/DB13
/DB12
/DB11
/DB10

ORDER PART

NUMBER

LTC2208CUP

UP PART

MARKING*

LTC2208UP

LTC2208IUP

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
*The temperature grade is identifi ed by a label on the shipping container.

= 150°C, option available, consult factory.

**T

JMAX

U

CO VERTER CHARACTERISTICS

The
temperature range, otherwise specifi cations are at T

PARAMETER CONDITIONS MIN TYP MAX UNITS

Integral Linearity Error Differential Analog Input (Note 5) TA = 25°C ±1.2 ±4.0 LSB
Integral Linearity Error Differential Analog Input (Note 5)
Differential Linearity Error Differential Analog Input
Offset Error (Note 6)
Offset Drift ±10 μV/
Gain Error External Reference
Full-Scale Drift Internal Reference ±30

Transition Noise External Reference 2.9 LSB

= 25°C. (Note 4)

A

External Reference ±15

●

denotes the specifi cations which apply over the full operating

●

±1.5 ±4.5 LSB

●

±0.3 ±1 LSB

●

±2 ±8.5 mV

●

±0.2 ±1.5 %FS

ppm/°C
ppm/°C

RMS

°C

2

2208fb

LTC2208

T

UU

A ALOG I PU

The
specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (A
V

IN, CM

I

Analog Input Leakage Current 0V ≤ A

IN

I

SENSE Input Leakage Current 0V ≤ SENSE ≤ VDD

SENSE

MODE Pin Pull-Down Current to GND 10 µA

I

MODE

I

LVDS Pin Pull-Down Current to GND 10 µA

LVDS

C

Analog Input Capacitance Sample Mode ENC+ < ENC– 6.5 pF

IN

Hold Mode ENC
t

Sample-and-Hold 1 ns

AP

Acquisition Delay Time
t

Sample-and-Hold 70 fs RMS

JITTER

Acquisition Delay Time Jitter
CMRR Analog Input 1V < (A

Common Mode Rejection Ratio
BW-3dB Full Power Bandwidth R

U

W

DY A IC ACCURACY

The

= 25°C. (Note 4)

A

Analog Input Common Mode Differential Input (Note 7)

otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SNR Signal-to-Noise Ratio 5MHz Input (2.25V Range, PGA = 0) 77.7 dBFS
5MHz Input (1.5V Range, PGA = 1) 75.3 dBFS

30MHz Input (2.25V Range, PGA = 0) T
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1) 75.2 dBFS

70MHz Input (2.25V Range, PGA = 0) 77.5 dBFS
70MHz Input (1.5V Range, PGA = 1) 75.1 dBFS

140MHz Input (2.25V Range, PGA = 0) 76.9 dBFS
140MHz Input (1.5V Range, PGA = 1) T
140MHz Input (1.5V Range, PGA = 1)

250MHz Input (2.25V Range, PGA = 0) 75.4 dBFS
250MHz Input (1.5V Range, PGA =1 ) 73.8 dBFS

SFDR Spurious Free 5MHz Input (2.25V Range, PGA = 0) 100 dBc
Dynamic Range 5MHz Input (1.5V Range, PGA = 1) 100 dBc

2
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1) 100 dBc

70MHz Input (2.25V Range, PGA = 0) 90 dBc
70MHz Input (1.5V Range, PGA = 1) 95 dBc

140MHz Input (2.25V Range, PGA = 0) 85 dBc
140MHz Input (1.5V Range, PGA = 1) T
140MHz Input (1.5V Range, PGA = 1)

250MHz Input (2.25V Range, PGA = 0) 78 dBc
250MHz Input (1.5V Range, PGA = 1)

nd

or 3rd Harmonic 30MHz Input (2.25V Range, PGA = 0) TA = 25°C 88 95 dBc

●

denotes the specifi cations which apply over the full operating temperature range, otherwise

+

–

– A

IN

= 25°C. AIN = –1dBFS. (Note 4)

A

) 3.135V ≤ V

IN

< 25Ω 700 MHz

S

●

denotes the specifi cations which apply over the full operating temperature range,

≤ 3.465V 1.5 or 2.25 V

DD

●

+

–

, A

≤ VDD

IN

IN

+

–

> ENC

+

–

= A

IN

) <1.5V 80 dB

IN

= 25°C 76.5 77.6 dBFS

A

= 25°C 73.8 74.8 dBFS

A

= 25°C 86 90 dBc

A

1 1.25 1.5 V

●

–1 1 µA

●

–3 3 µA

1.8 pF

●

76.1 77.3 dBFS

●

73.4 74.5 dBFS

●

87 94 dBc

●

84 89 dBc

83 dBc

P-P

2208fb

3

LTC2208

U

W

DY A IC ACCURACY

The
otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SFDR Spurious Free 5MHz Input (2.25V Range, PGA = 0) 100 dBc
Dynamic Range 5MHz Input (1.5V Range, PGA = 1) 100 dBc

4
or Higher 30MHz Input (1.5V Range, PGA = 1) 100 dBc

70MHz Input (2.25V Range, PGA = 0) 100 dBc
70MHz Input (1.5V Range, PGA = 1) 100 dBc

140MHz Input (2.25V Range, PGA = 0) 95 dBc
140MHz Input (1.5V Range, PGA = 1)

250MHz Input (2.25V Range, PGA = 0) 90 dBc
250MHz Input (1.5V Range, PGA = 1)

S/(N+D) Signal-to-Noise 5MHz Input (2.25V Range, PGA = 0) 77.7 dBFS
Plus Distortion Ratio 5MHz Input (1.5V Range, PGA = 1) 75.3 dBFS

30MHz Input (2.25V Range, PGA = 0) T
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1) 75.2 dBFS

70MHz Input (2.25V Range, PGA = 0) 77.4 dBFS
70MHz Input (1.5V Range, PGA = 1) 75 dBFS

140MHz Input (2.25V Range, PGA = 0) 76.4 dBFS
140MHz Input (1.5V Range, PGA = 1) T
140MHz Input (1.5V Range, PGA = 1)

250MHz Input (2.25V Range, PGA = 0) 73.6 dBFS
250MHz Input (1.5V Range, PGA = 1)

SFDR Spurious Free Dynamic Range 5MHz Input (2.25V Range, PGA = 0) 105 dBFS
at –25dBFS 5MHz Input (1.5V Range, PGA = 1) 105 dBFS

Dither “OFF” 30MHz Input (2.25V Range, PGA = 0) 105 dBFS
30MHz Input (1.5V Range, PGA = 1) 105 dBFS

70MHz Input (2.25V Range, PGA = 0) 105 dBFS
70MHz Input (1.5V Range, PGA = 1) 105 dBFS

14 0MHz Input (2.25V Range, PGA = 0) 100 dBFS
140MHz Input (1.5V Range, PGA = 1)

250MHz Input (2.25V Range, PGA = 0) 100 dBFS
250MHz Input (1.5V Range, PGA = 1)

SFDR Spurious Free Dynamic Range 5MHz Input (2.25V Range, PGA = 0) 115 dBFS
at –25dBFS 5MHz Input (1.5V Range, PGA = 1) 115 dBFS

Dither “ON” 30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1) 115 dBFS

70MHz Input (2.25V Range, PGA = 0) 115 dBFS
70MHz Input (1.5V Range, PGA = 1) 115 dBFS

140MHz Input (2.25V Range, PGA = 0) 110 dBFS
140MHz Input (1.5V Range, PGA = 1)

250MHz Input (2.25V Range, PGA = 0) 105 dBFS
250MHz Input (1.5V Range, PGA = 1)

th

Harmonic 30MHz Input (2.25V Range, PGA = 0)

= 25°C. AIN = –1dBFS unless otherwise noted. (Note 4)

A

●

denotes the specifi cations which apply over the full operating temperature range,

●

90 100 dBc

●

88 95 dBc

90 dBc

= 25°C 76.3 77.5 dBFS

A

= 25°C 73.6 74.5 dBFS

A

●

75.9 77.5 dBFS

●

73.2 74.5 dBFS

72.9 dBFS

100 dBFS

100 dBFS

●

100 115 dBFS

110 dBFS

105 dBFS

4

2208fb

LTC2208

WW

CO O ODE BIAS CHARACTERISTICS

The ● denotes the specifi cations which apply over
the full operating temperature range, otherwise specifi cations are at T

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage I
VCM Output Tempco I
VCM Line Regulation 3.135V ≤ V

V

Output Resistance 1mA ≤ | I

CM

U

W

= 25°C. (Note 4)

A

= 0 1.15 1.25 1.35 V

OUT

= 0 +40

OUT

≤ 3.465V 1 mV/ V

DD

| ≤ 1mA 2 Ω

OUT

ppm/°C

UU

DIGITAL I PUTS A D DIGITAL OUTPUTS

The
full operating temperature range, otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC–)

VID Differential Input Voltage (Note 7) ● 0.2 V
V

ICM

Externally Set (Note 7) 1.2 3.0 V
R

Input Resistance (See Figure 2) 6 kΩ

IN

CIN Input Capacitance (Note 7) 3 pF
LOGIC INPUTS (DITH, PGA, SHDN, RAND)
VIH High Level Input Voltage VDD = 3.3V
VIL Low Level Input Voltage V
IIN Digital Input Current VIN = 0V to VDD ● ±10 µA
C

IN

LOGIC OUTPUTS (CMOS MODE)
OV

= 3.3V

DD

VOH High Level Output Voltage VDD = 3.3V IO = –10µA 3.299 V
I

VOL Low Level Output Voltage VDD = 3.3V IO = 160µA 0.01 V
I

I

SOURCE

I

SINK

OVDD = 2.5V
VOH High Level Output Voltage VDD = 3.3V IO = –200µA 2.49 V

Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V

V

OL

OVDD = 1.8V
VOH High Level Output Voltage VDD = 3.3V IO = –200µA 1.79 V
VOL Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V

LOGIC OUTPUTS (LVDS MODE)
STANDARD LVDS

VOD Differential Output Voltage 100Ω Differential Load
VOS Output Common Mode Voltage 100Ω Differential Load

LOW POWER LVDS

VOD Differential Ouptut Voltage 100Ω Differential Load
VOS Output Common Mode Voltage 100Ω Differential Load

Common Mode Input Voltage Internally Set 1.6 V

= 3.3V

DD

Digital Input Capacitance

Output Source Current
Output Sink Current

(Note 7) 1.5 pF

V

OUT

V

OUT

= 25°C. (Note 4)

A

= 0V – 50 mA
= 3.3V 50 mA

●

denotes the specifi cations which apply over the

●

2 V

●

0.8 V

= –200µA ● 3.1 3.29 V

O

= 1.6mA ● 0.10 0.4 V

O

●

247 350 454 mV

●

1.125 1.2 1.375 V

●

125 175 250 mV

●

1.125 1.2 1.375 V

2208fb

5

LTC2208

WU

POWER REQUIRE E TS

The
range, otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

DD

P

Shutdown Power SHDN = VDD 0.2 mW

SHDN

STANDARD LVDS OUTPUT MODE

OVDD Output Supply Voltage (Note 8)
I

Analog Supply Current

VDD

I

Output Supply Current

OVDD

P

Power Dissipation

DIS

LOW POWER LVDS OUTPUT MODE

OVDD Output Supply Voltage (Note 8)
I

Analog Supply Current

VDD

I

Output Supply Current

OVDD

P

Power Dissipation

DIS

CMOS OUTPUT MODE

OVDD Output Supply Voltage (Note 8)
I

Analog Supply Current

VDD

P

Power Dissipation

DIS

Analog Supply Voltage (Note 8)

= 25°C. AIN = –1dBFS. (Note 4)

A

●

denotes the specifi cations which apply over the full operating temperature

●

3.135 3.3 3.465 V

●

3 3.3 3.6 V

●

380 450 mA

●

74 90 mA

●

1498 1782 mW

●

3 3.3 3.6 V

●

380 450 mA

●

31 50 mA

●

1356 1650 mW

●

0.5 3.6 V

●

380 450 mA

●

1250 1485 mW

UW

TI I G CHARACTERISTICS

The
range, otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fS Sampling Frequency (Note 8)
tL ENC Low Time Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)
tH ENC High Time Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)
tAP Sample-and-Hold Aperture Delay –1 ns

LVDS OUTPUT MODE (STANDARD and LOW POWER)

tD ENC to DATA Delay (Note 7)
t

ENC to CLKOUT Delay (Note 7)

C

t

DATA to CLKOUT Skew (tC-tD) (Note 7)

SKEW

t

Output Rise Time 0.5 ns

RISE

t

Output Fall Time 0.5 ns

FALL

Data Latency Data Latency 7 Cycles

CMOS OUTPUT MODE

tD ENC to DATA Delay (Note 7)
tC ENC to CLKOUT Delay (Note 7)
t

DATA to CLKOUT Skew (tC-tD) (Note 7)

SKEW

Data Latency Data Latency Full Rate CMOS 7 Cycles
Demuxed 7 Cycles

= 25°C. (Note 4)

A

●

denotes the specifi cations which apply over the full operating temperature

●

1 130 MHz

●

3.65 3.846 1000 ns

●

2.6 3.846 1000 ns

●

3.65 3.846 1000 ns

●

2.6 3.846 1000 ns

●

1.3 2.5 3.8 ns

●

1.3 2.5 3.8 ns

●

–0.6 0 0.6 ns

●

1.3 2.7 4.0 ns

●

1.3 2.7 4.0 ns

●

–0.6 0 0.6 ns

6

2208fb

ELECTRICAL CHARACTERISTICS

LTC2208

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V

DD

, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V

Note 4: V
ENC

–

= 2V

= 3.3V, f

DD

sine wave with 1.6V common mode, input range = 2.25V

P-P

= 130MHz, LVDS outputs, differential ENC+/

SAMPLE

without latchup.

DD

P-P

with differential drive (PGA = 0), unless otherwise specifi ed.

UWW

TI I G DIAGRA

LVDS Output Mode Timing

All Outputs are Differential and Have LVDS Levels

t

ANALOG

INPUT

ENC

ENC

D0-D15, OF

AP

N

t

H

–

+

t

D

N + 1

t

L

N – 7 N – 6 N – 5 N – 4 N – 3

Note 5: Integral nonlinearity is defi ned as the deviation of a code from a “best
fi t straight line” to the transfer curve. The deviation is measured from the
center of the quantization band.

Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code fl ickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.

Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.

N + 4

N + 2

N + 3

CLKOUT

CLKOUT

t

+

–

C

2208 TD01

2208fb

7

LTC2208

3

WUW

TI I G DIAGRA S

ANALOG

INPUT

–

ENC

+

ENC

DA0-DA15, OFA

CLKOUTA

CLKOUTB

Full-Rate CMOS Output Mode Timing

All Outputs are Single-Ended and Have CMOS Levels

t

AP

N

t

H

t

D

t

C

N + 1

N + 2

t

L

N – 7 N – 6 N – 5 N – 4 N – 3

N + 3

N + 4

DB0-DB15, OFB

ANALOG

INPUT

ENC

ENC

DA0-DA15, OFA

DB0-DB15, OFB

CLKOUTA

CLKOUTB

HIGH IMPEDANCE

2208 TD02

Demultiplexed CMOS Output Mode Timing

All Outputs are Single-Ended and Have CMOS Levels

t

AP

N

t

H

–

+

t

D

t

D

t

C

N + 1

N + 2

t

L

N – 8 N – 6 N – 4

N – 7 N – 5 N – 3

N + 3

N + 4

2208 TD0

8

2208fb

TYPICAL PERFOR

LTC2208

UW
CE CHARACTERISTICSA

Integral Nonlinearity (INL) vs
Output Code

2

1.5

1

0.5

0

–0.5

INL ERROR (LSB)

–1

–1.5

–2

0

16384

128K Point FFT, f

32768

OUTPUT CODE

IN

–1dBFS, PGA = 0

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

10

0

30

20

FREQUENCY (MHz)

49152

& /

= 4.93MHz,

40

50

65536

60

2208 G15

Differential Nonlinearity (DNL) vs
Output Code

1

0.8

0.6

0.4

0.2

0

0.2

DNL ERROR (LSB)

0.4

0.6

0.8

1

0

16384

32768

OUTPUT CODE

64k Point FFT, fIN = 15.1MHz,
–1dBFS, PGA = 0

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

–130

0

20

10

FREQUENCY (MHz)

40

30

49152

50

2208 G02

60

2208 G03

65536

AC Grounded Input Histogram

10000

9000

8000

7000

6000

5000

COUNT

4000

3000

2000

1000

0

32736 32740 32744 32748 32752 32756

OUTPUT CODE

64k Point FFT, 15.1MHz, –20dBFS,
PGA = 0, Internal Dither “Off”

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0

20

10

FREQUENCY (MHz)

40

30

2208 G14

50

60

2208 G04

64k Point FFT, 15.1MHz, –20dBFS,
PGA = 0, Internal Dither “On”

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

–130

0

20

10

FREQUENCY (MHz)

40

30

32k Point 2-Tone FFT,

= 21.14 MHz and 14.25MHz,

f

IN

–7dBFS, PGA = 0

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

–120

50

60

2208 G05

0

20

10

FREQUENCY (MHz)

30

50

40

60

2208 G06

32k Point 2-Tone FFT,

= 20.14 MHz and 14.25MHz,

f

IN

–25dBFS, PGA = 0

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

–120

0

20

10

FREQUENCY (MHz)

30

50

40

60

2208 G07

2208fb

9

LTC2208

UW

TYPICAL PERFOR A CE CHARACTERISTICS

SFDR vs Input Level, fIN = 15MHz,
PGA = 0, Dither “Off”

140
130
120
110
100

90
80
70
60
50
40

SFDR (dBc AND dBFS)

30
20
10

0

–80

–60

–70

INPUT LEVEL (dBFS)

–50

–30

–40 0

128K Point FFT, fIN = 30.1 MHz,
–25dBFS, PGA = 0, Dither “On”

0
–10
–20
–30
–40
–50
–60
–70

–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

10

0

20

FREQUENCY (MHz)

40

30

–20 –10

50

2208 G08

60

2208 G17

SFDR vs Input Level, fIN = 15MHz,
PGA = 0, Dither “On”

140
130
120
110
100

90

80

70

60

50
40

SFDR (dBc AND dBFS)

30
20
10

0

–80

–60

–70

INPUT LEVEL (dBFS)

–50

–30

–40 0

64K Point FFT, fIN = 70.1 MHz,
–1dBFS, PGA = 0

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

10

0

20

FREQUENCY (MHz)

40

30

–20 –10

50

2208 G09

60

2208 G18

64K Point FFT, f

= 30.1 MHz,

IN

–1dBFS, PGA = 0

0
–10
–20
–30

–40
–50

–60

–70
–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

10

0

30

20

FREQUENCY (MHz)

64K Point FFT, fIN = 70.1 MHz,
–10dBFS, PGA = 0

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

10

0

30

20

FREQUENCY (MHz)

40

50

60

2208 G16

40

50

60

2208 G19

64K Point FFT, fIN = 70.1 MHz,
–20dBFS, PGA = 0

0
–10
–20
–30
–40
–50
–60
–70

–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

10

0

30

20

FREQUENCY (MHz)

10

128K Point FFT, fIN = 70.1 MHz,
–25dBFS, PGA = 0, Dither “On”

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

40

50

60

2208 G20

–130

10

0

20

FREQUENCY (MHz)

40

30

50

60

2208 G21

64K Point FFT, fIN = 70.1 MHz,
–1dBFS, PGA = 1

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

10

0

30

20

FREQUENCY (MHz)

40

50

60

2208 G22

2208fb

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2208

SFDR vs Input Level,

= 70.2MHz,

f

IN

PGA = 0, Dither “Off”

130

120

110

100

90

80

70

60

SFDR (dBc AND dBFS)

50

40

30

–80

–70 –50

–60

64K Point FFT, f

–40

INPUT LEVEL (dBFS)

IN

74.4 MHz, –15dBFS, PGA = 0

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

10

0

30

20

FREQUENCY (MHz)

SFDR vs Input Level,

= 140.2MHz,

f

IN

PGA = 1, Dither “Off”

130

120

110

100

90

80

70

60

SFDR (dBc AND dBFS)

50

40

30

–80

–70 –50

–60

–40

INPUT LEVEL (dBFS)

–10

–20

–30

2208 G28

= 67.2 MHz and

40

50

60

2208 G25

–10

–20

–30

2208 G30

130

120

110

100

SFDR (dBc AND dBFS)

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

–120

130

120

110

100

SFDR (dBc AND dBFS)

0

SFDR vs Input Level,

= 70.2MHz,

f

IN

PGA = 0, Dither “On”

90

80

70

60

50

40

30

–80

–70 –50

–60

–40

INPUT LEVEL (dBFS)

–30

–20

64K Point FFT, fIN = 140.1 MHz,
–1dBFS, PGA = 0

0

10

0

20

FREQUENCY (MHz)

40

30

SFDR vs Input Level,

= 140.2MHz,

f

IN

PGA = 1, Dither “On”

90

80

70

60

50

40

30

–80

–70 –50

–60

–40

INPUT LEVEL (dBFS)

–30

–20

64K Point FFT, fIN = 67.2 MHz and

74.4 MHz, –7dBFS, PGA = 0

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

–10

2208 G29

–130

0

10

0

20

FREQUENCY (MHz)

40

30

50

60

2208 G24

64K Point FFT, fIN = 140.1 MHz,
–1dBFS, PGA = 1

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

50

60

2208 G27

–120

10

0

20

FREQUENCY (MHz)

40

30

50

60

2208 G26

64K Point FFT, fIN = 170.1 MHz,
–1dBFS, PGA = 1

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

–10

2208 G31

0

–120

10

0

20

FREQUENCY (MHz)

40

30

50

60

2208 G34

2208fb

11

LTC2208

UW

TYPICAL PERFOR A CE CHARACTERISTICS

64K Point FFT, fIN = 250.1MHz,
–1dBFS, PGA = 1

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

–120

10

0

30

20

FREQUENCY (MHz)

64K Point FFT, fIN = 380MHz,
–10dBFS, PGA = 1

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

–120

10

0

30

20

FREQUENCY (MHz)

64K Point FFT, fIN = 250.1MHz,
–10dBFS, PGA = 1

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

40

50

60

2208 G36

–120

10

0

20

FREQUENCY (MHz)

40

30

50

60

2208 G37

SFDR (HD2 and HD3) vs
Input Frequency

105

100

95

90

85

SFDR (dBc)

80

75

70

40

50

60

2208 G39

65

0

PGA = 1

PGA = 0

100 200 400

INPUT FREQUENCY (MHz)

300

500

2208 G23

64K Point FFT, fIN = 380MHz,
–1dBFS, PGA = 1

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

–120

10

0

30

20

FREQUENCY (MHz)

SNR vs Input Frequency

78

77

76

75

74

SNR (dBFS)

73

72

71

70

0

PGA = 1

100 200 400

INPUT FREQUENCY (MHz)

40

PGA = 0

300

50

60

2208 G38

500

2208 G40

SNR and SFDR vs Sample Rate,

= 5MHz

f

IN

110

105

100

95

90

85

SNR AND SFDR (dBFS)

80

75

70

SFDR

SNR

25

0

50

100

75

SAMPLE RATE (Msps)

12

125

LIMIT

150

175

2208 G32

200

SNR and SFDR vs Supply
Voltage (VDD), f

110

105

100

95

90

85

SNR AND SFDR (dBFS)

80

75

70

2.8

3

SUPPLY VOLTAGE (V)

= 5MHz

IN

LOWER LIMIT

SFDR

UPPER LIMIT

SNR

3.2

3.4

& /!!

3.6

IV

DD

Wave, –1dBFS

420

400

380

360

IVDD (mA)

340

320

300

0

vs Sample Rate, 5MHz Sine

50 100 150

SAMPLE RATE (Msps)

2208 G13

2208fb

UW

TYPICAL PERFOR A CE CHARACTERISTICS

SNR and SFDR vs Duty Cycle

110

1.01

LTC2208

Normalized Full Scale vs
Temperature, Internal Reference,
5 Units

100

90

80

SFDR AND SNR (dBFS)

70

60

30

SNR DCS OFF
SNR DCS ON
SFDR DCS OFF
SFDR DCS ON

40

DUTY CYCLE (%)

50

Input Offset Voltage vs
Temperature, 5 Units

5

4

3

2

1

0

–1

–2

OFFSET VOLTAGE (mV)

–3

–4

–5

–20 0 20 40

–40

TEMPERATURE (°C)

Mid-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

FULL-SCALE ERROR (%)

–0.6

–0.8

–1.0

10050

0

TIME AFTER WAKE-UP OR CLOCK START (µs)

200150

250

300 350 450

60

60 80

400

& /

2208 G12

2208 G42

70

500

1.005

1

0.995

NORMALIZED FULL SCALE

0.99
–40

–20 0 20 40

TEMPERATURE (°C)

SFDR vs Analog Input Common
Mode Voltage, 10MHz and 70 MHz,
–1dBFS, PGA = 0

110

105

100

95

90

85

80

SFDR (dBc)

75

70

65

60

10MHz

70MHz

0.5

0.75

ANALOG INPUT COMMON MODE VOLTAGE (V)

1

1.25 1.5

Full-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock

5

4

3

2

1

0

–1

–2

FULL-SCALE ERROR (%)

–3

–4

–5

200100

0

TIME FROM WAKE-UP OR CLOCK START (μs)

400300

500

600 700 900

60 80

2208 G11

1.75

2208 G41

800

2208 G43

2

1000

2208fb

13

LTC2208

U

UU

PI FU CTIO S

For CMOS Mode. Full Rate or Demultiplexed

SENSE (Pin 1): Reference Mode Select and External

Reference Input. Tie SENSE to VDD to select the internal

2.5V bandgap reference. An external reference of 2.5V or

1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).

GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.

VCM (Pin 3): 1.25V Output. Optimum voltage for input com-

mon mode. Must be bypassed to ground with a minimum
of 2.2µF. Ceramic chip capacitors are recommended.

VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.
Bypass to GND with 1µF ceramic chip capacitors.

+

A

(Pin 8): Positive Differential Analog Input.

IN

–

A

(Pin 9): Negative Differential Analog Input.

IN

ENC+ (Pin 12): Positive Differential Encode Input. The

sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2kΩ resistor. Output
data can be latched on the rising edge of ENC+.

CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle
at the sample rate in full rate CMOS mode or at 1/2 the
sample rate in demultiplexed mode. Latch the data on the
falling edge of CLKOUTB.

CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA
will toggle at the sample rate in full rate CMOS mode or
at 1/2 the sample rate in demultiplexed mode. Latch the
data on the rising edge of CLKOUTA.

DA0-DA15 (Pins 42-48 and 51-59): Digital Outputs, A Bus.
DA15 is the MSB. Output bus for full rate CMOS mode
and demultiplexed mode.

OFA (Pin 60): Over/Under Flow Digital Output for the A
Bus. OFA is high when an over or under fl ow has occurred
on the A bus.

LVDS (Pin 61): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3V
LVDS to 2/3V
ing LVDS to V

selects demultiplexed CMOS mode. Connecting

DD

selects Low Power LVDS mode. Connect-

DD

selects Standard LVDS mode.

DD

ENC– (Pin 13): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC
Internally biased to 1.6V through a 6.2kΩ resistor. By­pass to ground with a 0.1µF capacitor for a single-ended
Encode signal.

SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.

DITH (Pin 20): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal
dither. Refer to Internal Dither section of this data sheet
for details on dither operation.

DB0-DB15 (Pins 21-30 and 33-38): Digital Outputs, B Bus.
DB15 is the MSB. Active in demultiplexed mode. The B
bus is in high impedance state in full rate CMOS.

OGND (Pins 31 and 50): Output Driver Ground.

OVDD (Pins 32 and 49): Positive Supply for the Output

Drivers. Bypass to ground with 1µF capacitor.

OFB (Pin 39): Over/Under Flow Digital Output for the B Bus.
OFB is high when an over or under fl ow has occurred on the
B bus. At high impedance state in full rate CMOS mode.

–

.

MODE (Pin 62): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3V
binary output format and enables the clock duty cycle sta­bilizer. Connecting MODE to 2/3V
output format and enables the clock duty cycle stabilizer.
Connecting MODE to V
format and disables the clock duty cycle stabilizer.

RAND (Pin 63): Digital Output Randomization Selection
Pin. RAND low results in normal operation. RAND high
selects D1-D15 to be EXCLUSIVE-ORed with D0 (the
LSB). The output can be decoded by again applying an
XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.

PGA (Pin 64): Programmable Gain Amplifi er Control Pin. Low
selects a front-end gain of 1, input range of 2.25V
selects a front-end gain of 1.5, input range of 1.5V

GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package must be soldered to
ground.

selects 2’s complement output

DD

selects 2’s complement

DD

selects offset

DD

P-P

P-P

. High

.

2208fb

14

LTC2208

U

UU

PI FU CTIO S

For LVDS Mode. STANDARD or LOW POWER

SENSE (Pin 1): Reference Mode Select and External

Reference Input. Tie SENSE to V

2.5V bandgap reference. An external reference of 2.5V or

1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).

GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.

(Pin 3): 1.25V Output. Optimum voltage for input com-

V

CM

mon mode. Must be bypassed to ground with a minimum
of 2.2µF. Ceramic chip capacitors are recommended.

(Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.

V

DD

Bypass to GND with 1µF ceramic chip capacitors.

+

(Pin 8): Positive Differential Analog Input.

A

IN

–

(Pin 9): Negative Differential Analog Input.

A

IN

+

(Pin 12): Positive Differential Encode Input. The

ENC

sampled analog input is held on the rising edge of ENC
Internally biased to 1.6V through a 6.2kΩ resistor. Output
data can be latched on the rising edge of ENC

–

(Pin 13): Negative Differential Encode Input. The

ENC

sampled analog input is held on the falling edge of ENC
Internally biased to 1.6V through a 6.2kΩ resistor. By­pass to ground with a 0.1µF capacitor for a single-ended
Encode signal.

SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are set in
high impedance state.

DITH (Pin 20): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of the data sheet for details
on dither operation.

–

/D0+ to D15–/D15+ (Pins 21-30, 33-38, 41-48 and

D0
51-58): LVDS Digital Outputs. All LVDS outputs require

differential 100Ω termination resistors at the LVDS receiver.

+

/D15– is the MSB.

D15

to select the internal

DD

+

.

+

.

–

.

OGND (Pins 31 and 50): Output Driver Ground.

(Pins 32 and 49): Positive Supply for the Output

OV

DD

Drivers. Bypass to ground with 0.1µF capacitor.

–

CLKOUT

0utput. Latch data on the rising edge of CLKOUT
edge of CLKOUT

OF

/CLKOUT+ (Pins 39 and 40): LVDS Data Valid

+

–

.

–

/OF+ (Pins 59 and 60): Over/Under Flow Digital Output

, falling

OF is high when an over or under fl ow has occurred.

LVDS (Pin 61): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3V
LVDS to 2/3V
ing LVDS to V

selects demultiplexed CMOS mode. Connecting

DD

selects Low Power LVDS mode. Connect-

DD

selects Standard LVDS mode.

DD

MODE (Pin 62): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3V

selects offset

DD

binary output format and enables the clock duty cycle sta­bilizer. Connecting MODE to 2/3V

selects 2’s complement

DD

output format and enables the clock duty cycle stabilizer.
Connecting MODE to V

selects 2’s complement output

DD

format and disables the clock duty cycle stabilizer.

RAND (Pin 63): Digital Output Randomization Selection Pin.
RAND low results in normal operation. RAND high selects
D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The
output can be decoded by again applying an XOR operation
between the LSB and all other bits. The mode of operation
reduces the effects of digital output interference.

PGA (Pin 64): Programmable Gain Amplifi er Control Pin. Low
selects a front-end gain of 1, input range of 2.25V
selects a front-end gain of 1.5, input range of 1.5V

P-P

. High

.

P-P

GND (Exposed Pad Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package must be sol­dered to ground.

2208fb

15

LTC2208

–

BLOCK DIAGRA

+

A

IN

INPUT

S/H

–

A

IN

DITHER
SIGNAL

GENERATOR

FIRST PIPELINED

ADC STAGE

W

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

CORRECTION LOGIC

AND

SHIFT REGISTER

V

GND

DD

SENSE

V

CM

BUFFER

RANGE

SELECT

VOLTAGE

REFERENCE

PGA

ADC CLOCKS

ADC
REFERENCE

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

+

ENC

ENC

–

PGA RAND

Figure 1. Functional Block Diagram

CONTROL

LOGIC

OV

DD

CLKOUT+
CLKOUT

+

OF

–

OF

+

2208 F01

D15

–

D15

•

•

•

+

D0

–

D0

OUTPUT

DRIVERS

DITHM0DE

LVD SSHDN

OGND

16

2208fb

OPERATIO

LTC2208

U

DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band lim­ited to frequencies above DC to below half the sampling
frequency.

Signal-to-Noise Ratio

The signal-to-noise (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components, except the
fi rst fi ve harmonics.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:

(

THD = –20Log

where V1 is the RMS amplitude of the fundamental fre­quency and V
through nth harmonics.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to

IMD is the change in one sinusoidal input caused

THD.
by the presence of another sinusoidal input at a different
frequency.

√⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯(⎯⎯⎯⎯⎯⎯⎯⎯V⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯2⎯⎯⎯⎯⎯⎯⎯⎯2⎯⎯⎯⎯⎯⎯⎯⎯ ⎯⎯⎯⎯⎯⎯⎯⎯+⎯⎯⎯⎯⎯⎯⎯⎯ ⎯⎯⎯⎯⎯⎯⎯⎯V⎯⎯⎯⎯⎯⎯⎯⎯3⎯⎯⎯⎯⎯⎯⎯⎯

through VN are the amplitudes of the second

2

2

⎯⎯⎯⎯⎯⎯⎯⎯+ ⎯⎯⎯⎯⎯⎯⎯⎯V⎯⎯⎯⎯⎯⎯⎯⎯4⎯⎯⎯⎯⎯⎯⎯⎯2⎯⎯⎯⎯⎯⎯⎯⎯ ⎯⎯⎯⎯⎯⎯⎯⎯+⎯⎯⎯⎯⎯⎯⎯⎯ ⎯⎯⎯⎯⎯⎯⎯⎯.⎯⎯⎯⎯⎯⎯⎯⎯.⎯⎯⎯⎯⎯⎯⎯⎯.⎯⎯⎯⎯⎯⎯⎯⎯ ⎯⎯⎯⎯⎯⎯⎯⎯V⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯N⎯⎯⎯⎯⎯⎯⎯

2

)/V

)

1

If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3rd order IMD terms include (2fa + fb),
(fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is
defi ned as the ration of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.

Spurious Free Dynamic Range (SFDR)

The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.

Full Power Bandwidth

The Full Power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.

Aperture Delay Time

+

The time from when a rising ENC
to the instant that the input signal is held by the sample­and-hold circuit.

Aperture Delay Jitter

The variation in the aperture delay time from convertion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:

SNR

= –20log (2π • f

JITTER

equals the ENC– voltage

IN

• t

JITTER

)

2208fb

17

LTC2208

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APPLICATIO S I FOR ATIO

CONVERTER OPERATION

The LTC2208 is a CMOS pipelined multistep converter
with a front-end PGA. As shown in Figure 1, the converter
has fi ve pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.

The LTC2208 has two phases of operation, determined
by the state of the differential ENC
brevity, the text will refer to ENC
ENC high and ENC

+

less than ENC– as ENC low.

+

/ENC– input pins. For

+

greater than ENC– as

Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplifi er. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplifi ed and
output by the residue amplifi er. Successive stages oper­ate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2208 CMOS
differential sample and hold. The differential analog inputs
are sampled directly onto sampling capacitors (C

SAMPLE

)
through NMOS transitors. The capacitors shown attached
to each input (C

PARASITIC

) are the summation of all other

capacitance associated with each input.

During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions for high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the

When ENC is low, the analog input is sampled differen­tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplifi er which
drives the fi rst pipelined ADC stage. The fi rst stage acquires
the output of the S/H amplifi er during the high phase of
ENC. When ENC goes back low, the fi rst stage produces
its residue which is acquired by the second stage. At
the same time, the input S/H goes back to acquiring the
analog input. When ENC goes high, the second stage
produces its residue which is acquired by the third stage.
An identical process is repeated for the third and fourth
stages, resulting in a fourth stage residue that is sent to
the fi fth stage for fi nal evaluation.

Each ADC stage following the fi rst has additional range to
accommodate fl ash and amplifi er offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.

A

A

ENC

ENC

LTC2208

V

DD

+

IN

V

DD

–

IN

V

DD

1.6V

6k

+

–

6k

1.6V

Figure 2. Equivalent Input Circuit

C

PARASITIC

1.8pF

C

PARASITIC

1.8pF

C

SAMPLE

4.9pF

C

SAMPLE

4.9pF

2208 F02

2208fb

18

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APPLICATIO S I FOR ATIO

LTC2208

input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.

Common Mode Bias

The ADC sample-and-hold circuit requires differential
drive to achieve specifi ed performance. Each input should
swing ± 0.5625V for the 2.25V range (PGA = 0) or ±0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The VCM output pin (Pin 3) is designed
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with 2.2µF or greater.

Input Drive Impedence

As with all high performance, high speed ADCs the dy­namic performance of the LTC2208 can be infl uenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can infl uence SFDR. At the falling edge of ENC the
sample and hold circuit will connect the 4.9pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally, the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F encode); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.

For the best performance it is recommended to have a
source impedence of 100Ω or less for each input. The
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.

INPUT DRIVE CIRCUITS

Input Filtering

A fi rst order RC low pass fi lter at the input of the ADC can
serve two functions: limit the noise from input circuitry and

provide isolation from ADC S/H switching. The LTC2208
has a very broadband S/H circuit, DC to 700MHz; it can
be used in a wide range of applications; therefore, it is not
possible to provide a single recommended RC fi lter.

Figures 3, 4a and 4b show three examples of input RC
fi ltering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated—this will help suppress random noise as well
as noise coupled from the digital circuitry. The LTC2208
does not require any input fi lter to achieve data sheet
specifi cations; however, no fi ltering will put more stringent
noise requirements on the input drive circuitry.

Transformer Coupled Circuits

Figure 3 shows the LTC2208 being driven by an RF trans­former with a center-tapped secondary. The secondary
center tap is DC biased with V

, setting the ADC input

CM

signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used; however,
as the turns ratio increases so does the impedance seen by
the ADC. Source impedance greater than 50Ω can reduce

the input bandwidth and increase high frequency distor­tion. A disadvantage of using a transformer is the loss of
low frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.

Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.

V

CM

35Ω

35Ω

2.2µF

8.2pF

8.2pF

8.2pF

5Ω

5Ω

+

A

IN

LTC2208

–

A

IN

2208 F03

2208fb

5Ω

10Ω

T1

0.1µF

10Ω

T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2µF

Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 5MHz to 100MHz

19

LTC2208

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APPLICATIO S I FOR ATIO

Figure 4a shows transformer coupling using a transmis­sion line balun transformer. This type of transformer has
much better high frequency response and balance than
fl ux coupled center tap transformers. Coupling capacitors
are added at the ground and input primary terminals to
allow the secondary terminals to be biased at 1.25V. Figure
4b shows the same circuit with components suitable for
higher input frequencies.

V

CM

2.2µF

ANALOG

INPUT

0.1µF

T1

1:1

0.1µF

T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2µF

25Ω

25Ω

0.1µF

4.7pF

5Ω

4.7pF

5Ω

4.7pF

+

A

IN

LTC2208

–

A

IN

2208 F04a

Figure 4a. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 100MHz to 250MHz

V

CM

2.2µF

ANALOG

INPUT

0.1µF

T1

1:1

0.1µF

T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2µF

25Ω

25Ω

0.1µF

2.2pF

2.2pF

5Ω

5Ω

+

A

IN

LTC2208

–

A

IN

2208 F04b

Figure 4b. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 250MHz to 500MHz

Direct Coupled Circuits

Figure 5 demonstrates the use of a differential amplifi er to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of any op amp or closed-loop amplifi er will de­grade the ADC SFDR at high input frequencies. Additionally,
wideband op amps or differential amplifi ers tend to have
high noise. As a result, the SNR will be degraded unless
the noise bandwidth is limited prior to the ADC input.

Reference Operation

Figure 6 shows the LTC2208 reference circuitry consisting
of a 2.5V bandgap reference, a programmable gain ampli­fi er and control circuit. The LTC2208 has three modes of

V

CM

2.2µF

12pF

12pF

+

A

IN

LTC2208

–

A

IN

2208 F05

ANALOG

INPUT

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

+

+

CM

–

–

AMPLIFIER = LTC6600-20,
LTC1993, ETC.

Figure 5. DC Coupled Input with Differential Amplifi er

reference operation: Internal Reference, 1.25V external
reference or 2.5V external reference. To use the internal
reference, tie the SENSE pin to V

. To use an external

DD

reference, simply apply either a 1.25V or 2.5V reference
voltage to the SENSE input pin. Both 1.25V and 2.5V applied
to SENSE will result in a full scale range of 2.25V
= 0). A 1.25V output, V

is provided for a common mode

CM

P-P

(PGA

bias for input drive circuitry. An external bypass capacitor is
required for the V

output. This provides a high frequency

CM

low impedance path to ground for internal and external
circuitry. This is also the compensation capacitor for the
reference; it will not be stable without this capacitor. The
minimum value required for stability is 2.2µF.

RANGE

SELECT

BUFFER

AND GAIN
CONTROL

INTERNAL

ADC

REFERENCE

PGA

2.5V

BANDGAP

REFERENCE

1.25V

2208 F06

2208fb

TIE TO VDD TO USE

INTERNAL 2.5V

REFERENCE

OR INPUT FOR

EXTERNAL 2.5V

REFERENCE

OR INPUT FOR

EXTERNAL 1.25V

REFERENCE

SENSE

V

CM

2.2µF

Figure 6. Reference Circuit

20

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APPLICATIO S I FOR ATIO

LTC2208

The internal programmable gain amplifi er provides the
internal reference voltage for the ADC. This amplifi er has
very stringent settling requirements and is not accessible
for external use.

The SENSE pin can be driven ±5% around the nominal 2.5V
or 1.25V external reference inputs. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
SENSE pin should be tied to V

as close to the converter

DD

as possible. If the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with 1µF ceramic capacitor.

V

CM

2.2µF

SENSE

2.2µF

LTC2208

2208 F07

3.3V

1µF

1.25V

2

LTC1461-2.5

6

4

Figure 7. A 2.25V Range ADC with
an External 2.5V Reference

PGA Pin

The PGA pin selects between two gain settings for the ADC
front-end. PGA = 0 selects an input range of 2.25V
PGA = 1 selects an input range of 1.5V

. The 2.25V input

P-P

P-P

;

range has the best SNR; however, the distortion will be
higher for input frequencies above 100MHz. For applica­tions with high input frequencies, the low input range will
have improved distortion; however, the SNR will be 1.8dB
worse. See the typical performance curves section.

In applications where jitter is critical (high input frequen­cies), take the following into consideration:

1. Differential drive should be used.

2. Use as large an amplitude possible. If using trans-

former coupling, use a higher turns ratio to increase the
amplitude.

3. If the ADC is clocked with a fi xed frequency sinusoidal

signal, fi lter the encode signal to reduce wideband
noise.

4. Balance the capacitance and series resistance at both

encode inputs such that any coupled noise will appear
at both inputs as common mode noise.

The encode inputs have a common mode range of 1.2V

. Each input may be driven from ground to VDD for

to V

DD

single-ended drive.

V

LTC2208

1.6V

V

DD

+

ENC

V

–

ENC

Figure 8a. Equivalent Encode Input Circuit

DD

TO INTERNAL

ADC CLOCK

DRIVERS

6k

1.6V

DD

6k

2208 F08a

Driving the Encode Inputs

The noise performance of the LTC2208 can depend on
the encode signal quality as much as for the analog input.
The encode inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a

1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.

Any noise present on the encode signal will result in ad­ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.

0.1µF

0.1µF

T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE

T1

50Ω

8.2pF

50Ω

0.1µF

ENC

100Ω

ENC

Figure 8b. Transformer Driven Encode

+

LTC2208

–

2208 F08b

2208fb

21

LTC2208

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APPLICATIO S I FOR ATIO

+

1.6V

3.3V

ENC

ENC

–

ENC

ENC

LTC2208

+

–

2208 F09

LTC2208

2208 F10

V

THRESHOLD

MC100LVELT22

Figure 10. ENC Drive Using a CMOS to PECL Translator

= 1.6V

0.1µF

Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter

3.3V

Q0

D0

Q0

Maximum and Minimum Encode Rates

The maximum encode rate for the LTC2208 is 130Msps.
For the ADC to operate properly the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 3.65ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS. When using a single-ended ENCODE
signal asymmetric rise and fall times can result in duty
cycles that are far from 50%.

An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3V

or 2/3VDD using external resistors.

DD

The lower limit of the LTC2208 sample rate is determined
by droop of the sample and hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specifi ed minimum operating frequency
for the LTC2208 is 1Msps.

DIGITAL OUTPUTS

Digital Output Modes

The LTC2208 can operate in four digital output modes:
standard LVDS, low power LVDS, full rate CMOS, and
demultiplexed CMOS. The LVDS pin selects the mode of
operation. This pin has a four level logic input, centered at
0, 1/3V
be used to set the 1/3V

, 2/3VDD and VDD. An external resistor divider can

DD

and 2/3VDD logic levels. Table 1

DD

shows the logic states for the LVDS pin.

Table 1. LVDS Pin Function

LVDS Digital Output Mode

0V(GND)
1/3V
2/3VDD Low Power LVDS
VDD LVDS

Demultiplexed CMOS

DD

Full-Rate CMOS

Digital Output Buffers (CMOS Modes)

Figure 11 shows an equivalent circuit for a single output
buffer in CMOS Mode, Full-Rate or Demultiplexed. Each
buffer is powered by OV

and OGND, isolated from the

DD

ADC power and ground. The additional N-channel transistor
in the output driver allows operation down to low voltages.
The internal resistor in series with the output makes the
output appear as 50Ω to external circuitry and eliminates

the need for external damping resistors.

As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2208 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as a ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the

2208fb

22

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APPLICATIO S I FOR ATIO

LTC2208

output may be used but is not required since the ADC has
a series resistor of 43Ω on chip.

Lower OV

voltages will also help reduce interference

DD

from the digital outputs.

LTC2208

DATA

FROM

LATCH

V

DD

PREDRIVER

LOGIC

V

DD

OV

DD

Figure 11. Equivalent Circuit for a Digital Output Buffer

2208 F11

OV

DD

OGND

0.5V
TO 3.6V

0.1µF

TYPICAL
DATA
OUTPUT

Digital Output Buffers (LVDS Modes)

Figure 12 shows an equivalent circuit for an LVDS output

+

pair. A 3.5mA current is steered from OUT

to OUT– or

vice versa, which creates a ±350mV differential voltage
across the 100Ω termination resistor at the LVDS receiver.
A feedback loop regulates the common mode output volt­age to 1.20V. For proper operation each LVDS output pair
must be terminated with an external 100Ω termination

LTC2208

3.5mA

V

DD

V

DD

resistor, even if the signal is not used (such as OF+/OF– or

+

CLKOUT

/CLKOUT–). To minimize noise the PC board
traces for each LVDS output pair should be routed close
together. To minimize clock skew all LVDS PC board traces
should have about the same length.

In Low Power LVDS Mode 1.75mA is steered between
the differential outputs, resulting in ±175mV at the LVDS
receiver’s 100Ω termination resistor. The output com-

mon mode voltage is 1.20V, the same as standard LVDS
Mode.

Data Format

The LTC2208 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. This pin has a four level

logic input, centered at 0, 1/3V
external resistor divider can be user to set the 1/3V
and 2/3V

logic levels. Table 2 shows the logic states

DD

, 2/3VDD and VDD. An

DD

DD

for the MODE pin.

Table 2. MODE Pin Function

Clock Duty
MODE Output Format Cycle Stabilizer

0(GND)
1/3VDD Offset Binary On
2/3VDD 2’s Complement On
V

2’s Complement Off

DD

OV

DD

Offset Binary Off

OV

DD

3.3V

0.1µF

DATA

FROM

LATCH

PREDRIVER

LOGIC

10k 10k

+

1.20V

–

Figure 12. Equivalent Output Buffer in LVDS Mode

OV

43Ω

DD

100Ω

43Ω

OGND

2208 F12

LVDS

RECEIVER

2208fb

23

LTC2208

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APPLICATIO S I FOR ATIO

Overfl ow Bit

An overfl ow output bit (OF) indicates when the converter
is over-ranged or under-ranged. In CMOS mode, a logic
high on the OFA pin indicates an overfl ow or underfl ow on
the A data bus, while a logic high on the OFB pin indicates
an overfl ow on the B data bus. In LVDS mode, a differ-

+

ential logic high on OF

/OF– pins indicates an overfl ow

or underfl ow.

Output Clock

The ADC has a delayed version of the encode input avail­able as a digital output, CLKOUT. The CLKOUT pin can
be used to synchronize the converter data to the digital
system. This is necessary when using a sinusoidal en­code. In both CMOS modes, A bus data will be updated
as CLKOUTA falls and CLKOUTB rises. In demultiplexed
CMOS mode the B bus data will be updated as CLKOUTA
falls and CLKOUTB rises.

In Full Rate CMOS Mode, only the A data bus is active;
data may be latched on the rising edge of CLKOUTA or
the falling edge of CLKOUTB.

In demultiplexed CMOS mode CLKOUTA and CLKOUTB
will toggle at 1/2 the frequency of the encode signal. Both
the A bus and the B bus may be latched on the rising edge
of CLKOUTA or the falling edge of CLKOUTB.

Digital Output Randomizer

LSB and all other bits. The LSB, OF and CLKOUT output
are not affected. The output Randomizer function is active
when the RAND pin is high.

CLKOUT

OF

D15

D14

CLKOUT

OF

D15/D0

D14/D0

•

•

D2

D1

RAND = HIGH,

SCRAMBLE

ENABLED

Figure 13. Functional Equivalent of Digital Output Randomizer

RAND

•

D2/D0

D1/D0

D0D0

2208 F13

Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
off chip, these unwanted tones can be randomized, trading
a slight increase in the noise fl oor for a large reduction in
unwanted tone amplitude.

The digital output is “Randomized” by applying an exclu­sive-OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the

24

Output Driver Power

Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV

, should be tied

DD

to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered
by a 1.8V supply, then OV

1.8V supply. In CMOS mode OV

should be tied to that same

DD

can be powered with

DD

any logic voltage up to the 3.6V. OGND can be powered
with any voltage from ground up to 1V and must be less
than OV
and OV

. The logic outputs will swing between OGND

DD

. In LVDS Mode, OVDD should be connected to

DD

a 3.3V supply and OGND should be connected to GND.

2208fb

WUUU

APPLICATIO S I FOR ATIO

LTC2208

PC BOARD

LTC2208

CLKOUT

OF

D15/D0

D14/D0

D2/D0

D1/D0

D0

FPGA

Internal Dither

The LTC2208 is a 16-bit ADC with a very linear transfer
function; however, at low input levels even slight imper fec­tions in the transfer function will result in unwanted tones.
Small errors in the transfer function are usually a result
of ADC element mismatches. An optional internal dither
mode can be enabled to randomize the input location on

D15

the ADC transfer curve, resulting in improved SFDR for
low signal levels.

D14

•

•

•

D2

As shown in Figure 15, the output of the sample-and-hold
amplifi er is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the

D1

dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The dither
DAC is calibrated to result in less than 0.5dB elevation in

D0

the noise fl oor of the ADC, as compared to the noise fl oor
with dither off.

2208 F14

Figure 14. Descrambling a Scrambled Digital Output

LTC2208

+

AIN

ANALOG

INPUT

AIN

–

S/H

AMP

CLOCK/DUTY

CYCLE

CONTROL

+–

ENC

ENC

Figure 15. Functional Equivalent Block Diagram of Internal Dither Circuit

16-BIT
PIPELINED
ADC CORE

PRECISION

DAC

DIGITAL

SUMMATION

OUTPUT

DRIVERS

MULTIBIT DEEP

PSEUDO-RANDOM

NUMBER

GENERATOR

DITH

DITHER ENABLE

HIGH = DITHER ON

LOW = DITHER OFF

CLKOUT

OF

D15

•

•

•

D0

2208 F15

2208fb

25

LTC2208

U

WUU

S I FOR ATIOAPPLICATIO

Grounding and Bypassing

The LTC2208 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTC2208 has been optimized for a fl owthrough layout so
that the interaction between inputs and digital outputs is
minimized. Layout for the printed circuit board should

ensure that digital and analog signal lines are separated
as much as possible. In particular, care should be taken
not to run any digital track alongside an analog signal
track or underneath the ADC.

High quality ceramic bypass capacitors should be used
at the V
be located as close to the pins as possible. The traces

DD, VCM

, and OVDD pins. Bypass capacitors must

connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.

The LTC2208 differential inputs should run parallel and
close to each other. The input traces should be as short
as possible to minimize capacitance and to minimize
noise pickup.

Heat Transfer

Most of the heat generated by the LTC2208 is transferred
from the die through the bottom-side exposed pad. For
good electrical and thermal performance, the exposed
pad must be soldered to a large grounded pad on the PC
board. It is critical that the exposed pad and all ground
pins are connected to a ground plane of suffi cient area
with as many vias as possible.

26

2208fb

LTC2208

U

WUU

S I FOR ATIOAPPLICATIO

Layer 1 Component Side Layer 2 GND Plane

2208fb

27

LTC2208

U

WUU

S I FOR ATIOAPPLICATIO

Layer 3 GND Layer 4 GND

28

2208fb

LTC2208

U

WUU

S I FOR ATIOAPPLICATIO

Layer 5 GND Layer 6 Bottom Side

2208fb

29

LTC2208

U

WUU

S I FOR ATIOAPPLICATIO

R26

R25

4990Ω

4990Ω

R29

4990Ω

3.3V

1357911131517192123252729313335373941434547495153

J1E J1O

246

8

1012141618202224262830323436384042444648505254

MEC8-150-02-L-D-EDGE_CONNRE-DIM

54443424140393835343332313029

VC5

48

VC4

47

VC3

26

VC2

25

VC1

12

3.3V
EN12

3

246

ON

OFF

J4

VDD

GND

135

CC

V

C25

0.1µF

C26

0.1µF

EN34

222746

R3

R37

C16

EN58

DNP

100Ω

0.1µF

EN78ENI1N

13

R17

R16

100Ω

C18

OPT

C19

O1P

O2P

O1N

O2N

I1P

I2N

45678

100Ω

R18

100Ω

OPT

O3P

O4P

O3N

O4N

U3

FIN1108

I2P

I3N

I3P

I4N

I4P

9

101114151617181920

R20

100Ω

R19

100Ω

O5P

O5N

I5N

I5P

R22

100Ω

R21

100Ω

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

28

VE5

O6P

O7P

O6N

O7N

I6N

I6P

I7N

R23

100Ω

484746454443424140393837363534

D11+

D11–

OVDD49

OGND50

D12–

D12+

D13–

D13+

D14–

D14+

D15–

D15+

OF–

OF+

LVDS

MODE

RAND

PGA

SENSE

GND2

123456789

37

O8P

O8N

VE4

36

VE3

23

VE2

2

VE1

1

I7P

I8N

I8P

21

R30

100Ω

D9+

D9–

D8+

D10+

D10–

VCM

GND

VDD5

VDD6

GND7

5557596163656769717375777981838587899193959799

565860626466687072747678808284868890929496

VC5

48

VC4

47

VC3

26

VC2

25

VC1

12

3.3V
EN12

EN34

EN58

EN78ENI1N

3

222746

13

R31

33

D8–

D7+

D7–

D8+

D8–

D5+

ENCP

ENCN

GND14

VDD15

D5–

VDD16

CLKOUT–

CLKCOUT+

U2

LTC2208IUP

AINP

AINN

GND10

GND11

10111213141516

98

100

454443424140393835343332313029

O1P

O2P

O3P

O4P

O5P

O6P

O1N

O2N

I1P

I2N

I2P

45678

100Ω

R32

100Ω

65

OVDD32

32

OGND31

31

D4+

30

D4–

29

D3+

27

D3–

27

D2+

26

D2–

25

D1+

24

D1–

23

D0+

22

D0–

21

DITH

20

SHDN

19

GND18

18

VDD17

17

O3N

O4N

U4

FIN1108

I3N

I3P

I4N

I4P

9

101114151617181920

R35

100Ω

R34

100Ω

R33

100Ω

O7P

O5N

O6N

O7N

I5N

I5P

I6N

I6P

I7N

I7P

R40

R39

100Ω

R38

100Ω

R7

1000Ω

R24

100k

28

VE5

37

O8P

O8N

VE4

36

VE3

23

VE2

2

VE1

1

I8N

I8P

21

100Ω

3.3V

C20

0.1µF

65732

C27

0.1µF
6CL

6DA

U1

24LC02ST

8

VCC

C29

C28

0.1µF

C36

0.1µF

C35

0.1µF

C34

0.1µF

C38

R43

C24

FERRITE BEAD

C22

0.1µF
R42

C14

FERRITE BEAD

876

R41

100Ω

U5

FIN1101K8X

123

WP

ARRAY

0.1µF

4.7µF

4.7µF

4.7µF

RIN+

RIN–

A2A1A0

EEPROM

C30

0.1µF

VCC

DOUT+

GNDENGND

2208 F16

1

4

GND

C31

0.1µF

C32

0.1µF

5

DOUT–

C15

0.1µF

4

30

8.2pF

246

ON

OFF

DITHER

J3

CC

SHDN

RUN

V

135

CC

R4

V

5.1Ω

C3

0.01µF

C1

0.01µF

C8

4.7pF

R28

R27

10Ω

10Ω

R11

33.2Ω

R12

33.2Ω

R9

10Ω

T1

L1

R45

86.6Ω

C6

0.01µF

J5

••

T2

000000

••

MABA-007159-

56nH

AIN

R10

10Ω

R15

100Ω

C7

0.01µF

R44

C10

86.6Ω

8.2pF

R36

86.6Ω

C8

8.2pF

R14

1000Ω

R13

TP1

C17

2.2µF

EXT REF

100Ω

R5

C4

5.1Ω

R2

49.9ΩR149.9Ω

••

T3

ETC1-1-13

C2

0.01µF

J7

CLOCK

ENCODE

C13

2.2µF

C12

0.1µF

C5

0.01µF

246

R8

VDD

GND

CONNECTOR

GND

1000Ω

T2

WBC1-1LB

WBC1-1LB

MABAES0060

MABAES0060

86.6

43.2

86.6

56nH

8.2pF

DC996B-A LTC2208IUP 16 4.7pF 86.6

18nH

3.9pF

DC996B-B LTC2208IUP 16 1.8pF 182

56nH

8.2pF

DC996B-C LTC2208IUP-14 14 4.7pF 86.6

43.2

18nH 182

3.9pF

DC996B-D LTC2208IUP-14 14 1.8pF

2208fb

R36, 44

L1

C9-10

U2 BITS C8 R45

ASSEMBLY

* VERSION TABLE

J2 MODE

R6 1000Ω

135

CC

V

246

J9

AUX PWR

135

TP5

TP2

3.3V

PWR

PACKAGE DESCRIPTIO

LTC2208

U

UP Package

64-Lead Plastic QFN (9mm × 9mm)

(Reference LTC DWG # 05-08-1705)

0.70 ±0.05

7.15 ±0.05

7.15 ±0.05

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

9 .00 ± 0.10

(4 SIDES)

PIN 1 TOP MARK
(SEE NOTE 5)

7.50 REF

(4 SIDES)

8.10 ±0.05 9.50 ±0.05

PACKAGE OUTLINE

0.75 ± 0.05

R = 0.10

TYP

7.50 REF

(4-SIDES)

R = 0.115

7.15 ± 0.10

TYP

PIN 1

CHAMFER

C = 0.35

6463

0.40 ± 0.10

1
2

0.200 REF

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

6. DRAWING NOT TO SCALE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.00 – 0.05

7.15 ± 0.10

(UP64) QFN 0406 REV C

0.25 ± 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

2208fb

31

LTC2208

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1747 12-Bit, 80MSPS ADC 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
LTC1748 14-Bit, 80Msps ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1749 12-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 87dB SFDR
LTC1750 14-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR
LT1993 High Speed Differential Op Amp 600MHz BW, 75dBc Distortion at 70MHz
LTC2202 16-Bit, 10MSPS ADC 150mW, 81.6dB SNR, 100dB SFDR
LTC2203 16-Bit, 25MSPS ADC 230mW, 81.6dB SNR, 100dB SFDR
LTC2204 16-Bit, 40Msps ADC 470mW, 79dB SNR, 100dB SFDR
LTC2205 16-Bit, 65Msps ADC 530mW, 79dB SNR, 100dB SFDR
LTC2206 16-Bit, 80Msps ADC 725mW, 77.9dB SNR, 100dB SFDR
LTC2207 16-Bit, 105Msps ADC 900mW, 77.9dB SNR, 100dB SFDR
LTC2208 16-Bit, 130Msps ADC 1250mW, 77.7dB SNR, 100dB SFDR
LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm x 9mm QFN Package
LTC2220-1 12-Bit, 185Msps ADC 910mW, 67.5dB SNR, 9mm x 9mm QFN Package
LTC2249 14-Bit, 65Msps ADC 230mW, 73dB SNR, 5mm x 5mm QFN Package
LTC2250 10-Bit, 105Msps ADC 320mW, 61.6dB SNR, 5mm x 5mm QFN Package
LTC2251 10-Bit, 125Msps ADC 395mW, 61.6dB SNR, 5mm x 5mm QFN Package
LTC2252 12-Bit, 105Msps ADC 320mW, 70.2dB SNR, 5mm x 5mm QFN Package
LTC2253 12-Bit, 125Msps ADC 395mW, 70.2dB SNR, 5mm x 5mm QFN Package
LTC2254 14-Bit, 105Msps ADC 320mW, 72.5dB SNR, 5mm x 5mm QFN Package
LTC2255 14-Bit, 125Msps ADC 395mW, 72.4dB SNR, 5mm x 5mm QFN Package
LTC2299 Dual 14-Bit, 80Msps ADC 445mW, 73dB SNR, 9mm x 9mm QFN Package
LT5512 DC-3GHz High Signal Level DC to 3GHz, 21dBm IIP3, Integrated LO Buffer

Downconverting Mixer
LT5514 Ultralow Distortion IF Amplifi er/ADC 450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step

Driver with Digitally Controlled Gain
LT5522 600MHz to 2.7GHz High Linearity 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,

Downconverting Mixer NF = 12.5dB, 50Ω Single-Ended RF and LO Ports

32

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone]

●

FAX: [phone] ● www.linear.com

2208fb

LT 0107 REV B • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2005