Datasheet LTC1929 Datasheet (Linear Technology)

LTC1929

Final Electrical Specifications

2-Phase, High Efficiency,
Synchronous Step-Down

Switching Regulator

FEATURES

■

2-Phase Single Output Controller

■

Reduces Required Input Capacitance and Power
Supply Induced Noise

■

Current Mode Control Ensures Current Sharing

■

Phase-Lockable Fixed Frequency: 150kHz to 300kHz

■

True Remote Sensing Differential Amplifier

■

OPTI-LOOPTM Compensation Improves Transient
Response

■

±

1% Output Voltage Accuracy

■

Wide VIN Range: 4V to 36V Operation

■

Very Low Dropout Operation: 99% Duty Cycle

■

Adjustable Soft-Start Current Ramping

■

Internal Current Foldback

■

Short-Circuit Shutdown Timer with Defeat Option

■

Overvoltage Soft-Latch Eliminates Nuisance Trips

■

Available in 28-Lead SSOP Package

U

APPLICATIO S

■

Desktop Computers

■

Internet/Network Servers

■

Large Memory Arrays

■

DC Power Distribution Systems

U

August 1999

DESCRIPTIO

The LTC®1929 is a 2-phase, single output, synchronous
step-down current mode switching regulator controller
that drives N-channel external power MOSFET stages in a
phase-lockable fixed frequency architecture. The 2-phase
controller drives its two output stages out of phase at
frequencies up to 300kHz to minimize the RMS ripple
currents in both input and output capacitors. The 2-phase
technique effectively multiplies the fundamental frequency
by two, improving transient response while operating
each channel at an optimum frequency for efficiency.
Thermal design is also simplified.

An internal differential amplifier provides true remote
sensing of the regulated supply’s positive and negative
output terminals as required by high current applications.

The RUN/SS pin provides soft-start and a defeatable,
timed, latched short-circuit shutdown to shut down both
channels. Internal foldback current limit provides protec­tion for the external sychronous MOSFETs in the event of
an output fault. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP is a trademark of Linear Technology Corporation.

TYPICAL APPLICATIO

1000pF

10k

SS

8.06k

U

10Ω

1µH

10µF ×4
35V
CERAMIC

L1

1µH

D1

L2

0.002Ω

0.1µF

0.1µF

S

100pF

8.06k

S

C

OUT

L1, L2: CEPH149-1ROMC

S

V

IN

RUN/SS

I

TH

SGND

V

DIFFOUT

EAIN

–

V

OS

+

V

OS

: T510E108K004AS

LTC1929

BOOST1

PGND
SENSE1
SENSE1

BOOST2

INTV
SENSE2
SENSE2

TG1

SW1

BG1

TG2

SW2

BG2

S

0.47µF

S

+
–

S

S

S

CC

+
–

0.47µF

S

10µF

+

D2

Figure 1. High Current 2-Phase Step-Down Converter

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.002Ω

+

V

IN

5V TO 28V

V

OUT

1.6V/40A

C

OUT

1000µF ×2
4V

1929 TA01

1

LTC1929

WW

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

Input Supply Voltage (VIN).........................36V to –0.3V

Topside Driver Voltages (BOOST1,2).........42V to –0.3V

Switch Voltage (SW1, 2) .............................36V to –5 V

SENSE1+, SENSE2+, SENSE1–,

SENSE2– Voltages........................ (1.1)INTVCC to –0.3V

EAIN, V

RUN/SS, AMPMD Voltages..........................7V to –0.3V

Boosted Driver Voltage (BOOST-SW) ..........7V to –0.3V

PLLFLTR, PLLIN, V

ITH Voltage................................................2.7V to –0.3V

Peak Output Current <1µs(TGL1,2, BG1,2)................ 3A

INTVCC RMS Output Current................................ 50mA

Operating Ambient Temperature Range

LTC1929C.................................................. 0°C to 85°C

LTC1929I .............................................. – 40°C to 85°C

Junction Temperature (Note 2)............................. 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

OS

+

–

, V

, EXTVCC, INTVCC,

OS

DIFFOUT

Voltages .... INTVCC to –0.3V

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

RUN/SS
SENSE1
SENSE1

EAIN

PLLFLTR

PLLIN

SGND

V

DIFFOUT

V

OS

V

OS

SENSE2
SENSE2

1

+

2

–

3
4
5
6
7

NC

8

I

TH

9

10

–

11

+

12

–

13

+

14

G PACKAGE

28-LEAD PLASTIC SSOP

T

= 125°C, θJA = 95°C/W

JMAX

28
27
26
25
24
23
22
21
20
19
18
17
16
15

NC
TG1
SW1
BOOST1
V

IN

BG1
EXTV

CC

INTV

CC

PGND
BG2
BOOST2
SW2
TG2
AMPMD

Consult factory for Military grade parts.

ORDER PART

NUMBER

LTC1929CG
LTC1929IG

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. V

A

= 15V, V

IN

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loop

V

EAIN

V

SENSEMAX

I

INEAIN

V

LOADREG

V

REFLNREG

V

OVL

Regulated Feedback Voltage (Note 3); ITH Voltage = 1.2V ● 0.792 0.800 0.808 V
Maximum Current Sense Threshold V

–

= 5V 65 75 85 mV

SENSE

Feedback Current (Note 3) –5 –50 nA
Output Voltage Load Regulation (Note 3)

Measured in Servo Loop; I
Measured in Servo Loop; I

Voltage = 0.7V 0.05 0.3 %

TH

Voltage = 2V –0.1 –0.5 %

TH

Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 3) 0.002 %/V
Output Overvoltage Threshold Measured at V

EAIN

● 0.84 0.86 0.88 V

UVLO Undervoltage Lockout VIN Ramping Down 3 3.5 4 V
g

m

g

mOL

I

Q

I

RUN/SS

V

RUN/SS

V

RUN/SSLO

I

SCL

Transconductance Amplifier g

m

ITH = 1.2V; Sink/Source 5µA; (Note 3) 3 mmho
Transconductance Amplifier Gain ITH = 1.2V; (gmxZL; No Ext Load); (Note 3) 1.5 V/mV
Input DC Supply Current (Note 4)

Normal Mode EXTV

Shutdown V
Soft-Start Charge Current V
RUN/SS Pin ON Threshold V
RUN/SS Pin Latchoff Arming V

Tied to V

CC

= 0V 20 40 µA

RUN/SS

= 1.9V –1.2 µA

RUN/SS

Rising 1.0 1.5 1.9 V

RUN/SS

Rising from 3V 4.1 V

RUN/SS

RUN/SS Discharge Current Soft Short Condition V

= 4.5V

V

RUN/SS

OUT

; V

= 5V 470 µA

OUT

= 0.5V; 0.5 2.0 4.0 µA

EAIN

2

LTC1929

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. V

A

= 15V, V

IN

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

SDLHO

I

SENSE

DF

MAX

Shutdown Latch Disable Current V
Total Sense Pins Source Current Each Channel: V

= 0.5V 1.6 5 µA

EAIN

SENSE1–, 2

– = V

SENSE1+, 2

+ = 0V –60 µA

Maximum Duty Factor In Dropout 98 99.5 %
Top Gate Transition Time:

TG1, 2 t
TG1, 2 t

r
f

Rise Time C
Fall Time C

= 3300pF 30 90 ns

LOAD

= 3300pF 40 90 ns

LOAD

Bottom Gate Transition Time:

BG1, 2 t
BG1, 2 t

TG/BG t

BG/TG t

r
f

1D

Rise Time C
Fall Time C

Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time C

2D

Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time C

= 3300pF 30 90 ns

LOAD

= 3300pF 20 90 ns

LOAD

= 3300pF Each Driver 90 ns

LOAD

= 3300pF Each Driver 90 ns

LOAD

Internal VCC Regulator

V

INTVCC

V

INT INTVCC Load Regulation ICC = 0 to 20mA; V

LDO

V

EXT EXTVCC Voltage Drop ICC = 20mA; V

LDO

V

EXTVCC

V

LDOHYS

Internal VCC Voltage 6V < VIN < 30V; V

EXTVCC

EXTVCC Switchover Voltage ICC = 20mA, EXTV
EXTVCC Switchover Hysteresis ICC = 20mA, EXTV

= 4V 4.8 5.0 5.2 V

EXTVCC

= 4V 0.2 1.0 %

EXTVCC

= 5V 120 240 mV
Ramping Positive ● 4.5 4.7 V

CC

Ramping Negative 0.2 V

CC

Oscillator and Phase-Locked Loop

f

NOM

f

LOW

f

HIGH

R

PLLIN

I

PLLFLTR

R

RELPHS

Nominal Frequency V
Lowest Frequency V
Highest Frequency V

= 1.2V 200 220 250 kHz

PLLFLTR

= 0V 110 140 170 kHz

PLLFLTR

≥ 2.4V 270 310 350 kHz

PLLFLTR

PLLIN Input Resistance 50 kΩ
Phase Detector Output Current

Sinking Capability f

Sourcing Capability f

PLLIN
PLLIN

< f
> f

OSC
OSC

–15 µA
15 µA

Controller 2-Controller 1 Phase 180 Deg

Differential Amplifier/Op Amp Gain Block (Note 5)

A

DA

CMRR

DA

R

IN

V

OS

I

B

A

OL

V

CM

CMRR

OA

PSRR

OA

I

CL

V

O(MAX)

GBW Gain-Bandwidth Product Op Amp Mode; I

Gain Differential Amp Mode 0.995 1 1.005 V/V
Common Mode Rejection Ratio Differential Amp Mode; 0V < VCM < 5V 46 55 dB
Input Resistance Differential Amp Mode; Measured at VOS+ Input 80 kΩ
Input Offset Voltage Op Amp Mode; VCM = 2.5V; V

I

= 1mA

DIFFOUT

= 5V; 6 mV

DIFFOUT

Input Bias Current Op Amp Mode 30 200 nA
Open Loop DC Gain Op Amp Mode; 0.7V ≤ V

< 10V 5000 V/mV

DIFFOUT

Common Mode Input Voltage Range Op Amp Mode 0 3 V
Common Mode Rejection Ratio Op Amp Mode; 0V < VCM < 3V 70 90 dB
Power Supply Rejection Ratio Op Amp Mode; 6V < VIN < 30V 70 90 dB
Maximum Output Current Op Amp Mode; V
Maximum Output Voltage Op Amp Mode; I

= 0V 10 35 mA

DIFFOUT

= 1mA 10 11 V

DIFFOUT

= 1mA 2 MHz

DIFFOUT

SR Slew Rate Op Amp Mode; RL = 2k 5 V/µs

3

LTC1929

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.

Note 2: T
dissipation P

LTC1929CG: TJ = TA + (PD • 95°C/W)

is calculated from the ambient temperature TA and power

J

according to the following formulas:

D

UUU

PI FU CTIO S

RUN/SS (Pin 1): Combination of Soft-Start, Run Control
Input and Short-Circuit Detection Timer. A capacitor to
ground at this pin sets the ramp time to full current output.
Forcing this pin below 0.8V causes the IC to shut down all
internal circuitry. All functions are disabled in shutdown.

SENSE1+, SENSE2+ (Pins 2,14): The (+) Input to the
Differential Current Comparators. The ITH pin voltage and
built-in offsets between SENSE– and SENSE+ pins in
conjunction with R

SENSE1–, SENSE2– (Pins 3, 13): The (–) Input to the
Differential Current Comparators.

EAIN (Pin 4): Input to the Error Amplifier that compares
the feedback voltage to the internal 0.8V reference voltage.
This pin is normally connected to a resistive divider from
the output of the differential amplifier (DIFFOUT).

PLLFLTR (Pin 5): The Phase-Locked Loop’s Low Pass
Filter is tied to this pin. Alternatively, this pin can be driven
with an AC or DC voltage source to vary the frequency of
the internal oscillator.

PLLIN (Pin 6): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with
50kΩ. The phase-locked loop will force the rising top gate
signal of controller 1 to be synchronized with the rising
edge of the PLLIN signal.

NC (Pins 7, 28): Not connected.

ITH (Pin 8): Error Amplifier Output and Switching Regula-

tor Compensation Point. Both current comparator’s thresh­olds increase with this control voltage. The normal voltage
range of this pin is from 0V to 2.4V

set the current trip threshold.

SENSE

Note 3: The LTC1929 is tested in a feedback loop that servos V
specified voltage and measures the resultant V

Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.

Note 5: When the AMPMD pin is high, the IC pins are connected directly to
the internal op amp inputs. When the AMPMD pin is low, internal MOSFET
switches connect four 40k resistors around the op amp to create a
standard unity-gain differential amp.

EAIN

.

ITH

to a

SGND (Pin 9): Signal Ground, common to both control­lers, must be routed separately from the input switched
current ground path to the common (–) terminal(s) of the
C

capacitor(s).

OUT

V

DIFFOUT

(Pin 10): Output of a Differential Amplifier that

provides true remote output voltage sensing. This pin
normally drives an external resistive divider that sets the
output voltage.

–

V

OS

+

, V

(Pins 11, 12): Inputs to an Operational Ampli-

OS

fier. Internal precision resistors capable of being elec­tronically switched in or out can configure it as a differen­tial amplifier or an uncommitted Op Amp.

AMPMD (Pin 15): This Logic Input pin controls the
connections of internal precision resistors that configure
the operational amplifier as a unity-gain differential ampli­fier.

TG2, TG1 (Pins 16, 27): High Current Gate Drives for Top
N-Channel MOSFETS. These are the outputs of floating
drivers with a voltage swing equal to INTVCC superim­posed on the switch node voltage SW.

SW2, SW1 (Pins 17, 26): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to VIN.

BOOST2, BOOST1 (Pins 18, 25): Bootstrapped Supplies
to the Topside Floating Drivers. Capacitors are connected
between the Boost and Switch pins, and Schottky diodes
are tied between the Boost and INTVCC pins.

BG2, BG1 (Pins 19, 23): Voltage Swing High Current Gate
Drives for Bottom Synchronous N-Channel MOSFETS.
Voltage swing at these pins is from ground to INTVCC.

4

UUU

PI FU CTIO S

LTC1929

PGND (Pin 20): Driver Power Ground. Connects to sources
of bottom N-channel MOSFETS and the (–) terminals of
CIN.

INTVCC (Pin 21): Output of the Internal 5V Linear Low
Dropout Regulator and the EXTVCC Switch. The driver and
control circuits are powered from this voltage source.

Decouple to power ground with a 1µF ceramic capacitor
placed directly adjacent to the IC and minimum of 4.7µF
additional tantalum or other low ESR capacitor.

UU

W

FU CTIO AL DIAGRA

PLLIN

F

IN

R

LP

C

LP

PLLLPF

V

OS

V

OS

AMPMD

DIFFOUT

V

IN

V

IN

EXTV

INTV

5V

+

SGND

PHASE DET

50k

OSCILLATOR

–

+

0V POSITION

4.7V

CC

CC

CLK1
CLK2

–

+

V

0.8V

+
–

5V
LDO
REG

INTERNAL

SUPPLY

A1

REF

DUPLICATE FOR
SECOND CHANNEL

V

IN

1.2µA

6V

4(VFB)

I1

SLOPE

COMP

SRQ

Q

–
+

EXTVCC (Pin 22): External Power Input to an Internal
Switch . This switch closes and supplies INTV

bypass-

CC,

ing the internal low dropout regulator whenever EXTVCC is
higher than 4.7V. See EXTVCC Connection in the Applica­tions Information section. Do not exceed 7V on this pin
and ensure V

EXTVCC

≤ V

INTVCC

.

VIN (Pin 24): Main Supply Pin. Should be closely decoupled
to the IC’s signal ground pin.

V

CC

IN

D

B

C

B

L

+

C

OUT

+

V

OUT

R

C

C

SS

DROP

OUT
DET

45k

+–

SHDN

4(VFB)

BOT

FORCE BOT

SHDN

45k

2.4V

OV

RUN

SOFT

START

SWITCH

EA

LOGIC

–

+

+
–

INTV

BOOST

INTV

CC

30k

30k

CC

TG

SW

BG

PGND

SENSE

SENSE

EAIN

I

TH

RUN/SS

+

–

R

SENSE

R1

R2

C

C

TOP

BOT

INTV

V

FB

0.80V

0.86V

C

IN

1929 FBD

5

LTC1929

OPERATIO

U

(Refer to Functional Diagram)

Main Control Loop

The LTC1929 uses a constant frequency, current mode
step-down architecture with inherent current sharing.
During normal operation, the top MOSFET is turned on
each cycle when the oscillator sets the RS latch, and
turned off when the main current comparator, I1, resets
the RS latch. The peak inductor current at which I1 resets
the RS latch is controlled by the voltage on the ITH pin,
which is the output of the error amplifier EA. The differen­tial amplifier, A1, produces a signal equal to the differential
voltage sensed across the output capacitor but re-refer­ences it to the internal signal ground (SGND) reference.
The EAIN pin receives a portion of this voltage feedback
signal at the DIFFOUT pin which is compared to the
internal reference voltage by the EA. When the load current
increases, it causes a slight decrease in the EAIN pin
voltage relative to the 0.8V reference, which in turn causes
the ITH voltage to increase until the average inductor
current matches the new load current. After the top
MOSFET has turned off, the bottom MOSFET is turned on
for the rest of the period.

The top MOSFET drivers are biased from floating boot­strap capacitor CB, which normally is recharged during
each off cycle through an external Schottky diode. When
VIN decreases to a voltage close to V
may enter dropout and attempt to turn on the top MOSFET
continuously. A dropout detector detects this condition
and forces the top MOSFET to turn off for about 400ns
every 10th cycle to recharge the bootstrap capacitor.

The main control loop is shut down by pulling Pin 1 (RUN/
SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with the
ITH voltage clamped at approximately 30% of its maximum
value. As CSS continues to charge, ITH is gradually re­leased allowing normal operation to resume. When the
RUN/SS pin is low, all LTC1929 functions are shut down.
If V

has not reached 70% of its nominal value when C

OUT

has charged to 4.1V, an overcurrent latchoff can be
invoked as described in the Applications Information
section.

, however, the loop

OUT

SS

Low Current Operation

The LTC1929 operates in a continuous, PWM control
mode. The resulting operation at low output currents
optimizes transient response at the expense of substantial
negative inductor current during the latter part of the
period. The level of ripple current is determined by the
inductor value, input voltage, output voltage, and fre­quency of operation.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
DC frequency control input of the oscillator that operates
over a 140kHz to 310kHz range corresponding to a DC
voltage input from 0V to 2.4V. When locked, the PLL aligns
the turn on of the top MOSFET to the rising edge of the
synchronizing signal. When PLLIN is left open, the PLLFLTR
pin goes low, forcing the oscillator to minimum frequency.

Input capacitance ESR requirements and efficiency losses
are substantially reduced because the peak current drawn
from the input capacitor is effectively divided by two and
power loss is proportional to the RMS current squared. A
two stage, single output voltage implementation can re­duce input path power loss by 75% and radically reduce
the required RMS current rating of the input capacitor(s).

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and most
of the IC circuitry is derived from INTVCC. When the
EXTVCC pin is left open, an internal 5V low dropout
regulator supplies INTVCC power. If the EXTVCC pin is
taken above 4.7V, the 5V regulator is turned off and an
internal switch is turned on connecting EXTVCC to INTVCC.
This allows the INTVCC power to be derived from a high
efficiency external source such as the output of the regu­lator itself or a secondary winding, as described in the
Applications Information section. An external Schottky
diode can be used to minimize the voltage drop from
EXTVCC to INTV
the specified INTVCC current. Voltages up to 7V can be
applied to EXTVCC for additional gate drive capability.

in applications requiring greater than

CC

6

OPERATIO

LTC1929

U

(Refer to Functional Diagram)

Differential Amplifier

This amplifier provides true differential output voltage
sensing. Sensing both V
tion in high current applications and/or applications hav­ing electrical interconnection losses. The AMPMD pin
allows selection of internal, precision feedback resistors
for high common mode rejection differencing applica­tions, or direct access to the actual amplifier inputs
without these internal feedback resistors for other applica­tions. The AMPMD pin is grounded to connect the internal
precision resistors in a unity-gain differencing application,
or tied to the INTVCC pin to bypass the internal resistors
and make the amplifier inputs directly available. The
amplifier is a unity-gain stable, 2MHz gain-bandwidth,
>120dB open-loop gain design. The amplifier has an
output slew rate of 5V/µs and is capable of driving capaci-
tive loads with an output RMS current typically up to
25mA. The amplifier is not capable of sinking current and
therefore must be resistively loaded to do so.

OUT

+

and V

–

benefits regula-

OUT

Short-Circuit Detection

The RUN/SS capacitor is used initially to limit the inrush
current from the input power source. Once the controllers
have been given time, as determined by the capacitor on
the RUN/SS pin, to charge up the output capacitors and
provide full load current, the RUN/SS capacitor is then
used as a short-circuit timeout circuit. If the output voltage
falls to less than 70% of its nominal output voltage the
RUN/SS capacitor begins discharging assuming that the
output is in a severe overcurrent and/or short-circuit
condition. If the condition lasts for a long enough period
as determined by the size of the RUN/SS capacitor, the
controller will be shut down until the RUN/SS pin voltage
is recycled. This built-in latchoff can be overidden by
providing a current >5µA at a compliance of 5V to the
RUN/SS pin. This current shortens the soft-start period
but also prevents net discharge of the RUN/SS capacitor
during a severe overcurrent and/or short-circuit condi­tion. Foldback current limiting is activated when the output
voltage falls below 70% of its nominal level whether or not
the short-circuit latchoff circuit is enabled.

U

WUU

APPLICATIO S I FOR ATIO

The basic LTC1929 application circuit is shown in Figure␣ 1
on the first page. External component selection is driven
by the load requirement, and begins with the selection of
R

SENSE1, 2

chosen. Next, the power MOSFETs and D1 and D2 are
selected. The operating frequency and the inductor are
chosen based mainly on the amount of ripple current.
Finally, CIN is selected for its ability to handle the input
ripple current (that PolyPhaseTM operation minimizes) and
C

OUT

ripple voltage and load step specifications (also minimized
with PolyPhase). Current mode architecture provides in­herent current sharing between output stages. The circuit
shown in Figure␣ 1 can be configured for operation up to an
input voltage of 28V (limited by the external MOSFETs).

R

SENSE

R

SENSE1, 2

current. The LTC1929 current comparator has a maxi-

. Once R

is chosen with low enough ESR to meet the output

Selection For Output Current

are chosen based on the required output

SENSE1, 2

are known, L1 and L2 can be

mum threshold of 75mV/R
mode range of SGND to 1.1( INTVCC). The current com­parator threshold sets the peak inductor current, yielding
a maximum average output current I
value less half the peak-to-peak ripple current, ∆IL.

Allowing a margin for variations in the LTC1929 and
external component values yields:

R

Operating Frequency

The LTC1929 uses a constant frequency, phase-lockable
architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
and Frequency Synchronization in the Applications Infor­mation section for additional information.

PolyPhase is a registered trademark of Linear Technology Corporation.

SENSE

= 2(50mV/I

MAX

)

and an input common

SENSE

equal to the peak

MAX

7

LTC1929

U

WUU

APPLICATIO S I FOR ATIO

A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure␣ 2. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 310kHz.

2.5

2.0

1.5

1.0

FREQSET PIN VOLTAGE (V)

0.5

0

120 170 220 270 320

OPERATING FREQUENCY (kHz)

1929 F02

Figure 2. Operating Frequency vs V

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge and transition losses. In addition to
this basic tradeoff, the effect of inductor value on ripple
current and low current operation must also be consid­ered. The PolyPhase approach reduces both input and
output ripple currents while optimizing individual output
stages to run at a lower fundamental frequency, enhancing
efficiency.

The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL per individual section, N,
decreases with higher inductance or frequency and in­creases with higher VIN or V



V

∆I

OUT OUT

=−

L

fL

V

1



V



IN

:

OUT






where f is the individual output stage operating frequency.

PLLFLTR

In a 2-phase converter, the net ripple current seen by the
output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.

Figure 3 shows the net ripple current seen by the output
capacitors for the 1- and 2-phase configurations. The
output ripple current is plotted for a fixed output voltage as
the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations, simplifying the
design process.

Accepting larger values of ∆IL allows the use of low
inductances, but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is ∆I
= 0.4(I

)/2, where I

OUT

is the total load current. Remem-

OUT

L

ber, the maximum ∆IL occurs at the maximum input
voltage. The individual inductor ripple currents are deter­mined by the inductor, input and output voltages.

1.0

OUT/VIN

)]

1-PHASE
2-PHASE

)

1929 F03

0.9

0.8

0.7

0.6

/fL

0.5

O

O(P-P)

V

∆I

0.4

0.3

0.2

0.1
0

0.1 0.2 0.3 0.4

Figure 3. Normalized Output Ripple Current vs
Duty Factor [I

DUTY FACTOR (V

≈ 0.3 (∆I

RMS

0.5 0.6 0.7 0.8 0.9

O(P–P)

Inductor Core Selection

Once the values for L1 and L2 are known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ® cores. Actual core
loss is independent of core size for a fixed inductor value,

Kool Mµ is a registered trademark of Magnetics, Inc.

8

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APPLICATIO S I FOR ATIO

but it is very dependent on inductance selected. As induc­tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con­centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc­tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple.

not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu­facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be­cause they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.

Power MOSFET, D1 and D2 Selection

Do

V

Main SwitchDuty Cycle

Synchronous SwitchDuty Cycle

The MOSFET power dissipations at maximum output
current are given by:











I

I

MAX




2






2








V

P

MAIN

P

SYNC

where δ is the temperature dependency of R
is a constant inversely related to the gate drive current.

OUTINMAX

=

V

2

kV

IN

()

VVVI

–

IN OUTINMAX

=

OUT

=

V

IN



VV

IN OUT

=





2

1

R

+

δ

()

Cf

RSS

()()

2

DS ON

2



1

+

()





()

R

δ

DS ON

+

()

–

V

IN

DS(ON)






and k

Two external power MOSFETs must be selected for each
controller with the LTC1929: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTVCC volt­age. This voltage is typically 5V during start-up (see
EXTVCC Pin Connection). Consequently, logic-level thresh­old MOSFETs must be used in most applications. The only
exception is if low input voltage is expected (VIN < 5V);
then, sublogic-level threshold MOSFETs (V
should be used. Pay close attention to the BV
cation for the MOSFETs as well; most of the logic-level
MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “ON”
resistance R
input voltage, and maximum output current. When the
LTC1929 is operating in continuous mode the duty factors
for the top and bottom MOSFETs of each output stage are
given by:

, reverse transfer capacitance C

DS(ON)

GS(TH)

DSS

< 3V)

specifi-

RSS

,

Both MOSFETs have I2R losses but the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
high current efficiency generally improves with larger
MOSFETs, while for V
increase to the point that the use of a higher R
with lower C
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.

The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C
FET characteristics. The constant k = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.

The Schottky diodes, D1 and D2 shown in Figure 1 conduct
during the dead-time between the conduction of the two
large power MOSFETs. This helps prevent the body diode

RSS

> 20V the transition losses rapidly

IN

actual provides higher efficiency. The

vs. Temperature curve, but

DS(ON)

is usually specified in the MOS-

RSS

< 20V the

IN

DS(ON)

device

9

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APPLICATIO S I FOR ATIO

of the bottom MOSFET from turning on, storing charge
during the dead-time, and requiring a reverse recovery
period which would reduce efficiency. A 1A to 3A (depend­ing on output current) Schottky diode is generally a good
compromise for both regions of operation due to the
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance.

CIN and C

In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V
VIN. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a close form
equation can be found in Application Note 77. Figure 4
shows the input capacitor ripple current for a 2-phase
configuration with the output voltage fixed and input
voltage varied. The input ripple current is normalized
against the DC output current. The graph can be used in
place of tedious calculations. The minimum input ripple
current can be achieved when the input voltage is twice the
output voltage. The minimum is not quite zero due to
inductor ripple current.

In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:

Selection

OUT

OUT

/

These worst-case conditions are commonly used for
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the capacitor manufacturer if there is any ques­tion.

It is important to note that the efficiency loss is propor­tional to the input RMS current

squared

and therefore a
2-stage implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the re­duction of the input ripple current in a 2-phase system. The
required amount of input capacitance is further reduced by
the factor, 2, due to the effective increase in the frequency
of the current pulses.

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically once the ESR require­ment has been met, the RMS current rating generally far
exceeds the I

RIPPLE(P-P)

output ripple (∆V

requirements. The steady state

) is determined by:

OUT

V

OUT

V

IN

Figure 4. Normalized RMS Input Ripple Current vs
Duty Factor for 1 and 2 Output Stages

k

−21

=

4

0.6

0.5

0.4

0.3

0.2

DC LOAD CURRENT

RMS INPUT RIPPLE CURRNET

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

where k = 1, 2.

DUTY FACTOR (V

1-PHASE
2-PHASE

OUT/VIN

10

∆∆V I ESR

≈+

OUT RIPPLE





16

Where f = operating frequency of each stage, C



output capacitance and ∆I

RIPPLE



1



fC



OUT

OUT

= combined inductor

=

ripple currents.
The output ripple varies with input voltage since ∆IL is a

function of input voltage. The output ripple will be less than
50mV at max VIN with ∆IL = 0.4I

C
C

required ESR < 4(R

OUT

> 1/(16f)(R

OUT

SENSE

SENSE

)

OUT(MAX)

) and

/2 assuming:

The emergence of very low ESR capacitors in small,

0.9

)

1929 F04

surface mount packages makes very physically small
implementations possible. The ability to externally com­pensate the switching regulator loop using the ITH pin(OPTI­LOOP compensation) allows a much wider selection of

LTC1929

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APPLICATIO S I FOR ATIO

output capacitor types. OPTI-LOOP compensation effec­tively removes constraints on output capacitor ESR. The
impedance characteristics of each capacitor type are sig­nificantly different than an ideal capacitor and therefore
require accurate modeling or bench evaluation during
design.

Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance through­hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo and the Panasonic SP
surface mount types have the lowest (ESR)(size) product
of any aluminum electrolytic at a somewhat higher price.
An additional ceramic capacitor in parallel with OS-CON
type capacitors is recommended to reduce the inductance
effects.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum elec­trolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer sur­face mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV or the KEMET T510
series of surface mount tantalums, available in case heights
ranging from 2mm to 4mm. Other capacitor types include
Sanyo OS-CON, Nichicon PL series and Sprague 595D
series. Consult the manufacturer for other specific recom­mendations. A combination of capacitors will often result
in maximizing performance and minimizing overall cost
and size.

INTVCC Regulator

An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. The INTV
regulator powers the drivers and internal circuitry of the
LTC1929. The INTVCC pin regulator can supply up to 50mA
peak and must be bypassed to power ground with a
minimum of 4.7µF tantalum or electrolytic capacitor. An
additional 1µF ceramic capacitor placed very close to the
IC is recommended due to the extremely high instanta­neous currents required by the MOSFET gate drivers.

CC

High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi­mum junction temperature rating for the LTC1929 to be
exceeded. The supply current is dominated by the gate
charge supply current, in addition to the current drawn
from the differential amplifier output. The gate charge is
dependent on operating frequency as discussed in the
Efficiency Considerations section. The supply current can
either be supplied by the internal 5V regulator or via the
EXTVCC pin. When the voltage applied to the EXTVCC pin
is less than 4.7V, all of the INTVCC load current is supplied
by the internal 5V linear regulator. Power dissipation for
the IC is higher in this case by (IIN)(VIN – INTVCC) and
efficiency is lowered. The junction temperature can be
estimated by using the equations given in Note 1 of the
Electrical Characteristics. For example, the LTC1929 V
current is limited to less than 24mA from a 24V supply:

TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C

Use of the EXTVCC pin reduces the junction temperature
to:

TJ = 70°C + (24mA)(5V)(95°C/W) = 81.4°C

The input supply current should be measured while the
controller is operating in continuous mode at maximum
V

and the power dissipation calculated in order to pre-

IN

vent the maximum junction temperature from being ex­ceeded.

EXTVCC Connection

The LTC1929 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
When the voltage applied to EXTV
internal regulator is turned off and the switch closes,
connecting the EXTV
supplying internal and MOSFET gate driving power. The
switch remains closed as long as the voltage applied to
EXTVCC remains above 4.5V. This allows the MOSFET
driver and control power to be derived from the output
during normal operation (4.7V < V
the internal regulator when the output is out of regulation
(start-up, short-circuit). Do not apply greater than 7V to
the EXTVCC pin and ensure that EXTV
using the application circuits shown. If an external voltage
source is applied to the EXTVCC pin when the VIN supply is

pin to the INTV

CC

rises above 4.7V, the

CC

pin thereby

CC

EXTVCC

< 7V) and from

< V

CC

+ 0.3V when

IN

IN

11

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APPLICATIO S I FOR ATIO

not present, a diode can be placed in series with the
LTC1929’s V
EXTV

and the V

CC

VIN.
Significant efficiency gains can be realized by powering

INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by the
ratio: (Duty Factor)/(Efficiency). For 5V regulators this
means connecting the EXTVCC pin directly to V
ever, for 3.3V and other lower voltage regulators, addi­tional circuitry is required to derive INTVCC power from the
output.

The following list summarizes the four possible connec­tions for EXTV

1. EXTVCC left open (or grounded). This will cause INTV
to be powered from the internal 5V regulator resulting in
a significant efficiency penalty at high input voltages.

2. EXTVCC connected directly to V
connection for a 5V regulator and provides the highest
efficiency.

3. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 7V range, it may be used to
power EXTVCC providing it is compatible with the MOSFET
gate drive requirements.

4. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency gains
can still be realized by connecting EXTVCC to an output­derived voltage which has been boosted to greater than

4.7V but less than 7V. This can be done with either the

pin and a Schottky diode between the

IN

pin, to prevent current from backfeeding

IN

. How-

OUT

CC:

. This is the normal

OUT

CC

inductive boost winding as shown in Figure 5a or the
capacitive charge pump shown in Figure 5b. The charge
pump has the advantage of simple magnetics.

Topside MOSFET Driver Supply (CB,DB) (Refer to
Functional Diagram)

External bootstrap capacitors CB1 and CB2 connected to
the BOOST1 and BOOST2 pins supply the gate drive
voltages for the topside MOSFETs. Capacitor CB in the
Functional Diagram is charged though diode DB from
INTVCC when the SW pin is low. When the topside MOSFET
turns on, the driver places the CB voltage across the gate­source of the desired MOSFET. This enhances the MOSFET
and turns on the topside switch. The switch node voltage,
SW, rises to VIN and the BOOST pin rises to VIN + V

INTVCC

.
The value of the boost capacitor CB needs to be 30 to 100
times that of the total input capacitance of the topside
MOSFET(s). The reverse breakdown of DB must be greater
than V

IN(MAX).

The final arbiter when defining the best gate drive ampli­tude level will be the input supply current. If a change is
made that decreases input current, the efficiency has
improved. If the input current does not change then the
efficiency has not changed either.

Output Voltage

The LTC1929 has a true remote voltage sense capablity.
The sensing connections should be returned from the load
back to the differential amplifier’s inputs through a com­mon, tightly coupled pair of PC traces. The differential

OPTIONAL EXTVCC CONNECTION
5V < V

< 7V

EXTV

SEC

LTC1929

CC

V

TG1

SW1

BG1

PGND

C

IN

IN

+

N-CH

N-CH

V

IN

1N4148

T1

R

SENSE

+

C

IN

V

IN

V

SEC

+

1µF

V

OUT

+

C

OUT

1929 F05a

EXTV

LTC1929

CC

TG1

N-CH

SW1

BG1

N-CH

PGND

V

IN

BAT85 0.22µF

VN2222LL

R

L1

Figure 5a. Secondary Output Loop with EXTVCC Connection Figure 5b. Capacitive Charge Pump for EXTV

12

SENSE

+

BAT85

BAT85

V

OUT

+

C

OUT

1929 F05b

CC

LTC1929

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APPLICATIO S I FOR ATIO

amplifier rejects common mode signals capacitively or
inductively radiated into the feedback PC traces as well as
ground loop disturbances. The differential amplifier out­put signal is divided down and compared with the internal
precision 0.8V voltage reference by the error amplifier.

The differential amplifier can be used in either of two
configurations according to the voltage applied to the
AMPMD pin. The first configuration, with the connections
illustrated in the Functional Diagram, utilizes a set of
internal precision resistors to enable precision instrumen­tation-type measurement of the output voltage. This con­figuration is activated when the AMPMD pin is tied to
ground. When the AMPMD pin is tied to INTVCC, the
resistors are disconnected and the amplifier inputs are
made directly available. The amplifier can then be used as
a general purpose op amp. The amplifier has a 0V to 3V
common mode input range limitation due to the internal
switching of its inputs. The output is an NPN emitter
follower without any internal pull-down current. A DC
resistive load to ground is required in order to sink current.
The output will swing from 0V to 10V (VIN ≥ V

Soft-Start/Run Function

The RUN/SS pin provides three functions: 1) Run/Shut­down, 2) soft-start and 3) a defeatable short-circuit latchoff
timer. Soft-start reduces the input power sources’ surge
currents by gradually increasing the controller’s current
limit I

TH(MAX)

extreme load transients from tripping the overcurrent
latch. A small pull-up current (>5µA) supplied to the RUN/
SS pin will prevent the overcurrent latch from operating.
The following explanation describes how the functions
operate.

An internal 1.2µA current source charges up the C
capacitor. When the voltage on RUN/SS reaches 1.5V, the
controller is permitted to start operating. As the voltage on
RUN/SS increases from 1.5V to 3.0V, the internal current
limit is increased from 25mV/R
The output current limit ramps up slowly, taking an
additional 1.4s/µF to reach full current. The output current
thus ramps up slowly, reducing the starting surge current

. The latchoff timer prevents very short,

SENSE

DIFFOUT

to 75mV/R

+ 2V).

SS

SENSE

.

required from the input power supply. If RUN/SS has been
pulled all the way to ground there is a delay before starting
of approximately:

15

.

t

DELAY SS SS

The time for the output current to ramp up is then:

t

IRAMP SS SS

By pulling both RUN/SS controller pins below 0.8V the
LTC1929 is put into low current shutdown (IQ < 40µA). The
RUN/SS pins can be driven directly from logic as shown in
Figure 6. Diode D1 in Figure 6 reduces the start delay but
allows CSS to ramp up slowly providing the soft-start
function. The RUN/SS pin has an internal 6V zener clamp
(see Functional Diagram).

Fault Conditions: Overcurrent Latchoff

The RUN/SS pin also provides the ability to latch off the
controllers when an overcurrent condition is detected. The
RUN/SS capacitor, CSS, is used initially to limit the inrush
current of both controllers. After the controllers have been
started and been given adequate time to charge up the
output capacitors and provide full load current, the RUN/
SS capacitor is used for a short-circuit timer. If the output
voltage falls to less than 70% of its nominal value, after
CSS reaches 4.1V, CSS begins discharging on the assump­tion that the output is in an overcurrent condition. If the
condition lasts for a long enough period as determined by
the size of CSS, the controller will be shut down until the
RUN/SS pin voltage is recycled. If the overload occurs
during start-up, the time can be approximated by:

T

≈ (CSS • 0.6V)/(1.2µA) = 5 • 105 (CSS)

LO1

If the overload occurs after start-up the voltage on the
RUN/SS capacitor will continue charging and will provide
additional time before latching off:

T

≈ (CSS • 3V)/(1.2µA) = 2.5 • 106 (CSS)

LO2

V

=

12

.

A

µ

315

.

VV

−

=

12

.

µ

CsFC

A

125

./

=µ

()

125

CsFC

./

=µ

()

13

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This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, RSS, to the RUN/SS pin as
shown in Figure 6. This resistance shortens the soft-start
period and prevents the discharge of the RUN/SS capaci­tor during a severe overcurrent and/or short-circuit con­dition. When deriving the 5µA current from VIN as in the
figure, current latchoff is always defeated. The diode
connecting of this pull-up resistor to INTVCC, as in
Figure␣ 6, eliminates any extra supply current during shut­down while eliminating the INTV
ing controller start-up.

Why should you defeat current latchoff? During the
prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is com­plete whether to rely solely on foldback current limiting or
to enable the latchoff feature by removing the pull-up
resistor.

The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci­tance is given by:

CSS > (C

OUT

)(V

)(10-4)(R

OUT

The minimum recommended soft-start capacitor of CSS =

0.1µF will be sufficient for most applications.

V

3.3V OR 5V RUN/SS

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

IN

RSS*

D1

C

SS

Figure 6. RUN/SS Pin Interfacing

loading from prevent-

CC

)

SENSE

INTV

CC

RSS*

D1*

RUN/SS

C

1929 F06

SS

Phase-Locked Loop and Frequency Synchronization

The LTC1929 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the
center frequency fO. A voltage applied to the PLLFLTR pin
of 1.2V corresponds to a frequency of approximately
220kHz. The nominal operating frequency range of the
LTC1929 is 140kHz to 310kHz.

The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec­tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆fH, is equal to the capture range, ∆f

C:

∆fH = ∆fC = ±0.5 fO (150kHz-300kHz)

The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 7.

If the external frequency (f
lator frequency f

, current is sourced continuously,

0SC

) is greater than the oscil-

PLLIN

pulling up the PLLFLTR pin. When the external frequency
is less than f

, current is sunk continuously, pulling

0SC

down the PLLFLTR pin. If the external and internal fre­quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond­ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor CLP holds the voltage. The
LTC1929 PLLIN pin must be driven from a low impedance
source such as a logic gate located close to the pin.

The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically R

=10kΩ and CLP is 0.01µF to

LP

0.1µF.

14

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APPLICATIO S I FOR ATIO

2.4V

PHASE

50k

DETECTOR

DIGITAL

PHASE/

FREQUENCY

DETECTOR

EXTERNAL

OSC

PLLIN

Figure 7. Phase-Locked Loop Block Diagram

Minimum On-Time Considerations

Minimum on-time t

ON(MIN)

is the smallest time duration
that the LTC1929 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that

V

t

ON MIN

()

<

Vf

OUT

IN

()

If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1929 will begin to skip
cycles resulting in nonconstant frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.

R

LP

10k

PLLFLTR

1929 F07

OSC

C

LP

If an application can operate close to the minimum on­time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement.

As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of I

OUT(MAX)

at V

IN(MAX)

.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1929 circuits: 1) LTC1929 VIN current (in­cluding loading on the differential amplifier output),

2) INTVCC regulator current, 3) I2R losses and 4) Topside
MOSFET transition losses.

1) The VIN current has two components: the first is the
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control cur­rents; the second is the current drawn from the differential
amplifier output. VIN current typically results in a small
(<0.1%) loss.

The minimum on-time for the LTC1929 is generally less
than 200ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases. This is of
particular concern in forced continuous applications with
low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre­spondingly larger current and voltage ripple.

2) INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTVCC to
ground. The resulting dQ/dt is a current out of INTVCC that
is typically much larger than the control circuit current. In
continuous mode, I

GATECHG

= (QT + QB), where QT and Q

B

are the gate charges of the topside and bottom side
MOSFETs.

15

LTC1929

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APPLICATIO S I FOR ATIO

Supplying INTV
from an output-derived source will scale the V
required for the driver and control circuits by the ratio
(Duty Factor)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTVCC current results in approxi­mately 3mA of VIN current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from VIN) to only a few percent.

3) I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi­mately the same R
MOSFET can simply be summed with the resistances of L,
R
R

and ESR to obtain I2R losses. For example, if each

SENSE

=10mΩ, RL=10mΩ, and R

DS(ON)

total resistance is 25mΩ. This results in losses ranging
from 2% to 8% as the output current increases from 3A to
15A per output stage for a 5V output, or a 3% to 12% loss
per output stage for a 3.3V output. Efficiency varies as the
inverse square of V
and output power level. The combined effects of increas­ingly lower output voltages and higher currents required
by high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!

4) Transition losses apply only to the topside MOSFET(s),
and only when operating at high input voltages (typically
20V or greater). Transition losses can be estimated from:

Transition Loss = (1.7) V
Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and input fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and a very low ESR at the
switching frequency. A 25W supply will typically require a

power through the EXTVCC switch input

CC

current

IN

, then the resistance of one

DS(ON)

=5mΩ, then the

SENSE

for the same external components

OUT

2

I

IN

O(MAX) CRSS

f

SENSE

,

minimum of 20µF to 40µF of capacitance having a maxi-
mum of 10mΩ to 20mΩ of ESR. The LTC1929 2-phase
architecture typically halves this input capacitance re­quirement over competing solutions. Other losses includ­ing Schottky conduction losses during dead-time and
inductor core losses generally account for less than 2%
total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C

generating the feedback error signal that

OUT

(ESR), where ESR is the effective

LOAD

OUT

(∆I

) also begins to charge or

LOAD

shifts by an

OUT

forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem.

to its steady-state value. During this recovery

OUT

can be monitored for excessive overshoot or

OUT

The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response.

Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin. The ITH external components
shown in the Figure 1 circuit will provide an adequate
starting point for most applications.

The I

series RC-CC filter sets the dominant pole-zero

TH

loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full-load current having a rise time
of <2µs will produce output voltage and ITH pin waveforms

16

LTC1929

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APPLICATIO S I FOR ATIO

that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step
resulting from the step change in output current may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why it
is better to look at the Ith pin signal which is in the feedback
loop and is the filtered and compensated control loop
response. The gain of the loop will be increased by
increasing RC and the bandwidth of the loop will be
increased by decreasing CC. If RC is increased by the same
factor that CC is decreased, the zero frequency will be kept
the same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual over­all supply performance.

A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C

LOAD

should be controlled so that the load rise time is limited to
approximately 25 • C
require a 250µs rise time, limiting the charging current to
about 200mA.

, causing a rapid drop in V

OUT

to C

is greater than1:50, the switch rise time

OUT

. Thus a 10µF capacitor would

LOAD

. No regulator can

OUT

Automotive Considerations: Plugging into the
Cigarette Lighter

As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main battery line in an automo­bile is the source of a number of nasty potential transients,
including load-dump, reverse-battery, and double-bat­tery.

Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.

The network shown in Figure 8 is the most straightforward
approach to protect a DC/DC converter from the ravages
of an automotive battery line. The series diode prevents
current from flowing during reverse-battery, while the
transient suppressor clamps the input voltage during
load-dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the LT1929 has a maximum input voltage of 36V,
most applications will be limited to 30V by the MOSFET
BV

.

DSS

50A I

RATING

PK

12V

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

Figure 8. Automotive Application Protection

1.5KA24A

V

IN

LTC1929

1929 F08

17

LTC1929

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APPLICATIO S I FOR ATIO

Design Example (Using Two Phases)

As a design example, assume VIN = 5V (nominal), VIN␣ =␣ 5.5V
(max), V
R

SENSE1

R

SENSE1

If L1 = L2 = 2µH the actual value of the ripple current for
each channel, the following equation is used:

∆I

The highest value of the ripple current occurs at the
maximum input voltage:

∆I

The ripple current for each inductor is 20% at maximum
output current which is conservative.

Next verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum VIN:

t

ON MIN

Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the sense pin current for both
channels.

R

1

= 1.8V, I

OUT

and R

SENSE2

= R

SENSE2



V

OUT OUT

=−

L

=

L

()

()

MIN

()

1





fL

18

..

kHz H

310 2

V

==

Vf

IN MAX

kV

20

=

224



k

10

=





= 20A, TA = 70°C and f␣ =␣ 310kHz,

MAX

can immediately be calculated:
= 50mV/10A = 0.005Ω



V





V

IN



18

−

1



55

.



µ

()

OUT

()






24 18

..





V kHz

5 5 310

.



OUT

VV

−

.

18

.

VV

−






OUT

V











18

.

()

30

=

≈

V

195

.

k

A







≈µ

1

s

The power dissipation on the topside MOSFET can be
easily estimated. Using a Siliconix Si4420DY for example;
R
voltage with Tj (estimated) = 110°C at an elevated ambient
temperature:

The worst-case power disipated by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem­perature rise is:

A short-circuit to ground will result in a folded back current
of:

The worst-case power disipated by the synchronous
MOSFET under short-circuit conditions at elevated ambi­ent temperature and estimated 50°C junction temperature
rise is:

= 0.013Ω, C

DS(ON)

P

MAIN

P

SYNC

I

=

SC

P

SYNC

= 300pF. At maximum input

RSS

2

V

.

18

=

0 013 1 7 5 5 10 300

()

=
=

25

0 005

.

=
=

10 1 0 005 110 25

()+()

V

.

55

...

Ω

+

kHz W

310 0 65

..

55 18

.

129

mV

..

55 18

360

=

VV

−

.

V

55

W



1



+



Ω

2



VV

−

.

V

55
mW

.

[]

()()( )

.

10 1 48 0 013

()()

ns V

200 5 5

2

...

5 28 1 48 0 013

()()

()

2

VApF

2

..

A

()

H

µ

A

()



.



=



2

CC

°− °

Ω

A

528

.

()

Ω

Choosing 1% resistors; R1=13.2k and R2=16.5k yields an
output voltage of 1.80V.

18

which is much less than normal, full-load conditions.
Incidentally, since the load no longer dissipates power in
the shorted condition, total system power dissipation is
decreased by over 99%.

LTC1929

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APPLICATIO S I FOR ATIO

The duty factors when the peak RMS input current occurs
is at D = 0.25 and D = 0.75 according to Figure 4. Calculate
the worst-case required RMS current rating at the input
voltage that produces a duty cycle nearest to the peak.

CIN will require an RMS current rating of:

1855121218551

A

.
.

RMS

C requiredI A

IN RMS

The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
and multiplying by the factor obtained from Figure␣ 3 along
with the calculated duty factor. The output ripple in con­tinuous mode will be highest at the maximum input
voltage since the duty factor is <50%. The maximum
output current ripple is:

=

20

()

=

476

.



−−−






.



2

.



PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1929. These items are also illustrated graphically in
the layout diagram of Figure␣ 11. Check the following in
your layout:

1) Are the signal and power grounds segregated? The
LTC1929 signal ground pin should return to the (–) plate
of C
sources of the bottom N-channel MOSFETs, anodes of the
Schottky diodes, and (–) plates of CIN, which should have
as short lead lengths as possible.

2) Does the LTC1929 V
of C
plate(s) of C
connected between the V
any feedforward capacitor across R1 should be as close as
possible to the LTC1929.

separately. The power ground returns to the

OUT

+

pin connect to the (+) plate(s)

? Does the LTC1929 V

OUT

? The resistive divider R1, R2 must be

OUT

OS

DIFFOUT

–

pin connect to the (–)

OS

and signal ground and



V

∆∆I

COUT

I

COUTMAX

VmAmV

OUTRIPPLE RMS

An alternate calculation just uses the equation for output
ripple current at D = 1.8V/5.5 = 0.33:

∆I

RIPPLE

VmAmV

OUTRIPPLE RMS

OUT OUT

=−

1



fL



=

kHz H

310 2

()

=

097

.

A

=Ω

20 097 194

218

()

=

310 2

kHz H

=

099

.

A

=Ω

20 099 197





V



V



IN

V

18

..

µ

()

..

()

.

V

µ

()

..

()



033

.

at D F

33





066

.







−

1





=



1 2033 1 033

−




12033 1





=

%..



V

18

054

.



V

55

.



..

()

−

()

.

()

−
+








3) Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitors between
SENSE+ and SENSE– pin pairs should be as close as
possible to the LTC1929. Ensure accurate current sensing
with Kelvin connections.

4) Do the (+) plates of CIN connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the AC current to the MOSFETs. Keep the input
current path formed by the input capacitor, top and bottom
MOSFETs, and the Schottky diode on the same side of the
PC board in a tight loop to minimize conducted and
radiated EMI.

5) Is the INTVCC 1µF ceramic decoupling capacitor con-
nected closely between INTVCC and the power ground pin?
This capacitor carries the MOSFET driver peak currents. A
small value is used to allow placement immediately adja­cent to the IC.

6) Keep the switching nodes, SW1 (SW2), away from
sensitive small-signal nodes. Ideally the switch nodes
should be placed at the furthest point from the LTC1929.

7) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.

19

LTC1929

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APPLICATIO S I FOR ATIO

The diagram in Figure 9 illustrates all branch currents in a
2-phase switching regulator. It becomes very clear after
studying the current waveforms why it is critical to keep
the high-switching-current paths to a small physical size.
High electric and magnetic fields will radiate from these
“loops” just as radio stations transmit signals. The output
capacitor ground should return to the negative terminal of
the input capacitor and not share a common ground path
with any switched current paths. The left half of the circuit
gives rise to the “noise” generated by a switching regula­tor. The ground terminations of the sychronous MOSFETs
and Schottky diodes should return to the bottom plate(s)
of the input capacitor(s) with a short isolated PC trace
since very high switched currents are present. A separate
isolated path from the bottom plate(s) of the input
capacitor(s) should be used to tie in the IC power ground
pin (PGND) and the signal ground pin (SGND). This
technique keeps inherent signals generated by high cur­rent pulses from taking alternate current paths that have
finite impedances during the total period of the switching
regulator. External OPTI-LOOP compensation allows over­compensation for PC layouts which are not optimized but
this is not the recommended design procedure.

RMS current is calculated, higher effective duty factor
results and the peak current levels are divided as long as
the currents in each stage are balanced. Refer to Applica­tion Note 19 for a detailed description of how to calculate
RMS current for the single stage switching regulator.
Figures 3 and 4 help to illustrate how the input and output
currents are reduced by using an additional phase. The
input current peaks drop in half and the frequency is
doubled for this 2-phase converter. The input capacity
requirement is thus reduced theoretically by a factor of
four! Ceramic input capacitors with their unbeatably low
ESR characteristics can be used.

Figure 4 illustrates the RMS input current drawn from the
input capacitance vs the duty cycle as determined by the
ratio of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 50%
in a 2-phase solution due to the current splitting between
the two stages.

An interesting result of the 2-phase solution is that the V
which produces worst-case ripple current for the input
capacitor, V
duces zero input current ripple in the 2-phase design.

= VIN/2, in the single phase design pro-

OUT

IN

Simplified Visual Explanation of How a 2-Phase
Controller Reduces Both Input and Output RMS Ripple
Current

A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is divided by, and
the effective ripple frequency is multiplied up by the
number of phases used (assuming that the input voltage
is greater than the number of phases used times the output
voltage). The output ripple amplitude is also reduced by,
and the effective ripple frequency is increased by the
number of phases used. Figure 10 graphically illustrates
the principle.

The worst-case RMS ripple current for a single stage
design peaks at twice the value of the output voltage . The
worst-case RMS ripple current for a two stage design
results in peaks at 1/4 and 3/4 of input voltage. When the

The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V
term from the stage that has its bottom MOSFET on
subtracts current from the (VIN - V
resulting from the stage which has its top MOSFET on. The
output ripple current is:



−−

12 1

V

2

∆I

RIPPLE

where D is duty factor.
The input and output ripple frequency is increased by the

number of stages used, reducing the output capacity
requirements. When VIN is approximately equal to 2(V
as illustrated in Figures 3 and 4, very low input and output
ripple currents result.

OUT

=

fL

DD




−+

12 1



/L discharge current

OUT

)/L charging current

OUT



()



D




OUT

)

20

LTC1929

U

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APPLICATIO S I FOR ATIO

SW1

V

IN

R

IN

+

C

IN

SW2

L1

D1

L2

R

SENSE1

R

SENSE2

V

OUT

C

OUT

+

R

L

BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.

Figure 9. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator

SW V

I

CIN

I

COUT

D2

1929 F09

DUAL PHASESINGLE PHASE

SW1 V

SW2 V

I

L1

I

L2

I

CIN

I

COUT

RIPPLE

1929 F10

Figure 10. Single and 2-Phase Current Waveforms

21

LTC1929

C16

0.47µF

C3, C4: OS-CON 6SP680M

C18–C21: T510E108M004

L1, L2: SUMIDA CEP149-1R0MC

Q1–Q8: FDS6670A OR FDS7760A

28272625242322212019181716

15

123456789

1011121314

C17

1000pF

NC

TG1

SW1

BOOST1

V

IN

BG1

EXTV

CC

INTV

CC

PGND

BG2

BOOST2

SW2

TG2

AMPMD

RUN/SS

SENSE1

+

SENSE1–EAIN

PLLFLTR

PLLINNCI

TH

SGND

V

DIFFOUTVOS

–

V

OS

+

SENSE2–SENSE2

+

U1

LTC1929

Q8

Q7

Q6

Q5

Q4

L1

1µH

R4

0.002Ω

Q3

Q2

Q1

C12

1µF

C13

2.2µF

C8

0.47µF

D1

BAT54A

V

IN

+

V

IN

–

5V

C22

1µF

C23

1µF

+

C3

C2

1µF

C1, 1000pF

+

C4

12

3

C14

10µF

L2

1µH

R8

0.002Ω

R1

10Ω

1929 TA03

+

C18

R9

50Ω

+

C19

+

C20

+

C21

C24

10µF

V

OUT

+

V

OUT

–

V

OSENSE

+

V

OSENSE

–

1.6V/40A

REMOTE SENSE

R10

50Ω

R3

10k

C7

0.1µF

R2

2.7k

C9, 0.01µF

C10, 100pF

C11, 1nF

C15

470pF

R7

8.06k

R6

8.06k

R5, 10k

U

TYPICAL APPLICATIO S

Figure 11. 5V Input, 1.6V/40A CPU Power Supply

22

U

TYPICAL APPLICATIO S

100

90

80

70

EFFICIENCY (%)

60

VIN = 5V

= 1.6V

V

OUT

50

5 10 15 20 25 30 35 40

0

LOAD CURRENT (A)

1929 TA04

Figure 12. Efficiency Plot for Circuit of Figure 11

LTC1929

PACKAGE DESCRIPTIO

0.205 – 0.212**
(5.20 – 5.38)

U

Dimensions in inches (millimeters) unless otherwise noted.

G Package

28-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

0.397 – 0.407*

(10.07 – 10.33)

2526 22 21 20 19 181716 1523242728

12345678 9 10 11 12 1413

° – 8°

0

0.301 – 0.311
(7.65 – 7.90)

0.068 – 0.078
(1.73 – 1.99)

0.005 – 0.009
(0.13 – 0.22)

*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0.022 – 0.037
(0.55 – 0.95)

0.0256
(0.65)

BSC

0.010 – 0.015
(0.25 – 0.38)

0.002 – 0.008
(0.05 – 0.21)

G28 SSOP 0694

23

LTC1929

TYPICAL APPLICATIO

1000pF

0.1µF

13.2k

INTV

CC

33pF

10k

100pF

220pF

16.5k

10
11
12
13
14

1000pF

1
2
3
4
5
6
7
8
9

U

RUN/SS
SENSE1
SENSE1
EAIN
PLLFLTR
PLLIN
NC
I

TH

SGND
V

DIFFOUT

–

V

OS

+

V

OS

SENSE2
SENSE2

+
–

LTC1929

–
+

TG1

SW1

BOOST1

V

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

AMPMD

L1

28

NC

27
26
25
24

IN

23
22

CC

21

CC

20
19
18
17
16
15

0.22µF

1µF,25V

D4

0.22µF

D3

10Ω

0.1µF

4.7µF

6.3V

+

L2

22µF
50V

0.005Ω

M2M1

M4M3

0.005Ω

GND

D1
MBRM
140T3

C

D2
MBRM
140T3

OUT

+

2X270µF
2V

V

IN

5V TO
28V

V

OUT

1.8V/20A

VIN: 5V TO 28V
V

: 1.8V/20A

OUT

SWITCHING FREQUENCY = 310kHz

MI – M4: FAIRCHILD FDS6680A
L1 – L2: 2µH SUMIDA CEE125-2R1NC
C

: PANASONIC EEFUEOD271R

OUT

D3, D4: CENTRAL CMDSH-3TR

1929 TA02

Figure 13. 1.8V/20A CPU Power Supply

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≤ 6V

24

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone] ● www.linear-tech.com

1929i LT/TP 0899 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1999