Datasheet LTC1878 Datasheet (Linear Technology)

LTC1878

Final Electrical Specifications

OUTPUT CURRENT (mA)

80

75

EFFICIENCY (%)

85

90

95

100

0.1 10 100 1000

1878 TA02

70

1

VIN = 6V

VIN = 4.2V

VIN = 3.6V

Burst Mode OPERATION
V

OUT

= 3.3V

L = 10µH

High Efficiency

Monolithic Synchronous

Step-Down Regulator

FEATURES

■

High Efficiency: Up to 95%

■

Very Low Quiescent Current: Only 10µA
During Operation

■

600mA Output Current at VIN = 3.3V

■

2.65V to 6V Input Voltage Range

■

550kHz Constant Frequency Operation

■

Synchronizable from 400kHz to 700kHz

■

Selectable Burst ModeTM Operation/
Pulse Skipping Mode

■

No Schottky Diode Required

■

Low Dropout Operation: 100% Duty Cycle

■

0.8V Reference Allows Low Output Voltages

■

Shutdown Mode Draws < 1µA Supply Current

■

±2% Output Voltage Accuracy

■

Current Mode Control for Excellent Line and
Load Transient Response

■

Overcurrent and Overtemperature Protected

■

Available in 8-Lead MSOP Package

U

APPLICATIO S

■

Cellular Telephones

■

Wireless Modems

■

Personal Information Appliances

■

Portable Instruments

■

Distributed Power Systems

■

Battery-Powered Equipment

U

May 2000

DESCRIPTIO

The LTC®1878 is a high efficiency monolithic synchro­nous buck regulator using a constant frequency, current
mode architecture. Supply current during operation is
only 10µA and drops to < 1µA in shutdown. The 2.65V to
6V input voltage range makes the LTC1878 ideally suited
for single Li-Ion battery-powered applications. 100% duty
cycle provides low dropout operation, extending battery
life in portable systems.

Switching frequency is internally set at 550kHz, allowing
the use of small surface mount inductors and capacitors.
For noise sensitive applications the LTC1878 can be
externally synchronized from 400kHz to 700kHz. Burst
Mode operation is inhibited during synchronization or
when the SYNC/MODE pin is pulled low, preventing low
frequency ripple from interfering with audio circuitry.

The internal synchronous switch increases efficiency and
eliminates the need for an external Schottky diode. Low
output voltages are easily supported with the 0.8V feed­back reference voltage. The LTC1878 is available in a
space saving 8-lead MSOP package.

For higher input voltage (12V abs max) applications, refer
to the LTC1877 data sheet.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a trademark of Linear Technology Corporation.

TYPICAL APPLICATIO

High Efficiency Step-Down Converter

V

IN

2.65V
TO 6V

22µF**

CER

220pF

*

TOKO D62CB A920CY-100M

**

TAIYO-YUDEN CERAMIC JMK325BJ226MM

***

SANYO POSCAP 6TPA47M

†

V

CONNECTED TO VIN FOR 2.65V < VIN < 3.3V

OUT

7

SYNC

6

V

IN

1

RUN

2

I

TH

LTC1878

GND

4

SW

U

10µH*

5

20pF

V

OUT

3.3V

†

Efficiency vs Output Load Current

+

47µF***

887k

3

V

FB

280k

1878 TA01

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

1

LTC1878

1
2
3
4

8
7
6
5

TOP VIEW

MS8 PACKAGE

8-LEAD PLASTIC MSOP

PLL LPF
SYNC/MODE
V

IN

SW

RUN

I

TH

V

FB

GND

WWWU

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

UU

W

(Note 1)

Input Supply Voltage (VIN)...........................– 0.3V to 7V

ITH, PLL LPF Voltage ................................–0.3V to 2.7V

RUN, VFB Voltages ......................................–0.3V to V

SYNC/MODE Voltage ..................................–0.3V to V

IN
IN

ORDER PART

NUMBER

LTC1878EMS8

SW Voltage ................................... –0.3V to (VIN + 0.3V)

P-Channel MOSFET Source Current (DC) ........... 800mA

N-Channel MOSFET Sink Current (DC) ............... 800mA

Peak SW Sink and Source Current ........................ 1.5A

T

= 125°C, θJA = 150°C/W

JMAX

MS8 PART MARKING

LTNX

Operating Ambient Temperature Range

(Note 2) .................................................. – 40°C to 85°C

Consult factory for Industrial and Military grade parts.

Junction Temperature (Note 3)............................ 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 3.6V unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

VFB

V

FB

∆V

OVL

∆V

FB

V

LOADREG

V

IN

I

Q

f

OSC

f

SYNC

I

PLL LPF

R

PFET

R

NFET

Feedback Current (Note 4) ● 430 nA
Regulated Output Voltage (Note 4) 0°C ≤ TA ≤ 85°C 0.784 0.8 0.816 V

(Note 4) –40°C ≤ T

Output Overvoltage Lockout ∆V
Reference Voltage Line Regulation VIN = 2.65V to 6V (Note 4) 0.05 0.2 %/V
Output Voltage Load Regulation Measured in Servo Loop; V

Input Voltage Range ● 2.65 6 V
Input DC Bias Current (Note 5)

Pulse Skipping Mode 2.65V < V
Burst Mode Operation V
Shutdown V

Oscillator Frequency VFB = 0.8V 495 550 605 kHz

SYNC Capture Range 400 700 kHz
Phase Detector Output Current

Sinking Capability f
Sourcing Capability f

R

of P-Channel MOSFET ISW = 100mA 0.5 0.7 Ω

DS(ON)

R

of N-Channel MOSFET ISW = –100mA 0.6 0.8 Ω

DS(ON)

= V

OVL

OVL

Measured in Servo Loop; V

IN

SYNC/MODE

= 0V, VIN = 6V 0 1 µA

RUN

V

= 0V 80 kHz

FB

< f

PLLIN

OSC

> f

PLLIN

OSC

≤ 85°C ● 0.74 0.8 0.84 V

A

– V

< 6V, V
= VIN, I

FB

= 0.9V ● 0.1 0.5 %

ITH

= 1.6V ● –0.1 –0.5 %

ITH

SYNC/MODE
OUT

= 0V, I

= 0A 10 15 µA

= 0A 230 350 µA

OUT

● 20 50 110 mV

● 3 10 20 µA

● –3 –10 –20 µA

2

LTC1878

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 3.6V unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

PK

I

LSW

V

SYNC/MODE

I

SYNC/MODE

V

RUN

I

RUN

Peak Inductor Current VIN = 3.3V, VFB = 0.7V, Duty Cycle < 35% 0.8 1.0 1.25 A
SW Leakage V
SYNC/MODE Threshold V

= 0V, VSW = 0V or 6V, VIN = 6V ±0.01 ±1 µA

RUN

SYNC/MODE

Rising ● 0.2 1.0 1.5 V

SYNC/MODE Leakage Current ±0.01 ±1 µA
RUN Threshold V

Rising ● 0.2 0.7 1.5 V

RUN

RUN Input Current ±0.01 ±1 µA

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The LTC1878E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating

Note 4: The LTC1878 is tested in a feedback loop which servos VFB to the
balance point for the error amplifier (V

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency.
temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: T
dissipation P

is calculated from the ambient temperature TA and power

J

according to the following formulas:

D

LTC1878EMS8: TJ = TA + (PD)(150°C/W)

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Input Voltage

100

95

90

85

80

75

EFFICIENCY (%)

70

65

60

I

= 100mA

LOAD

= 300mA

I

LOAD

I

Burst Mode OPERATION

= 2.5V

V

OUT

L = 10µH

34 6

2

INPUT VOLTAGE (V)

LOAD

= 0.1mA

5

I

LOAD

I

LOAD

= 10mA

= 1mA

7

8

1878 G01

Efficiency vs Output Current Efficiency vs Output Current

100

VIN = 3.6V

90
80
70
60
50
40

EFFICIENCY (%)

30
20
10

0

VIN = 4.2V

VIN = 3.6V

VIN = 4.2V

PULSE SKIPPING MODE
Burst Mode OPERATION

= 1.8V

V

OUT

L = 10µH

0.1 10 100 1000

1
OUTPUT CURRENT (mA)

1878 G02

= 1.2V).

ITH

95

90

L = 15µH

85

80

75

70

EFFICIENCY (%)

65

60

Burst Mode OPERATION

55

V

IN

V

OUT

50

0.1 10 100 1000

L = 10µH

= 6V

= 2.5V

1
OUTPUT CURRENT (mA)

1878 G03

3

LTC1878

TEMPERATURE (°C)

–50

300

250

200

150

100

50

0

25 75

1878 G12

–25 0

50 125100

SUPPLY CURRENT (µA)

PULSE SKIPPING

MODE

Burst Mode

OPERATION

VIN = 3.6V

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Output Current

95

90

85

80

EFFICIENCY (%)

75

70

65

0.1 10 100 1000

VIN = 3V

VIN = 3.6V

VIN = 4.2V

VIN = 6V

1
OUTPUT CURRENT (mA)

V

OUT

L = 10µH

Oscillator Frequency
vs Supply Voltage

605
595
585
575
565
555
545
535
525
515

OSCILLATOR FREQUENCY (kHz)

505
495

0

2

4

SUPPLY VOLTAGE (V)

6

= 1.8V

1878 G04

1878 G07

0.814

0.809

0.804

0.799

0.794

REFERENCE VOLTAGE (V)

0.789

0.784

1.83

1.82

1.81

1.80

1.79

OUTPUT VOLTAGE (V)

1.78

8

1.77

Reference Voltage

Reference Voltage
vs Temperature

vs Temperature

VIN = 3.6V

–50

–25 0

50 100 125

25 75

TEMPERATURE (°C)

1878 G05

605
595
585
575
565
555
545
535

FREQUENCY (kHz)

525
515
505
495

Output Voltage vs Load Current R

0.9

0.8

0.7

0.6

(Ω)

0.5

0.4

DS(ON)

R

0.3

PULSE SKIPPING MODE
V

= 3.6V

IN

L = 10µH

100 300

200

0

400

LOAD CURRENT (mA)

700

600

800

1878 G08

500 900

0.2

0.1

Oscillator Frequency
vs Temperature

VIN = 3.6V

–25

–50

DS(ON)

0

0

TEMPERATURE (°C)

vs Input Voltage

MAIN

SWITCH

10

3

2

INPUT VOLTAGE (V)

5025

SYNCHRONOUS
SWITCH

5678

4

10075

125

1878 G06

1878 G09

DC Supply Current

R

vs Temperature

DS(ON)

1.2
SYNCHRONOUS SWITCH

MAIN SWITCH

1.1

1.0

0.9

(Ω)

0.8

0.7

DS(ON)

R

0.6

0.5

0.4

0.3

4

–50 –25

0 25 50 125
TEMPERATURE (°C)

VIN = 3V

VIN = 5V

75 100

1878 G10

vs Input Voltage

250

V

= 1.8V

OUT

200

150

100

DC SUPPLY CURRENT (µA)

50

0

01

PULSE SKIPPING

MODE

Burst Mode

OPERATION

4

3

2

INPUT VOLTAGE (V)

6

7

1878 G11

5

DC Supply Current
vs Temperature

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1878

Switch Leakage vs Temperature

2.5
VIN = 7V

RUN = 0V

2.0

1.5

1.0

SWITCH LEAKAGE (µA)

0.5

0

–25 0 50

–50

SYNCHRONOUS

25

TEMPERATURE (°C)

Pulse Skipping Mode Operation

SW

5V/DIV

V

OUT

20mV/DIV

AC

COUPLED

I

L

200mA/DIV

MAIN

SWITCH

SWITCH

75 100 125

1878 G13

1.2
RUN = 0V

1.0

0.8

0.6

0.4

SWITCH LEAKAGE (nA)

0.2

0

13

0

Start-Up from Shutdown Load Step Response

RUN

2V/DIV

V

OUT

1V/DIV

I

L

500mA/DIV

SYNCHRONOUS

SWITCH

MAIN

SWITCH

24

INPUT VOLTAGE (V)

5

Burst Mode OperationSwitch Leakage vs Input Voltage

SW

5V/DIV

V

OUT

50mV/DIV

AC

COUPLED

I

L

200mA/DIV

6

7

1878 G20

8

V

OUT

50mV/DIV

COUPLED

500mA/DIV

1V/DIV

AC

I

L

I

TH

V

= 4.2V

IN

V

= 1.5V

OUT

L = 10µH

C

IN

C

OUT

I

LOAD

10µs/DIV

= 22µF

= 47µF

= 50mA

1878 G14

V

= 4.2V

IN

V

= 1.5V

OUT

L = 10µH

C

IN

C

OUT

I

LOAD

V

OUT

100mV/DIV

COUPLED

500mA/DIV

I

1V/DIV

1µs/DIV

= 22µF

= 47µF

= 50mA

Load Step Response

AC

I

L

TH

V

= 3.6V

IN

= 1.5V

V

OUT

L = 10µH

= 22µF

C

IN

C

OUT

I

LOAD

PULSE SKIPPING MODE

1878 G15

40µs/DIV
= 47µF

= 50mA TO 500mA

= 3.6V

V

IN

= 1.5V

V

OUT

L = 10µH

1878 G18

C
C
I

LOAD

IN
OUT

40µs/DIV

= 22µF

= 47µF

= 500mA

V

OUT

100mV/DIV

COUPLED

500mA/DIV

I

1V/DIV

1878 G16

Load Step Response

AC

I

L

TH

V

= 3.6V

IN

= 1.5V

V

OUT

L = 10µH

= 22µF

C

IN

C

OUT

I

LOAD

Burst Mode OPERATION

V

= 3.6V

IN

= 1.5V

V

OUT

L = 10µH

40µs/DIV
= 47µF

= 50mA TO 500mA

40µs/DIV

= 22µF

C

IN

= 47µF

C

OUT

I

= 200mA TO 500mA

LOAD

PULSE SKIPPING MODE

1878 G19

1878 G17

5

LTC1878

U

UU

PI FU CTIO S

RUN (Pin 1): Run Control Input. Forcing this pin below

0.4V shuts down the LTC1878. In shutdown all functions
are disabled drawing <1µA supply current. Forcing this
pin above 1.2V enables the LTC1878. Do not leave RUN
floating.

ITH (Pin 2): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.5V
to 1.9V.

VFB (Pin 3): Feedback Pin. Receives the feedback voltage
from an external resistive divider across the output.

GND (Pin 4): Ground Pin.
SW (Pin 5): Switch Node Connection to Inductor. This pin

U

U

W

FU CTIO AL DIAGRA

connects to the drains of the internal main and synchro­nous power MOSFET switches.

VIN (Pin 6): Main Supply Pin. Must be closely decoupled
to GND, Pin 4.

SYNC/MODE (Pin 7): External Clock Synchronization and
Mode Select Input. To synchronize with an external clock,
apply a clock with a frequency between 400kHz and
700kHz. To select Burst Mode operation, tie to VIN. Ground­ing this pin selects pulse skipping mode. Do not leave this
pin floating.

PLL LPF (Pin 8): Output of the Phase Detector and Control
Input of Oscillator. Connect a series RC lowpass network
from this pin to ground if externally synchronized. If
unused, this pin may be left open.

PLL LPF

8

SYNC/MODE

7

0.6V

3

V

FB

RUN

1

BURST

DEFEAT

–
+

V

0.8V REF

X

IN

SHUTDOWN

Y = “0” ONLY WHEN X IS A CONSTANT “1”

Y

SLOPE

–

OVDET

+

COMP

+

EA

–

V

Ω

VCO

FREQ

SHIFT

0.85V

V

REF

0.8V

gm = 0.5m

IN

–
+

OSC

SLEEP

V

V

IN

0.8V

V

6

IN

EN

–

0.45V

IN

I

2

+

S

R

RS LATCH

TH

BURST

Q

Q

SLEEP

SWITCHING

LOGIC

AND

BLANKING

CIRCUIT

–

I

COMP

ANTI-

SHOOT-

THRU

I

RCMP

+

+
–

6Ω

SW

5

GND

4

1878 BD

6

OPERATIO

LTC1878

U

Main Control Loop

The LTC1878 uses a constant frequency, current mode
step-down architecture. Both the main (P-channel
MOSFET) and synchronous (N-channel MOSFET) switches
are internal. During normal operation, the internal top
power MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the current com­parator, I
current at which I
the voltage on the ITH pin, which is the output of error
amplifier EA. The VFB pin, described in the Pin Functions
section, allows EA to receive an output feedback voltage
from an external resistive divider. When the load current
increases, it causes a slight decrease in the feedback
voltage relative to the 0.8V reference, which in turn,
causes the I
tor current matches the new load current. While the top
MOSFET is off, the bottom MOSFET is turned on until
either the inductor current starts to reverse as indicated by
the current reversal comparator I
the next clock cycle.

, resets the RS latch. The peak inductor

COMP

resets the RS latch is controlled by

COMP

voltage to increase until the average induc-

TH

, or the beginning of

RCMP

BURST comparator trips, causing the internal sleep line to
go high and forces off both power MOSFETs. The I
is then disconnected from the output of the EA amplifier
and parked a diode voltage above ground.

In sleep mode, both power MOSFETs are held off and a
majority of the internal circuitry is partially turned off,
reducing the quiescent current to 10µA. The load current
is now being supplied solely from the output capacitor.
When the output voltage drops, the I
the output of the EA amplifier and the top MOSFET is again
turned on and this process repeats.

Short-Circuit Protection

When the output is shorted to ground, the frequency of the
oscillator is reduced to about 80kHz, 1/7 the nominal
frequency. This frequency foldback ensures that the
inductor current has ample time to decay, thereby pre­venting runaway. The oscillator’s frequency will progres­sively increase to 550kHz (or the synchronized frequency)
when V

rises above 0.3V.

FB

pin reconnects to

TH

TH

pin

Comparator OVDET guards against transient overshoots
>6.25% by turning the main switch off and keeping it off
until the fault is removed.

Burst Mode Operation

The LTC1878 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
tie the SYNC/MODE pin to V
(V

SYNC/MODE

enable PWM pulse skipping mode, connect the SYNC/
MODE pin to GND. In this mode, the efficiency is lower at
light loads, but becomes comparable to Burst Mode
operation when the output load exceeds 50mA. The ad­vantage of pulse skipping mode is lower output ripple and
less interference to audio circuitry.

When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 250mA,
even though the voltage at the I
value. The voltage at the I
average current is greater than the load requirement. As
the I

TH

> 1.5V). To disable Burst Mode operation and

voltage drops below approximately 0.45V, the

or connect it to a logic high

IN

pin indicates a lower

TH

pin drops when the inductor’s

TH

Frequency Synchronization

A phase-locked loop (PLL) is available on the LTC1878 to
allow the internal oscillator to be synchronized to an
external source connected to the SYNC/MODE pin. The
output of the phase detector at the PLL LPF pin operates
over a 0V to 2.4V range corresponding to 400kHz to
700kHz. When locked, the PLL aligns the turn-on of the top
MOSFET to the rising edge of the synchronizing signal.

When the LTC1878 is clocked by an external source, Burst
Mode operation is disabled; the LTC1878 then operates in
PWM pulse skipping mode. In this mode, when the output
load is very low, current comparator I
tripped for several cycles and force the main switch to stay
off for the same number of cycles. Increasing the output
load slightly allows constant frequency PWM operation to
resume. This mode exhibits low output ripple as well as
low audio noise and reduced RF interference while provid­ing reasonable low current efficiency.

Frequency synchronization is inhibited when the feedback
voltage V
from interfering with the frequency foldback for short­circuit protection.

is below 0.6V. This prevents the external clock

FB

COMP

may remain

7

LTC1878

OPERATIO

U

Dropout Operation

When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi­mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle until it reaches 100% duty cycle. The output voltage
will then be determined by the input voltage minus the
voltage drop across the internal P-channel MOSFET and
the inductor.

Low Supply Operation

The LTC1878 is designed to operate down to an input
supply voltage of 2.65V although the maximum allowable
output current is reduced at this low voltage. Figure 1
shows the reduction in the maximum output current as a
function of input voltage for various output voltages.

1200

L = 10µH

1000

V

= 1.5V

OUT

800

600

400

V

= 2.5V

OUT

= 3.3V

V

OUT

Another important detail to remember is that at low input
supply voltages, the R

of the P-channel switch

DS(ON)

increases. Therefore, the user should calculate the power
dissipation when the LTC1878 is used at 100% duty cycle
with a low input voltage (see Thermal Considerations in
the Applications Information section).

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in constant fre­quency architectures by preventing subharmonic oscilla­tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. As a result, the
maximum inductor peak current is reduced for duty cycles
>40%. This is shown in the decrease of the inductor peak
current as a function of duty cycle graph in Figure 2.

1100

VIN = 3.3V

1000

900

800

MAX OUTPUT CURRENT (mA)

200

0

2.5

Figure 1. Maximum Output Current vs Input Voltage

4.5 5.5 6.5

3.5
INPUT VOLTAGE (V)

7.5

1878 F01

WUUU

APPLICATIO S I FOR ATIO

The basic LTC1878 application circuit is shown on the first
page. External component selection is driven by the load
requirement and begins with the selection of L followed by
C

and C

IN

Inductor Value Calculation

The inductor selection will depend on the operating fre­quency of the LTC1878. The internal nominal frequency is
550kHz, but can be externally synchronized from 400kHz
to 700kHz.

OUT

.

700

MAXIMUM INDUCTOR PEAK CURRENT (mA)

600

Figure 2. Maximum Inductor Peak Current vs Duty Cycle

20

0

DUTY CYCLE (%)

60

80

40

100

1878 F02

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. However, oper­ating at a higher frequency generally results in lower
efficiency because of increased internal gate charge losses.

The inductor value has a direct effect on ripple current. The
ripple current ∆IL decreases with higher inductance or
frequency and increases with higher VIN or V

OUT

.

8

WUUU

APPLICATIO S I FOR ATIO

LTC1878

∆=

I

1

L OUT

fL

()()



1

V

−





V

OUT

V

IN






(1)

Accepting larger values of ∆IL allows the use of low
inductance, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ∆IL = 0.4(I

MAX

).

The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
250mA. Lower inductor values (higher ∆IL) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.

Inductor Core Selection

Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will
increase.

New designs for surface mount inductors are available
from Coiltronics, Coilcraft, Dale and Sumida.

C

IN

and C

Selection

OUT

In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle V

OUT/VIN

. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:

OUT

12/

, where

VVV

()

[]

CI

required I

IN OMAX

RMS

≅

This formula has a maximum at V
I

= I

RMS

/2. This simple worst-case condition is com-

OUT

OUT IN OUT

IN

−

V

IN

= 2V

monly used for design because even significant deviations
do not offer much relief. Note the capacitor manufacturer’s
ripple current ratings are often based on 2000 hours of life.
This makes it advisable to further derate the capacitor, or
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the manufacturer if there is any question.

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically, once the ESR require­ment is satisfied, the capacitance is adequate for filtering.
The output ripple ∆V

is determined by:

OUT

Ferrite designs have very low core losses and are pre­ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur­rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!

Kool Mµ (from Magnetics, Inc.) is a very good, low loss
core material for toroids with a “soft” saturation character­istic. Molypermalloy is slightly more efficient at high
(>200kHz) switching frequencies but quite a bit more
expensive. Toroids are very space efficient, especially
when you can use several layers of wire, while inductors
wound on bobbins are generally easier to surface mount.

∆≅∆ +

V I ESR

OUT L





8

where f = operating frequency, C



fC

1

OUT






= output capacitance

OUT

and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. For the LTC1878, the general rule for
proper operation is:

C

required ESR < 0.25Ω

OUT

The choice of using a smaller output capacitance
increases the output ripple voltage due to the frequency
dependent term but can be compensated for by using
capacitor(s) of very low ESR to maintain low ripple
voltage. The ITH pin compensation components can be

Kool Mµ is a registered trademark of Magnetics, Inc.

9

LTC1878

WUUU

APPLICATIO S I FOR ATIO

opti

mized to provide stable high performance transient

response regardless of the output capacitor selected.
ESR is a direct function of the volume of the capacitor.

Manufacturers such as Taiyo-Yuden, AVX, Kemet, Sprague
and Sanyo should be considered for high performance
capacitors. The POSCAP solid electrolytic chip capacitor
available from Sanyo is an excellent choice for output bulk
capacitors due to its low ESR/size ratio. Once the ESR
requirement for C
rating generally far exceeds the I

has been met, the RMS current

OUT

RIPPLE(P-P)

requirement.

external and internal oscillators. This type of phase detec­tor will not lock up on input frequencies close to the har­monics of the VCO center frequency. The PLL hold-in range
∆fH is equal to the capture range, ∆fH = ∆fC = ±150kHz.

The output of the phase detector is a pair of complemen­tary current sources charging or discharging the external
filter network on the PLL LPF pin. The relationship
between the voltage on the PLL LPF pin and operating
frequency is shown in Figure 4. A simplified block diagram
is shown in Figure 5.

When using tantalum capacitors, it is critical that they are
surge tested for use in switching power supplies. A good
choice is the AVX TPS series of surface mount tantalum,
available in case heights ranging from 2mm to 4mm. Other
capacitor types include KEMET T510 and T495 series and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.

Output Voltage Programming

The output voltage is set by a resistive divider according
to the following formula:

R

2

VV

=+

OUT



08 1

.










R

1

(2)

The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 3.

LTC1878

V

GND

0.8V ≤ V

FB

OUT

≤ 6V

R2

R1

1878 F03

800

700

600

500

400

OSCILLATOR FREQUENCY (kHz)

300

0

Figure 4. Relationship Between Oscillator
Frequency and Voltage at PLL LPF Pin

PHASE
DETECTOR

SYNC/

MODE

DIGITAL

PHASE/

FREQUENCY

DETECTOR

0.8 1.2 1.6

0.4

2.4V

V

PLL LPF

(V)

PLL LPF

1878 F04

R

LP

VCO

2.0

C

LP

Figure 3. Setting the LTC1878 Output Voltage

Phase-Locked Loop and Frequency Synchronization

The LTC1878 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external frequency source. The frequency range
of the voltage-controlled oscillator is 400kHz to 700kHz. The
phase detector used is an edge sensitive digital type that
provides zero degrees phase shift between the

10

1878 F05

Figure 5. Phase-Locked Loop Block Diagram

If the external frequency (V

SYNC/MODE

) is greater than
550kHz, the center frequency, current is sourced
continuously, pulling up the PLL LPF pin. When the
external frequency is less than 550kHz, current is sunk
continuously, pulling down the PLL LPF pin. If the

LOAD CURRENT (mA)

0.1 1

0.00001

POWER LOST (W)

0.001

1

10 100 1000

1878 F06

0.0001

0.01

0.1

V

OUT

= 1.5V

V

OUT

= 2.5V

V

OUT

= 3.3V

V

IN

= 4.2V

L = 10µH

Burst Mode OPERATION

WUUU

APPLICATIO S I FOR ATIO

external and internal frequencies are the same but exhibit
a phase difference, the current sources turn on for an
amount of time corresponding to the phase difference.
Thus the voltage on the PLL LPF pin is adjusted until the
phase and frequency of the external and internal oscilla­tors are identical. At this stable operating point the phase
comparator output is high impedance and the filter
capacitor CLP holds the voltage.

LTC1878

The loop filter components CLP and R
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
component’s CLP and RLP determine how fast the loop
acquires lock. Typically R

0.01µF. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallows setting the internal oscillator frequency by a DC
voltage on the V

Efficiency Considerations

The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:

where L1, L2, etc. are the individual losses as a percentage
of input power.

Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC1878 circuits: VIN quiescent current and I2R
losses. The VIN quiescent current loss dominates the
efficiency loss at very low load currents whereas the I2R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 6.

1. The VIN quiescent current is due to two components:

smooth out the

LP

PLL LPF

LP

pin.

= 10k and C

is 2200pF to

LP

Efficiency = 100% – (L1 + L2 + L3 + ...)

the DC bias current as given in the electrical character­istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the

Figure 6. Power Lost vs Load Current

internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge dQ moves from VIN to ground. The resulting
dQ/dt is the current out of V
the DC bias current. In continuous mode, I

that is typically larger than

IN

GATECHG

=
f(QT + QB) where QT and QB are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to VIN and thus
their effects will be more pronounced at higher supply
voltages.

2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R

and the duty cycle

DS(ON)

(DC) as follows:

R

The R

SW

DS(ON)

= (R

DS(ON)TOP

for both the top and bottom MOSFETs can

)(DC) + (R

DS(ON)BOT

)(1 – DC)

be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.

Other losses including CIN and C

ESR dissipative

OUT

losses and inductor core losses generally account for less
than 2% total additional loss.

11

LTC1878

WUUU

APPLICATIO S I FOR ATIO

Thermal Considerations

In most applications the LTC1878 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC1878 is running at high ambient tempera­ture with low supply voltage and high duty cycles, such
as in dropout, the heat dissipated may exceed the maxi­mum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.

To avoid the LTC1878 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera­ture rise is given by:

TR = (PD)(θJA)

where PD is the power dissipated by the regulator and q

JA

is the thermal resistance from the junction of the die to the
ambient temperature.

The junction temperature, TJ, is given by:

TJ = TA + T

R

where TA is the ambient temperature.
As an example, consider the LTC1878 in dropout at an

input voltage of 3V, a load current of 500mA, and an
ambient temperature of 70°C. From the typical perfor­mance graph of switch resistance, the R

DS(ON)

of the

P-channel switch at 70°C is approximately 0.7Ω. There­fore, power dissipated by the part is:

LOAD

2

• R

DS(ON)

= 0.175W

PD = I

For the MSOP package, the θJA is 150°C/W. Thus, the
junction temperature of the regulator is:

TJ = 70°C + (0.175)(150) = 96°C

which is below the maximum junction temperature of
125°C.

Note that at higher supply voltages, the junction tempera­ture is lower due to reduced switch resistance (R

DS(ON)

).

Checking Transient Response

The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to (∆I
resistance of C
discharge C

• ESR), where ESR is the effective series

LOAD

OUT

, which generates a feedback error signal.

OUT

The regulator loop then acts to return V
state value. During this recovery time V

immediately shifts by an amount

OUT

. ∆I

also begins to charge or

LOAD

to its steady-

OUT

can be moni-

OUT

tored for overshoot or ringing that would indicate a stabil­ity problem. The internal compensation provides adequate
compensation for most applications. But if additional
compensation is required, the I

pin can be used for

TH

external compensation using RC, CC1 as shown in
Figure 7. (The 220pF capacitor, CC2, is typically needed for
noise decoupling.)

12

OPTIONAL

R

C

C

C2

LTC1878

1

C

C1

RUN

2

I

SYNC/MODE

TH

3

V

FB

4

GND

Figure 7. LTC1878 Layout Diagram

PLL LPF

V

SW

8

7

6

IN

5

BOLD LINES INDICATE
HIGH CURRENT PATHS

L1

R2

R1

+

+

+

V

+

OUT

C

OUT

–

1878 F07

V

IN

C

IN

–

WUUU

APPLICATIO S I FOR ATIO

LTC1878

A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.

PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1878. These items are also illustrated graphically in
the layout diagram of Figure 7. Check the following in your
layout:

1. Are the signal and power grounds segregated? The
LTC1878 signal ground consists of the resistive
divider, the optional compensation network (RC and
CC1) and CC2. The power ground consists of the (–)
plate of CIN, the (–) plate of C
LTC1878. The power ground traces should be kept
short, direct and wide. The signal ground and power
ground should converge to a common node in a star­ground configuration.

, causing a rapid drop in V

OUT

. No regulator can

OUT

and Pin 4 of the

OUT

LOAD

).

Design Example

As a design example, assume the LTC1878 is used in a
single lithium-ion battery-powered cellular phone applica­tion. The input voltage will be operating from a maximum
of 4.2V down to about 2.7V. The load current requirement
is a maximum of 0.3A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is

2.5V. With this information we can calculate L using
equation (1),

L

Substituting V
f = 550kHz in equation (3) gives:

L

A 15µH inductor works well for this application. For best
efficiency choose a 1A inductor with less than 0.25Ω
series resistance.

C

will require an RMS current rating of at least 0.15A at

IN

temperature and C

0.25Ω. In most applications, the requirements for these
capacitors are fairly similar.

1

=

fI

()∆()

L

25

kHz mA

550 120



V

OUT

V

.

()..

−

1



OUT



= 2.5V, V






will require an ESR of less than

OUT



V

OUT



V



IN

= 4.2V, ∆IL=120mA and

IN



V

25

1

42

=µ

15 3



V



.

(3)

H=−

2. Does the VFB pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con­nected between the (+) plate of C

3. Does the (+) plate of C
possible? This capacitor provides the AC current to the
internal power MOSFETs.

4. Keep the switching node SW away from sensitive small
signal nodes.

connect to VIN as closely as

IN

and signal ground.

OUT

For the feedback resistors, choose R1 = 412k. R2 can
then be calculated from equation (2) to be:



V

R

2

Figure 8 shows the complete circuit along with its effi­ciency curve.

OUT



08



.



R k use

1 1 875 5 8=−

=





. ; 87k

13

LTC1878

OUTPUT CURRENT (mA)

75

EFFICIENCY (%)

80

85

90

95

0.1 10 100 1000

70

1

V

OUT

= 2.5V

L = 15µH

VIN = 3V

VIN = 4.2V

VIN = 3.6V

1878 F08b

WUUU

APPLICATIO S I FOR ATIO

220pF

412k

LTC1878

1

RUN

2

I

3

V

4

GND

TH

FB

PLL LPF

SYNC/MODE

SW

887k

20pF

Figure 8. Single Lithium-Ion to 2.5V/0.3A Regulator from Design Example

22µF**

8

CER

7
6

V

IN

15µH*

5

+

47µF***

SUMIDA CD54-150

*

TAIYO-YUDEN CERAMIC JMK325BJ226MM

**

SANYO POSCAP 6TPA47M

***

U

TYPICAL APPLICATIO S

1878 F08a

V

IN

2.65V
TO 4.2V

V

OUT

2.5V

220pF

14

220pF

LTC1878

1

RUN

I

TH

V

FB

GND

PLL LPF

SYNC/MODE

2

3

4

TOKO D62CB A920CY-100M

*

TAIYO-YUDEN CERAMIC JMK325BJ226MM

**

3- to 4-Cell NiCd/NiMH to 1.8V/0.5A Regulator

LTC1878

1

RUN

I

TH

V

FB

GND

PLL LPF

SYNC/MODE

2

3

4

TOKO D62CB A920CY-100M

*

TAIYO-YUDEN CERAMIC JMK325BJ226MM

**

Single Li-Ion to 2.5V/0.6A Regulator

Using All Ceramic Capacitors

8

7

6

V

IN

SW

10µH*

5

20pF

887k

412k

1878 TA03

Using All Ceramic Capacitors

8

7

6

V

IN

SW

10µH*

5

887k

20pF

698k

1878 TA04

C

OUT

22µF
CER

C
22µF
CER

OUT

V

IN

3V TO 4.2V

**

V

OUT

2.5V

0.6A

**

V

OUT

1.8V

**

0.5A

C

IN

22µF
CER

C

IN

22µF
CER

**

V

IN

2.7V TO 6V

TYPICAL APPLICATIO S

LTC1878

U

Externally Synchronized 2.5V/0.6A Regulator

Using All Ceramic Capacitors

220pF

220pF

LTC1878

1

RUN

I

TH

V

FB

GND

PLL LPF

SYNC/MODE

V

SW

IN

2

3

4

TOKO D62CB A920CY-100M

*

TAIYO-YUDEN CERAMIC JMK325BJ226MM

**

8

7

6

5

0.01µF

EXT CLOCK
700kHz

10µH*

Low Noise 2.5V/0.3A Regulator

1

2

3

4

RUN

I

TH

V

GND

FB

LTC1878

SYNC/MODE

PLL LPF

V

SW

8

7

6

IN

15µH*

5

10k

20pF

20pF

887k

887k

412k

1878 TA04

V

IN

V

OUT

2.5V

**

C

OUT

0.6A

22µF
CER

V

OUT

OUT

***

2.5V

0.3A

+

C
47µF

6.3V

C

IN

22µF
CER

C

IN

22µF
CER

**

**

3V TO 6V

V

IN

2.65V TO 6V

220pF

SUMIDA CD54-150

*

TAIYO-YUDEN CERAMIC JMK325BJ226MM

**

SANYO POSCAP CTPA47M

***

3- to 4-Cell NiCd/NiMH to 3.3V/0.5A Regulator

Using All Ceramic Capacitors

LTC1878

1

RUN

2

I

SYNC/MODE

TH

3

V

FB

4

GND

TOKO D62CB A920CY-100M

*

TAIYO-YUDEN CERAMIC JMK325BJ226MM

**

†

CONNECTED TO VIN FOR 2.7V < VIN < 3.3V

V

OUT

PLL LPF

V

SW

8

7

6

IN

10µH*

5

20pF

412k

1878 TA06

887k

280k

1878 TA06

C

OUT

22µF
CER

V

†

V

OUT

3.3V

0.5A

**

C

IN

22µF
CER

**

IN

2.7V TO 6V

15

LTC1878

TYPICAL APPLICATIO

Single Li-Ion to 2.5V/0.5A Regulator with Precision 2.7V Undervoltage Lockout

U

44.2
1%

2.37M
1%

0.1µF

1.58M
1%

1.18M
1%

LTC1540

1

GND

2

–

V

3

+

IN

4

–

IN

OUT

REF

HYS

8

7

+

V

6

5

PACKAGE DESCRIPTIO

0.007

(0.18)

0.021

(0.53 ± 0.015)

* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

± 0.006

° – 6° TYP

0

220pF

0.01µF

10k

*

**

LTC1878

1

RUN

2

I

SYNC/MODE

TH

3

V

FB

4

GND

TOKO D62CB A920CY-100M
TAIYO-YUDEN CERAMIC JMK325BJ226MM

PLL LPF

V

SW

8

7

6

IN

10µH*

5

20pF

887k

412k

1878 TA08

U

Dimensions in inches (millimeters) unless otherwise noted.

MS8 Package

8-Lead Plastic MSOP

(LTC DWG # 05-08-1660)

0.118 ± 0.004*
(3.00 ± 0.102)

0.193 ± 0.006

(4.90 ± 0.15)

SEATING

PLANE

0.040

± 0.006

(1.02 ± 0.15)

0.012
(0.30)

REF

0.0256
(0.65)

BSC

0.034 ± 0.004
(0.86 ± 0.102)

0.006 ± 0.004

(0.15 ± 0.102)

C

OUT

22µF
CER

12

V

IN

V

OUT

2.5V

**

0.6A

8

7

6

5

0.118 ± 0.004**
(3.00 ± 0.102)

MSOP (MS8) 1098

4

3

C

IN

22µF
CER

**

2.7V TO 4.2V

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Linear Technology Corporation

16

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

 LINEAR TECHNOLOGY CORPORATION 2000

to 450mA,

OUT

to 500mA, VIN from 4V to 10V

to 600mA,

OUT

to 600mA,

OUT

to 600mA

OUT

1878i LT/TP 0500 4K • PRINTED IN USA