Page 1
LTC1877
Final Electrical Specifications
High Efficiency
Monolithic Synchronous
Step-Down Regulator
FEATURES
■
High Efficiency: Up to 95%
■
Very Low Quiescent Current: Only 10µA
During Operation
■
600mA Output Current at VIN = 5V
■
2.65V to 10V Input Voltage Range
■
550kHz Constant Frequency Operation
■
Synchronizable from 400kHz to 700kHz
■
Selectable Burst ModeTM Operation/
Pulse Skipping Mode
■
No Schottky Diode Required
■
Low Dropout Operation: 100% Duty Cycle
■
0.8V Reference Allows Low Output Voltages
■
Shutdown Mode Draws < 1µA Supply Current
■
±2% Output Voltage Accuracy
■
Current Mode Control for Excellent Line and
Load Transient Response
■
Overcurrent and Overtemperature Protected
■
Available in 8-Lead MSOP Package
U
APPLICATIONS
■
Cellular Telephones
■
Wireless Modems
■
Personal Information Appliances
■
Portable Instruments
■
Distributed Power Systems
■
Battery-Powered Equipment
U
May 2000
DESCRIPTION
The LTC®1877 is a high efficiency monolithic synchronous buck regulator using a constant frequency, current
mode architecture. Supply current during operation is
only 10µA and drops to < 1µA in shutdown. The 2.65V to
10V input voltage range makes the LTC1877 ideally suited
for both single and dual Li-Ion battery-powered applications. 100% duty cycle provides low dropout operation,
extending battery life in portable systems.
Switching frequency is internally set at 550kHz, allowing
the use of small surface mount inductors and capacitors.
For noise sensitive applications the LTC1877 can be
externally synchronized from 400kHz to 700kHz. Burst
Mode operation is inhibited during synchronization or
when the SYNC/MODE pin is pulled low, preventing low
frequency ripple from interfering with audio circuitry.
The internal synchronous switch increases efficiency and
eliminates the need for an external Schottky diode. Low
output voltages are easily supported with the 0.8V feedback reference voltage. The LTC1877 is available in a
space saving 8-lead MSOP package. Lower input voltage
applications (less than 7V abs max) should refer to the
LTC1878 data sheet.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
TYPICAL APPLICATION
High Efficiency Step-Down Converter
V
IN
2.65V
TO 10V
*TOKO D62CB A920CY-100M
**TAIYO-YUDEN CERAMIC LMK325BJ106MN
***SANYO POSCAP 6TPA47M
†
V
OUT
10µF**
CER
220pF
CONNECTED TO VIN FOR 2.65V < VIN < 3.3V
7
SYNC
6
V
IN
LTC1877
1
RUN
2
I
TH
GND
U
Efficiency vs Output Current
100
VIN = 3.6V
95
10µH*
5
SW
V
FB
4
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20pF
887k
3
280k
+
V
OUT
3.3V
47µF***
1877 TA01
†
90
85
80
75
VIN = 5V
70
EFFICIENCY (%)
65
60
55
50
0.1
VIN = 10V
VIN = 7.2V
V
= 3.3V
OUT
L = 10µH
Burst Mode OPERATION
1.0 100
OUTPUT CURRENT (mA)
10
1000
1877 • TA02
1
Page 2
LTC1877
1
2
3
4
8
7
6
5
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
PLL LPF
SYNC/MODE
V
IN
SW
RUN
I
TH
V
FB
GND
WW
W
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage (VIN).........................– 0.3V to 12V
U
U
W
PACKAGE/ORDER INFORMATION
ORDER PART
NUMBER
ITH, PLL LPF Voltage ................................–0.3V to 2.7V
RUN, VFB Voltages ......................................–0.3V to V
SYNC/MODE Voltage ..................................–0.3V to V
IN
IN
LTC1877EMS8
SW Voltage ................................... –0.3V to (VIN + 0.3V)
P-Channel MOSFET Source Current (DC) ........... 800mA
N-Channel MOSFET Sink Current (DC) ............... 800mA
Peak SW Sink and Source Current ........................ 1.5A
T
= 125°C, θJA = 150°C/ W
JMAX
MS8 PART MARKING
LTLU
Operating Ambient Temperature Range
Extended Commercial (Note 2)........... –40°C to 85°C
Consult factory for Military grade parts.
Junction Temperature (Note 3)............................ 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 5V unless otherwise specified.
U
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
VFB
V
FB
∆V
OVL
∆V
FB
V
LOADREG
V
IN
I
Q
f
OSC
f
SYNC
I
PLL LPF
R
PFET
R
NFET
Feedback Current (Note 4) ● 430 nA
Regulated Output Voltage (Note 4) 0°C ≤ TA ≤ 85°C 0.784 0.8 0.816 V
(Note 4) –40°C ≤ TA ≤ 85°C ● 0.74 0.8 0.84 V
Output Overvoltage Lockout ∆V
Reference Voltage Line Regulation VIN = 2.65V to 10V (Note 4) 0.05 0.15 %/V
Output Voltage Load Regulation Measured in Servo Loop; V
Input Voltage Range ● 2.65 10 V
Input DC Bias Current (Note 5)
Pulse Skipping Mode 2.65V < V
Burst Mode Operation V
Shutdown V
Oscillator Frequency VFB = 0.8V 495 550 605 kHz
SYNC Capture Range 400 700 kHz
Phase Detector Output Current
Sinking Capability f
Sourcing Capability f
R
of P-Channel MOSFET ISW = 100mA 0.65 0.85 Ω
DS(ON)
R
of N-Channel MOSFET ISW = –100mA 0.75 0.95 Ω
DS(ON)
= V
OVL
Measured in Servo Loop; V
SYNC/MODE
RUN
VFB = 0V 80 kHz
PLLIN
PLLIN
– V
OVL
FB
= 0.9V to 1.2V ● 0.1 0.5 %
ITH
= 1.6V to 1.2V ● –0.1 –0.5 %
ITH
< 10V, V
IN
= VIN, I
= 0V, VIN = 10V 0 1 µA
< f
OSC
> f
OSC
SYNC/MODE
OUT
= 0V, I
=0A 10 15 µA
=0A 230 350 µA
OUT
● 20 50 110 mV
● 3 10 20 µA
● –3 –10 –20 µA
2
Page 3
LTC1877
OUTPUT CURRENT (mA)
0.1
EFFICIENCY (%)
10
1000
95
90
85
80
75
70
65
60
55
1877 • G03
1.0 100
L = 15µH
L = 10µH
VIN = 10V
V
OUT
= 3.3V
Burst Mode OPERATION
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 5V unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
PK
I
LSW
V
SYNC/MODE
I
SYNC/MODE
V
RUN
I
RUN
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC1877 is guaranteed to meet specified performance from 0°C
to 70°C. Specifications over the –40°C to 85°C operating temperature range
are assured by design, characterization and correlation with statistical process
controls.
Peak Inductor Current VFB = 0.7V, Duty Cycle < 35% 0.8 1.0 1.25 A
SW Leakage V
= 0V, VSW = 0V or 8.5V, VIN = 8.5V ±0.01 ±1 µA
RUN
SYNC/MODE Threshold ● 0.2 1.0 1.5 V
SYNC/MODE Leakage Current ±0.01 ±1 µA
RUN Threshold ● 0.2 0.7 1.5 V
RUN Input Current ±0.01 ±1 µA
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation P
according to the following formulas:
D
LTC1877EMS8: TJ = TA + (PD)(150°C/W)
Note 4: The LTC1877 is tested in a feedback loop which servos VFB to the
balance point for the error amplifier (V
= 1.2V).
ITH
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
UW
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Input Voltage
100
95
90
85
80
75
70
EFFICIENCY (%)
65
60
V
L = 10µH
55
Burst Mode OPERATION
50
0
I
= 100mA
LOAD
I
= 300mA
LOAD
= 2.5V
OUT
2
4
INPUT VOLTAGE (V)
I
= 10mA
LOAD
I
LOAD
I
= 0.1mA
LOAD
68
= 1mA
10
1877 • G01
12
Efficiency vs Output Current
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.1
VIN = 3.6V
VIN = 7.2V
VIN = 3.6V
1.0 100
OUTPUT CURRENT (mA)
PULSE SKIPPING MODE
Burst Mode OPERATION
10
VIN = 7.2V
V
= 2.5V
OUT
L = 10µH
Efficiency vs Output Current
1000
1877 • G02
3
Page 4
LTC1877
UW
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Current
95
VIN = 3.6V
90
85
80
75
70
EFFICIENCY (%)
65
60
55
50
0.1
VIN = 7.2V
VIN = 5V
1.0 100
OUTPUT CURRENT (mA)
10
Oscillator Frequency vs Supply
Voltage
605
595
585
575
565
555
545
535
525
OSCILLATOR FREQUENCY (kHz)
515
505
495
2
0
4
SUPPLY VOLTAGE (V)
VIN = 10V
L = 10µH
V
OUT
86
= 2.5V
1877 • G04
1877 • G07
1000
1210
Reference Voltage vs
Temperature
0.814
VIN = 5V
0.809
0.804
0.799
0.794
REFERENCE VOLTAGE (V)
0.789
0.784
–50
–25 0
TEMPERATURE (°C)
50 100 125
25 75
Output Voltage vs Load Current
2.53
PULSE SKIPPING MODE
2.52
2.51
2.50
2.49
2.48
2.47
2.46
OUTPUT VOLTAGE (V)
2.45
2.44
2.43
V
IN
L = 10µH
0
= 4.2V
200
LOAD CURRENT (mA)
400
600
1877 • G05
1877 • G08
800
Oscillator Frequency vs
Temperature
605
VIN = 5V
595
585
575
565
555
545
535
FREQUENCY (kHz)
525
515
505
495
–25
–50
R
DS(ON)
1.2
1.0
0.8
(Ω)
0.6
DS(ON)
R
0.4
0.2
0
013579
0
TEMPERATURE (°C)
vs Input Voltage
2468
INPUT VOLTAGE (V)
5025
SYNCHRONOUS
SWITCH
MAIN SWITCH
10075
1877 • G06
1877 • G09
125
10
4
1.4
1.2
1.0
(Ω)
0.8
DS(ON)
R
0.6
0.4
0.2
R
–50
vs Temperature
DS(ON)
VIN = 3V
–25 0
TEMPERATURE (°C)
VIN = 5V
SYNCHRONOUS SWITCH
MAIN SWITCH
50 100 125
25 75
1877 • G10
DC Supply Current vs Input
Voltage
250
200
V
OUT
150
100
DC SUPPLY CURRENT (µA)
50
0
0
PULSE SKIPPING MODE
= 1.8V
Burst Mode OPERATION
2
4
INPUT VOLTAGE (V)
DC Supply Current vs
Temperature
300
VIN = 5V
250
200
150
100
SUPPLY CURRENT (µA)
50
0
6
8
10
1877 • G11
–50
PULSE SKIPPING MODE
BURST MODE OPERATION
–25 0
25 75
TEMPERATURE (°C)
50 100 125
1877 G19
Page 5
UW
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1877
Switch Leakage vs Temperature
1400
VIN = 10V
RUN = 0V
1200
1000
800
600
400
SWITCH LEAKAGE (nA)
200
0
–50
–25 0
TEMPERATURE (°C)
MAIN SWITCH
SYNCHRONOUS
SWITCH
50 100 125
25 75
Start-Up from Shutdown
RUN
5V/DIV
V
OUT
1V/DIV
1877 • G12
Switch Leakage vs Input Voltage
16
RUN = 0V
14
12
10
8
6
SWITCH LEAKAGE (nA)
4
2
0
0
SYNCHRONOUS
SWITCH
MAIN SWITCH
24 8
INPUT VOLTAGE (V)
6
AC COUPLED
V
OUT
50mV/DIV
500mA/DIV
SW
5V/DIV
V
OUT
20mV/DIV
AC COUPLED
I
L
200mA/DIV
10
1877 • G13
Load Step Response
I
L
Burst Mode Operation
V
V
C
IN
OUT
IN
= 5V
= 1.5V
= 10µF
10µs/DIV
L = 10µH
C
OUT
I
LOAD
= 47µF
= 50mA
1877 • G14
500mA/DIV
V
OUT
50mV/DIV
AC COUPLED
500mA/DIV
I
1V/DIV
I
L
V
= 5V
IN
= 1.5V
V
OUT
L = 10µH
Load Step Response
I
L
TH
= 5V
V
IN
V
OUT
L
= 10µH
10µs/DIV10µs/DIV
= 1.5V
50µs/DIV
40µs/DIV
C
IN
C
OUT
I
LOAD
Burst Mode OPERATION
= 10µF
C
IN
C
OUT
I
LOAD
= 10µF
= 47µF
= 50mA TO 500mA
= 47µF
= 500mA
1877 • G15
1877 • G17
I
1V/DIV
V
OUT
50mV/DIV
AC COUPLED
500mA/DIV
I
1V/DIV
TH
V
= 5V
IN
= 1.5V
V
OUT
= 10µH
L
Load Step Response
I
L
TH
= 5V
V
IN
= 1.5V
V
OUT
= 10µH
L
40µs/DIV
C
= 10µF
IN
= 47µF
C
OUT
= 50mA TO 500mA
I
LOAD
PULSE SKIPPING MODE
20µs/DIV
C
= 10µF
IN
= 47µF
C
OUT
= 200mA TO 500mA
I
LOAD
PULSE SKIPPING MODE
1877 • G16
1877 • G18
5
Page 6
LTC1877
UUU
PIN FUNCTIONS
RUN (Pin 1): Run Control Input. Forcing this pin below
0.4V shuts down the LTC1877. In shutdown all functions
are disabled drawing <1µA supply current. Forcing this pin
above 1.2V enables the LTC1877. Do not leave RUN
floating.
ITH (Pin 2): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.5V
to 1.9V.
VFB (Pin 3): Feedback Pin. Receives the feedback voltage
from an external resistive divider across the output.
GND (Pin 4): Ground Pin.
SW (Pin 5): Switch Node Connection to Inductor. This pin
UU
W
FUNCTIONAL DIAGRA
PLL LPF
8
BURST
DEFEAT
X
Y = “0” ONLY WHEN X IS A CONSTANT “1”
Y
connects to the drains of the internal main and synchronous power MOSFET switches.
VIN (Pin 6): Main Supply Pin. Must be closely decoupled
to GND, Pin 4.
SYNC/MODE (Pin 7): External Clock Synchronization and
Mode Select Input. To synchronize with an external clock,
apply a clock with a frequency between 400kHz and
700kHz. To select Burst Mode operation, tie to VIN. Grounding this pin selects pulse skipping mode. Do not leave this
pin floating.
PLL LPF (Pin 8): Output of the Phase Detector and Control
Input of Oscillator. Connect a series RC lowpass network
from this pin to ground if externally synchronized. If
unused, this pin may be left open.
V
IN
SYNC/MODE
7
0.6V
3
V
FB
RUN
1
–
+
V
0.8V REF
IN
SHUTDOWN
VCO
FREQ
SHIFT
0.85V
V
REF
0.8V
gm = 0.5m
–
OVDET
+
SLOPE
COMP
OSC
–
+
EA
–
+
0.45V
SLEEP
V
IN
Ω
V
IN
I
2
TH
EN
–
+
BURST
Q
S
R
Q
RS LATCH
SLEEP
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
0.8V
–
I
COMP
ANTI
SHOOT-
THRU
I
RCMP
V
6
IN
+
+
–
6Ω
SW
5
GND
4
1877 BD
6
Page 7
OPERATIO
LTC1877
U
(Refer to Functional Diagram)
Main Control Loop
The LTC1877 uses a constant frequency, current mode
step-down architecture. Both the main (P-channel MOSFET)
and synchronous (N-channel MOSFET) switches are internal. During normal operation, the internal top power
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the current comparator,
I
, resets the RS latch. The peak inductor current at
COMP
which I
on the ITH pin, which is the output of error amplifier EA. The
VFB pin, described in the Pin Functions section, allows EA
to receive an output feedback voltage from an external
resistive divider. When the load current increases, it
causes a slight decrease in the feedback voltage relative to
the 0.8V reference, which in turn, causes the I
increase until the average inductor current matches the
new load current. While the top MOSFET is off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse as indicated by the current reversal
comparator I
cycle.
resets the RS latch is controlled by the voltage
COMP
TH
, or the beginning of the next clock
RCMP
voltage to
BURST comparator trips, causing the internal sleep line
to go high and forces off both power MOSFETs. The I
is then disconnected from the output of the EA amplifier
and parked a diode voltage above ground.
In sleep mode, both power MOSFETs are held off and a
majority of the internal circuitry is partially turned off,
reducing the quiescent current to 10µA. The load current
is now being supplied solely from the output capacitor.
When the output voltage drops, the I
the output of the EA amplifier and the top MOSFET is again
turned on and this process repeats.
Short-Circuit Protection
When the output is shorted to ground, the frequency of the
oscillator is reduced to about 80kHz, 1/7 the nominal
frequency. This frequency foldback ensures that the
inductor current has ample time to decay, thereby preventing runaway. The oscillator’s frequency will progressively increase to 550kHz (or the synchronized frequency)
when V
rises above 0.3V.
FB
pin reconnects to
TH
TH
pin
Comparator OVDET guards against transient overshoots
> 6.25% by turning the main switch off and keeping it off
until the fault is removed.
Burst Mode Operation
The LTC1877 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
tie the SYNC/MODE pin to V
(V
SYNC/MODE
and enable PWM pulse skipping mode, connect the SYNC/
MODE pin to GND. In this mode, the efficiency is lower at
light loads, but becomes comparable to Burst Mode
operation when the output load exceeds 50mA. The advantage of pulse skipping mode is lower output ripple and
less interference to audio circuitry.
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 250mA,
even though the voltage at the I
value. The voltage at the I
average current is greater than the load requirement. As
the I
TH
> 1.5V). To disable Burst Mode operation
voltage drops below approximately 0.45V, the
or connect it to a logic high
IN
pin indicates a lower
TH
pin drops when the inductor’s
TH
Frequency Synchronization
A phase-locked loop (PLL) is available on the LTC1877 to
allow the internal oscillator to be synchronized to an
external source connected to the SYNC/MODE pin. The
output of the phase detector at the PLL LPF pin operates
over a 0V to 2.4V range corresponding to 400kHz to
700kHz. When locked, the PLL aligns the turn-on of the top
MOSFET to the rising edge of the synchronizing signal.
When the LTC1877 is clocked by an external source, Burst
Mode operation is disabled; the LTC1877 then operates in
PWM pulse skipping mode. In this mode, when the output
load is very low, current comparator I
tripped for several cycles and force the main switch to stay
off for the same number of cycles. Increasing the output
load slightly allows constant frequency PWM operation to
resume. This mode exhibits low output ripple as well as
low audio noise and reduced RF interference while providing reasonable low current efficiency.
Frequency synchronization is inhibited when the feedback
voltage V
from interfering with the frequency foldback for shortcircuit protection.
is below 0.6V. This prevents the external clock
FB
COMP
may remain
7
Page 8
LTC1877
OPERATIO
U
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle until it reaches 100% duty cycle. The output voltage
will then be determined by the input voltage minus the
voltage drop across the internal P-channel MOSFET and
the inductor.
Low Supply Operation
The LTC1877 is designed to operate down to an input
supply voltage of 2.65V although the maximum allowable
output current is reduced at this low voltage. Figure 1
shows the reduction in the maximum output current as a
function of input voltage for various output voltages.
1200
V
= 2.5V
= 3.3V
OUT
V
= 5V
OUT
1000
800
600
400
V
= 1.5V
OUT
V
OUT
Another important detail to remember is that at low input
supply voltages, the R
of the P-channel switch
DS(ON)
increases. Therefore, the user should calculate the power
dissipation when the LTC1877 is used at 100% duty cycle
with a low input voltage (see Thermal Considerations in
the Applications Information section).
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. As a result, the
maximum inductor peak current is reduced for duty cycles
>40%. This is shown in the decrease of the inductor peak
current as a function of duty cycle graph in Figure 2.
1100
1000
900
800
VIN = 5V
MAX OUTPUT CURRENT (mA)
200
0
0
Figure 1. Maximum Output Current vs Input Voltage
468
2
VIN (V)
U
L = 10µH
10 12
1877 • F01
WUU
APPLICATIONS INFORMATION
The basic LTC1877 application circuit is shown on the first
page. External component selection is driven by the load
requirement and begins with the selection of L followed by
C
and C
IN
Inductor Value Calculation
The inductor selection will depend on the operating frequency of the LTC1877. The internal nominal frequency is
550kHz, but can be externally synchronized from 400kHz
to 700kHz.
OUT
.
700
MAXIMUM INDUCTOR PEAK CURRENT (mA)
600
Figure 2. Maximum Inductor Peak Current vs Duty Cycle
20
0
DUTY CYCLE (%)
60
80
40
100
1877 F02
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. However, operating at a higher frequency generally results in lower
efficiency because of increased internal gate charge losses.
The inductor value has a direct effect on ripple current. The
ripple current ∆IL decreases with higher inductance or
frequency and increases with higher VIN or V
OUT
.
8
Page 9
LTC1877
CI
VVV
V
IN OMAX
OUT IN OUT
IN
required I
RMS
≅
−
()
[]
12/
U
WUU
APPLICATIONS INFORMATION
∆=
I
1
L OUT
fL
()()
1
V
−
Accepting larger values of ∆IL allows the use of low
inductance, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ∆IL = 0.4(I
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
250mA. Lower inductor values (higher ∆IL) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Kool Mµ (from Magnetics, Inc.) is a very good, low loss
core material for toroids with a “soft” saturation characteristic. Molypermalloy is slightly more efficient at high
(>200kHz) switching frequencies but quite a bit more
expensive. Toroids are very space efficient, especially
when you can use several layers of wire, while inductors
Kool Mµ is a registered trademark of Magnetics, Inc.
V
OUT
V
IN
MAX
(1)
).
wound on bobbins are generally easier to surface mount.
New designs for surface mount inductors are available
from Coiltronics, Coilcraft, Dale and Sumida.
C
IN
and C
Selection
OUT
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle V
OUT/VIN
. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
This formula has a maximum at V
I
= I
RMS
/2. This simple worst-case condition is com-
OUT
IN
= 2V
OUT
, where
monly used for design because even significant deviations
do not offer much relief. Note the capacitor manufacturer’s
ripple current ratings are often based on 2000 hours of life.
This makes it advisable to further derate the capacitor, or
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
The selection of C
is driven by the required effective
OUT
series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering.
The output ripple ∆V
∆≅∆ +
V I ESR
OUT L
where f = operating frequency, C
is determined by:
OUT
1
fC
OUT
OUT
8
= output capacitance
and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. For the LTC1877, the general rule for
proper operation is:
C
required ESR < 0.25Ω
OUT
The choice of using a smaller output capacitance
increases the output ripple voltage due to the frequency
dependent term but can be compensated for by using
capacitor(s) of very low ESR to maintain low ripple voltage. The ITH pin compensation components can be opti-
9
Page 10
LTC1877
U
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APPLICATIONS INFORMATION
mized to provide stable high performance transient
response regardless of the output capacitor selected.
ESR is a direct function of the volume of the capacitor.
Manufacturers such as Taiyo Yuden, AVX, Sprague, Kemet
and Sanyo should be considered for high performance
capacitors. The POSCAP solid electrolytic capacitor available from Sanyo is an excellent choice for output bulk
capacitors due to its low ESR/size ratio. Once the ESR
requirement for C
rating generally far exceeds the I
When using tantalum capacitors, it is critical that they are
surge tested for use in switching power supplies. A good
choice is the AVX TPS series of surface mount tantalum,
available in case heights ranging from 2mm to 4mm. Other
capacitor types include KEMET T510 and T495 series and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
Output Voltage Programming
has been met, the RMS current
OUT
RIPPLE(P-P)
requirement.
that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will
not lock up on input frequencies close to the harmonics of
the VCO center frequency. The PLL hold-in range ∆fH is
equal to the capture range, ∆fH = ∆fC = ±150kHz.
The output of the phase detector is a pair of complementary current sources charging or discharging the external
filter network on the PLL LPF pin. The relationship
between the voltage on the PLL LPF pin and operating
frequency is shown in Figure 4. A simplified block diagram
is shown in Figure 5.
If the external frequency (V
SYNC/MODE
) is greater than
550kHz, the center frequency, current is sourced continuously, pulling up the PLL LPF pin. When the external
800
700
The output voltage is set by a resistive divider according
to the following formula:
R
2
VV
=+
OUT
08 1
.
R
1
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 3.
0.8V ≤ V
V
FB
LTC1877
GND
Figure 3. Setting the LTC1877 Output Voltage
OUT
≤ 10V
R2
R1
1877 F03
Phase-Locked Loop and Frequency Synchronization
The LTC1877 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external frequency source. The frequency range
of the voltage-controlled oscillator is 400kHz to 700kHz.
The phase detector used is an edge sensitive digital type
600
500
400
OSCILLATOR FREQUENCY (kHz)
300
0
Figure 4. Relationship Between Oscillator
Frequency and Voltage at PLL LPF Pin
PHASE
DETECTOR
SYNC/
MODE
DIGITAL
PHASE/
FREQUENCY
DETECTOR
Figure 5. Phase-Locked Loop Block Diagram
0.8 1.2 1.6
0.4
2.4V
V
PLL LPF
(V)
R
PLL LPF
VCO
1877 • F04
LP
2.0
1877 F05
C
LP
10
Page 11
LTC1877
U
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APPLICATIONS INFORMATION
frequency is less than 550kHz, current is sunk continuously, pulling down the PLL LPF pin. If the external and
internal frequencies are the same but exhibit a phase
difference, the current sources turn on for an amount of
time corresponding to the phase difference. Thus the
voltage on the PLL LPF pin is adjusted until the phase and
frequency of the external and internal oscillators are
identical. At this stable operating point the phase comparator output is high impedance and the filter capacitor
CLP holds the voltage.
The loop filter components CLP and R
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
component’s CLP and RLP determine how fast the loop
acquires lock. Typically R
= 10k and C
LP
0.01µF. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallows setting the internal oscillator frequency by a DC
voltage on the V
PLL LPF
pin.
smooth out the
LP
is 2200pF to
LP
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge dQ moves from VIN to ground. The resulting
dQ/dt is the current out of V
the DC bias current. In continuous mode, I
that is typically larger than
IN
GATECHG
=
f(QT + QB) where QT and QB are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to VIN and thus
their effects will be more pronounced at higher supply
voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
and the duty cycle
DS(ON)
(DC) as follows:
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC1877 circuits: VIN quiescent current and I2R
losses. The VIN quiescent current loss dominates the
efficiency loss at very low load currents whereas the I2R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 6.
1. The VIN quiescent current is due to two components:
the DC bias current as given in the electrical characteristics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
R
The R
= (R
SW
DS(ON)
DS(ON)TOP
for both the top and bottom MOSFETs can
)(DC) + (R
DS(ON)BOT
)(1 – DC)
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
Other losses including CIN and C
ESR dissipative
OUT
losses and inductor core losses generally account for less
than 2% total additional loss.
1
= 4.2V
V
IN
L = 10µH
V
= 1.5V
0.1
0.01
0.001
POWER LOST (W)
0.0001
0.00001
Figure 6. Power Lost vs Load Current
OUT
= 2.5V
V
OUT
= 3.3V
V
OUT
Burst Mode OPERATION
0.1 1
LOAD CURRENT (mA)
10 100 1000
1877 F06
11
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LTC1877
U
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APPLICATIONS INFORMATION
Thermal Considerations
In most applications the LTC1877 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC1877 is running at high ambient temperature with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance.
To avoid the LTC1877 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The temperature rise is given by:
TR = (PD)(θJA)
where PD is the power dissipated by the regulator and θ
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, TJ, is given by:
TJ = TA + T
R
where TA is the ambient temperature.
As an example, consider the LTC1877 in dropout at an
input voltage of 3V, a load current of 500mA, and an
ambient temperature of 70°C. From the typical performance graph of switch resistance, the R
DS(ON)
P-channel switch at 70°C is approximately 0.9Ω. Therefore, power dissipated by the part is:
LOAD
2
• R
DS(ON)
= 0.225W
PD = I
For the MSOP package, the θJA is 150°C/W. Thus, the
junction temperature of the regulator is:
TJ = 70°C + (0.225)(150) = 104°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (R
of the
DS(ON)
JA
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to (∆I
resistance of C
discharge C
• ESR), where ESR is the effective series
LOAD
OUT
, which generates a feedback error signal.
OUT
The regulator loop then acts to return V
state value. During this recovery time V
immediately shifts by an amount
OUT
. ∆I
also begins to charge or
LOAD
to its steady-
OUT
can be moni-
OUT
tored for overshoot or ringing that would indicate a stability problem. The internal compensation provides adequate
compensation for most applications. But if additional
compensation is required, the I
pin can be used for
TH
external compensation using RC, CC1 as shown in
Figure 7. (The 220pF capacitor, CC2, is typically needed for
noise decoupling.)
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
, causing a rapid drop in V
OUT
. No regulator can
OUT
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C
LOAD
).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1877. These items are also illustrated graphically in
the layout diagram of Figure 7. Check the following in your
layout:
1. Are the signal and power grounds segregated? The
LTC1877 signal ground consists of the resistive
divider, the optional compensation network (RC and
CC1) and CC2. The power ground consists of the (–)
plate of CIN, the (–) plate of C
and Pin 4 of the
OUT
12
Page 13
LTC1877
U
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APPLICATIONS INFORMATION
C
C2
OPTIONAL
C
C1
R
C
LTC1877. The power ground traces should be kept
short, direct and wide. The signal ground and power
ground should converge to a common node in a starground configuration.
2. Does the VFB pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be connected between the (+) plate of C
3. Does the (+) plate of C
connect to VIN as closely as
IN
and signal ground.
OUT
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node SW away from sensitive small
signal nodes.
Design Example
As a design example, assume the LTC1877 is used in a
single lithium-ion battery-powered cellular phone application. The input voltage will be operating from a maximum
of 4.2V down to about 2.7V. The load current requirement
is a maximum of 0.3A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is
2.5V. With this information we can calculate L using
equation (1),
LTC1877
1
RUN
2
I
SYNC/MODE
TH
3
V
FB
4
GND
Figure 7. LTC1877 Layout Diagram
PLL LPF
R2
V
SW
8
7
6
IN
5
BOLD LINES INDICATE
HIGH CURRENT PATHS
L1
R2
+
C
R1
L
1
=
fI
()∆()
L
Substituting V
OUT
V
OUT
OUT
+
V
OUT
–
+
1877 F07
1
= 2.5V, V
+
V
IN
C
IN
–
V
OUT
−
V
IN
= 4.2V, ∆IL=120mA and
IN
(3)
f = 550kHz in equation (3) gives:
L
550 120
V
25
.
kHz mA
()..
1
25
42
V
=µ
15 3
V
H=−
.
A 15µH inductor works well for this application. For best
efficiency choose a 1A inductor with less than 0.25Ω
series resistance.
C
will require an RMS current rating of at least 0.15A at
IN
temperature and C
will require an ESR of less than
OUT
0.25Ω. In most applications, the requirements for these
capacitors are fairly similar.
For the feedback resistors, choose R1 = 412k. R2 can
then be calculated from equation (2) to be:
V
R
OUT
2
08
R k use k
1 1 875 5 887=
–.;
.
=
Figure 8 shows the complete circuit along with its efficiency curve.
13
Page 14
LTC1877
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APPLICATIONS INFORMATION
1
220pF
RUN
2
I
3
V
4
GND
412k
*SUMIDA CD54-150
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***SANYO POSCAP 6TPA47M
TH
FB
PLL LPF
SYNC/MODE
LTC1877
V
SW
887k
20pF
Figure 8. Single Lithium-Ion to 2.5V/0.3A Regulator from Design Example
10µF**
8
CER
7
6
IN
15µH*
5
+
U
TYPICAL APPLICATIONS
V
IN
2.7V
TO 4.2V
V
OUT
2.5V
47µF***
1877 F08a
95
VIN = 3.0V
90
85
80
VIN = 4.2V
75
70
EFFICIENCY (%)
65
60
55
50
0.1
1.0 10
OUTPUT CURRENT (mA)
VIN = 3.6V
V
= 2.5V
OUT
L = 15µH
100 1000
1877 • F08b
Dual Lithium-Ion to 2.5V/0.6A Regulator
Using All Ceramic Capacitors
1
RUN
2
I
SYNC/MODE
TH
220pF
*SUMIDA CD54-150
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***TAIYO YUDEN CERAMIC JMK325BJ226MM
LTC1877
3
V
FB
4
GND
PLL LPF
V
SW
8
7
6
IN
5
15µH*
4-to 6-Cell NiCd/NiMH to 1.8V/0.6A Regulator
Using All Ceramic Capacitors
1
RUN
2
I
SYNC/MODE
TH
220pF
*TOKO D62CB A920CY-100M
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***TAIYO YUDEN CERAMIC JMK325BJ226MM
LTC1877
3
V
FB
4
GND
PLL LPF
V
SW
8
7
6
IN
5
10µH*
C
IN
10µF
CER
20pF
C
10µF
CER
20pF
V
IN
**
887k
412k
**
IN
887k
698k
≤ 8.4V
V
OUT
2.5V/0.6A
***
C
OUT
22µF
CER
V
IN
≤ 9V
V
OUT
1.8V/0.6A
C
OUT
22µF
CER
1877 TA04
1877 TA03
***
14
Page 15
U
TYPICAL APPLICATIONS
LTC1877
Externally Synchronized 2.5V/0.6A Regulator
Using all Ceramic Capacitors
1
RUN
I
TH
V
FB
GND
PLL LPF
SYNC/MODE
LTC1877
V
SW
IN
2
220pF
3
4
*TOKO D62CB A920CY-100M
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***TAIYO YUDEN CERAMIC JMK325BJ226MM
8
7
6
5
0.01µF
EXT
CLOCK
700kHz
10µH*
20pF
PACKAGE DESCRIPTION
0.007
(0.18)
0.021 ± 0.006
(0.53 ± 0.015)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0° – 6° TYP
Low Noise 2.5V/0.3A Regulator
V
IN
4V
TO 10V
10k
887k
412k
CIN**
10µF
CER
C
OUT
22µF
CER
V
OUT
2.5V
/0.6A
***
1877 TA05
1
RUN
2
I
SYNC/MODE
TH
220pF
*SUMIDA CD54-150
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***SANYO POSCAP 6TPA47M
LTC1877
3
V
FB
4
GND
PLL LPF
V
SW
8
7
6
IN
5
U
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
SEATING
PLANE
(LTC DWG # 05-08-1660)
0.040 ± 0.006
(1.02 ± 0.15)
0.012
(0.30)
0.0256
REF
(0.65)
TYP
0.034 ± 0.004
(0.86 ± 0.102)
0.006 ± 0.004
(0.15 ± 0.102)
0.118 ± 0.004*
(3.00 ± 0.102)
0.192 ± 0.004
(4.88 ± 0.10)
15µH*
8
12
7
6
3
20pF
5
0.118 ± 0.004**
(3.00 ± 0.102)
4
MSOP (MS8) 1197
887k
412k
V
IN
2.85V
TO 10V
CIN**
10µF
CER
V
OUT
2.5V/0.3A
***
C
OUT
47µF
6.3V
1877 TA06
15
Page 16
LTC1877
TYPICAL APPLICATION
U
Single Lithium-Ion to 3.3V/0.3A Regulator
220pF
1
RUN
2
I
SYNC/MODE
TH
LTC1877
3
V
FB
4
GND
PLL LPF
V
SW
8
7
6
IN
5
10µH*
20pF
10µF**
887k
280k
V
+
Li-Ion BATTERY
–
3V TO 4.2V
V
3.3V/0.25A
47µF***
IN
OUT
*TOKO D62CB A920CY-100M
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***SANYO POSCAP 6TPA47M
1877 TA07
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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from 2.65V to 8.5V
IN
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V
from 2.5V to 5.5V
IN
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V
IN
Pin, Constant Frequency, I
REF
from 2.65V to 8.5V
to 500mA, Secondary Winding
OUT
to 500mA, 1MHz Operation,
OUT
LTC1735 High Efficiency, Synchronous Step-Down Converter 16-Pin SO and SSOP, VIN up to 36V, Fault Protection
LTC1772 Low Input Voltage Current Mode Step-Down DC/DC Controller 550kHz, 6-Pin SOT-23, I
up to 5A, VIN from 2.2V to 10V
OUT
LTC1878 High Efficiency Monolithic Step-Down Regulator 550kHz, MS8, VIN up to 6V, IQ = 10µA, I
to 450mA,
OUT
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to 600mA,
OUT
to 600mA,
OUT
to 600mA
OUT
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
1877i LT/TP 0500 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2000
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