Datasheet LTC1852, LTC1853 Datasheet (LINEAR TECHNOLOGY)

400ksps, Low Power, Sampling ADCs

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

1.0

0.5

0

–0.5

–1.0

INL ERROR (LSBs)

1852 F01

FEATURES

■

Flexible 8-Channel Multiplexer

Single-Ended or Differential Inputs
Two Gain Ranges
Unipolar or Bipolar Operation

■

Scan Mode and Programmable Sequencer
Eliminate Configuration Software Overhead

■

Low Power: 3mW at 250ksps

■

2.7V to 5.5V Supply Range

■

Internal or External Reference Operation

■

Parallel Output Includes MUX Address

■

Nap and Sleep Shutdown Modes

■

Pin Compatible up-grade 1.25Msps 10-Bit LTC1850
and 12-Bit LTC1851

U

APPLICATIO S

■

High Speed Data Acquisition

■

Test and Measurement

■

Imaging Systems

■

Telecommunications

■

Industrial Process Control

■

Spectrum Analysis

LTC1852/LTC1853

8-Channel, 10-Bit/12-Bit,

U

DESCRIPTIO

The 10-bit LTC®1852 and 12-bit LTC1853 are complete
8-channel data acquisition systems. They include a flex­ible 8-channel multiplexer, a 400ksps successive approxi­mation analog-to-digital converter, an internal reference
and a parallel output interface. The multiplexer can be
configured for single-ended or differential inputs, two gain
ranges and unipolar or bipolar operation. The ADCs have
a scan mode that will repeatedly cycle through all 8
multiplexer channels and can also be programmed to
sequence through up to 16 addresses and configurations.
The sequence can also be read back from internal memory.

The reference and buffer amplifier provide pin strappable
ranges of 4.096V, 2.5V and 2.048V. The parallel output
includes the 10-bit or 12-bit conversion result plus the 4­bit multiplexer address. The digital outputs are powered
from a separate supply allowing for easy interface to 3V
digital logic. Typical power consumption is 10mW at
400ksps from a single 5V supply and 3mW at 250ksps
from a single 3V supply.

, LTC and LT are registered trademarks of Linear Technology Corporation.

BLOCK DIAGRA

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

REFOUT

REFIN

REFCOMP

8-CHANNEL

MULTIPLEXER

2.5V

REFERENCE

REF AMP

+
–

W

LTC1853

12-BIT

SAMPLING

ADC

INTERNAL

CLOCK

CONTROL LOGIC

PROGRAMMABLE

SEQUENCER

DATA

LATCHES

AND

OUTPUT

DRIVERS

18523 BD

M1
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
M0

OV

DD

BUSY
DIFF

OUT

A2

OUT

A1

OUT

A0

OUT

D11/S2
D10/S1
D9/S0
D8
D7
D6
D5
D4
D3
D2
D1
D0

OGND

Integral Linearity

/S6
/S5
/S4
/S3

18523f

1

LTC1852/LTC1853

A

S

OVDD = V

W

O

LUTEXI TIS

(Notes 1, 2)

DD

A

WUW

U

ARB

G

Supply Voltage (VDD)................................................. 6V

Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)

Digital Input Voltage (Note 4) ....................–0.3V to 10V

Digital Output Voltage..................–0.3V to (VDD + 0.3V)

Power Dissipation.............................................. 500mW

WU

/

PACKAGE

CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7

COM

REFOUT

REFIN

REFCOMP

GND

V

DD

V

DD

GND

/S6

DIFF

OUT

/S5

A2

OUT

/S4

A1

OUT

/S3

A0

OUT

D9/S2
D8/S1
D7/S0

D6

T

O

RDER I FOR ATIO

TOP VIEW

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

FW PACKAGE

48-LEAD PLASTIC TSSOP

= 150°C, θJA = 110°C/W

JMAX

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

M1
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
M0
OV

DD

OGND
BUSY
NC
NC
D0
D1
D2
D3
D4
D5

ORDER PART

NUMBER

LTC1852CFW
LTC1852IFW

Ambient Operating Temperature Range

LTC1852C/LTC1853C ............................ 0°C to 70°C

LTC1852I/LTC1853I .......................... –40°C to 85°C

Storage Temperature Range .................–65°C to 150°C

Lead Temperature (Soldering, 10 sec)................ 300°C

U

REFOUT

REFIN

REFCOMP

DIFF

OUT

A2

OUT

A1

OUT

A0

OUT

D11/S2

D10/S1

D9/S0

1

CH0

2

CH1

3

CH2

4

CH3

5

CH4

6

CH5

7

CH6

8

CH7

9

COM

10
11
12
13

GND

14

V

DD

15

V

DD

16

GND

17

/S6

18

/S5

19

/S4

20

/S3

21
22
23
24

D8

FW PACKAGE

48-LEAD PLASTIC TSSOP

T

= 150°C, θJA = 110°C/W

JMAX

TOP VIEW

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

M1
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
M0
OV

DD

OGND
BUSY
D0
D1
D2
D3
D4
D5
D6
D7

ORDER PART

NUMBER

LTC1853CFW
LTC1853IFW

Consult LTC Marketing for parts specified with wider operating temperature ranges.

2

18523f

LTC1852/LTC1853

U

CO VERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V to 5.5V, REFCOMP < VDD (Notes 5, 6)

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 10 12 Bits
Integral Linearity Error (Note 7) ● ±0.25 ±1 ±0.35 ±1LSB
Differential Linearity Error ● ±0.25 ±1 ±0.25 ±1LSB
Offset Error (Bipolar and Unipolar) (Note 8)

Gain = 1 (PGA = 1) REFCOMP ≥ 2V
Gain = 2 (PGA = 0)

Offset Error Match (Bipolar and Unipolar) ±0.5 ±1LSB
Unipolar Gain Error With External 4.096V Reference

Gain = 1 (PGA = 1) Applied to REFCOMP (Note 12) ±2 ±4LSB
Gain = 2 (PGA = 0) V

Unipolar Gain Error Match ±0.5 ±1LSB
Bipolar Gain Error With External 4.096V Reference

Gain = 1 (PGA = 1) Applied to REFCOMP (Note 12) ±2 ±4LSB
Gain = 2 (PGA = 0) V

Bipolar Gain Error Match ±0.5 ±1LSB
Unipolar Gain Error With External 2.5V Reference

Gain = 1 (PGA = 1) Applied to REFCOMP ● ±1 ±3 ±1.5 ±8LSB
Gain = 2 (PGA = 0) V

Bipolar Gain Error With External 2.5V Reference

Gain = 1 (PGA = 1) Applied to REFCOMP ● ±1 ±3 ±1.5 ±8LSB
Gain = 2 (PGA = 0) V

Full-Scale Error Temperature Coefficient 15 15 ppm/°C

= 4.75V to 5.25V, fS ≤ 400kHz ±4 ±8LSB

DD

= 4.75V to 5.25V, fS ≤ 400kHz ±4 ±8LSB

DD

= 2.7V to 5.5V, fS ≤ 250kHz ● ±2 ±6 ±3 ±16 LSB

DD

= 2.7V to 5.5V, fS ≤ 250kHz ● ±2 ±6 ±3 ±16 LSB

DD

The ● denotes the specifications which apply over the full operating

LTC1852 LTC1853

● ±0.5 ±2 ±1 ±6LSB

● ±1 ±4 ±2 ±12 LSB

UU

A ALOG I PUT

specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

I

IN

C

IN

t

ACQ

t

S(MUX)

t

AP

t

jitter

CMRR Analog Input Common Mode Rejection Ratio 60 dB

Analog Input Range (Note 9) 2.7V ≤ VDD ≤ 5.5V, REFCOMP ≤ V
Unipolar, Gain = 1 (PGA = 1) 0 – REFCOMP V
Unipolar, Gain = 2 (PGA = 0) 0 – REFCOMP/2 V
Bipolar, Gain = 1 (PGA = 1) ±REFCOMP/2 V
Bipolar, Gain = 2 (PGA = 0) ±REFCOMP/4 V

Analog Input Leakage Current ● ±1 µA
Analog Input Capacitance Between Conversions (Gain = 1) 15 pF

Sample-and-Hold Acquisition Time 50 150 ns
Multiplexer Settling Time (Includes t
Sample-and-Hold Aperture Delay Time VDD = 5V –0.5 ns
Sample-and-Hold Aperture Delay Time Jitter VDD = 5V 2 ps

U

W

DY A IC ACCURACY

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

S/(N + D) Signal-to-Noise Plus Distortion Ratio 40kHz Input Signal 72.5 dB
THD Total Harmonic Distortion 40kHz Input Signal, First 5 Harmonics –80 dB
SFDR Spurious Free Dynamic Range 40kHz Input Signal –85 dB

The ● denotes the specifications which apply over the full operating temperature range, otherwise

DD

Between Conversions (Gain = 2) 25 pF
During Conversions 5 pF

) 50 150 ns

ACQ

TA = 25°C. (Note 5)

18523f

RMS

3

LTC1852/LTC1853

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I TER AL REFERE CE

PARAMETER CONDITIONS MIN TYP MAX UNITS

REFOUT Output Voltage I
REFOUT Output Temperature Coefficient I
REFOUT Line Regulation 2.7 ≤ VDD ≤ 5.5, I
Reference Buffer Gain 1.6368 1.6384 1.6400 V/V
REFCOMP Output Voltage External 2.5V Reference (VDD = 5V) 4.092 4.096 4.100 V

REFCOMP Impedance Impedance to GND, REFIN = V

TA = 25°C. (Notes 5, 6)

= 0 2.48 2.50 2.52 V

OUT

= 0 ±15 ppm/°C

OUT

= 0 0.01 LSB/V

OUT

Internal 2.5V Reference (V

= 5V) 4.060 4.096 4.132 V

DD

DD

19.2 kΩ

UU

DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IN

C

IN

V

OH

V

OL

I

OZ

C

OZ

I

SOURCE

I

SINK

High Level Input Voltage VDD = 5.25V ● 2.4 V
Low Level Input Voltage VDD = 4.75V ● 0.8 V
Digital Input Current VIN = 0V to V
Digital Input Capacitance 1.5 pF
High Level Output Voltage VDD = 4.75V, IO = –10µA 4.5 V

= 4.75V, IO = –200µA ● 4V

V

DD

Low Level Output Voltage VDD = 4.75V, IO = 160µA 0.05 V

= 4.75V, IO = 1.6mA ● 0.10 0.4 V

V

DD

Hi-Z Output Leakage D11 to D0, A0, A1, A2
Hi-Z Capacitance D11 to D0 CS High (Note 9) ● 15 pF
Output Source Current V
Output Sink Current V

OUT

, DIFF

OUTVOUT

OUT

OUT

= 0V to VDD, CS High ● ±10 µA

= 0V –20 mA
= V

The ● denotes the specifications which apply over the

DD

DD

● ±5 µA

30 mA

UU

DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IN

C

IN

V

OH

V

OL

I

OZ

C

OZ

I

SOURCE

I

SINK

High Level Input Voltage VDD = 3.3V ● 1.9 V
Low Level Input Voltage VDD = 2.7V ● 0.45 V
Digital Input Current VIN = 0V to V
Digital Input Capacitance 1.5 pF
High Level Output Voltage VDD = 2.7V, IO = –10µA 2.5 V

= 2.7V, IO = –200µA ● 2V

V

DD

Low Level Output Voltage VDD = 2.7V, IO = 160µA 0.05 V

= 2.7V, IO = 1.6mA ● 0.10 0.4 V

V

DD

Hi-Z Output Leakage D11 to D0, A0, A1, A2
Hi-Z Capacitance D11 to D0 CS High (Note 9) ● 15 pF
Output Source Current V
Output Sink Current V

OUT

, DIFF

OUTVOUT

OUT

OUT

= 0V to VDD, CS High ● ±10 µA

= 0V –10 mA
= V

The ● denotes the specifications which apply over the

DD

DD

● ±5 µA

15 mA

18523f

4

LTC1852/LTC1853

WU

POWER REQUIRE E TS

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

DD

OV
I

DD

P

DISS

I

DDPD

DD

Analog Positive Supply Voltage (Note 10) ● 2.7 5.5 V
Output Positive Supply Voltage (Note 10) ● 2.7 5.5 V
Positive Supply Current VDD = OVDD = 5V, fS = 400kHz ● 23mA

Power Dissipation VDD = OVDD = 5V, fS = 400kHz ● 10 15 mW

Power Down Positive Supply Current
Nap Mode SHDN = Low, CS = Low 0.5 mA
Sleep Mode SHDN = Low, CS = High 20 µA

Power Down Power Dissipation VDD = VDD = OVDD = 5V, fS = 400kHz
Nap Mode SHDN = Low, CS = Low 2.5 mW
Sleep Mode SHDN = Low, CS = High 0.1 mW

Power Down Power Dissipation VDD = VDD = OVDD = 3V, fS = 250kHz
Nap Mode SHDN = Low, CS = Low 1.5 mW
Sleep Mode SHDN = Low, CS = High 0.06 mW

The ● denotes the specifications which apply over the full operating temperature

V

= OVDD = 2.7V, fS = 250kHz ● 0.83 1.33 mA

DD

V

= OVDD = 2.7V, fS = 250kHz ● 2.25 4 mW

DD

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 5)

The ● denotes the specifications which apply over the full operating temperature

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

SAMPLE(MAX)

t

CONV

t

ACQ

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

Maximum Sampling Frequency VDD = 5.5V ● 400 kHz

V

= 2.7V ● 250 kHz

DD

Acquisition + Conversion VDD = 5.5V ● 2.5 µs

VDD = 2.7V ● 4.0 µs

Conversion Time VDD = 5.5V ● 2.0 µs

VDD = 2.7V ● 3.5 µs

Acquisition Time (Note 13) ● 150 ns
CS to RD Setup Time (Notes 9, 10) ● 0ns
CS to CONVST Setup Time (Notes 9, 10) ● 10 ns
CS to SHDN Setup Time (Notes 9, 10) 200 ns
SHDN to CONVST Wake-Up Time Nap Mode (Note 10) 200 ns

Sleep Mode (Note 10) 10 ms

CONVST Low Time (Notes 10, 11) ● 50 ns
CONVST to BUSY Delay CL = 25pF 10 ns

● 60 ns

Data Ready Before BUSY 20 35 ns

● 15 ns

Delay Between Conversions (Note 10) ● 50 ns
Wait Time RD After BUSY ● –5 ns
Data Access Time After RD CL = 25pF 20 35 ns

● 45 ns

CL = 100pF 25 45 ns

● 60 ns

BUS Relinquish Time 10 30 ns

0°C to 70°C
–40°C to 85°C ● 40 ns

● 35 ns

18523f

5

LTC1852/LTC1853

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t

12

t

13

t

14

t

15

t

16

t

17

t

18

t

19

t

20

t

21

t

22

t

23

t

24

t

25

t

26

t

27

Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.

Note 2: All voltage values are with respect to ground with OGND and GND
wired together unless otherwise noted.

Note 3: When these pin voltages are taken below ground or above VDD,
they will be clamped by internal diodes. This product can handle input
currents of 100mA below ground or above V

Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents of
100mA below ground without latchup. These pins are not clamped to VDD.

Note 5: V
specified.

Note 6: Linearity, offset and full-scale specifications apply for a single­ended input on any channel with COM grounded.

Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.

RD Low Time ● t
CONVST High Time (Note 10) ● 50 ns
Latch Setup Time (Note 10) ● 10 ns
Latch Hold Time (Notes 9, 10) ● 10 ns
WR Low Time (Note 10) ● 50 ns
WR High Time (Note 10) ● 50 ns
M1 to M0 Setup Time (Notes 9, 10) ● 10 ns
M0 to BUSY Delay M1 High 20 ns
M0 to WR (or RD) Setup Time (Notes 9, 10) ● t
M0 High Pulse Width (Note 10) ● 50 ns
RD High Time Between Readback Reads (Note 10) ● 50 ns
Last WR (or RD) to M0 (Note 10) ● 10 ns
M0 to RD Setup Time (Notes 9, 10) ● t
M0 to CONVST (Note 10) ● t
Aperture Delay –0.5 ns
Aperture Jitter 2ps

without latchup.

DD

= 5V, f

DD

= 400kHz, tr = tf = 2ns unless otherwise

SAMPLE

The ● denotes the specifications which apply over the full operating temperature

10

19

19
19

Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 1111 1111 1111 and 0000 0000 0000.
For the LTC1853 and between 11 1111 1111 and 00 0000 0000 for the
LTC1852.

Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns

high at a critical point during the conversion it can create small errors. For
the best results, ensure that CONVST returns high either within 400ns
after the start of the conversion or after BUSY rises.

Note 12: The analog input range is determined by the voltage on
REFCOMP. The gain error specification is tested with an external 4.096V
but is valid for any value of REFCOMP greater than 2V and less than

– 0.5V.)

(V

DD

Note 13: MUX address is updated immediately after BUSY falls.

ns

ns

ns
ns

RMS

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Differential Linearity

1.0

0.5

0

DNL ERROR (LBS)

–0.5

–1.0

0 4096

CODE

1852 F02

6

8192 Point FFT with
fIN = 39.599kHz

0

–20

–40

–60

–80

AMPLITUDE (dB)

–100

–120

0200

FREQUENCY (kHz)

1852 F03

18523f

LTC1852/LTC1853

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UU

PI FU CTIO S

CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can
be used single ended relative to the analog input common
pin or differentially in pairs (CH0 and CH1, CH2 and CH3,
CH4 and CH5, CH6 and CH7).

COM (Pin 9): Analog Input Common Pin. For single-ended
operation (DIFF = 0), COM is the “–” analog input. COM is
disabled when DIFF is high.

REFOUT (Pin 10): Internal 2.5V Reference Output. Bypass
to analog ground plane with 1µF.

REFIN (Pin 11): Reference Mode Select/Reference Buffer
Input. REFIN selects the reference mode and acts as the
reference buffer input. REFIN tied to ground (Logic 0) will
produce 2.048V on the REFCOMP pin. REFIN tied to the
positive supply (Logic 1) disables the reference buffer to
allow REFCOMP to be driven externally. For voltages
between 1V and 2.6V, the reference buffer produces an
output voltage on the REFCOMP pin equal to 1.6384 times
the voltage on REFIN (4.096V on REFCOMP for a 2.5V
input on REFIN).

REFCOMP (Pin 12): Reference Buffer Output. REFCOMP
sets the full-scale input span. The reference buffer pro­duces an output voltage on the REFCOMP pin equal to

1.6384 times the voltage on the REFIN pin (4.096V on
REFCOMP for a 2.5V input on REFIN). REFIN tied to
ground will produce 2.048V on the REFCOMP pin.
REFCOMP can be driven externally if REFIN is tied to the
positive supply. Bypass to analog ground plane with 10µF
tantalum in parallel with 0.1µF ceramic or 10µF ceramic.

GND (Pins 13, 16): Ground. Tie to analog ground plane.
VDD (Pins 14, 15): Positive Supply. Bypass to analog

ground plane with 10µF tantalum in parallel with 0.1µF
ceramic or 10µF ceramic.

DIFF

Active when RD is low. Following a conversion, the single­ended/differential bit of the present conversion is available
on this pin concurrent with the conversion result. In
Readback mode, the single-ended/differential bit of the
current sequencer location (S6) is available on this pin.
The output swings between OVDD and OGND.

/S6 (Pin 17): Three-State Digital Data Output.

OUT

A2

/S5, A1

OUT

State Digital MUX Address Outputs. Active when RD is
low. Following a conversion, the MUX address of the
present conversion is available on these pins concurrent
with the conversion result. In Readback mode, the MUX
address of the current sequencer location (S5-S3) is
available on these pins. The outputs swing between OV
and OGND.

D9/S2 (Pin 21, LTC1852): Three-State Digital Data Out­put. Active when RD is low. Following a conversion, bit 9
of the present conversion is available on this pin. In
Readback mode, the unipolar/bipolar bit of the current
sequencer location (S2) is available on this pin. The output
swings between OVDD and OGND.

D11/S2 (Pin 21, LTC1853): Three-State Digital Data Out­put. Active when RD is low. Following a conversion, bit 11
of the present conversion is available on this pin. In
Readback mode, the unipolar/bipolar bit of the current
sequencer location (S2) is available on this pin. The output
swings between OVDD and OGND.

D8/S1 (Pin 22, LTC1852): Three-State Digital Data Out­puts. Active when RD is low. Following a conversion, bit 8
of the present conversion is available on this pin. In
Readback mode, the gain bit of the current sequencer
location (S1) is available on this pin. The output swings
between OVDD and OGND.

D10/S1 (Pin 22, LTC1853): Three-State Digital Data Out­puts. Active when RD is low. Following a conversion, bit 10
of the present conversion is available on this pin. In
Readback mode, the gain bit of the current sequencer
location (S1) is available on this pin. The output swings
between OVDD and OGND.

D7/S0 (Pin 23, LTC1852): Three-State Digital Data Out­puts. Active when RD is low. Following a conversion, bit 7
of the present conversion is available on this pin. In
Readback mode, the end of sequence bit of the current
sequencer location (S0) is available on this pin. The output
swings between OVDD and OGND.

OUT

/S4, A0

/S3 (Pins 18 to 20): Three-

OUT

DD

18523f

7

LTC1852/LTC1853

U

UU

PI FU CTIO S

D9/S0 (Pin 23, LTC1853): Three-State Digital Data Out­puts. Active when RD is low. Following a conversion, bit 9
of the present conversion is available on this pin. In
Readback mode, the end of sequence bit of the current
sequencer location (S0) is available on this pin. The output
swings between OVDD and OGND.

D6 to D0 (Pins 24 to 30, LTC1852): Three-State Digital
Data Outputs. Active when RD is low. The outputs swing
between OVDD and OGND.

D8 to D0 (Pins 24 to 32, LTC1853): Three-State Digital
Data Outputs. Active when RD is low. The outputs swing
between OVDD and OGND.

NC (Pins 31 to 32, LTC1852): No Connect. There is no
internal connection to these pins.

BUSY (Pin 33): Converter Busy Output. The BUSY output
has two functions. At the start of a conversion, BUSY will
go low and remain low until the conversion is completed.
The rising edge may be used to latch the output data. BUSY
will also go low while the part is in Program/Readback
mode (M1 high, M0 low) and remain low until M0 is brought
back high. The output swings between OVDD and OGND.

OGND (Pin 34): Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.

A0 to A2 (Pins 39 to 41): MUX Address Input Pins.
DIFF (Pin 42): Single-Ended/Differential Select Input. A

low logic level selects single ended, a high logic level
selects differential.

WR (Pin 43): Write Input. In Direct Address mode, WR low
enables the MUX address and configuration input pins
(Pins 37 to 42). WR can be tied low or the rising edge of
WR can be used to latch the data. In Program mode, WR
is used to program the sequencer. WR low enables the
MUX address and configuration input pins (Pins 37 to 42).
The rising edge of WR latches the data and increments the
counter to the next sequencer location.

RD (Pin 44): Read Input. During normal operation, RD
enables the output drivers when CS is low. In Readback
mode (M1 high, M0 low), RD going low reads the current
sequencer location, RD high advances to the next se­quencer location.

CONVST (Pin 45): Conversion Start Input. This active low
signal starts a conversion on its falling edge.

CS (Pin 46): Chip Select Input. The chip select input must
be low for the ADC to recognize the CONVST and RD
inputs. If SHDN is low, a low logic level on CS selects Nap
mode; a high logic level on CS selects Sleep mode.

OVDD (Pin 35): Digital Data Output Supply. Normally tied
to 5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10µF tantalum in parallel with 0.1µF ceramic
or 10µF ceramic.

M0 (Pin 36): Mode Select Pin 0. Used in conjunction with
M1 to select operating mode. See Table 5.

PGA (Pin 37): Gain Select Input. A high logic level selects
gain = 1, a low logic level selects gain = 2.

UNI/BIP (Pin 38): Unipolar/Bipolar Select Input. Logic low
selects a unipolar input span, a high logic level selects a
bipolar input span.

SHDN (Pin 47): Power Shutdown Input. A low logic level
will invoke the Shutdown mode selected by the CS pin. CS
low selects Nap mode, CS high selects Sleep mode. Tie
high if unused.

M1 (Pin 48): Mode Select Pin 1. Used in conjunction with
M0 to select operating mode. See Table 5.

18523f

8

LTC1852/LTC1853

U

UU

PI FU CTIO S

NOMINAL (V) ABSOLUTE MAXIMUM (V)

PIN NAME DESCRIPTION MIN TYP MAX MIN MAX

1 to 8 CH0 to CH7 Analog Inputs 0 V
9 COM Analog Input Common Pin 0 V

DD

DD

10 REFOUT 2.5V Reference Output 2.5 – 0.3 VDD + 0.3
11 REFIN Reference Buffer Input 0 2.5 V

DD

12 REFCOMP Reference Buffer Output 4.096 –0.3 VDD + 0.3
13 GND Ground 0 –0.3 VDD + 0.3
14 V
15 V

DD

DD

Positive Supply 2.7 5 5.5 –0.3 6

Positive Supply 2.7 5 5.5 –0.3 6
16 GND Ground 0 –0.3 VDD + 0.3
17 DIFF
18 A2
19 A1
20 A0
21 D9/S2 (LTC1852) Data Output OGND OV
21 D11/S2 (LTC1853) Data Output OGND OV
22 D8/S1 (LTC1852) Data Output OGND OV
22 D10/S1 (LTC1853) Data Output OGND OV
23 D7/S0 (LTC1852) Data Output OGND OV
23 D9/S0 (LTC1853) Data Output OGND OV
24 to 30 D6 to D0 (LTC1852) Data Outputs OGND OV
24 to 32 D8 to D0 (LTC1853) Data Outputs OGND OV

/S6 Single-Ended/Differential Output OGND OV

OUT

/S5 MUX Address Output OGND OV

OUT

/S4 MUX Address Output OGND OV

OUT

/S3 MUX Address Output OGND OV

OUT

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

31 to 32 NC (LTC1852) No Connect
33 BUSY Converter Busy Output OGND OV

DD

34 OGND Output Ground 0 –0.3 VDD + 0.3
35 OV

DD

36 M0 Mode Select Pin 0 0 V
37 PGA Gain Select Input 0 V
38 UNI/BIP Unipolar/Bipolar Input 0 V
39 to 41 A0 to A2 MUX Address Inputs 0 V
42 DIFF Single-Ended/Differential Input 0 V
43 WR Write Input, Active Low 0 V
44 RD Read Input, Active Low 0 V
45 CONVST Conversion Start Input, Active Low 0 V
46 CS Chip Select Input, Active Low 0 V
47 SHDN Shutdown Input, Active Low 0 V
48 M1 Mode Select Pin 1 0 V

Output Supply 2.7 5 5.5 –0.3 6

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

–0.3 VDD + 0.3
–0.3 VDD + 0.3

–0.3 VDD + 0.3

–0.3 VDD + 0.3
–0.3 VDD + 0.3
–0.3 VDD + 0.3
–0.3 VDD + 0.3
–0.3 VDD + 0.3
–0.3 VDD + 0.3
–0.3 VDD + 0.3
–0.3 VDD + 0.3
–0.3 VDD + 0.3
–0.3 VDD + 0.3
–0.3 VDD + 0.3
–0.3 VDD + 0.3

–0.3 VDD + 0.3

–0.3 6
–0.3 6
–0.3 6
–0.3 6
–0.3 6
–0.3 6
–0.3 6
–0.3 6
–0.3 6
–0.3 6
–0.3 6

18523f

9

LTC1852/LTC1853

WUUU

APPLICATIO S I FOR ATIO

The LTC1852/LTC1853 are complete and very flexible data
acquisition systems. They consist of a 10-bit/12-bit,
400ksps capacitive successive approximation A/D con­verter with a wideband sample-and-hold, a configurable
8-channel analog input multiplexer, an internal reference
and reference buffer amplifier, a 16-bit parallel digital
output and digital control logic, including a programmable
sequencer.

CONVERSION DETAILS

T

he core analog-to-digital converter in the
LTC1853
an internal sample-and-hold circuit to convert an analog
signal to a 10-bit/12-bit parallel output. Conversion start
is controlled by the CS and CONVST inputs. At the start of
the conversion, the successive approximation register
(SAR) is reset. Once a conversion cycle is begun, it cannot
be restarted. During the conversion, the internal differen­tial capacitive DAC output is sequenced by the SAR from
the most significant bit (MSB) to the least significant bit
(LSB). The outputs of the analog input multiplexer are
connected to the sample-and-hold capacitors (C
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 150ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase, the comparator zeroing switches
are open, putting the comparator into compare mode. The
input switches connect C
the differential analog input charge onto the summing
junction. This input charge is successively compared with
the binary weighted charges supplied by the differential
ca

pacitive DAC. Bit decisions are made by the high speed
comparator. At the end of the conversion, the differential
DAC output balances the input charges. The SAR contents
(a 10-bit/12-bit data word), which represents the differ­ence of the analog input multiplexer outputs, and the 4-bit
address word are loaded into the 14-bit/16-bit output
latches.

uses a successive approximation algorithm and

SAMPLE

to ground, transferring

LTC1852/

SAMPLE

)

DYNAMIC PERFORMANCE

Signal-to-(Noise + Distortion) Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency. The effective number of bits (ENOBs) is a
measurement of the resolution of an ADC and is directly
related to the S/(N + D) by the equation:

ENOB = [S/(N + D) – 1.76]/6.02

where ENOB is the effective number of bits and S/(N + D)
is expressed in dB. At the maximum sampling rate of
400kHz, the LTC1852/LTC1853 maintain near ideal ENOBs
up to and beyond the Nyquist input frequency of 200kHz.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:

222 2

VVV Vn

+++

THD Log

=

20

where V1 is the RMS amplitude of the fundamental
frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The LTC1852/LTC1853
have good distortion performance up to the Nyquist
frequency and beyond.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.

234

V

1

...

10

18523f

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APPLICATIO S I FOR ATIO

LTC1852/LTC1853

If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func­tion can create distortion products at the sum and differ­ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include (fa ± fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:

Amplitude at fa fb

IMD fa fb Log

±

=

()

20

Amplitude at fa

±

()

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spec­tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.

Full-Power and Full-Linear Bandwidth

The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re­duced by 3dB for a full-scale input signal.

The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB for the LTC1853 (11
effective bits) or 56dB for the LTC1852 (9 effective bits).
The LTC1852/LTC1853 have been designed to optimize
input bandwidth, allowing the ADC to undersample input
signals with frequencies above the converter’s Nyquist
frequency. The noise floor stays very low at high frequen­cies; S/(N + D) becomes dominated by distortion at
frequencies far beyond Nyquist.

ANALOG INPUT MULTIPLEXER

The analog input multiplexer is controlled using the single­ended/differential pin (DIFF), three MUX address pins (A2,
A1, A0), the unipolar/bipolar pin (UNI/BIP) and the gain
select pin (PGA). The single-ended/differential pin (DIFF)
allows the user to configure the MUX as eight single­ended channels relative to the analog input common pin
(COM) when DIFF is low or as four differential pairs (CH0
and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) when
DIFF is high. The channels (and polarity in the differential
case) are selected using the MUX address inputs as shown

in Table 1. Unused inputs (including the COM in the
differential case) should be grounded to prevent noise
coupling.

Table 1. Multiplexer Address Table

MUX ADDRESS SINGLE-ENDED CHANNEL SELECTION

DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

0000+ –
0001 + –
0010 + –
0011 + –
0100 + –
0101 + –
0110 + –
0111 + –

MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION

DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

1000+ – *
1001– + *
1010 + – *
1011 – + *
1100 + – *
1101 – + *
1110 + – *
1111 – + *

*Not used in differential mode. Connect to AGND.

In addition to selecting the MUX channel, the LTC1852/
LTC1853 also allows the user to select between two gains
and unipolar or bipolar inputs for a total of four input
spans. PGA high selects a gain of 1 (the input span is equal
to the voltage on REFCOMP). PGA low selects a gain of 2
where the input span is equal to half of the voltage on
REFCOMP. UNI/BIP low selects a unipolar input span,
UNI/BIP high selects a bipolar input span. Table 2 summa­rizes the possible input spans.

Table 2. Input Span Table

INPUT SPAN

UNI/BIP PGA REFCOMP = 4.096V

0 0 0 – REFCOMP/2 0 – 2.048V
0 1 0 – REFCOMP 0 – 4.096V
10±REFCOMP/4 ±1.024V
11±REFCOMP/2 ±2.048V

18523f

11

LTC1852/LTC1853

WUUU

APPLICATIO S I FOR ATIO

The LTC1852/LTC1853 have a unique differential sample­and-hold circuit that allows rail-to-rail inputs. The ADC will
always convert the difference of the “+” and “–” inputs
independent of the common mode voltage. The common
mode rejection holds up to high frequencies. The only
requirement is that both inputs can not exceed the AV
power supply voltage or ground. When a bipolar input
span is selected the “+” input can swing ±full scale relative
to the “–” input but neither input can exceed AVDD or go
below ground.

Integral nonlinearity errors (INL) and differential nonlin­earity errors (DNL) are independent of the common mode
voltage, however, the bipolar offset will vary. The change
in bipolar offset is typically less than 0.1% of the common
mode voltage.

Some AC applications may have their performance limited
by distortion. Most circuits exhibit higher distortion when
signals approach the supply or ground. THD will degrade
as the inputs approach either power supply rail. Distortion
can be reduced by reducing the signal amplitude and
keeping the common mode voltage at approximately
midsupply.

DD

analog input(s) must settle after the small current spike
before the next conversion starts (settling time must be
less than 150ns for full throughput rate).

Choosing an Input Amplifier

Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
+1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz should be less than 100Ω.
The second requirement is that the closed-loop bandwidth
must be greater than 10MHz to ensure adequate small­signal settling for full throughput rate. The following list is
a summary of the op amps that are suitable for driving the
LTC1852/LTC1853, more detailed information is available
in the Linear Technology Databooks, the LinearView
CD-ROM and on our web site at www.linear-tech.com.

LT®1360: 50MHz Voltage Feedback Amplifier. ±2.5V to
±15V supplies. 5mA supply current. Low distortion.

TM

Driving the Analog Inputs

The inputs of the LTC1852/LTC1853 are easy to drive.
Each of the analog inputs can be used as a single-ended
input relative to the input common pin (CH0-COM, CH1­COM, etc.) or in pairs (CH0 and CH1, CH2 and CH3, CH4
and CH5, CH6 and CH7) for differential inputs. Regardless
of the MUX configuration, the “+” and “–” inputs are
sampled at the same instant. Any unwanted signal that is
common mode to both inputs will be reduced by the
common mode rejection of the sample-and-hold circuit.
The inputs draw only one small current spike while charg­ing the sample-and-hold capacitors at the end of conver­sion. During conversion, the analog inputs draw only a
small leakage current. If the source impedance of the
driving circuit is low, then the LTC1852/LTC1853 inputs
can be driven directly. As source impedance increases, so
will acquisition time. For minimum acquisition time with
high source impedance, a buffer amplifier should be used.
The only requirement is that the amplifier driving the

LT1363: 70MHz Voltage Feedback Amplifier. ±2.5V to
±15V supplies. 7.5mA supply current. Low distortion.

LT1364/LT1365: Dual and Quad 70MHz Voltage Feedback
Amplifiers. ±2.5V to ±15V supplies. 7.5mA supply current
per amplifier. Low distortion.

LT1468/LT1469: Single and Dual 90MHz Voltage Feed­back Amplifier. ±5V to ±15V supplies. 7mA supply current
per amplifier. Lowest noise and low distortion.

LT1630/LT1631: Dual and Quad 30MHz Rail-to-Rail Volt­age Feedback Amplifiers. Single 3V to ±15V supplies.

3.5mA supply current per amplifier. Low noise and low
distortion.

LT1632/LT1633: Dual and Quad 45MHz Rail-to-Rail Volt­age Feedback Amplifiers. Single 3V to ±15V supplies.

4.3mA supply current per amplifier. Low distortion.
LT1806/LT1807: Single and Dual 325MHz Rail-to-Rail

Voltage Feedback Amplifier. Single 3V to ±5V supplies.
13mA supply current. Lowest distortion.

12

LinearView is a trademark of Linear Technology Corporation.

18523f

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APPLICATIO S I FOR ATIO

LTC1852/LTC1853

LT1809/LT1810: Single and Dual 180MHz Rail-to-Rail
Voltage Feedback Amplifier. Single 3V to ±15V supplies.
20mA supply current. Lowest distortion.

LT1812/LT1813: Single and Dual 100MHz Voltage Feed­back Amplifier. Single 5V to ±5V supplies. 3.6mA supply
current. Low noise and low distortion.

Input Filtering

The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1852/LTC1853 noise and distortion. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For instance, a 200Ω source resistor
and a 1000pF capacitor to ground on the input will limit the
input bandwidth to 800kHz.The capacitor also acts as a
charge reservoir for the input sample-and-hold and iso­lates the ADC input from sampling glitch sensitive cir­cuitry. High quality capacitors and resistors should be
used since these components can add distortion. NPO and
silver mica type dielectric capacitors have excellent linear­ity. Carbon surface mount resistors can also generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.

REFERENCE

The LTC1852/LTC1853 includes an on-chip, temperature
compensated, curvature corrected, bandgap reference
that is factory trimmed to 2.500V and has a very flexible 3­pin interface. REFOUT is the 2.5V bandgap output, REFIN
is the input to the reference buffer and REFCOMP is the
reference buffer output. The input span is determined by
the voltage appearing on the REFCOMP pin as shown in
Table 2. The reference buffer has a gain of 1.6384 and is
factory trimmed by forcing an external 2.500V on the
REFIN pin and trimming REFCOMP to 4.096V. The 3-pin
interface allows for three pin-strappable Reference modes
as well as two additional external Reference modes. For
voltages on the REFIN pin ranging from 1V to 2.6V, the
output voltage on REFCOMP will equal 1.6384 times the
voltage on the REFIN pin. In this mode, the REFIN pin can
be tied to REFOUT to use the internal 2.5V reference to get

4.096V on REFCOMP or driven with an external reference
or DAC. If REFIN is tied low, the internal 2.5V reference
divided by 2 (1.25V) is connected internally to the input of
the reference buffer resulting in 2.048V on REFCOMP. If
REFIN is tied high, the reference buffer is disabled and
REFCOMP can be tied to REFOUT to achieve a 2.5V span
or driven with an external reference or DAC. Table 3
summarizes the Reference modes.

Table 3. Reference Mode Table

MODE REFIN REFCOMP

REFIN Tied Low 0V Input 2.048V Output
REFIN is Buffer Input 1V to 2.6V Input 1.6384V to 4.26V Output

(1.6384 • REFIN)

REFIN Tied High 5V Input Input, 19.2kΩ to Ground

Full Scale and Offset

In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero during
a calibration sequence. Offset error must be adjusted
before full-scale error. Zero offset is achieved by adjusting
the offset applied to the “–” input. For single-ended inputs,
this offset should be applied to the COM pin. For differen­tial inputs, the “–” input is dictated by the MUX address.
For zero offset error, apply 0.5LSB (actual voltage will vary
with input span selected) to the “+” input and adjust the
offset at the “–” input until the output code flickers
between 0000 0000 0000 and 0000 0000 0001 for the
LTC1853 and between 00 0000 0000 and 00 0000 0001 for
the LTC1852.

As mentioned earlier, the internal reference is factory
trimmed to 2.500V. To make sure that the reference buffer
gain is not compensating for trim errors in the reference,
REFCOMP is trimmed to 4.096V with an extremely accu­rate external 2.5V reference applied to REFIN. Likewise, to
make sure that the full-scale gain trim is not compensating
for errors in the reference buffer gain, the input full-scale
gain is trimmed with an extremely accurate 4.096V refer­ence applied to REFCOMP (REFIN = 5V to disable the
reference buffer). This allows the use of either a 2.5V
reference applied to REFIN or a 4.096V reference applied
to REFCOMP to achieve accurate results. Full-scale errors
can be trimmed to zero by adjusting the appropriate
reference voltage. For unipolar inputs, an input voltage of

18523f

13

LTC1852/LTC1853

SINGLE-ENDED/

DIFFERENTIAL BIT

UNIPOLAR/

BIPOLAR BIT

S6 S5

A2 A0

END OF

SEQUENCE BIT

PGA BIT

18523 F01

A1

MUX ADDRESS

S4 S3 S2 S1 S0

WUUU

APPLICATIO S I FOR ATIO

FS – 1.5LSBs should be applied to the “+” input and the
appropriate reference adjusted until the output code flick­ers between 1111 1111 1110 and 1111 1111 1111 for the
LTC1853 and between 11 1111 1110 and 11 1111 1111 for
the LTC1852.

For bipolar inputs, an input voltage of FS – 1.5LSBs should
be applied to the “+” input and the appropriate reference
adjusted until the output code flickers between 0111 1111
1110 and 0111 1111 1111 for the LTC1853 and between
01 1111 1110 and 01 1111 1111 for the LTC1852.

These adjustments as well as the factory trims affect all
channels. The channel-to-channel offset and gain error
matching are guaranteed by design to meet the specifica­tions in the Converter Characteristics table.

OUTPUT DATA FORMAT

The LTC1852/LTC1853 have a 14 bit/16-bit parallel out­put. The output word normally consists of a 10-bit/12-bit
conversion result data word and a 4-bit address (three
address bits A2

OUT

, A1

OUT

, A0

and the DIFF

OUT

OUT

bit).
The output drivers are enabled when RD is low provided
the chip is selected (CS is low). All 14/16 data output pins
and BUSY are supplied by OVDD and OGND to allow easy
interface to 3V or 5V digital logic.

The data format of the conversion result is automatically
selected and determined by the UNI/BIP input pin. If the
UNI/BIP pin is low indicating a unipolar input span
(0 – REFCOMP assuming PGA = 1), the format for the
data is straight binary with 1 LSB = FS/4096 (1mV for
REFCOMP = 4.096V). For the LTC1853 and 1LSB = FS/
1024 (4mV for REFCOMP = 4.096V) for the LTC1852.

If the UNI/BIP pin is high indicating a bipolar input span
(±REFCOMP/2 for PGA = 1), the format for the data is
two’s complement binary with 1 LSB = [(+FS) – (–FS)]/
4096 (1mV for REFCOMP = 4.096V). For the LTC1853 and
1LSB = [(+FS) – (– FS)]/1024 (4mV for REFCOMP =

4.096V) for the LTC1852.

The three most significant bits of the data word (D11, D10
and D9 for the LTC1853; D9, D8 and D7 for the LTC1852)
also function as output bits when reading the contents of
the programmable sequencer. During readback, a 7-bit
status word (S6-S0) containing the contents of the cur­rent sequencer location is available when RD is low. The
individual bits of the status word are outlined in Figure 1.
During readback, the D8 to D0 pins (LTC1853) or D6 to D0
pins (LTC1852) remain high impedance irrespective of
the state of RD.

Unipolar Transfer Characteristic
(UNI/BIP = 0)

1111...1111

1111...1110

1111...1101

1000...0001

1000...0000

0111...1111

OUTPUT CODE

0111...1110

0000...0010

0000...0001

0000...0000

0111...1111

0111...1110

0111...1101

0000...0001

0000...0000

1111...1111

OUTPUT CODE

1111...1110

1000...0010

1000...0001

1000...0000

0 FS – 1LBS

INPUT VOLTAGE (V)

Bipolar Transfer Characteristic
(UNI/BIP = 1)

–FS –1LBS 0 1LBS FS – 1LBS

INPUT VOLTAGE (V)

BIPOLAR

ZERO

FS = V

FS =

REFCOMP

V

REFCOMP

2

18523 F01A

18523 F01B

In both cases, the code transitions occur midway between
successive integer LSB values (i.e., –FS + 0.5LSB,
–FS + 1.5LSB, ... – 1.5LSB, –0.5LSB, 0.5LSB, 1.5LSB, ...
FS – 1.5LSB, FS – 0.5LSB).

14

Figure 1. Readback Status Word

18523f

WUUU

SHDN

CONVST

t

4

18523 F03

APPLICATIO S I FOR ATIO

LTC1852/LTC1853

BOARD LAYOUT AND BYPASSING

To obtain the best performance from the LTC1852/
LTC1853, a printed circuit board with ground plane is
required. The ground plane under the ADC area should be
as free of breaks and holes as possible, such that a low
impedance path between all ADC grounds and all ADC
decoupling capacitors is provided. It is critical to prevent
digital noise from being coupled to the analog inputs,
reference or analog power supply lines. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particu­lar, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.

An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 34 (OGND), Pin 13 (GND), Pin 16 (GND) and all other
analog grounds should be connected to this single analog
ground point. The bypass capacitors should also be con­nected to this analog ground plane. No other digital
grounds should be connected to this analog ground plane.
In some applications, it may be desirable to connect the
OVDD to the logic system supply and OGND to the logic
system ground. In these cases, OVDD should be bypassed
to OGND instead of the analog ground plane.

Low impedance analog and digital power supply common
returns are essential to the low noise operation of the ADC
and the foil width for these tracks should be as wide as
possible. In applications where the ADC data outputs and
control signals are connected to a continuously active
microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
from the microprocessor to the sucessive approximation
comparator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversions or
by using three-state buffers to isolate the ADC bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.

The LTC1852/LTC1853 have differential inputs to mini­mize noise coupling. Common mode noise on the “+” and
“–” inputs will be rejected by the input CMRR. The LTC1852/
LTC1853 will hold and convert the difference between
whichever input is selected as the “+” input and whichever

input is selected as the “–” input. Leads to the inputs
should be kept as short as possible.

SUPPLY BYPASSING

High quality, low series resistance ceramic 10µF bypass
capacitors should be used. Surface mount ceramic ca­pacitors such as Murata GRM235Y5V106Z016 provide
excellent bypassing in a small board space. Alternatively,
10µF tantalum capacitors in parallel with 0.1µF ceramic
capacitors can be used. Bypass capacitors must be lo­cated as close to the pins as possible. The traces connect­ing the pins and the bypass capacitors must be kept short
and should be made as wide as possible.

DIGITAL INTERFACE

Internal Clock

The A/D converter has an internal clock that eliminates
the need of synchronization between the external clock
and the CS and RD signals found in other ADCs. The
internal clock is factory trimmed to achieve a typical
conversion time of 1400ns, and a maximum conversion
time over the full operating temperature range of 2µs. No
external adjustments are required. The guaranteed maxi­mum acquisition time is 150ns. In addition, a throughput
time of 2.5µs and a minimum sampling rate of 400ksps
is guaranteed.

Figure 2. CS to SHDN Timing

CS

t

2

CONVST

t

1

RD

Figure 3. SHDN to CONVST Wake-Up Timing

18523 F04

18523f

15

LTC1852/LTC1853

WUUU

APPLICATIO S I FOR ATIO

CS

t

2

CONVST

t

1

RD

Figure 4. CS to CONVST Setup Timing

18523 F04

Power Shutdown

The LTC1852/LTC1853 provide two power shutdown
modes, Nap and Sleep, to save power during inactive
periods. The Nap mode reduces the power to 2.5mW and
leaves only the digital logic and reference powered up. The
wake-up time from Nap to active is 200ns. In Sleep mode,
all bias currents are shut down and only leakage current
remains—about 20µA. Wake-up time from sleep mode is
much slower since the reference circuit must power-up
and settle to 0.005% for full 12-bit accuracy (0.02% for full
10-bit accuracy). Sleep mode wake-up time is dependent
on the value of the capacitor connected to the REFCOMP
(Pin 12). The wake-up time is 10ms with the recom­mended 10µF capacitor.

Shutdown is controlled by Pin 47 (SHDN); the ADC is in
shutdown when it is low. The shutdown mode is selected
with Pin 46 (CS); low selects Nap.

ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY is
low during a conversion. If CONVST returns high at a
critical point during the conversion it can create small
errors. For the best results, ensure that CONVST returns
high either within 400ns after the start of the conversion
or after BUSY rises.

Figures 5 through 9 show several different modes of
operation. In modes 1a and 1b (Figures 5 and 6),
CS and RD are both tied low. The falling edge of
CONVST starts the conversion. The data outputs are
always enabled and data can be latched with the
BUSY rising edge. Mode 1a shows operation with a narrow
logic low CONVST pulse. Mode 1b shows a narrow logic
high CONVST pulse.

In mode 2 (Figure 7), CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the
RD signal. Mode 2 can be used for operation with a shared
MPU databus.

In slow memory and ROM modes (Figures 8 and 9),CS is
tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).

Timing and Control

Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
applied to the CONVST pin will start a conversion after the

t

CONV

t

5

CONVST

t

6

BUSY

t

DATA DATA (N – 1) DATA N

Figure 5. Mode 1a CONVST Starts a Conversion. Data Outputs Always Enabled (CS = RD = 0)

16

In slow memory mode, the processor applies a logic low
to RD ( = CONVST), starting the conversion. BUSY goes
low, forcing the processor into a Wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results

t

8

7

18523 F05

18523f

WUUU

APPLICATIO S I FOR ATIO

t

13

CONVST

t

CONV

LTC1852/LTC1853

t

t

5

8

t

6

BUSY

t

7

DATA DATA (N – 1) DATA N

Figure 6. Mode 1b CONVST Starts a Conversion, RD = CS = 0

t

CONV

CONVST

BUSY

RD

DATA

t

5

t

6

t

8

t

13

t

9

t

12

t

10

DATA N

t

11

Figure 7. Mode 2 CONVST Starts a Conversion. Data is Read by RD, CS = 0

t

6

18523 F06

18523 F07

t

CONV

RD = CONVST

t

6

BUSY

t

10

DATA DATA (N – 1) DATA (N + 1)DATA N DATA N

t

7

t

8

t

11

Figure 8. Slow Memory Mode Timing, CS = 0

CONVST

BUSY

DATA

t

CONV

t

6

t

10

t

11

DATA (N – 1) DATA N

t

8

Figure 9. ROM Mode Timing, CS = 0

18523 F08

18523 F09

18523f

17

LTC1852/LTC1853

WUUU

APPLICATIO S I FOR ATIO

ap

pear on the data outputs; BUSY goes high releasing the
processor, and the processor takes RD ( = CONVST) back
high and reads the new conversion data.

In ROM mode, the processor takes RD ( = CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.

MODES OF OPERATION

Direct Address Mode

The simplest mode of operation is the Direct Address
mode. This mode is selected when both the M1 and M0
pins are low. In this mode, the address input pins directly
control the MUX and the configuration input pins directly
control the input span. The address and configuration
input pins are enabled when WR is low. WR can be tied low
if the pins will be constantly driven or the rising edge of WR
can be used to latch and hold the inputs for as long as WR
is held high.

Scan Mode

Scan mode is selected when M1 is low and M0 is high.
This mode allows the converter to scan through all of the
input channels sequentially and repeatedly without the
user having to provide an address. The address input pins
(A2 to A0) are ignored but the DIFF, PGA and UNI/BIP pins
are still enabled when WR is low. As in the direct address
mode, WR can be held low or the rising edge of WR can
be used to latch and hold the information on these pins for
as long as WR is held high. The DIFF pin selects the scan
pattern. If DIFF is held low, the scan pattern will consist of
all eight channels in succession, single-ended relative to
COM (CH0-COM, CH1-COM, CH2-COM, CH3-COM, CH4­COM, CH5-COM, CH6-COM, CH7-COM, repeat). At the
maximum conversion rate the throughput rate for each
channel would be 400ksps/8 or 50ksps. If DIFF is held
high, the scan pattern will consist of four differential pairs
(CH0-CH1, CH2-CH3, CH4-CH5, CH6-CH7, repeat). At the
maximum conversion rate, the throughput rate for each
pair would be 400ksps/4 or 100ksps. It is possible to drive
the DIFF input pin while the part is in Scan mode to achieve
combinations of single-ended and differential inputs. For

instance, if the A0

pin is tied to the DIFF input pin, the

OUT

scan pattern will consist of four single-ended inputs and
two differential pairs (CH0-COM single-ended, CH1-COM
single-ended, CH2-CH3 differential, CH4-COM single­ended, CH5-COM single-ended, CH6-CH7 differential,
repeat).

The scan counter is reset to zero whenever the M0 pin
changes state so that the first conversion after M0 rises
will be MUX Address 000 (CH0-COM single-ended or CH0­CH1 differential depending on the state of the DIFF pin). A
conversion is initiated by the falling edge of CONVST. After
each conversion, the address counter is advanced (by one
if DIFF is low, by two if DIFF is high) and the MUX address
for the present conversion is available on the address
output pins (DIFF

OUT

, A2

OUT

to A0

) along with the

OUT

conversion result.

Program/Readback Mode

The LTC1852 and LTC1853 include a sequencer that can
be programmed to run a sequence of up to 16 locations
containing a MUX address and input configuration. The
MUX address and input configuration for each location are
programmed using the DIFF, A2 to A0, UNI/BIP and PGA
pins and are stored in memory along with an end-of­sequence (EOS) bit that is generated automatically. The
six input address and configuration bits plus the EOS bit
can be read back by accessing the 7-bit readback status
word (S6-S0) through the data output pins. The sequencer
memory is a 16 × 7 block of memory represented by the
block diagram in Figure 10.

DIFF A2 A1 A0 UNI/BIP PGA EOS

LOCATION 0000

LOCATION 0001

LOCATION 0010

•

•

•

•

•

•

LOCATION 1110

LOCATION 1111

Figure 10. Sequencer Memory Block Diagram

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

18523 F10

18523f

18

WUUU

APPLICATIO S I FOR ATIO

LTC1852/LTC1853

The sequencer is accessed by taking the M1 mode pin
high. With M1 high, the sequencer memory is accessed by
taking the M0 mode pin low. This will cause BUSY to go
low, disabling conversions during the programming and
readback of the sequencer. The sequencer is reset to
location 0000 whenever M1 or M0 changes state. One of
these signals should be cycled prior to any read or write
operation to guarantee that the sequencer will be pro-

and advance the pointer to the next location. A logic 1 on
the D9/S0 (D7/S0) pin indicates the last location in the
current sequence but all 16 locations can be read by
continuing to clock RD. After 16 reads, the pointer is reset
to location 0000. When all programming and/or reading of
the sequencer memory is complete, M0 is taken high.
BUSY will come back high enabling CONVST and indicat­ing that the part is ready to start a conversion.

grammed or read starting at location 0000.

Sequence Run Mode

The sequencer is programmed sequentially starting from
location 0000. RD and WR should be held high, the
appropriate signals applied to the DIFF pin, the A2 to A0
MUX address pins, the UNI/BIP pin and the PGA pin and
WR taken low to write to the memory. WR going high will
latch the data into memory and advance the pointer to the
next sequencer location. Up to 16 locations can be pro­grammed and the last location written before M0 is taken
back high will be the last location in the sequence. After 16
writes, the pointer is reset to location 0000 and any
subsequent writes will erase all of the previous contents
and start a new sequence.

Once the sequencer is programmed, M0 is taken high.
BUSY will also come back high enabling CONVST and the
next falling CONVST will begin a conversion using the
MUX address and input configuration stored in location
0000 of the sequencer memory. After each conversion, the
sequencer pointer is advanced by one and the MUX
address ( the actual channel or channels being converted,
not the sequencer pointer) for the present conversion is
available on the address output pins along with the con­version result. When the sequencer finishes converting
the last programmed location, the sequencer pointer will
return to location 0000 for the next conversion. The

The sequencer memory can be read by holding WR high
and strobing RD. Taking RD low accesses the sequencer

sequencer will also reset to location 0000 anytime the M1
or M0 pin changes state.

memory and enables the data output pins. The sequencer
should be reset to location 0000 before beginning a read
operation (by applying a positive pulse to MO). The seven
output bits will be available on the DIFF
A1

/S4, A0

OUT

(LTC1853) or DIFF

/S3, D11/S2, D10/S1 and D9/S0 pins

OUT

OUT

/S6, A2

OUT

/S5, A1

OUT

/S6, A2

/S4, A0

OUT

OUT

/S5,

OUT

S3, D9/S2, D8/S1 and D7/S0 pins (LTC1852). The D8 to
D0 (LTC1853) or D6 to D0 (LTC1852) data output pins will
remain high impedance during readback. RD going high
will return the data output pins to a high impedance state

Table 5

OPERATION MODE M1 M0 WR RD COMMENTS

Direct Address 0 0 0 OE Address and Configuration are Driven from External Pins

0 0 OE Address and Configuration are Latched on Rising Edge of WR or Falling Edge of CONVST

Scan 0 1 0 OE Address is Provided by Internal Scan Counter, Configuration is Driven from External Pins

0 1 OE Configuraton is Latched on Rising Edge of WR or Falling Edge of CONVST

Program 1 0 1 Write Sequencer Location, WR Low Enables Inputs, Rising Edge of WR Latches Data and

Advances to Next Location

Readback 1 0 1 Read Sequencer Location, Falling Edge of RD Enables Output, Rising Edge of RD

Advances to Next Location

Sequence Run 1 1 X OE Run Programmed Sequence, Falling Edge of CONVST Starts Conversion and Advances to

Next Location

The contents of the sequencer memory will be retained as
long as power is contiuously applied to the part. This
allows the user to switch from Sequence Run mode to
either Direct Address or Scan Mode and back without
losing the programmed sequence. The part can also be

/

disabled using CS or shutdown in Nap or Sleep mode
without losing the programmed sequence. Table 5 out­lines the operational modes of the LTC1852/LTC1853.
Figures 11 and 12 show the timing diagrams for writing to,
reading from and running a sequence.

18523f

19

LTC1852/LTC1853

WUUU

APPLICATIO S I FOR ATIO

23

t

12

t

10

t

n + 1

LOCATION

n

LOCATION

0001

LOCATION

18523 F11

M1

22

t

24

t

23

t

15

t

14

t

0000

LOCATION

11

t

Figure 11. Sequencer I/O

16

t

17

t

19

18

t

M0

CONVST

WR

20

t

RD

L0CATION 0000 L0CATION 0001 L0CATION n

DIFF

L0CATION 0000 L0CATION 0001 L0CATION n

A2 TO A0

L0CATION 0000 L0CATION 0001 L0CATION n

UNI/BIP

L0CATION 0000 L0CATION 0001 L0CATION n

PGA

t

Hi-Z

Hi-Z

BUSY

S6 TO S0

20

D6 TO D0 (LTC1852)

D8 TO D0 (LTC1853)

18523f

WUUU

APPLICATIO S I FOR ATIO

5

t

0000

CONVERT

0010

CONVERT

0001

CONVERT

8

t

LTC1852/LTC1853

18523 F12

0000

DATA

0010

DATA

10

t

11

t

0001

DATA

7

t

0000

DATA

M1

6

t

0000

CONVERT

25

t

17

t

23

t

L0CATION 0010

15

t

L0CATION 0010

L0CATION 0010

Figure 12. Programming and Running a Sequence

14

t

16

WR

t

RD

18

t

M0

CONVST

20

t

L0CATION 0000 L0CATION 0001

DIFF

L0CATION 0000 L0CATION 0001

A2 TO A0

L0CATION 0000 L0CATION 0001

UNI/BIP

19

t

L0CATION 0000 L0CATION 0001 L0CATION 0010

PGA

BUSY

Hi-Z

OUT

OUT

DIFF

TO A0

OUT

A2

D9 TO D0 (LTC1852)

D11 TO D0 (LTC1853)

18523f

21

LTC1852/LTC1853

TYPICAL APPLICATIO S

LTC1853 Hardwired for 8-Channel Single-Ended Scan with Unipolar 0V to 4.096V Operation

V

CH0

1

CH1

2

CH2

3

CH3

10µF

1µF

4

5

6

7

8

9

10

11

12

CH4

CH5

CH6

CH7

COM

REFOUT

REFIN

REFCOMP

GND GND

8-CHANNEL

MULTIPLEXER

2.5V

REFERENCE

REF AMP

13 16

INPUT
CONFIGURATION:
ALL 8 CHANNELS

SINGLE ENDED

TO COM

CH0–CH7:

0V TO 4.096V

2.5V

4.096V

0.1µF

U

14

DD

1.6384X

5V

0.1µF

10µF

15

V

DD

LTC1853

CONTROL LOGIC

AND

PROGRAMMABLE

SEQUENCER

INTERNAL

CLOCK

+
–

12-BIT

SAMPLING

ADC

DATA

LATCHES

OUTPUT

DRIVERS

DIFF

A2
A1
A0

SHDN

CONVST

WR

DIFF

UNI/BIP

PGA

OV

BUSY

/S6

OUT

/S5

OUT

/S4

OUT

/S3

OUT

D11/S2
D10/S1

D9/S0

OGND 34

18523 TA01

48

M1

36

M0

47
46

CS

45
44

RD

43
42
41

A2

40

A1

39

A0

38
37

35

DD

33
17
18
19
20
21
22
23
24

D8

25

D7

26

D6

27

D5

28

D4

29

D3

30

D2

31

D1

32

D0

5V

5V
5V

CONVERT

CLOCK

2.7V TO V

10µF

DD

0.1µF

22

18523f

TYPICAL APPLICATIO S

LTC1853 Hardwired for 4-Channel Differential Scan with Bipolar ±1.024V Operation

1

CH0

+

2

CH1

–

3

CH2

+

4

CH3

2.5V

10µF

1µF

–

5

CH4

+

–
+

–

10

11

12

6

7

8

9

REFOUT

REFIN

REFCOMP

MULTIPLEXER

CH5

CH6

CH7

COM

GND GND

13 16

INPUT

CONFIGURATION:

4 DIFFERENTIAL

CHANNELS: ±1.024V

4.096V

0.1µF

U

14

V

DD

8-CHANNEL

2.5V

REFERENCE

REF AMP

1.6384X

LTC1852/LTC1853

5V

10µF

LTC1853

12-BIT

ADC

0.1µF

INTERNAL

CLOCK

CONTROL LOGIC

PROGRAMMABLE

SEQUENCER

DATA

LATCHES

AND

OUTPUT

DRIVERS

DIFF

A2
A1
A0

SHDN

CONVST

DIFF

UNI/BIP

PGA

OV

BUSY

OUT
OUT
OUT
OUT

D11/S2
D10/S1

D9/S0

OGND 34

18523 TA02

WR

48

M1

36

M0

47
46

CS

45
44

RD

43
42
41

A2

40

A1

39

A0

38
37

35

DD

33
17

/S6

18

/S5

19

/S4

20

/S3

21
22
23
24

D8

25

D7

26

D6

27

D5

28

D4

29

D3

30

D2

31

D1

32

D0

5V
5V

CONVERT

CLOCK

5V

5V

10µF

3V TO 5V

0.1µF

15

V

DD

+

SAMPLING

–

U

PACKAGE DESCRIPTIO

FW Package

48-Lead Plastic TSSOP (6.1mm)

(Reference LTC DWG # 05-08-1651)

6.0 – 6.2**
(.236 – .244)

° – 8°

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

MILLIMETERS

(INCHES)

.09 – .20

(.0035 – .008)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

.45 – .75

(.018 – .029)

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0

12.4 – 12.6*
(.488 – .496)

48 46 4544434241 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 2547

1345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

2

-C­.50

(.0197)

BSC

.17 – .27

(.0067 – .0106)

(.311 – .327)

1.20

(.0473)

MAX

.05 – .15

(.002 – .006)

7.9 – 8.3

-T-

FW48 TSSOP 0501

18523f

23

C.10

LTC1852/LTC1853

TYPICAL APPLICATIO

U

Data buffering using two IDT7202LA15 1k x 9-bit FIFOs
allows rapid collection of 1024 samples and simple inter­face to low power, low speed, 8-bit microcontrollers. Data
and channel information are clocked in simultaneously
and read out as two bytes using READ HIGH FIFO and
READ LOW FIFO lines. In the event of bus contention,
resistors limit peak output current. If both FIFOs are read

INPUT
CONFIGURATION:
ALL 8 CHANNELS
SINGLE ENDED TO COM
CH0–CH7: 0V TO 4.096V

CH0

1

CH1

2

CH2

3

CH3

4

CH4

5

CH5

6

CH6

7

CH7

8

COM

9

REFOUT

10

2.5V

REFIN

11

1µF

8-CHANNEL

MULTIPLEXER

REFERENCE

REF AMP

0.1µF

V

2.5V

DD

14

1.6384X

REFCOMP

4.096V

10µF

5V

0.1µF

10µF

15

V

DD

LTC1853

CONTROL LOGIC

AND

PROGRAMMABLE

SEQUENCER

INTERNAL

CLOCK

+
–

12

12-BIT

SAMPLING

ADC

GND GND

13 16

DATA

LATCHES

OUTPUT

DRIVERS

OV

DD

DIFF

completely or reset before a burst of conversions, the
empty, half full, and full flags from only one FIFO need to
be monitored. The retransmit inputs may also be tied
together. Retransmit may be used to read data repeatedly,
allowing a memory limited processor to perform trans­form and filtering functions that would otherwise be
difficult.

0.1µF

5V

IDT7202LA15

2

D8

24

D7

25

D6

26

D5

27

D4

3

D3

4

D2

5

D1

6

D0

1

WR

8

FF

22

RS

XI

7

5V

24
25
26
27

22

28

GND

IDT7202LA15

2

D8
D7
D6
D5
D4

3

D3

4

D2

5

D1

6

D0

1

WR

8

FF
RS

XI

7

13

Q8

18

Q7

18

Q6

17

Q5

16

Q4

12

Q3

11

Q2

10

Q1

9

Q0

15

R

21

EF

20

HF

23

RT

14

0.1µF

28

GND

8 × 1k

READ_HIGH_FIFO
HIGH_FIFO_EMPTY
HIGH_FIFO_HALF_FULL
HIGH BYTE_FIFO_RETRANSMIT

HIGH_FIFO_FULL_FLAG
LOW_FIFO_FULL_FLAG
FIFO_RESET

13

Q8

8 × 1k

19

Q7

18

Q6

17

Q5

16

Q4

12

Q3

11

Q2

10

Q1

9

Q0

15

R

READ_LOW_FIFO

21

EF

LOW_FIFO_EMPTY

20

HF

LOW_FIFO_HALF_FULL

23

RT

LOW BYTE_FIFO_RETRANSMIT

14

DATA BUS

18523 TA03

8-BIT

D7
D6
D5
D4
D3
D2
D1
D0

35

SHDN

CONVST

DIFF

UNI/BIP

PGA

BUSY

OUT

A2

OUT

A1

OUT

A0

OUT

D11/S2
D10/S1

D9/S0

OGND 34

*CONVERT

UP TO 1024

M1
M0

CS

RD

WR

A2
A1
A0

/S6
/S5
/S4
/S3

D8
D7
D6
D5
D4
D3
D2
D1
D0

10µF

48
36
47
46
45
44
43
42
41
40
39
38
37

33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

CLOCK

5V

0.1µF

5V
5V

5V

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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LTC1415 12-Bit, 1.25Msps, Single 5V ADC 55mW Power Dissipation, 72dB SINAD
LTC1418 14-Bit, 200ksps, Single 5V ADC 15mW, Serial/Parallel ±10V
LTC1419 Low Power 14-Bit, 800ksps ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
LTC1604 16-Bit, 333ksps, ±5V ADC 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608
LTC1850/LTC1851 10-Bit/12-Bit, 8-Channel, 1.25Msps ADCs Pin-Compatible, Programmable Multiplexer and Sequencer

18523f

LT/TP 0802 2K • PRINTED IN THE USA

 LINEAR TECHNOLOGY CORPORATION 2001

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Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

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www.linear.com