Page 1
LOAD CURRENT (A)
0.01
70
EFFICIENCY (%)
90
95
100
0.1 1 10
1775 F01b
85
80
75
VIN = 10V
f = 150kHz
FCB = INTV
CC
V
OUT
= 5V
V
OUT
= 3.3V
查询LTC1775C供应商
FEATURES
LTC1775
High Power
TM
No R
SENSE
Current Mode
Synchronous Step-Down
Switching Regulator
U
DESCRIPTIO
■
Highest Efficiency Current Mode Controller
■
No Sense Resistor Required
■
300mV Maximum Current Sense Voltage
■
Stable High Current Operation
■
Dual N-Channel MOSFET Synchronous Drive
■
Wide VIN Range: 4V to 36V
■
Wide V
■
±1% 1.19V Reference
■
Programmable Fixed Frequency with Injection Lock
■
Very Low Drop Out Operation: 99% Duty Cycle
■
Forced Continuous Mode Control Pin
■
Optional Programmable Soft Start
■
Pin Selectable Output Voltage
■
Foldback Current Limit
■
Output Overvoltage Protection
■
Logic Controlled Micropower Shutdown: IQ < 30µA
■
Available in 16-Lead Narrow SSOP and SO Packages
Range: 1.19V to V
OUT
IN
U
APPLICATIO S
■
Notebook Computers
■
Automotive Electronics
■
Battery Chargers
■
Distributed Power Systems
The LTC®1775 is a synchronous step-down switching
regulator controller that drives external N-channel power
MOSFETs using few external components. Current mode
control with MOSFET VDS sensing eliminates the need for
a sense resistor and improves efficiency. Largely similar
to the LTC1625, the LTC1775 has twice the maximum
sense voltage for high current applications. The frequency
of a nominal 150kHz internal oscillator can be synchronized to an external clock over a 1.5:1 frequency range.
Burst ModeTM operation at low load currents reduces
switching losses and low dropout operation extends operating time in battery-powered systems. A forced continuous mode control pin can assist secondary winding
regulation by disabling Burst Mode operation when the
main output is lightly loaded.
Fault protection is provided by foldback current limiting
and an output overvoltage comparator. An external capacitor attached to the RUN/SS pin provides soft start
capability for supply sequencing. A wide supply range
allows operation from 4V (4.3V for LTC1775I) to 36V at the
input and 1.19V to VIN at the output.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No R
and Burst Mode are trademarks of Linear Technology Corporation.
SENSE
TYPICAL APPLICATION
LTC1775
SYNC
0.1µF
SS
RUN/SS
V
R
C
10k
I
TH
SGND
V
2.2nF
C
C
C
Figure 1. High Efficiency Step-Down Converter
PROG
OSENSE
V
SW
BOOST
INTV
PGND
IN
TK
TG
D
B
+
CMDSH-3
C
VCC
4.7µF
CC
BG
C
U
B
0.33µF
M1
SUD50N03-10
D1
MBRS340
M2
SUD50N03-10
L1
6µH
Efficiency vs Load Current
V
IN
C
+
22µF
30V
×4
+
1775 F01
5V TO
IN
28V
V
OUT
3.3V
10A
C
OUT
680µF
6.3V
1
Page 2
LTC1775
PACKAGE/ORDER I FOR ATIO
UU
W
WWWU
ABSOLUTE AXI U RATI GS
(Note 1)
Input Supply Voltage (VIN, TK) ................. 36V to –0.3V
Boosted Supply Voltage (BOOST)............. 42V to –0.3V
Boosted Driver Voltage (BOOST – SW) ...... 7V to –0.3V
Switch Voltage (SW) ....................................36V to – 5V
EXTVCC Voltage ...........................................7V to –0.3V
ITH Voltage................................................2.7V to –0.3V
FCB, RUN/SS, SYNC Voltages .....................7V to –0.3V
V
OSENSE
Peak Driver Output Current < 10µs (TG, BG) ............ 2A
INTVCC Output Current ........................................ 50mA
Operating Ambient Temperature Range
Junction Temperature (Note 2)............................. 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
, V
Voltages ........(INTVCC + 0.3V) to –0.3V
PROG
LTC1775C .............................................. 0°C to 70°C
LTC1775I (Note 5).............................. –40°C to 85°C
TOP VIEW
1
EXTV
CC
2
SYNC
3
RUN/SS
4
FCB
5
I
TH
6
SGND
7
V
OSENSE
8
V
PROG
GN PACKAGE
16-LEAD NARROW
PLASTIC SSOP
T
= 125°C, θJA = 130°C/W (GN)
JMAX
= 125°C, θJA = 110°C/W (S)
T
JMAX
Consult factory for Military grade parts.
16
V
IN
15
TK
14
SW
13
TG
12
BOOST
11
INTV
CC
10
BG
9
PGND
S PACKAGE
16-LEAD PLASTIC SO
ORDER PART
NUMBER
LTC1775CGN
LTC1775CS
LTC1775IGN
LTC1775IS
GN PART MARKING
1775
1775I
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
IINV
OSENSE
V
OUT
V
LINEREG
V
LOADREG
V
FCB
I
FCB
V
OVL
I
PROG
I
Q
V
RUN/SS
I
RUN/SS
∆V
SENSE(MAX)
Feedback Current V
Regulated Output Voltage ITH = 1.19V (Note 3)
1.19V (Adjustable) Selected V
3.3V Selected V
5V Selected V
Reference Voltage Line Regulation VIN = 4V to 20V, ITH = 1.19V (Note 3), 0.001 0.01 %/V
Output Voltage Load Regulation ITH = 2V (Note 3) ● – 0.020 – 0.2 %
Forced Continuous Threshold V
Forced Continuous Bias Current V
Output Overvoltage Lockout V
V
Input Current
PROG
3.3V V
OUT
5V V
OUT
Input DC Supply Current
Normal Mode EXTV
Shutdown V
RUN/SS Pin Threshold ● 0.8 1.4 2 V
Soft Start Current Source V
Maximum Current Sense Threshold V
Pin Open, ITH = 1.19V (Note 3) 10 50 nA
PROG
Pin Open ● 1.178 1.190 1.202 V
PROG
= 0V ● 3.220 3.300 3.380 V
PROG
= INTV
PROG
V
PROG
= 0.5V (Note 3) ● 0.035 0.2 %
I
TH
Ramping Negative ● 1.16 1.19 1.22 V
FCB
= 1.19V –1 –2 µA
FCB
PROG
V
PROG
V
PROG
RUN/SS
RUN/SS
OSENSE
CC
Pin Open
Pin Open 1.24 1.28 1.32 V
= 0V –3.5 –7 µA
= 5V 3.5 7 µA
= 5V (Note 4) 500 µA
CC
= 0V, 4V < VIN < 15V 15 30 µA
= 0V –1.2 –2.5 –4 µA
= 1V, V
Pin Open 260 300 340 mV
PROG
● 4.900 5.000 5.100 V
2
Page 3
LTC1775
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
TG Transition Time (Note 6)
TG t
R
TG t
F
BG t
R
BG t
F
Internal VCC Regulator
V
INTVCC
V
LDOINT
V
LDOEXT
V
EXTVCC
Oscillator
f
OSC
fH/f
OSC
V
SYNC
R
SYNC
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: T
is calculated from the ambient temperature TA and power
J
dissipation P
LTC1775CGN/LTC1775IGN: T
LTC1775CS/LTC1775IS: TJ = TA + (PD • 110°C/W)
Note 3: The LTC1775 is tested in a feedback loop that adjusts V
achieve a specified error amplifier output voltage (I
Rise Time C
Fall Time C
= 3300pF 50 150 ns
LOAD
= 3300pF 50 150 ns
LOAD
BG Transition Time (Note 6)
Rise Time C
Fall Time C
Internal VCC Voltage 6V < VIN < 30V, V
INTVCC Load Regulation ICC = 20mA, V
EXTVCC Voltage Drop ICC = 20mA, V
EXTVCC Switchover Voltage ICC = 20mA, V
= 3300pF 50 150 ns
LOAD
= 3300pF 50 150 ns
LOAD
= 4V ● 5.0 5.2 5.4 V
EXTVCC
= 4V –0.2 –1 %
EXTVCC
= 5V 180 300 mV
EXTVCC
Ramping Positive ● 4.5 4.7 V
EXTVCC
Oscillator Freqency SYNC = 0V 135 150 165 kHz
Maximum Synchronized Frequency Ratio 1.5
SYNC Pin Threshold (Figure 4) Ramping Positive 0.9 1.2 V
SYNC Pin Input Resistance 50 kΩ
Note 4: Typical in application circuit with EXTVCC tied to V
I
= 0A and FCB = INTVCC. Dynamic supply current is higher due
OUT
OUT
= 5V,
to the gate charge being delivered at the switching frequency. See
according to the following formula:
D
= TA + (PD • 130°C/W)
J
to
).
TH
OSENSE
Applications Information.
Note 5: Minimum input supply voltage is 4.3V at –40°C for industrial
grade parts.
Note 6: Rise and fall times are measured at 10% to 90% levels.
3
Page 4
LTC1775
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current Efficiency vs Input Voltage
100
90
80
70
EFFICIENCY (%)
60
50
0.001
Load Regulation
0
–0.1
–0.2
(%)
OUT
∆V
–0.3
–0.4
BURST
MODE
0.01
0.1
LOAD CURRENT (A)
CONTINUOUS
MODE
VIN = 10V
= 5V
V
OUT
= V
EXTV
CC
OUT
1.0
1775 • G01
FIGURE 1 CIRCUIT
10
100
95
90
85
EFFICIENCY (%)
80
75
70
0
5
I
LOAD
10 15 20
INPUT VOLTAGE (V)
ITH Pin Voltage vs Load Current
3.0
2.5
2.0
(V)
1.5
ITH
CONTINUOUS
V
MODE
1.0
BURST
0.5
MODE
I
= 5A
LOAD
= 500mA
V
= 5V
OUT
FIGURE 1 CIRCUIT
25 30
1775 • G02
FIGURE 1 CIRCUIT
= 20V
V
IN
= 5V
V
OUT
Efficiency vs Input Voltage
100
95
90
I
= 500mA
85
EFFICIENCY (%)
80
75
70
0
V
IN
LOAD
10 15 20 25 30
5
INPUT VOLTAGE (V)
– V
Dropout Voltage
OUT
vs Load Current
400
FIGURE 1 CIRCUIT
= 5V, 5% DROP
V
OUT
300
(mV)
200
OUT
– V
IN
V
100
I
= 5A
LOAD
V
= 3.3V
OUT
FIGURE 1 CIRCUIT
1775 • G03
–0.5
2
0
LOAD CURRENT (A)
6
8
4
10
1775 • G04
Input and Shutdown Current
vs Input Voltage INTV
1775 • G07
60
50
SHUTDOWN CURRENT (µA)
40
30
20
10
0
1200
1000
800
600
400
INPUT CURRENT (µA)
200
0
0
EXTVCC OPEN
510
INPUT VOLTAGE (V)
SHUTDOWN
EXTVCC = 5V
20 30 35
15 25
(%)
CC
∆INTV
–0.5
–1.0
0
1.0
0.5
0
0
24
LOAD CURRENT (A)
Load Regulation
CC
VIN = 15V
10
0
INTVCC LOAD CURRENT (mA)
81214
610
1775 • G05
20
30 40
1775 • G08
0
0
4
2
CURRENT LOAD (A)
68
1775 • G06
10
EXTVCC Switch Drop
vs INTVCC Load Current
500
VIN = 15V
= 5V
EXTV
CC
400
(mV)
300
CC
– INTV
200
CC
EXTV
100
50
0
10
0
INTV
CC
30
20
LOAD CURRENT (mA)
40
50
1775 • G09
4
Page 5
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC1775
Maximum Current Sense Voltage
vs Duty Cycle
350
300
250
200
150
100
50
MAXIMUM CURRENT SENSE VOLTAGE (mV)
0
0.2 0.4 0.8 1.0
0
0.6
DUTY CYCLE
FCB Pin Current vs Temperature
0
–0.5
–1.0
FCB CURRENT (µA)
–1.5
1775 • G10
Maximum Current Sense Voltage
vs Temperature
320
310
300
290
MAXIMUM CURRENT SENSE VOLTAGE (mV)
280
–40
–15 10
TEMPERATURE (°C)
60 110 135
35 85
RUN/SS Pin Current vs
Temperature
0
–1
–2
–3
RUN/SS CURRENT (µA)
–4
1775 • G11
Oscillator Frequency
vs Temperature
300
250
200
150
100
FREQUENCY (kHz)
50
0
–40
–15 10
Soft Start
RUN/SS
5V/DIV
V
OUT
5V/DIV
I
L
5A/DIV
SYNC = 1.5V
SYNC = 0V
60 110 135
35 85
TEMPERATURE (°C)
1775 • G12
–2.0
V
OUT
100mV
/DIV
5A/DIV
–40
I
L
–15 10
TEMPERATURE (°C)
V
= 20V
IN
= 5V
V
OUT
= 2A TO 8A
I
LOAD
FIGURE 1 CIRCUIT
60 110 135
35 85
100µs/DIV
1775 • G13
1530 G18
–5
–40
–15 10
Transient Response
(Burst Mode Operation)Transient Response
V
OUT
100mV
/DIV
I
L
5A/DIV
V
= 20V
IN
= 5V
V
OUT
= 100mA TO 2A
I
LOAD
FIGURE 1 CIRCUIT
60 110 135
35 85
TEMPERATURE (°C)
200µs/DIV
1775 • G14
1530 G17
= 20V
V
IN
= 5V
V
OUT
= 0.5Ω
R
LOAD
FIGURE 1 CIRCUIT
Burst Mode Operation
V
OUT
50mV
/DIV
I
TH
100mV
/DIV
I
L
2A/DIV
= 20V
V
IN
= 5V
V
OUT
= 100mA
I
LOAD
FIGURE 1 CIRCUIT
20ms/DIV
1530 G16
20µs/DIV
1530 G15
5
Page 6
LTC1775
U
UU
PI FU CTIO S
EXTVCC (Pin 1): INTVCC Switch Input. When the EXTV
voltage is above 4.7V, the switch closes and supplies
INTVCC power from EXTVCC. Do not exceed 7V at this pin.
SYNC (Pin 2): Synchronization Input for Internal Oscillator. The oscillator will nominally run at 150kHz when open,
225kHz when tied above 1.2V, and will lock over a 1.5:1
clock frequency range.
RUN/SS (Pin 3): Run Control and Soft Start Input. A
capacitor to ground at this pin sets the ramp time to full
current output (approximately 1s/µF). Forcing this pin
below 1.4V shuts down the device.
FCB (Pin 4): Forced Continuous Input. Tie this pin to
ground to force synchronous operation at low load
currents, to a resistive divider from the secondary output
when using a secondary winding, or to INTVCC to enable
Burst Mode operation at low load currents.
ITH (Pin 5): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage, forcing inductor current to be roughly proportional to V
2.4V.
SGND (Pin 6): Signal Ground. Connect to the (–) terminal
of C
OUT
V
OSENSE
from the remotely sensed output voltage or from an
external resistive divider across the output.
V
(Pin 8): Output Voltage Programming. When
PROG
V
OSENSE
a 3.3V output and V
. Nominal voltage range for this pin is 0V to
ITH
.
(Pin 7): Output Voltage Sense. Feedback input
is connected to the output, V
> 3.5V selects a 5V output.
PROG
< 0.8V selects
PROG
CC
Leaving V
an external resistive divider between the output and
V
OSENSE
PGND (Pin 9): Driver Power Ground. Connects to the
source of the bottom N-channel MOSFET, the (–) terminal
of C
BG (Pin 10): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.
INTVCC (Pin 11): Internal 5.2V Regulator Output. The
driver and control circuits are powered from this voltage.
Decouple this pin to power ground with a minimum of
4.7µF tantalum or other low ESR capacitor.
BOOST (Pin 12): Topside Floating Driver Supply. The (+)
terminal of the bootstrap capacitor connects here. This pin
swings from a Schottky diode drop below INTVCC to VIN +
INTVCC.
TG (Pin 13): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superimposed on the switch node voltage.
SW (Pin 14): Switch Node. The (–) terminal of the bootstrap capacitor connects here. This pin swings from a
diode drop below ground up to VIN.
TK (Pin 15): Top MOSFET Kelvin Sense. MOSFET V
sensing requires this pin to be routed to the drain of the top
MOSFET separately from VIN.
VIN (Pin 16): Main Supply Input. Decouple this pin to
ground with an RC filter (1Ω, 0.1µF) for applications
above 3A.
and the (–) terminal of CIN.
VCC
open allows the output voltage to be set by
PROG
.
DS
6
Page 7
LTC1775
U
U
W
FU CTIO AL DIAGRA
I
TH
5
R
C
C
C1
0.6V
RUN/SS
3
C
SS
SGND
6
INTV
CC
–
CL
+
= 1m
V
FB
1.19V
V
IN
3µA
6V
1.28V
g
m
–
EA
+
–
+
INTV
+
I
THB
–
Ω
+
–
0.6V
–
+
OV
CC
+
0.7V
I
1.19V
TK
SYNC
2
+
TA
×5.5
15
–
V
IN
+
C
IN
–
0.95V
–
1
0.5V
+
–
OSC
S
Q
TOP
R
SLEEP
B
SHUTDOWN
OVERVOLTAGE
FCNT
REV
SWITCH
LOGIC/
DROPOUT
COUNTER
+
F
–
INTV
CC
1µA
BA
×5.5
I
1.19V
REF
5.2V
LDO REG
+
+
2
–
BOOST
12
C
CC
4.7V
B
M1
D
B
+
C
VCC
M2
+
TG
13
SW
14
INTV
11
BG
10
PGND
V
9
IN
16
–
L1
V
8
PROG
V
7
OSENSE
FCB
EXTV
14
CC
V
OUT
+
C
OUT
1775 BD
7
Page 8
LTC1775
OPERATIO
U
Main Control Loop
The LTC1775 is a constant frequency, current mode
controller for DC/DC step-down converters. In normal
operation, the top MOSFET is turned on when the RS latch
is set by the on-chip oscillator and is turned off when the
current comparator I1 resets the latch. While the top
MOSFET is turned off, the bottom MOSFET is turned on
until either the inductor current reverses, as determined
by the current reversal comparator I2, or the next cycle
begins. Inductor current is measured by sensing the V
potential across the conducting MOSFET. The output of
the appropriate sense amplifier (TA or BA) is selected by
the switch logic and applied to the current comparator.
The voltage on the ITH pin sets the comparator threshold
corresponding to peak inductor current. The error amplifier EA adjusts this voltage by comparing the feedback
signal VFB from the output voltage with the internal 1.19V
reference. The V
voltage is taken directly from the V
from an on-chip resistive divider. When the load current
increases, it causes a drop in the feedback voltage relative
to the reference. The ITH voltage then rises until the
average inductor current again matches the load current.
The internal oscillator can be synchronized to an external
clock applied to the SYNC pin and can lock to a frequency
between 100% and 150% of its nominal 150kHz rate.
When the SYNC pin is left open, it is pulled low internally
and the oscillator runs at its normal rate. If this pin is taken
above 1.2V, the oscillator will run at its maximum 225kHz
rate.
Pulling the RUN/SS pin low forces the controller into its
shutdown state and turns off both MOSFETs. Releasing
the RUN/SS pin allows an internal 3µA current source to
charge up an external soft start capacitor CSS. When this
voltage reaches 1.4V, the controller begins switching, but
with the ITH voltage clamped at approximately 0.8V. As
CSS continues to charge, the clamp is raised until full range
operation is restored.
The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is normally recharged
from INTVCC through a diode DB when the top MOSFET is
turned off. As VIN decreases towards V
pin selects whether the feedback
PROG
OSENSE
pin or is derived
, the converter
OUT
DS
will attempt to turn on the top MOSFET continuously
(‘’dropout’’). A dropout counter detects this condition and
forces the top MOSFET to turn off for about 500ns every
tenth cycle to recharge the bootstrap capacitor.
An overvoltage comparator OV guards against transient
overshoots and other conditions that may overvoltage the
output. In this case, the top MOSFET is turned off and the
bottom MOSFET is turned on until the overvoltage condition is cleared.
Foldback current limiting for an output shorted to ground
is provided by a transconductance amplifer CL. As V
drops below 0.6V, the buffered ITH input to the current
comparator is gradually pulled down to a 0.95V clamp.
This reduces peak inductor current to about one fifth of its
maximum value.
Low Current Operation
The LTC1775 is capable of Burst Mode operation at low
load currents. If the error amplifier drives the ITH voltage
below 0.95V, the buffered ITH input to the current comparator will remain clamped at 0.95V. The inductor current
peak is then held at approximately 60mV/R
ITH then drops below 0.5V, the Burst Mode comparator B
will turn off both MOSFETs. The load current will be
supplied solely by the output capacitor until ITH rises
above the 50mV hysteresis of the comparator and switching is resumed. Burst Mode operation is disabled by
comparator F when the FCB pin is brought below 1.19V.
This forces continuous operation and can assist secondary winding regulation.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
of the internal circuitry of the LTC1775 is derived from the
INTVCC pin. When the EXTVCC pin is left open, an internal
5.2V low dropout regulator supplies the INTVCC power
from VIN. If EXTVCC is raised above 4.7V, the internal
regulator is turned off and an internal switch connects
EXTVCC to INTVCC. This allows a high efficiency source,
such as the primary or a secondary output of the converter
itself, to provide the INTVCC power.
DS(ON)(TOP)
FB
. If
8
Page 9
R
DS(ON)
(Ω)
0
MAXIMUM OUTPUT CURRENT (A)
15
20
25
0.08
1775 F03
10
5
0
0.02
0.04
0.06
0.10
IRL3803
SUD50N03-10
FDS8936A
Si9936
WUUU
APPLICATIO S I FOR ATIO
LTC1775
The basic LTC1775 application circuit is shown in Figure 1.
External component selection is primarily determined by
the maximum load current and begins with the selection of
the sense resistance for the desired current level. Since the
LTC1775 senses current using the on-resistance of the
power MOSFET, the maximum application current primarily determines the choice of MOSFET. The operating
frequency and the inductor are chosen based largely on
the desired amount of ripple current. Finally, CIN is selected for its ability to handle the RMS current into the
converter and C
is chosen with low enough ESR to
OUT
meet the output voltage ripple specification.
Power MOSFET Selection
The LTC1775 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V
threshold voltage V
transfer capacitance C
, on-resistance R
GS(TH)
and maximum current I
RSS
DS(ON)
(BR)DSS
, reverse
D(MAX)
,
.
The gate drive voltage is set by the 5.2V INTVCC supply.
Consequently, logic level threshold MOSFETs must be
used in LTC1775 applications. If low input voltage operation is expected (V
< 5V), then sub-logic level threshold
IN
MOSFETs should be used. Pay close attention to the
V
(BR)DSS
specification for the MOSFETs as well; many of
the logic level MOSFETs are limited to 30V or less.
The ρT is a normalized term accounting for the significant
variation in R
with temperature, typically about
DS(ON)
0.4%/°C as shown in Figure 2. Junction to ambient temperature TJA is around 20°C in most applications. For a
maximum ambient temperature of 70°C, using ρ
90°C
≅ 1.3
in the above equation is a reasonable choice. This equation
is plotted in Figure 3 to illustrate the dependence of
maximum output current on R
. Some popular
DS(ON)
MOSFETs are shown as data points.
2.0
1.5
1.0
0.5
NORMALIZED ON RESISTANCE
T
ρ
0
–50
0
JUNCTION TEMPERATURE (°C)
Figure 2. R
50
vs Temperature
DS(ON)
100
150
1775 F02
The MOSFET on-resistance is chosen based on the
required load current. The maximum average output current I
O(MAX)
the peak-to-peak ripple current ∆IL. The peak inductor
current is inherently limited in a current mode controller
by the current threshold ITH range. The corresponding
maximum VDS sense voltage is about 300mV under normal conditions. The LTC1775 will not allow peak inductor
current to exceed 300mV/R
equation is a good guide for determining the required
R
DS(ON)(MAX)
lowing some margin for ripple current, current limit and
variations in the LTC1775 and external component values:
R
DS ON MAX
()( )
is equal to the peak inductor current less half
DS(ON)(TOP)
. The following
at 25°C (manufacturer’s specification), al-
mV
240
≅
I
()
O MAX T
()
()
ρ
Figure 3. Maximum Output Current vs R
at VGS = 4.5V
DS(ON)
The 300mV maximum sense voltage of the LTC1775
allows a large current to be obtained from power MOSFET
switches. It also causes a significant amount of power
dissipation in those switches and careful attention must be
9
Page 10
LTC1775
0
1775 F04
7V
1µs < t
ON
< 4µs
5µs < t < 6µs
1.2V
∆I
V
fL
V
V
L
OUT OUT
IN
=
()( )
–1
WUUU
APPLICATIO S I FOR ATIO
paid to the resulting thermal issues. Under DC conditions,
the maximum power that can be dissipated by a MOSFET
switch limits the current through it:
I
DS MAX
()
R
DS ON
P
()
==
TT
J MAX A
R
θρ
JA DS ON TJ MAX
For example, the SUD50N03-10 with T
TA =70°, θJA = 30° C/W, R
DS(ON)
= 0.019Ω, ρ
–
()
() ( )
= 175°C,
J(MAX)
TJ(MAX)
= 1.8
can operate with a maximum DC current of 10A. In a
switching application, the actual power dissipation is
increased by the transition losses and is reduced by the
switch duty cycle. When the LTC1775 is operating in
continuous mode, the duty cycles for the MOSFETs are:
V
TopDuty Cycle
BottomDuty Cycle
OUT
=
V
IN
=
VV
–
IN OUT
V
IN
Operating Frequency and Synchronization
The choice of operating frequency and inductor value is a
trade-off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses, both gate charge loss and
transition loss. However, lower frequency operation
requires more inductance for a given amount of ripple
current.
The internal oscillator runs at a nominal 150kHz frequency
when the SYNC pin is left open or connected to ground.
Pulling the SYNC pin above 1.2V will increase the frequency by 50%. The oscillator will injection lock to a clock
signal applied to the SYNC pin with a frequency between
165kHz and 200kHz. The clock high level must exceed
1.2V for at least 1µs and no longer than 4µs as shown in
Figure 4. The top MOSFET turn-on will synchronize with
the rising edge of the clock.
The MOSFET power dissipations at maximum output
current are:
P
=
TOP
+
P
=
BOT
Both MOSFETs have I2R losses and the P
V
OUT
IR
()()()
V
IN
2
kV I C f
()( )( )( )()
IN O MAX RSS
–
VV
IN OUT
V
IN
2
() () ()
O MAX T TOP DS ON
ρ
()
()()()
IR
2
() () ()
O MAX T BOT DS ON
ρ
equation
TOP
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7 can be
used to estimate the amount of transition loss. The bottom
MOSFET losses are greatest at high input voltage or during
a short circuit when the duty cycle is nearly 100%. The
temperature rise of the MOSFETs depends on the effective
thermal resistance θJA of the heat sink used in the application. Check the temperature of the MOSFET when testing
applications and use appropriate heat sinking such as
board power planes to spread the heat.
Figure 4. SYNC Clock Waveform
Inductor Value Selection
Given the desired input and output voltages, the inductor
value and operating frequency directly determine the
ripple current:
Lower ripple current reduces losses in the inductor, ESR
losses in the output capacitors and output voltage ripple.
Thus, highest efficiency operation is obtained at low
frequency with small ripple current. To achieve this, however, requires a large inductor.
10
Page 11
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APPLICATIO S I FOR ATIO
LTC1775
A reasonable starting point is to choose a ripple current
that is about 40% of I
. Note that the largest ripple
O(MAX)
current occurs at the highest VIN. To guarantee that ripple
current does not exceed a specified maximum, the inductor should be chosen according to:
L
≥
fI
()( )
V
OUT
∆
() ()
L MAX
V
1
–
V
IN MAX
OUT
Burst Mode Operation Considerations
The choice of R
and inductor value also determines
DS(ON)
the load current at which the LTC1775 enters Burst Mode
operation. When bursting, the controller clamps the peak
inductor current to approximately:
mV
I
BURST PEAK
()
=
60
R
DS ON
()
The corresponding average current depends on the amount
of ripple current. Lower inductor values (higher ∆IL) will
reduce the load current at which Burst Mode operation
begins.
The output voltage ripple can increase during Burst Mode
operation if ∆IL is substantially less than I
BURST
. This will
primarily occur when the duty cycle is very close to unity
(VIN is close to V
) or if very large value inductors are
OUT
chosen. This is generally only a concern in applications
with V
≥ 5V. At high duty cycles, a skipped cycle
OUT
causes the inductor current to quickly descend to zero.
However, it takes multiple cycles to ramp the current back
up to I
BURST(PEAK)
. During this interval, the output capacitor must supply the load current and enough charge may
be lost to cause significant droop in the output voltage. It
is a good idea to keep ∆IL comparable to I
BURST(PEAK)
.
Otherwise, one might need to increase the output capacitance in order to reduce the voltage ripple or else disable
Burst Mode operation by forcing continuous operation
with the FCB pin.
Fault Conditions: Current Limit and Output Shorts
The LTC1775 current comparator can accommodate a
maximum sense voltage of 300mV. This voltage and the
sense resistance determine the maximum allowed peak
inductor current. The corresponding output current limit
is:
mV
I
LIMIT
300 1
=
R
()
DS ON T
()
()
–ρ∆
2
I
L
The current limit value should be checked to ensure that
I
LIMIT(MIN)
> I
. The minimum value of current limit
O(MAX)
generally occurs with the largest VIN at the highest ambient temperature, conditions which cause the highest power
dissipation in the top MOSFET. Note that it is important to
check for self-consistency between the assumed junction
temperature of the top MOSFET and the resulting value of
I
which heats the junction.
LIMIT
Caution should be used when setting the current limit
based upon R
of the MOSFETs. The maximum
DS(ON)
current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and
maximum values for R
, but not a minimum. A
DS(ON)
reasonable, but perhaps overly conservative, assumption
is that the minimum R
the typical value as the maximum R
lies the same amount below
DS(ON)
lies above it.
DS(ON)
Consult the MOSFET manufacturer for further guidelines.
The LTC1775 includes current foldback to help further
limit load current when the output is shorted to ground. If
the output falls by more than half, then the maximum
sense voltage is progressively lowered from 300mV to
about 80mV. Under short-circuit conditions with very low
duty cycle, the LTC1775 will begin skipping cycles in order
to limit the short-circuit current. In this situation the
bottom MOSFET R
will control the inductor current
DS(ON)
valley rather than the top MOSFET controlling the inductor
current peak. The short-circuit ripple current is determined by the minimum on-time t
ON(MIN)
of the LTC1775
(approximately 0.5µs), the input voltage, and inductor
value:
∆I
L(SC)
= t
ON(MIN) VIN
/L.
The resulting short-circuit current is:
mV
I
SC
=
80 1
R
()
()( )
DS ON BOT T
ρ
()
∆
I
+
()
LSC
2
11
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LTC1775
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APPLICATIO S I FOR ATIO
Normally, the top and bottom MOSFETs will be of the same
type. A bottom MOSFET with lower R
may be chosen if the resulting increase in short-circuit
current is tolerable. However, the bottom MOSFET should
never be chosen to have a higher nominal R
top MOSFET.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
the inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses rapidly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
DS(ON)
DS(ON)
than the top
than the
regulators. The diode may be omitted if the efficiency loss
can be tolerated.
Parasitic Lead Inductance Effects
Because the LTC1775 is designed to operate with relatively large currents through single (or multiple) MOSFET
switches, the lead inductance of these power switches can
become a significant concern. The table below shows
typical values of lead inductance for some common packages:
MOSFET Package Lead Inductance
TO-220 4nH to 12nH
DDPAK 4nH
DPAK 1.5nH
SO-8 1nH
Of particular concern are switches in TO-220 packages
which can have a series inductance of between 4nH and
12nH depending upon the depth of insertion into the
circuit board. When the main (top) switch is turned on, the
lead inductance LP forms a voltage divider with the power
inductor L1. The voltage V
the voltage from the switch on-resistance and increases
the current sense voltage.
VLP = (VIN – V
OUT
)LP/L1
across this parasitic adds to
LP
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire.
Because they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
which do not increase the height significantly.
Schottky Diode Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on and storing charge during the
dead time, which could cost as much as 1% in efficiency.
A 1A Schottky diode is generally a good size for 3A to 5A
Kool Mµ is a registered trademark of Magnetics, Inc.
12
The result is lower value of current limit than would have
been expected otherwise. For example, a 10nH lead inductance with a 5µH power inductor has 50mV across it when
VIN = 30V and V
will be reached when the switch voltage due to onresistance is only 250mV, a 17% reduction. This effect is
most noticeable at higher input voltages.
Lead inductance also reduces the benefit of the Schottky
diode D1 by delaying commutation of the inductor current
from the diode over to the synchronous (bottom) switch.
With the diode forward biased when the synchronous
switch turns on, there is only about 500mV applied across
the lead and trace inductance between the switch and the
diode. It takes about 400ns to commutate a 20A current in
this case. This delay reduces efficiency and can also
increase the foldback current limit of the LTC1775. The
= 5V. Thus, the 300mV current limit
OUT
Page 13
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APPLICATIO S I FOR ATIO
LTC1775
Schottky diode must be placed next to the synchronous
switch to minimize this effect. One also might consider
using a power switch with an integrated Schottky diode, or
omitting the diode altogether in high current applications.
CIN and C
Selection
OUT
In continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle V
OUT/VIN
. To
prevent large input voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS current is given by:
/
V
II
≅−
RMS O MAX
()
OUT
V
V
V
ININOUT
This formula has a maximum at VIN = 2V
= I
/2. This simple worst-case condition is com-
O(MAX)
12
1
, where I
OUT
RMS
monly used for design because even significant deviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life. This makes it advisable to further derate
the capacitor or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
placed in parallel to meet size or height requirements in the
design.
The selection of C
is primarily determined by the ESR
OUT
required to minimize voltage ripple. The output ripple
∆V
is approximately bounded by:
OUT
parallel with OS-CON capacitors is recommended to reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, special polymer and aluminum electrolytic capacitors are
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Several excellent surge-tested choices
are the AVX TPS and TPSV or the KEMET T510 series.
Aluminum electrolytic capacitors have significantly higher
ESR, but can be used in cost-driven applications providing
that consideration is given to ripple current ratings and
long term reliability. Other capacitor types include Nichicon
PL, NEC Neocap, Panasonic SP and Sprague 595D series.
INTVCC Regulator
An internal P-channel low dropout regulator produces the
5.2V supply which powers the drivers and internal circuitry within the LTC1775. The INTVCC pin can supply a
maximum RMS current of 50mA and must be bypassed to
ground with a minimum of 4.7µF tantalum or low ESR
electrolytic capacitance. Good bypassing is necessary to
supply the high transient currents required by the MOSFET
gate drivers.
∆∆V I ESR
OUT L
≤+
1
fC
8()()( )
OUT
Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied the capacitance is adequate for
filtering and has the required RMS current rating.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance throughhole capacitors. The OS-CON (organic semiconductor
dielectric) capacitor available from Sanyo has the lowest
product of ESR and size of any aluminum electrolytic at a
somewhat higher price. An additional ceramic capacitor in
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the LTC1775
to exceed its maximum junction temperature rating. Most
of the supply current drives the MOSFET gates unless an
external EXTVCC source is used. The junction temperature
can be estimated from the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC1775CGN
is limited to less than 14mA from a 30V supply:
TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked when
operating in continuous mode at high VIN. Relief can be
provided by using the EXTVCC pin to provide the gate drive
current.
13
Page 14
LTC1775
V
IN
TK
LTC1775
EXTV
CC
V
PUMP
≈ 2(V
OUT
– VD) < 7V
TG
SW
1775 F05b
L1
BG
PGND
+
C
OUT
V
OUT
BAT85
BAT85
BAT85
VN2222LL
V
IN
+
C
IN
+
1µF
0.22µF
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APPLICATIO S I FOR ATIO
EXTVCC Connection
The LTC1775 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
Whenever the EXTVCC pin is above 4.7V the internal 5.2V
regulator shuts off, the switch closes and INTVCC power is
supplied via EXTVCC until EXTVCC drops below 4.5V. This
allows the MOSFET gate drive and control power to be
derived from the output or other external source during
normal operation. When the output is out of regulation
(start-up, short circuit) power is supplied from the internal
regulator. Do not apply greater than 7V to the EXTVCC pin
and ensure that EXTVCC ≤ VIN.
Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current supplying
the driver and control currents will be scaled by a factor of
Duty Cycle/Efficiency. For 5V regulators this simply means
connecting the EXTVCC pin directly to V
3.3V and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output.
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC left open (or grounded). This will cause INTV
to be powered from the internal 5.2V regulator resulting
in a low current efficiency penalty of up to 10% at high
input voltages.
2. EXTVCC connected directly to V
OUT
connection for a 5V regulator and provides the highest
efficiency.
. However, for
OUT
CC
. This is the normal
Figure 5b: Capacitive Charge Pump for EXTV
CC
3. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage which has been boosted to
greater than 4.7V. This can be done with either an
inductive boost winding as shown in Figure 5a or a
capacitive charge pump as shown in Figure 5b.
4. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 7V range (EXTVCC < VIN),
it may be used to power EXTVCC.
Figure 6 shows how one can easily generate a suitable
EXTVCC voltage from VIN. This circuit still derives the gate
drive current from VIN, but it removes the power dissipation from the LTC1775 internal regulator and increases the
gate drive voltage.
V
IN
V
IN
+
C
V
IN
TK
OPTIONAL
EXTV
CONNECTION
5V < V
14
CC
< 7V
SEC
Figure 5a: Secondary Output Loop and EXTVCC Connection
EXTV
R4
FCB
R3
SGND
LTC1775
CC
TG
SW
BG
PGND
IN
1N4148
•
•
T1
+
1:N
V
SEC
+
C
SEC
1µF
V
OUT
C
OUT
Note that R
Figure 6. EXTVCC Power Supplied from V
DS(ON)
R1
Q1
D1
6.8V
EXTV
CC
1775 F06
IN
also varies with the gate drive level. If
gate drives other than the 5.2V INTVCC are used, this must
1775 F05a
be accounted for when selecting the MOSFET R
DS(ON)
.
Particular care should be taken with applications where
EXTVCC is connected to the output. When the output
Page 15
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APPLICATIO S I FOR ATIO
LTC1775
voltage is between 4.7V and 5.2V, INTVCC will be connected to the output and the gate drive is reduced. The
resulting increase in R
limit. Even applications with V
will also lower the current
DS(ON)
> 5.2V will traverse this
OUT
region during start-up and must take into account the
reduced current limit.
Topside MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor (CB in the functional diagram) connected to the BOOST pin supplies the gate drive
voltage for the topside MOSFET. This capacitor is charged
through diode DB from INTVCC when the SW node is low.
Note that the voltage across CB is about a diode drop below
INTVCC. When the top MOSFET turns on, the switch node
voltage rises to VIN and the BOOST pin rises to approximately VIN + INTVCC. During dropout operation, CB supplies the top driver for as long as ten cycles between refreshes. Thus, the boost capacitance needs to store about
100 times the gate charge required by the top MOSFET. In
many applications 0.1µF to 0.47µF is adequate.
When adjusting the gate drive level , the final arbiter is the
total input current for the regulator. If you make a change
and the input current decreases, then you improved the
efficiency. If there is no change in input current, then there
is no change in efficiency.
reduce the signal swing at the gate by a diode drop. Thus,
the LTC1775 requires an increased EXTVCC voltage of
about 6V (such as provided by the Figure 6 circuit) when
using this driver.
Output Voltage Programming
The LTC1775 has a pin selectable output voltage determined by the V
V
INTV
Open Adjustable
pin as follows:
PROG
PROG
0V 3.3V
CC
V
OUT
5V
Remote sensing of the output voltage is provided by the
V
OSENSE
internal resistive divider is used and the V
pin. For fixed 3.3V and 5V output applications an
OSENSE
pin is
connected directly to the output voltage as shown in
Figure 8a. When using an external resistive divider, the
V
pin is left open and the V
PROG
OSENSE
pin is connected to
feedback resistors as shown in Figure 8b. The output
voltage is set by the divider as:
R
2
VV
=+
OUT
119 1
.
R
1
External Gate Drive Buffer
The LTC1775 drivers are adequate for driving up to about
30nC into MOSFET switches. When using large single, or
multiple, MOSFET switches, external buffers may be required to provide additional gate drive capability. Special
purpose gate driver circuits such as the LTC1693 are ideal
in such cases. Alternately, the external buffer circuit shown
in Figure 7 can be used. Note that the bipolar devices
BOOST
Q1
FMMT619
TG
Q2
FMMT720
SW
GATE
OF M1
BG
Figure 7. Optional External Gate Driver
INTV
PGND
CC
Q3
FMMT619
Q4
FMMT720
GATE
OF M2
1775 F07
CONNECT FOR
= 5V
V
OUT
CONNECT FOR
= 3.3V
V
OUT
V
OUT
+
C
OUT
V
PROG
V
OSENSE
SGND
LTC1775
INTV
Figure 8a. Fixed 3.3V or 5V V
V
OUT
OPEN
+
R2
C
OUT
R1
Figure 8b. Adjustable V
V
PROG
V
OSENSE
SGND
LTC1775
OUT
CC
1775 F08a
OUT
1775 F08b
15
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LTC1775
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APPLICATIO S I FOR ATIO
Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides a soft
start function and a means to shut down the LTC1775. Soft
start reduces surge currents from VIN by gradually increasing the controller’s current limit I
TH(MAX)
. This pin
can also be used for power supply sequencing.
Pulling the RUN/SS pin below 1.4V puts the LTC1775 into
a low quiescent current shutdown (IQ < 30µA). This pin can
be driven directly from logic as shown in Figure 9. Releasing the RUN/SS pin allows an internal 3µA current source
to charge up the soft-start capacitor CSS. If RUN/SS has
been pulled all the way to ground there is a delay before
starting of approximately:
14
t
DELAY SS SS
=
CsFC
3
A
µ
V
05../
=µ
()
When the voltage on RUN/SS reaches 1.4V the LTC1775
begins operating with a clamp on ITH at 0.8V. As the
voltage on RUN/SS increases to approximately 3.1V, the
clamp on ITH is raised until its full 2.4V range is restored.
This takes an additional 0.5s/µF. During this time the load
current will be folded back to approximately 80mV/R
DS(ON)
until the output reaches half of its final value.
Diode D1 in Figure 9 reduces the start delay while allowing
CSS to charge up slowly for the soft start function. This
diode and CSS can be deleted if soft start is not needed. The
RUN/SS pin has an internal 6V zener clamp (See Functional Diagram).
3.3V
OR 5V
RUN/SS
D1
C
SS
Figure 9. RUN/SS Pin Interfacing
RUN/SS
C
SS
1775 F09
In addition to providing a logic input to force continuous
operation, the FCB pin provides a means to regulate a
flyback winding output. It can force continuous synchronous operation when needed by the flyback winding,
regardless of the main output load.
The secondary output voltage V
is normally set as
SEC
shown in Figure 5a by the turns ratio N of the transformer:
V
≅ (N + 1)V
SEC
OUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light main load current, then
V
will droop. An external resistor divider from V
SEC
the FCB pin sets a minimum voltage V
R
4
VV
SEC MIN()
If V
drops below this level, the FCB voltage forces
SEC
.≅+
119 1
R
3
continuous operation until V
SEC(MIN)
is again above its
SEC
:
SEC
to
minimum.
Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest amount of time
that the LTC1775 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required to turn on the top
MOSFET. Low duty cycle applications may approach this
minimum on-time limit and care should be taken to ensure
that:
V
OUT
t
ON MIN
<
()
()()
Vf
IN
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1775 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
FCB Pin Operation
When the FCB pin drops below its 1.19V threshold,
continuous synchronous operation is forced. In this case,
the top and bottom MOSFETs continue to be driven
regardless of the load on the main output. Burst Mode
operation is disabled and current reversal under light
loads is allowed in the inductor.
16
The minimum on-time for the LTC1775 is generally about
0.5µs. However, as the peak sense voltage (I
R
) decreases, the minimum on-time gradually
DS(ON)
L(PEAK) •
increases up to about 0.7µs. This is of particular concern
in forced continuous applications with low ripple current
at light loads. If the duty cycle drops below the minimum
on-time limit in this situation, a significant amount of
Page 17
WUUU
APPLICATIO S I FOR ATIO
LTC1775
cycle skipping can occur with correspondingly larger
current and voltage ripple.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power (×100%). Percent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power. It is often useful to analyze individual
losses to determine what is limiting the efficiency and
which change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1775 circuits:
1. INTVCC current. This is the sum of the MOSFET driver
and control currents. The driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched on and then off,
a packet of gate charge Qg moves from INTVCC to
ground. The resulting current out of INTVCC is typically
much larger than the control circuit current. In continuous mode, I
GATECHG
= f(Q
g(TOP)
+ Q
g(BOT)
).
By powering EXTVCC from an output-derived source,
the additional VIN current resulting from the driver and
control currents will be scaled by a factor of Duty Cycle/
Efficiency. For example, in a 20V to 5V application at
400mA load, 10mA of INTVCC current results in approximately 3mA of VIN current. This reduces the loss
from 10% (if the driver was powered directly from VIN)
to about 3%.
2. DC I2R Losses. Since there is no separate sense resistor, DC I2R losses arise only from the resistances of the
MOSFETs and inductor. In continuous mode the average output current flows through L, but is “chopped”
between the top MOSFET and the bottom MOSFET. If
the two MOSFETs have approximately the same R
DS(ON)
,
then the resistance of one MOSFET can simply be
summed with the resistance of L to obtain the DC I2R
loss. For example, if each R
DS(ON)
= 0.05Ω and RL =
0.15Ω, then the total resistance is 0.2Ω. This results in
losses ranging from 2% to 8% as the output current
increases from 0.5A to 2A for a 5V output. I2R losses
cause the efficiency to drop at high output currents.
3. Transition losses apply only to the topside MOSFET,
and only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from:
Transition Loss = (1.7)(V
IN
2
)(I
O(MAX)
)(C
RSS
)(f)
4. LTC1775 VIN supply current. The VIN current is the DC
supply current to the controller excluding MOSFET gate
drive current. Total supply current is typically about
850µA. If EXTVCC is connected to 5V, the LTC1775 will
draw only 330µA from VIN and the remaining 520µA will
come from EXTVCC. VIN current results in a small
(<1%) loss which increases with VIN.
Other losses including CIN and C
ESR dissipative
OUT
losses, Schottky conduction losses during dead time and
inductor core losses, generally account for less than 2%
total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to (∆I
resistance of C
)(ESR), where ESR is the effective series
LOAD
OUT
immediately shifts by an amount
OUT
, and C
begins to charge or dis-
OUT
charge. The regulator loop acts on the resulting feedback
error signal to return V
this recovery time V
ringing which would indicate a stability problem. The I
to its steady-state value. During
OUT
can be monitored for overshoot or
OUT
TH
pin external components shown in Figure 1 will provide
adequate compensation for most applications.
A second, more severe transient is caused by connecting
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
, causing a rapid drop in V
OUT
. No regulator can
OUT
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive in order
to limit the inrush current to the load.
17
Page 18
LTC1775
WUUU
APPLICATIO S I FOR ATIO
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load dump, reverse and double
battery.
Load dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 10 is the most straightforward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse battery,
while the transient suppressor clamps the input voltage
during load dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC1775 has a maximum input
voltage of 36V, most applications will be limited to 30V by
the MOSFET V
(BR)DSS
.
Design Example
As a design example, take a supply with the following
specifications: VIN = 6V to 22V (15V nominal), V
I
O(MAX)
= 10A. The required R
can immediately be
DS(ON)
OUT
= 5V,
estimated:
mV
R
DS ON()
240
A
()(.)
10 1 3
.==Ω
0 018
A 0.019Ω Siliconix SUD50N03-10 MOSFET (θJA =
30°C/W) is close to this value.
For 40% ripple current at maximum VIN the inductor
should be:
V
L
150 0 4 10
( )( . )( )
5
kHz A
V
5
22
=µ
V
1
–.
64
H≥
Choosing a Magnetics 55380-A2 core with 8 turns of 15
gauge wire yields a 6µH inductor. The resulting maximum
ripple current will be:
∆I
LMAX()
V
5
kHz H
()()
150 6
µ
V
5
1
22
V
–.=
=
43
A
Next, check that the minimum value of the current limit is
acceptable. Assume a junction temperature about 20°C
above the 70°C ambient with ρ
mV
I
LIMIT
300
≥
(. )(.)
Ω
0019 1312
–.
90°C
43 10
= 1.3.
AA
=
18
50A I
PK
RATING
V
IN
LTC1775
PGND
Figure 10. Automotive Application Protection
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
12V
1775 F10
Now double-check the assumed TJ:
5
P
TOP
V
=
22
V
1 7 22 10 170 150
.
()()()( )( )
=+=
056 021 077
...
2
10 1 3 0 019
A
()()
..
()
2
Ω
+
V A pF kHz
WW mW
TJ = 70°C + (0.77W)(30°C/W) = 93°C
Since ρ(93°C) ≅ ρ(90°C), the solution is self-consistent.
Page 19
WUUU
APPLICATIO S I FOR ATIO
LTC1775
A short circuit to ground will result in a folded back
current of:
mV V s
I
SC
80
=
(. )(.)
Ω
0 013 1 1
+
with a typical value of R
1215 0 5
()(.)
and ρ(50°C) = 1.1. The
DS(ON)
µ
H
µ
6
=
62
.
A
resulting power dissipated in the bottom MOSFET is:
VV
15 5
P
=Ω=
BOT
15
–
V
2
AW
62 11 0013 037
(. )(.)(. ) .
which is less than under full load conditions.
C
C1
2.2nF
C
SS
0.1µF
R
10k
C
C
220pF
V
INTV
C2
OUT
LTC1775
1
EXTV
CC
2
SYNC
3
RUN/SS
4
FCB
CC
5
I
TH
6
SGND
7
V
OSENSE
8
V
PROG
V
SW
BOOST
INTV
BG
PGND
16
IN
15
TK
14
13
TG
12
11
CC
10
9
CIN is chosen for an RMS current rating of at least 5A at
temperature. C
is chosen with an ESR of 0.013Ω for
OUT
low output ripple. The output ripple in continuous mode
will be highest at the maximum input voltage and is
approximately:
∆VO = (∆I
)(ESR) = (4.3A)(0.013Ω) = 56mV
L(MAX)
The complete circuit is shown in Figure 11.
V
IN
6V TO 22V
R
F
1Ω
C
+
+
C
F
0.1µF
D
B
CMDSH-3
C
VCC
4.7µF
C
B
0.33µF
M1
SUD50N03-10
L1
6µH
D1
MBRS340
M2
SUD50N03-10
IN
+
22µF
30V
×4
V
OUT
5V
10A
+
C
OUT
680µF
6.3V
CIN: SANYO 30SC22M
C
: SANYO 6SP680M
OUT
L1: MAGENTICS 55380-A2, 8 TURNS, 15 GAUGE
Figure 11. 5V/10A Fixed Output from Design Example
1775 F11
19
Page 20
LTC1775
WUUU
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1775. These items are also illustrated graphically in
the layout diagram of Figure 12. Check the following in
your layout:
1) Connect the TK lead directly to the drain of the topside
MOSFET. Then connect the drain to the (+) plate of CIN.
This capacitor provides the AC current to the top
MOSFET.
2) The power ground pin connects directly to the source of
the bottom N-channel MOSFET. Then connect the source
to the anode of the Schottky diode (if used) and (–) plate
of CIN, which should have as short lead lengths as
possible.
3) The LTC1775 signal ground pin should connect to the
(–) plate of C
. Connect the (–) plate of C
OUT
to power
OUT
ground at the source of the bottom MOSFET. All smallsignal components (R2, CSS, CC, etc.) should return
directly to SGND.
4) Keep the switch node SW away from sensitive smallsignal nodes. Ideally the switch node should be placed
on the opposite side of the power MOSFETs from the
LTC1775.
5) Connect the INTVCC decoupling capacitor C
VCC
closely
to the INTVCC pin and the power ground pin. This
capacitor carries the MOSFET gate drive current.
6) Does the V
OSENSE
pin connect as close as possible to
the load? In adjustable applications, the resistive divider (R1, R2) must be connected between the load and
signal ground. Place the divider near the LTC1775 in
order to keep the high impedance V
OSENSE
node short.
7) For applications with multiple switching power converters connected to the same VIN, ensure that the input
filter capacitance for the LTC1775 is not shared with the
other converters. AC input current from another converter will cause substantial input voltage ripple that
may interfere with proper operation of the LTC1775. A
few inches of PC trace or wire (L
TRACE
≈ 100nH)
between CIN and the VIN supply is sufficient to prevent
sharing.
OPTIONAL 5V EXTV
CONNECTION
C
C
R2
R1
OUTPUT DIVIDER
REQUIRED
WITH V
PROG
BOLD LINES INDICATE HIGH CURRENT PATHS
CC
EXT
SS
CLK
INTV
R
C
OPEN
OPEN
CC
C1
1
2
3
4
5
6
7
8
EXTV
SYNC
RUN/SS
FCB
I
TH
SGND
V
OSENSE
V
PROG
LTC1775
CC
BOOST
INTV
PGND
Figure 12. LTC1775 Layout Diagram
V
SW
TK
TG
BG
L
TRACE
+
16
IN
15
14
13
C
12
11
CC
10
9
B
D
C
B
VCC
+
M2
M1
L1
V
IN
+
D1
C
IN
–
–
V
C
OUT
+
1775 F12
OUT
+
20
Page 21
TYPICAL APPLICATIO S
C
C1
C
R
2.2nF
SS
0.1µF
10k
C
220pF
INTV
C
C2
CC
CIN: SANYO 30SC22M
C
OUT
L1: SUMIDA CDRH-125
U
3.3V/5A Fixed Output
LTC1775
1
EXTV
CC
2
SYNC
3
RUN/SS
4
FCB
5
I
TH
6
SGND
7
V
OSENSE
8
V
PROG
: AVX TPSD107M010R0065
V
SW
BOOST
INTV
BG
PGND
IN
TK
TG
CC
LTC1775
V
IN
5V TO 28V
R
F
1Ω
C
IN
L1
10µH
+
22µF
30V
×2
+
1775 TA01
V
OUT
3.3V
5A
C
OUT
100µF
10V
0.065Ω
×4
C
+
F
0.1µF
D
B
CMDSH-3
C
VCC
4.7µF
C
0.1µF
B
M1
Si4412DY
D1
MBRS140T3
M2
Si4412DY
16
15
14
13
12
11
10
9
C
C1
2.2nF
C
SS
0.1µF
LTC1775
1
6V
EXTV
CC
2
SYNC
3
RUN/SS
4
R
10k
C
220pF
INTV
C
C2
FCB
CC
5
I
TH
6
SGND
7
V
OSENSE
8
V
PROG
CIN: SANYO 30SC22M
: SANYO 6SP680M
C
OUT
L1: MAGNETICS 55206-A2, 3.7µH, 6 TURNS, 13 GAUGE
V
SW
TG
BOOST
INTV
BG
PGND
16
IN
15
TK
14
13
12
11
CC
10
9
5V/20A Fixed Output
C
F
0.1µF
Q2
FMMT720
Q1
FMMT619
D
CMDSH-3
+
C
VCC
4.7µF
Q3
FMMT619
Q4
FMMT720
1Ω
R
B
F
C
B
0.47µF
M1
IRL3803
D1
MBRD835L
M2
IRL3803
+
L1
3.7µH
C
IN
22µF
30V
×8
+
1775 TA02
V
IN
6V TO 28V
V
OUT
5V
20A
C
OUT
680µF
6.3V
×2
21
Page 22
LTC1775
TYPICAL APPLICATIO S
1
2
3
C
C1
R
2.2nF
C
10k
220pF
CIN: SANYO 16SV220M
: SANYO 6SP680M
C
OUT
L1: 12µH, 5A
C
0.1µF
C
4
SS
5
C2
6
7
8
U
–5V/2.5A Positive to Negative Converter
C
F
0.1µF
16
BOOST
INTV
PGND
V
SW
TG
BG
IN
15
TK
14
13
12
D
B
+
CMDSH-3
C
VCC
4.7µF
11
CC
10
9
EXTV
SYNC
RUN/SS
FCB
I
TH
SGND
V
OSENSE
V
PROG
CC
LTC1775
R
F
1Ω
C
B
0.22µF
V
IN
5V TO 10V
M1
Si4412DY
MBR140T3
M2
Si4412DY
L1
12µH
D
C
+
IN
220µF
16V
1
1775 TA04
C
+
OUT
680µF
6.3V
V
OUT
–5V
2.5A
C
C1
2.2nF
C
0.1µF
R1
11k
12V Output, Single Inductor, Buck/Boost Converter
1
EXTV
SS
R
C
OPEN
20k
C
C2
220pF
R2
100k
: UNITED CHEMICON THCR70E1H226ZT-CBU
C
IN
: SANYO 165A-150M
C
OUT
L1: 13µH/11A
2
3
4
5
6
7
8
SYNC
RUN/SS
FCB
I
TH
SGND
V
OSENSE
V
PROG
CC
LTC1775
BOOST
INTV
PGND
V
SW
TK
TG
BG
R
F
1Ω
C
16
IN
15
14
13
12
D
CMDSH-3
11
CC
10
9
F
0.1µF
M1
Si4410DY
L1
13µH
C
B
C
B
0.33µF
VCC
4.7µF
D2
MBRD835L
M3
Si4410DY
+
M2
Si4410DY
D1
MBRS340
V
IN
6V TO 18V
C
IN
+
22µF
50V
×2
V
OUT
12V
C
+
OUT
150µF
16V
×2
V
I
IN
OUT
6.0
2.6
12
4.0
18
4.8
1775 TA05
22
Page 23
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
16
15
14
12 11 10
13
9
LTC1775
0.009
(0.229)
REF
0.015
± 0.004
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0.016 – 0.050
(0.406 – 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0° – 8° TYP
× 45°
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.229 – 0.244
(5.817 – 6.198)
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
16
15
12
0.386 – 0.394*
(9.804 – 10.008)
13
14
0.150 – 0.157**
(3.810 – 3.988)
5
4
3
678
0.004 – 0.0098
(0.102 – 0.249)
0.0250
(0.635)
BSC
GN16 (SSOP) 1098
12
11
10
9
0.010 – 0.020
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
× 45°
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
0.228 – 0.244
(5.791 – 6.197)
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.150 – 0.157**
(3.810 – 3.988)
4
5
0.050
(1.270)
BSC
3
2
1
7
6
8
0.004 – 0.010
(0.101 – 0.254)
S16 1098
23
Page 24
LTC1775
TYPICAL APPLICATIO S
1
2
3
C
C1
2.2nF
C
SS
0.1µF
R
10k
C
C
220pF
4
INTV
CC
5
C2
6
7
8
OPEN
CIN: KEMET T495X156M035AS
C
OUT
L1: SUMIDA CDRH127-6R1
U
2.5V/5A Adjustable Output
LTC1775
BOOST
INTV
PGND
V
SW
BG
IN
TK
TG
CC
EXTV
CC
SYNC
RUN/SS
FCB
I
TH
SGND
V
OSENSE
V
PROG
: KEMET T510X687K004AS
V
IN
5V TO 25V
R
F
1Ω
C
IN
L1
6.1µH
+
1775 TA03
R2
11k
1%
R1
10k
1%
15µF
35V
×3
+
V
2.5V
5A
C
OUT
680µF
4V
×2
OUT
C
+
F
0.1µF
D
B
CMDSH-3
C
VCC
4.7µF
C
B
0.22µF
M1
1/2 FDS8936A
D1
MBRS140
M2
1/2 FDS8936A
16
15
14
13
12
11
10
9
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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Frequency Ideal for 5V to 3.3V
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Current Mode Synchronous Step-Down Controller Burst Mode Operation, 16-Lead GN Package
SENSE
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Up to 36V
V
IN
LTC1629 PolyPhaseTM High Efficiency Step-Down Controller Current Mode Ensures Accurate Current Sharing,
Expandable Up to 200A, V
IN
LTC1649 3.3V Input High Power Step-Down Controller 2.7V to 5V Input, 90% Efficiency, Ideal for 3.3V to 1.xV – 2.xV
Up to 20A
LTC1702 Dual 2-Phase High Frequency, High Efficiency Voltage Mode 500kHz; VIN Up to 7V; V
, I
Synchronous Step-Down Controller I
OUT1
as High as 20A; No Sense Resistor Required
OUT2
OUT1
LTC1735 High Efficiency Synchronous Step-Down Controller Output Fault Protection, 16-Pin GN Package, 4V ≤ VIN ≤ 36V
PolyPhase is a trademark of Linear Technology Corporation.
Linear Technology Corporation
24
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
Saves Space, Fixed
SENSE
Up to 36V
, V
as Low as 2.x, 1.x,
OUT2
1775f LT/TP 0500 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1999
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