Datasheet LTC1736 Datasheet (Linear Technology)

FEATURES

■

Dual N-Channel MOSFET Synchronous Drive

■

Synchronizable/Programmable Fixed Frequency

■

Wide VIN Range: 3.5V to 36V Operation

■

5-Bit Digital-to-Analog V

Selection:

OUT

0.925V to 2.00V Range with 50mV/25mV Steps

■

OPTI-LOOPTM Compensation Minimizes C

■

±

1% Output Voltage Accuracy

■

Power Good Output Voltage Monitor

■

Active Voltage Positioning Compatible

■

Output Overvoltage Crowbar Protection

■

Internal Current Foldback

■

Latched Short-Circuit Shutdown Timer

OUT

with Defeat Option

■

Forced Continuous Control Pin

■

Optional Programmable Soft-Start

■

Remote Output Voltage Sense

■

Available in 24-Lead SSOP Package

U

APPLICATIO S

■

Notebook and Palmtop Computers, PDAs

■

Power Supply for Mobile Pentium® II and
Pentium III Processors

■

Low Voltage Power Supplies

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP and Burst Mode are trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.

LTC1736

5-Bit Adjustable

High Efficiency Synchronous

Step-Down Switching Regulator

U

DESCRIPTIO

The LTC®1736 is a synchronous step-down switching
regulator controller optimized for CPU power. The output
voltage is programmed by a 5-bit digital-to-analog con­verter (DAC) that adjusts the output voltage from 0.925V
to 2.00V according to Intel mobile VID specifications. The

0.8V reference is compatible with future microprocessor
generations.

The operating frequency (synchronizable up to 500kHz) is
set by an external capacitor allowing maximum flexibility
in optimizing efficiency. The output voltage is monitored by
a power good window comparator that indicates when the
output is within 7.5% of its programmed value.

Protection features include: internal foldback current lim­iting, output overvoltage crowbar and optional short-cir­cuit shutdown. Soft-start is provided by an external capaci­tor that can be used to properly sequence supplies. The
operating current level is user-programmable via an exter­nal current sense resistor. Wide input supply range allows
operation from 3.5V to 30V (36V maximum).

Pin defeatable Burst ModeTM operation provides high effi­ciency at low load currents. OPTI-LOOP compensation
allows the transient response to be optimized over a wide
range of output capacitance and ESR values.

TYPICAL APPLICATIO

C

OSC

47pF

C

SS

0.1µF

C

C1

R

C

330pF

33k

C

C2

47pF

47pF

U

V

IN

5V TO 24V

–

1000pF

VIDV
INTV

BOOST

PGND

SENSE

V

IN

C

0.22µF

B

M1
FDS6680A

M2
FDS6680A
×2

TG

SW

BG

D

B

CMDSH-3

CC

CC

+

4.7µF

+

C

OSC

RUN/SS

LTC1736

I

TH

PGOOD
VID4
VID3
VID2
VID1
VID0
SGND

V

SENSE

OSENSE

Figure 1. High Efficiency Step-Down Converter

C

IN

22µF/50V
×2
CERAMIC

D1
MBRS340T3

L1

1.2µH

R

SENSE

0.004Ω

V

OUT

1.35V TO 1.60V
12A

+

C

OUT

180µF/4V
×4

: PANASONIC EEFUEOG181R

C

OUT

: MARCON THCR70EIH226ZT

C

IN

L1: PANASONIC ETQP6RZIR20HFA

: IRC LRF2010-01-R004J

R

SENSE

1736 F01

1

LTC1736

WW

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

Input Supply Voltage (VIN).........................36V to –0.3V

Topside Driver Supply Voltage (BOOST)....42V to –0.3V

Switch Voltage (SW) ....................................36V to –5V

EXTVCC, VIDVCC, (BOOST – SW) Voltages ..7V to –0.3V

SENSE+, SENSE–..........................1.1(INTVCC) to –0.3V

FCB Voltage ............................(INTVCC + 0.3V) to –0.3V

ITH, V

OSENSE

RUN/SS, VID0 to VID4, PGOOD Voltages ....7V to –0.3V

Peak Driver Output Current <10µs (TG, BG) .............. 3A

INTVCC Output Current ......................................... 50mA

Operating Ambient Temperature Range

LTC1736C ............................................... 0°C to 85°C

LTC1736I............................................ –40°C to 85°C

Junction Temperature (Note 2)............................. 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

, VFB Voltage .........................2.7V to –0.3V

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

C

OSC

RUN/SS

I

TH

FCB

SGND

PGOOD

–

SENSE

+

SENSE

V

FB

V

10

OSENSE

11

VID0

12

VID1

24-LEAD PLASTIC SSOP

T

JMAX

1
2
3
4
5
6
7
8
9

G PACKAGE

= 125°C, θJA = 110°C/W

TG

24

BOOST

23

SW

22

V

21

IN

INTV

20

CC

BG

19

PGND

18

EXTV

17

VIDV

16

CC

VID4

15

VID3

14

VID2

13

Consult factory for Military grade parts.

CC

ORDER PART

NUMBER

LTC1736CG
LTC1736IG

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop

V

OSENSE

∆V

LINEREG

∆V

LOADREG

g

m

V

FCB

I

FCB

V

OVL

I

Q

Output Voltage Set Accuracy (Note 3) See Table 1 ● 1%
Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 3) 0.001 0.02 %/V
Output Voltage Load Regulation (Note 3)

Transconductance Amplifier g

Measured in Servo Loop; V
Measured in Servo Loop; V

m

= 0.7V ● 0.1 0.3 %

ITH

= 2V ● –0.1 –0.3 %

ITH

1.3 mmho

Forced Continuous Threshold ● 0.76 0.8 0.84 V
Forced Continuous Current V

= 0.85V – 0.17 –0.3 µA

FCB

Feedback Overvoltage Lockout ● 0.84 0.86 0.88 V
Input DC Supply Current (Note 4)

Normal Mode 450 µA
Shutdown V

V

RUN/SS

V

RUN/SS

I

RUN/SS

I

SCL

Run Pin Start Threshold V
Run Pin Begin Latchoff Threshold V
Soft-Start Charge Current V
RUN/SS Discharge Current Soft Short Condition, VFB = 0.5V, 0.5 2 4 µA

UVLO Undervoltage Lockout Measured at V
∆V

SENSE(MAX)

I

SENSE

t

ON(MIN)

Maximum Current Sense Threshold VFB = 0.7V ● 60 75 85 mV
SENSE Pins Total Source Current V
Minimum On-Time Tested with a Square Wave (Note 8) 160 200 ns

= 0V 15 25 µA

RUN/SS

, Ramping Positive 1.0 1.5 1.9 V

RUN/SS

, Ramping Positive 4.1 4.5 V

RUN/SS

= 0V –0.7 –1.2 µA

RUN/SS

V

= 4.5V

RUN/SS

Pin (VIN Ramping Down) ● 3.5 3.9 V

IN

SENSE

–

= V

+

= 0.8V 60 80 µA

SENSE

TG Transition Time: (Note 9)
TG t
TG t

r
f

Rise Time C

Fall Time C

= 3300pF 50 90 ns

LOAD

= 3300pF 50 90 ns

LOAD

2

LTC1736

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

BG Transition Time: (Note 9)
BG t

r

BG t

f

TG/BG T1D Top Gate Off to Synchronous C

Rise Time C

Fall Time C

= 3300pF 50 90 ns

LOAD

= 3300pF 40 80 ns

LOAD

= 3300pF Each Driver 100 ns

LOAD

Gate-On Delay Time
TG/BG T2D Synchronous Gate Off to Top C

= 3300pF Each Driver 70 ns

LOAD

Gate-On Delay Time

Internal VCC Regulator

V

INTVCC

V

LDO(INT)

V

LDO(EXT)

V

EXTVCC

V

EXTVCC(HYS)

Internal VCC Voltage 6V < VIN < 30V, V

Internal V

EXTVCC Drop Voltage ICC = 20mA, V

Load Regulation ICC = 0mA to 20mA, V

CC

EXTVCC

= 4V 5.0 5.2 5.4 V

EXTVCC

= 4V 0.2 1 %

EXTVCC

= 5V 130 200 mV
EXTVCC Switchover Voltage ICC = 20mA, EXTVCC Ramping Positive ● 4.5 4.7 V
EXTVCC Hysteresis 0.2 V

Oscillator

f

OSC

fH/f

OSC

f

FCB(SYNC)

Oscillator Frequency (Note 5), C

= 43pF 265 300 335 kHz

OSC

Maximum Sync Frequency Ratio 1.3
FCB Pin Threshold For Sync Ramping Negative 0.9 1.2 V

PGOOD Output

V

PGL

I

PGOOD

V

PG

PGOOD Voltage Low I
PGOOD Leakage Current V
PGOOD Trip Level V

= 2mA 110 200 mV

PGOOD

= 5V ±1 µA

PGOOD

with Respect to Set Output Voltage

OSENSE

V
V

Ramping Negative –6.0 –7.5 –9.5 %

OSENSE

Ramping Positive 6.0 7.5 9.5 %

OSENSE

VID Control

VIDV

CC

I

VIDVCC

R

VFB/VOSENSE

R

RATIO

R

PULL-UP

V

IDT

I

VIDLEAK

V

PULL-UP

VID Operating Supply Voltage 2.7 5.5 V
VID Supply Current (Note 6) VIDVCC = 3.3V 0.01 5 µA
Resistance Between V

OSENSE

and V

FB

10 kΩ

Resistor Ratio Accuracy Programmed from 0.925V to 2.00V ±0.05 %
VID0 to VID4 Pull-Up Resistance (Note 7) V

= 0.6V 40 kΩ

DIODE

VID Input Voltage Threshold 0.4 1.0 1.6 V
VID Input Leakage Current (Note 7) VIDVCC < VID < 7V 0.01 ±1 µA
VID Pull-Up Voltage VIDVCC = 3.3V 2.8 V

VIDVCC = 5V 4.5 V

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: T
dissipation P

LTC1736CG, LTC1736IG: T

is calculated from the ambient temperature TA and power

J

according to the following formulas:

D

= TA + (PD • 110°C/W)

J

Note 3: The LTC1736 is tested in a feedback loop that servos VFB to the
balance point for the error amplifier (V

ITH

= 1.2V).

Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.

Note 5: Oscillator frequency is tested by measuring the C
current (I

f

OSC

) and applying the formula:

OSC

11



8 477 10

.( )

=



CpF I I

()

OSC CHG DIS







11





11

+





1

–



+





OSC

charge

Note 6: With all five VID inputs floating (or tied to VIDV
current is typically <1µA. However, the VIDVCC current will rise and be
approximately equal to the number of grounded VID input pins times
(VIDVCC – 0.6V)/40k. (See the Applications Information section for more
detail.)

Note 7: Each built-in pull-up resistor attached to the VID inputs also has a
series diode to allow input voltages higher than the VIDV
damage or clamping. (See the Applications Information section for more
detail.)

Note 8: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current ≥40% of I

(see minimum on-time

MAX

considerations in the Applications Information section).
Note 9: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

) the VIDV

CC

supply without

CC

CC

3

LTC1736

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Load Current
(3 Operating Modes)

100

EXTVCC OPEN

90

BURST

80

70

60

50

EFFICIENCY (%)

40

30

20

0.001

0.01

SYNC

CONT

0.1

LOAD CURRENT (A)

VIN = 5V

= 1.6V

V

OUT

R

= 0.01Ω

S

= 300kHz

f

O

1

10

1736 G01

Efficiency vs Load Current Efficiency vs Input Voltage

100

EXTVCC = 5V

90

VIN = 5V

80

70

EFFICIENCY (%)

60

50

40

10mA 100mA 1A 10A

VIN = 24V

LOAD CURRENT (A)

VIN = 15V

1736 G02

100

EXTVCC = 5V

= 1.6V

V

OUT

95

FIGURE 1

90

85

EFFICIENCY (%)

80

75

70

0

10 15 20

5

INPUT VOLTAGE (V)

I

OUT

= 0.5A

I

= 5A

OUT

25 30

1736 G03

Efficiency vs Input Voltage

100

EXTVCC OPEN

= 1.6V

V

OUT

95

FIGURE 1

90

85

I

EFFICIENCY (%)

80

75

70

0

5

OUT

10 15 20

INPUT VOLTAGE (V)

Input and Shutdown Currents
vs Input Voltage

500

400

300

200

INPUT CURRENT (µA)

100

0

05

ALL VID BITS OPEN

EXTVCC OPEN

SHUTDOWN

EXTVCC = 5V

20

15

10

INPUT VOLTAGE (V)

= 0.5A

25

I

OUT

= 5A

25 30

1736 G04

30

1736 G07

Load Regulation

0

–0.1

(%)

OUT

–0.2

NORMALIZED V

–0.3

–0.4

2

0

6

4

LOAD CURRENT (A)

8

FCB = 0V

= 15V

V

IN

FIGURE 1

1736 G05

1210

ITH Voltage vs Load Current

2.5
VIN = 5V

= 1.6V

V

OUT

= 0.01Ω

R

SENSE

2.0

= 300kHz

f

O

CONTINUOUS

1.5

VOLTAGE (V)

1.0

TH

I

0.5

0

MODE

SYNCHRONIZED f = f

Burst Mode
OPERATION

0

234

1

LOAD CURRENT (A)

O

56

1736 G06

EXTVCC Switch Drop

INTVCC Line Regulation

100

SHUTDOWN CURRENT (µA)

80

60

40

20

0

35

6

1mA LOAD

5

4

3

VOLTAGE (V)

CC

2

INTV

1

0

0

510

INPUT VOLTAGE (V)

20 30 35

15 25

1736 G08

vs INTVCC Load Current

500

400

(mV)

300

CC

– INTV

200

CC

EXTV

100

0

10

0

INTVCC LOAD CURRENT (mA)

30

40

20

50

1736 G09

4

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Maximum Current Sense Threshold
vs Normalized Output Voltage
(Foldback)

80

70

60

50

40

30

20

CURRENT SENSE THRESHOLD (mV)

10

0

0

25

NORMALIZED OUTPUT VOLTAGE (%)

50

75

100

1736 G10

Maximum Current Sense Threshold
vs V

RUN/SS

80

V

60

40

20

CURRENT SENSE THRESHOLD (mV)

0

0

= 1.6V

SENSE(CM)

1234

V

(V)

RUN/SS

56

1736 G11

LTC1736

Maximum Current Sense Threshold
vs Sense Common Mode Voltage

80

76

72

68

64

CURRENT SENSE THRESHOLD (mV)

60

0.5

0

COMMON MODE VOLTAGE (V)

1 1.5 2

1736 G12

Maximum Current Sense Threshold
vs ITH Voltage

90
80
70
60
50
40

30
20
10

0

–10

CURRENT SENSE THRESHOLD (mV)

–20
–30

0.5

0

1.5

1

V

(V)

ITH

RUN/SS Pin Current
vs Temperature

0

V

= 0V

RUN/SS

–1

–2

Maximum Current Sense Threshold

V

vs Temperature

80

V

75

70

65

CURRENT SENSE THRESHOLD (mV)

2

2.5

1736 G13

60

–40

= 1.6V

SENSE(CM)

–15 10 35 60

TEMPERATURE (°C)

85 110 135

1736 G18

(V)

ITH

V

FCB Pin Current vs Temperature

0

V

= 0.85V

FCB

–0.2

–0.4

(%)

MAX

/I

OUT

vs V

ITH

RUN/SS

2.5

V

= 0.7V

OSENSE

2.0

1.5

1.0

0.5

0

0

234

1

V

RUN/SS

(V)

Output Current vs Duty Cycle

100

80

60

I

OUT/IMAX

(SYNCHRONIZED)

(FREE RUN)

I

OUT/IMAX

56

1736 G15

–3

RUN/SS CURRENT (µA)

–4

–5

–40 –15

60

35

10

TEMPERATURE (°C)

–0.6

FCB CURRENT (µA)

–0.8

110

135

1736 G16

85

–1.0

–40 –15

60

35

10

TEMPERATURE (°C)

110

135

1736 G17

85

40

20

f

= f

SYNC

AVERAGE OUTPUT CURRENT I

0

O

0

40 60 80

20

DUTY CYCLE (%)

100

1736 G14

5

LTC1736

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Oscillator Frequency
vs Temperature

300

C

= 47pF

OSC

290

280

270

FREQUENCY (kHz)

260

250

–40 –15

10

TEMPERATURE (°C)

Start-Up

V

OUT

1V/DIV

V

RUN/SS

5V/DIV

I

L

5A/DIV

= 15V

V

IN

= 1.6V

V

OUT

R

= 0.16Ω

LOAD

35

60

5ms/DIV

Dynamic VID Change,
Burst Mode Operation Defeated

FCB = 0V

V

OUT

100mV/DIV

I

L

5A/DIV

PGOOD

5V/DIV

20µs/DIV 20µs/DIV

110

1736 G19

135

1736 G22

V

OUT

10mV/DIV

5A/DIV

V

OUT(RIPPLE)

I

LOAD

I

L

EXT SYNC (f = f
V

= 15V

IN

= 1.6V

V

OUT

(Synchronized)

= 10mA I

10µs/DIV

)

O

85

100mV/DIV

PGOOD

1736 G20

20mV/DIV

5A/DIV

1736 G23

Dynamic VID Change,
Burst Mode Operation Enabled

FCB = PGOOD

V

OUT

I

L

5A/DIV

5V/DIV

V

OUT(RIPPLE)

(Burst Mode Operation)

= 50mA

LOAD

V

OUT

I

L

FCB = 5V
V

= 15V

IN

= 1.6V

V

OUT

50µs/DIV

1736 G21

1736 G24

V

20mV/DIV

5A/DIV

6

V

OUT(RIPPLE)

(Burst Mode Operation)

I

= 1.5A

LOAD

OUT

I

L

FCB = 5V

= 15V

V

IN

= 1.6V

V

OUT

5µs/DIV

1736 G25

V

OUT

50mV/DIV

5A/DIV

Load Step
(Burst Mode Operation)

I

L

10mA TO
11A LOAD STEP
FCB = 5V

= 15V

V

IN

= 1.6V

V

OUT

10µs/DIV

1736 G26

V

OUT

50mV/DIV

5A/DIV

Load Step (Continuous Mode)

I

L

0A TO
11A LOAD STEP
FCB = 0V

= 15V

V

IN

= 1.6V

V

OUT

10µs/DIV

1736 G27

UUU

PI FU CTIO S

LTC1736

C

(Pin 1): External capacitor C

OSC

ground sets the operating frequency.
RUN/SS (Pin 2): Combination of Soft-Start and Run

Control Inputs. A capacitor to ground at this pin sets the
ramp time to full output current. The time is approximately

1.25s/µF. Forcing this pin below 1.5V causes the device to
be shut down. In shutdown all functions are disabled.
Latchoff overcurrent protection is also invoked via this pin
as described in the Applications Information section.

ITH (Pin 3): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 2.4V.

FCB (Pin 4): Forced Continuous/Synchronization Input.
Tie this pin to ground for continuous synchronous opera­tion, to a resistive divider from the secondary output when
using a secondary winding, or to INTVCC to enable Burst
Mode operation at low load currents. Clocking this pin with
a signal above 1.5V
allows cycle skipping at low load currents and synchro­nizes the internal oscillator with the external clock.

SGND (Pin 5): Small-Signal Ground. All small-signal
components such as C
tion resistors and capacitor(s) should single-point tie to
this pin. This pin should, in turn, connect to PGND.

PGOOD (Pin 6): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on the V
not within ±7.5% of its set point.

SENSE– (Pin 7): The (–) Input to the Current Comparator.

disables Burst Mode operation but

P-P

, CSS plus the loop compensa-

OSC

from this pin to

OSC

OSENSE

pin is

VID0 to VID4 (Pins 11 to 15): Digital Inputs for controlling
the output voltage from 0.925V to 2.0V. Table 1 specifies
the V
inputs. The LSB (VID0) represents 50mV increments in
the upper voltage range (2.00V to 1.30V) and 25mV
increments in the lower voltage range (1.275V to 0.925V).
Logic Low = GND, Logic High = VIDVCC or Float.

VIDVCC (Pin 16): VID Input Supply Voltage. Can range
from 2.7V to 7V. Typically this pin is tied to INTVCC.

EXTV

to INTVCC. This switch closes and supplies VCC power
whenever EXTVCC is higher than 4.7V. See EXTVCC con­nection in the Applications Information section. Do not
exceed 7V to this pin and ensure EXTVCC ≤ VIN.

PGND (Pin 18): Driver Power Ground. This pin connects
to the source of the bottom N-channel MOSFET, the anode
of the Schottky diode and the (–) terminal of CIN.

BG (Pin 19): High Current Gate Drive for Bottom
N-Channel MOSFET. Voltage swing at this pin is from
ground to INTV

INTVCC (Pin 20): Output of the Internal 5.2V Regulator and
EXTVCC Switch. The driver and control circuits are pow­ered from this voltage. Decouple to power ground with a
1µF ceramic capacitor placed directly adjacent to the IC
together with a minimum of 4.7µF tantalum or other low
ESR capacitor.

V

(Pin 21): Main Supply Pin. This pin must be closely

IN

decoupled to power ground.

voltages for the 32 combinations of digital

OSENSE

(Pin 17): Input to the Internal Switch Connected

CC

.

CC

SENSE+ (Pin 8): The (+) Input to the Current Comparator.
Built-in offsets between SENSE– and SENSE+ pins in
conjunction with R

VFB (Pin 9): Divided Down V
Error Amplifier of the Regulator. The VID inputs program
a resistive divider between V
point on the divider is V
the output is in regulation. This pin can be bypassed to
SGND with 50pF to 100pF.

V

OSENSE

voltage from the output.

(Pin 10): Receives the remotely sensed feedback

set the current trip threshold.

SENSE

OSENSE

. The voltage on V

FB

Voltage Feeding the

OSENSE

and SGND; the tap

FB

is 0.8V when

SW (Pin 22): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground to
VIN.

BOOST (Pin 23): Supply to Topside Floating Driver. The
bootstrap capacitor is returned to this pin. Voltage swing
at this pin is from a diode drop below INTVCC to VIN +
INTVCC.

TG (Pin 24): High Current Gate Drive for Top N-Channel
MOSFET. This is the output of a floating driver with a
voltage swing equal to INTVCC superimposed on the
switch node voltage SW.

7

LTC1736

UU

W

FU CTIO AL DIAGRA

C

OSC

47pF

INTV

PGOOD

6

–
+

0.74V

V

1.2µA

6V

RUN/SS

0.86V

FB

C

V

OSENSE

10

R2

V

FB

10k

9

R1

SGND

5

VIDV

CC

16

CC

40k

VID4

VID3
VID2
VID1
VID0

15

14
13
12
11

VID

DECODER

0.8V

SS

2

C

OV

+
–

gm =1.3m

–

EA

+

START

CURRENT

LATCH-OFF

OSC

SD

RUN

SOFT

OVER-

C

C

+

V

INTV

INTV

C

INTVCC

20

BG
19

PGND

18

IN

+

C

IN

CC

D

B

V

C

B

D

1

SEC

+

C

SEC

•

•

V

OUT

+

C

CC

OUT

+

R

SENSE

1736 FD

R4

R3

Q

2k

+– –+

+

FCB

4

DROP

OUT
DET

TOP ON

45k

3mV

30k 30k

0.55V

BOT

–

+

+

–

45k

–

+

SENSE

F

B

SD

IREV

I2

4.8V

–

)

SYNC

ICMP

BURST
DISABLE
FC

A

0.17µA

C

I1

–
+

1.2V 0.8V

FORCE BOT

S

R

2.4V

–
+

BUFFERED
I

TH

SENSE

1

OSC

Ω

0.86V

4(V

FB

SLOPE COMP

R

C

I

TH

FC

INTV

0.8V
REF

SWITCH

LOGIC

V

CC

+
–

V

21

IN

UVL

BOOST

23

TOP

BOT

IN

5.2V
LDO
REG

EXTV

TG
24

SW

22

17783

CC

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OPERATIO

Main Control Loop

The LTC1736 uses a constant frequency, current mode
step-down architecture. During normal operation, the
top MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the main current
comparator I1 resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on Pin ITH, which is the output of the error
amplifier EA. Pin V
allows EA to receive an output feedback voltage VFB from
the internal resistive divider. When the load current
increases, it causes a slight decrease in VFB relative to the

0.8V reference, which in turn causes the ITH voltage to
increase until the average inductor current matches the

(Refer to Functional Diagram)

OSENSE

, described in the Pin Functions,

8

new load current. While the top MOSFET is off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current com­parator I2, or the beginning of the next cycle.

The top MOSFET driver is powered from a floating
bootstrap capacitor CB. This capacitor is normally re­charged from INTVCC through an external Schottky diode
when the top MOSFET is turned off. As VIN decreases
towards V

, the converter will attempt to turn on the

OUT

top MOSFET continuously (‘’dropout’’). A dropout counter
detects this condition and forces the top MOSFET to turn
off for about 500ns every tenth cycle to recharge the
bootstrap capacitor.

OPERATIO

LTC1736

U

(Refer to Functional Diagram)

The main control loop is shut down by pulling Pin 2 (RUN/
SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with the
ITH voltage clamped at approximately 30% of its maximum
value. As CSS continues to charge, ITH is gradually re­leased allowing normal operation to resume. If V
not reached 70% of its final value when CSS has charged
to 4.1V, latchoff can be invoked as described in the
Applications Information section.

The internal oscillator can be synchronized to an external
clock applied to the FCB pin and can lock to a frequency
between 90% and 130% of its nominal rate set by capaci­tor C

An overvoltage comparator OV guards against transient
overshoots (>7.5%) as well as other more serious condi­tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned on
until the overvoltage condition is cleared.

Foldback current limiting for an output shorted to ground
is provided by amplifier A. As VFB drops below 0.6V, the
buffered ITH input to the current comparator is gradually
pulled down to a 0.86V clamp. This reduces peak inductor
current to about 1/4 of its maximum value.

Low Current Operation

The LTC1736 has three low current modes controlled by
the FCB pin. Burst Mode operation is selected when the
FCB pin is above 0.8V (typically tied to INTVCC). During
Burst Mode operation, if the error amplifier drives the I
voltage below 0.86V, the buffered ITH input to the current
comparator will be clamped at 0.86V. The inductor current
peak is then held at approximately 20mV/R
4 of maximum output current). If ITH then drops below

0.5V, the Burst Mode comparator B will turn off both
MOSFETs to maximize efficiency. The load current will be
supplied solely by the output capacitor until ITH rises
above the 60mV hysteresis of the comparator and switch­ing is resumed. Burst Mode operation is disabled by
comparator F when the FCB pin is brought below 0.8V.

OSC

.

SENSE

has

OUT

TH

(about 1/

This forces continuous operation and can assist second­ary winding regulation.

When the FCB pin is driven by an external oscillator, a low
noise cycle-skipping mode is invoked and the internal
oscillator is synchronized to the external clock by com­parator C. In this mode the 25% minimum inductor
current clamp is removed, providing constant frequency
discontinuous operation over the widest possible output
current range. This constant frequency operation is not
quite as efficient as Burst Mode operation, but provides a
lower noise, constant frequency spectrum.

The FCB pin is tied to ground when forced continuous
operation is desired. This operation is the least efficient
mode, but is desirable in certain applications. The output
can source or sink current in this mode. When sinking
current while in forced continuous operation, current will
be forced back into the main power supply potentially
boosting the input supply to dangerous voltage levels—
BEWARE.

Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff

The RUN/SS capacitor, CSS, is used initially to limit the
inrush current of the switching regulator. After the con­troller has been started and been given adequate time to
charge up the output capacitors and provide full load
current, CSS is used as a short-circuit time-out circuit. If
the output voltage falls to less than 70% of its nominal
output voltage, CSS begins discharging on the assumption
that the output is in an overcurrent and/or short-circuit
condition. If the condition lasts for a long enough period
as determined by the size of the CSS, the controller will be
shut down until the RUN/SS pin voltage is recycled. This
built-in latchoff can be overridden by providing a current
>5µA at a compliance of 5V to the RUN/SS pin. This
current shortens the soft-start period but also prevents net
discharge of C
circuit condition. Foldback current limiting is activated
when the output voltage falls below 70% of its nominal
level whether or not the short-circuit latchoff circuit is
enabled.

during an overcurrent and/or short-

SS

9

LTC1736

OPERATIO

U

(Refer to Functional Diagram)

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and most
of the internal circuitry of the LTC1736 is derived from the
INTVCC pin. When the EXTVCC pin is left open, an internal

5.2V low dropout regulator supplies the INTVCC power
from VIN. If EXTVCC is raised above 4.7V, the internal
regulator is turned off and an internal switch connects
EXTVCC to INTVCC. This allows a high efficiency source,
such as the notebook main 5V system supply or a second­ary output of the converter itself, to provide the INTV
power. Voltages up to 7V can be applied to EXTVCC for
additional gate drive capability.

To provide clean start-up and to protect the MOSFETs,
undervoltage lockout is used to keep both MOSFETs off
until the input voltage is above 3.5V.

U

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APPLICATIO S I FOR ATIO

The basic LTC1736 application circuit is shown in
Figure 1 on the first page of this data sheet. External
component selection is driven by the load requirement
and begins with the selection of R
known, C
FETs and D1 are selected. The operating frequency and the
inductor are chosen based largely on the desired amount
of ripple current. Finally, CIN is selected for its ability to
handle the large RMS current into the converter and C
is chosen with low enough ESR to meet the output voltage
ripple and transient specifications. The circuit shown in
Figure 1 can be configured for operation up to an input
voltage of 28V (limited by the external MOSFETs).

and L can be chosen. Next, the power MOS-

OSC

SENSE

. Once R

SENSE

is

OUT

VID Control

Bits VID0 to VID4 are logic inputs setting the output volt­age using an internal 5-bit DAC as a feedback resistive
voltage divider. The output voltage can be set in 50mV or
25mV increments from 0.925V to 2.0V according to
Table 1. Pins VID0 to VID4 are internally pulled up to
VIDVCC.

PGOOD

A window comparator monitors the output voltage and its
open-drain output is pulled low when the divided down
output voltage is not within ±7.5% of the reference voltage
of 0.8V.

mV

R

SENSE

C

Selection for Operating Frequency

OSC

and Synchronization

The choice of operating frequency and inductor value is a
trade-off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses, both gate charge loss and
transition loss. However, lower frequency operation re­quires more inductance for a given amount of ripple
current.

50

=

I

MAX

R

R
The LTC1736 current comparator has a maximum thresh­old of 75mV/R
SGND to 1.1(INTVCC). The current comparator threshold
sets the peak of the inductor current, yielding a maximum
average output current I
half the peak-to-peak ripple current, ∆IL.

Allowing a margin for variations in the LTC1736 and
external component values yields:

Selection For Output Current

SENSE

is chosen based on the required output current.

SENSE

and an input common mode range of

SENSE

equal to the peak value less

MAX

10

The LTC1736 uses a constant-frequency architecture with
the frequency determined by an external oscillator capaci­tor C
voltage on C
C

OSC

capacitor reaches 1.19V, C
process then repeats.

The value of C
frequency assuming no external clock input on the FCB
pin:

. Each time the topside MOSFET turns on, the

OSC

is reset to ground. During the on-time

OSC

is charged by a fixed current. When the voltage on the

is reset to ground. The

OSC

is calculated from the desired operating

OSC

LTC1736

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APPLICATIO S I FOR ATIO



16110

CpF

()

OSC



Frequency





A graph for selecting C
Figure 2. The maximum recommended switching fre­quency is 550kHz .

The internal oscillator runs at its nominal frequency (fO)
when the FCB pin is pulled high to INTVCC or connected to
ground. Clocking the FCB pin above and below 0.8V will
cause the internal oscillator to lock to an external clock
signal with a frequency between 0.9fO and 1.3fO. The clock
high level must exceed 1.3V for at least 0.3µs, and the
clock low level must be less than 0.3V for at least 0.3µs.
The top MOSFET turn-on will synchronize with the rising
edge of the external clock.

Attempting to synchronize to too high an external fre­quency (above 1.3fO) can result in inadequate slope com­pensation and possible loop instability at high duty cycles.
If this condition exists simply lower the value of C
f

= fO according to Figure 2.

EXT

100.0

87.5

75.0

62.5

50.0

VALUE (pF)

37.5

OSC

C

25.0

12.5

0

0 100 200 300 400 500 600

Figure 2. Timing Capacitor Value

When synchronized to an external clock, Burst Mode op­eration is disabled but the inductor current is not allowed
to reverse. The 25% minimum inductor current clamp
present in Burst Mode operation is removed, providing
constant frequency discontinuous operation over the wid­est possible output current range. In this mode the
synchronous MOSFET is forced on once every 10 clock

7

.( )

OPERATING FREQUENCY (kHz)




–=

11





versus frequency is given in

OSC

1736 F02

OSC

so

cycles to recharge the bootstrap capacitor. This minimizes
audible noise while maintaining reasonably high efficiency.

Inductor Value Calculation

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate-charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.

The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL decreases with higher induc­tance or frequency and increases with higher VIN or V

∆I

1

=

L OUT

fL

()()



V

1

–




V

OUT

V

IN





OUT

:

Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.3 to 0.4(I

). Remember,

MAX

the maximum ∆IL occurs at the maximum input voltage.
The inductor value also has an effect on low current

operation. The transition to low current operation begins
when the inductor current reaches zero while the bottom
MOSFET is on. Burst Mode operation begins when the
average inductor current required results in a peak current
below 25% of the current limit determined by R

SENSE

.

Lower inductor values (higher ∆IL) will cause this to occur
at higher load currents, which can cause a dip in efficiency
in the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.

Inductor Core Selection

Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite,

11

LTC1736

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APPLICATIO S I FOR ATIO

molypermalloy or Kool Mµ® cores. Actual core loss is
independent of core size for a fixed inductor value, but it
is very dependent on the inductance selected. As induc­tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con­centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc­tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu­facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be­cause they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
that do not increase the height significantly.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for use
with the LTC1736: An N-channel MOSFET for the top
(main) switch and an N-channel MOSFET for the bottom
(synchronous) switch.

The peak-to-peak gate drive levels are set by the INTV
voltage. This voltage is typically 5.2V during start-up. (See
EXTVCC Pin Connection.) Consequently, logic-level thresh­old MOSFETs must be used in most LTC1736 applica­tions. The only exception is when low input voltage is
expected (V
MOSFETs (V
attention to the BV
well; most of the logic level MOSFETs are limited to 30V or
less.

Selection criteria for the power MOSFETs include the “ON”
resistance R
input voltage and maximum output current. When the
LTC1736 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:

< 5V); then, sublogic level threshold

IN

GS(TH)

DS(ON)

< 3V) should be used. Pay close

specification for the MOSFETs as

DSS

, reverse transfer capacitance C

CC

RSS

,

V

Main SwitchDuty Cycle

Synchronous SwitchDuty Cycle

The MOSFET power dissipations at maximum output
current are given by:

V

P

MAIN

P

SYNC

where δ is the temperature dependency of R
is a constant inversely related to the gate drive current.

Both MOSFETs have I2R losses while the topside
N-Channel equation includes an additional term for tran­sition losses, which are highest at high input voltages. For
V

< 20V the high current efficiency generally improves

IN

with larger MOSFETs, while for V
losses rapidly increase to the point that the use of a higher
R

DS(ON)

efficiency. The synchronous MOSFET losses are greatest
at high input voltage or during a short circuit when the duty
cycle in this switch is nearly 100%.

The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C
characteristics. The constant k = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.

The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on and storing charge during the
dead-time, which could cost as much as 1% in efficiency.
A 3A Schottky is generally a good size for 10A to 12A
regulators due to the relatively small average current.

Kool Mµ is a registered trademark of Magnetics, Inc.

OUT

=

V

IN

kV I C f

()( )( )()

IN MAX RSS

VV

–

IN OUT

=

V

IN

device with lower C

2

IR

()

MAX DS ON

2

IR

()

MAX

DS(ON)

is usually specified in the MOSFET

RSS

OUT

=

V

IN

VV

–

IN OUT

=

V

IN

+

11δ

()

2

+

()

actually provides higher

RSS

vs Temperature curve, but

+

()

δ

DS ON

()

DS(ON)

> 20V the transition

IN

and k

12

LTC1736

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APPLICATIO S I FOR ATIO

Larger diodes can result in additional transition losses due
to their larger junction capacitance. The diode may be
omitted if the efficiency loss can be tolerated.

CIN Selection

In continuous mode, the source current of the top
N-channel MOSFET is a square wave of duty cycle V
VIN. To prevent large voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS capacitor current is given by:

/

II

≅

RMS O MAX

()

V

OUT

V

V



V



ININOUT



This formula has a maximum at V
= I

/2. This simple worst-case condition is commonly

OUT

–1






12

IN

= 2V

, where I

OUT

used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.

C

Selection

OUT

The selection of C

is primarily determined by the

OUT

effective series resistance (ESR) to minimize voltage ripple.
The output ripple (∆V

) in continuous mode is deter-

OUT

mined by:

∆∆V I ESR

≈+

OUT L





8

Where f = operating frequency, C



fC

1

OUT






= output capaci-

OUT

tance, and ∆IL = ripple current in the inductor. The output
ripple is highest at maximum input voltage since ∆I
increases with input voltage. Typically, once the ESR
requirement for C
rating generally far exceeds the I
With ∆IL = 0.3I

OUT(MAX)

has been met, the RMS current

OUT

RIPPLE(P-P)

requirement.

the output ripple will be less than

50mV at max VIN assuming:

OUT

RMS

/

L

C

required ESR < 2.2 R

C

OUT

OUT

> 1/(8fR

SENSE

)

SENSE

The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran­tees that the output capacitance does not significantly
discharge during the operating frequency period due to
ripple current. The choice of using smaller output capaci­tance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage at or below
50mV. The ITH pin OPTI-LOOP compensation compo­nents can be optimized to provide stable, high perfor­mance transient response regardless of the output capaci­tors selected.

The selection of output capacitors for CPU or other appli­cations with large load current transients is primarily
determined by the voltage tolerance specifications of the
load. The resistive component of the capacitor, ESR,
multiplied by the load current change plus any output
voltage ripple must be within the voltage tolerance of the
load (CPU).

The required ESR due to a load current step is:

R

< ∆V/∆I

ESR

where ∆I is the change in current from full load to zero load
(or minimum load) and ∆V is the allowed voltage deviation
(not including any droop due to finite capacitance).

The amount of capacitance needed is determined by the
maximum energy stored in the inductor. The capacitance
must be sufficient to absorb the change in inductor current
when a high current to low current transition occurs. The
opposite load current transition is generally determined by
the control loop OPTI-LOOP components, so make sure
not to over compensate and slow down the response. The
minimum capacitance to assure the inductors’ energy is
adequately absorbed is:

2

LI

∆

C

OUT

()

>

2

VV

∆

OUT

()

where ∆I is the change in load current.

13

LTC1736

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APPLICATIO S I FOR ATIO

Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance through­hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.

In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling, and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Spe­cial polymer surface mount capacitors offer very low ESR
but have much lower capacitive density per unit volume
than other capacitor types. These capacitors offer a very
cost-effective output capacitor solution and are an ideal
choice when combined with a controller having high loop
bandwidth. Tantalum capacitors offer the highest capaci­tance density and are often used as output capacitors for
switching regulators having controlled soft-start. Several
excellent surge-tested choices are the AVX TPS, AVX
TPSV or the KEMET T510 series of surface mount
tantalums, available in case heights ranging from 2mm to
4mm. Aluminum electrolytic capacitors can be used in
cost-driven applications providing that consideration is
given to ripple current ratings, temperature and long-term
reliability. A typical application will require several to many
aluminum electrolytic capacitors in parallel. A combina­tion of the above mentioned capacitors will often result in
maximizing performance and minimizing overall cost.
Other capacitor types include Nichicon PL series, NEC
Neocap, Panasonic SP and Sprague 595D series. Consult
manufacturers for other specific recommendations.

Like all components, capacitors are not ideal. Each ca­pacitor has its own benefits and limitations. Combina­tions of different capacitor types have proven to be a very
cost effective solution. Remember also to include high
frequency decoupling capacitors. They should be placed
as close as possible to the power pins of the load. Any
inductance present in the circuit board traces negates
their usefulness.

INTVCC Regulator

An internal P-channel low dropout regulator produces the

5.2V supply that powers the drivers and internal circuitry
within the LTC1736. The INTVCC pin can supply a maxi­mum RMS current of 50mA and must be bypassed to
ground with a minimum of 4.7µF tantalum, 10µF special
polymer or low ESR type electrolytic capacitor. Good
bypassing is required to supply the high transient currents
required by the MOSFET gate drivers.

Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the
maximum junction temperature rating for the LTC1736 to
be exceeded. The system supply current is normally
dominated by the gate charge current. Additional loading
of INTVCC also needs to be taken into account for the
power dissipation calculations. The total INTVCC current
can be supplied by either the 5.2V internal linear regulator
or by the EXTVCC input pin. When the voltage applied to
the EXTVCC pin is less than 4.7V, all of the INTVCC current
is supplied by the internal 5.2V linear regulator. Power
dissipation for the IC in this case is highest: (VIN)(I
and overall efficiency is lowered. The gate charge is
dependent on operating frequency as discussed in the
Efficiency Considerations section. The junction tempera­ture can be estimated by using the equations given in
Note 2 of the Electrical Characteristics. For example, the
LTC1736G is limited to less than 17mA from a 30V supply
when not using the EXTVCC pin as follows:

TJ = 70°C + (17mA)(30V)(110°C/W) = 126°C

Use of the EXTVCC input pin reduces the junction tempera­ture to:

TJ = 70°C + (17mA)(5V)(110°C/W) = 79°C

To prevent maximum junction temperature from being
exceeded, the input supply current must be checked
operating in continuous mode at maximum VIN.

EXTVCC Connection

The LTC1736 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
Whenever the EXTVCC pin is above 4.7V the internal 5.2V

INTVCC

),

14

LTC1736

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APPLICATIO S I FOR ATIO

regulator shuts off, the switch closes and INTVCC power is
supplied via EXTVCC until EXTVCC drops below 4.5V. This
allows the MOSFET gate drive and control power to be
derived from the output or other external source during
normal operation. When the output is out of regulation
(start-up, short circuit) power is supplied from the internal
regulator. Do not apply greater than 7V to the EXTVCC pin
and ensure that EXTVCC < VIN.

Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
simply means connecting the EXTVCC pin directly to V
However, for VID programmed regulators and other lower
voltage regulators, additional circuitry is required to de­rive INTVCC power from the output.

The following list summarizes the three possible connec­tions for EXTV

1. EXTVCC Left Open (or Grounded). This will cause INTV
to be powered from the internal 5.2V regulator resulting
in a low current efficiency penalty of up to 10% at high
input voltages.

2. EXTVCC Connected to an External Supply (this option is
the most likely used). If an external supply is available
in the 5V to 7V range, such as notebook main 5V
system power, it may be used to power EXTVCC provid­ing it is compatible with the MOSFET gate drive
requirements. This is the typical case as the 5V power
is almost always present and is derived by another high
efficiency regulator.

3. EXTVCC Connected to an Output-Derived Boost Net­work. For this low output voltage regulator, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with either the inductive
boost winding or the capacitive charge pump circuits.
Refer to the LTC1735 data sheet for details. The charge
pump has the advantage of simple magnetics.

CC:

OUT

CC

.

Output Voltage Programming

The output voltage is digitally set to levels between 0.925V
and 2.00V using the voltage identification (VID) inputs
VID0 to VID4. The internal 5-bit DAC configured as a
precision resistive voltage divider sets the output voltage
in 50mV or 25mV increments according to Table 1.

The VID codes (00000-11110) are engineered to be com­patible with Intel Mobile Pentium II and Pentium III pro­cessor specifications for output voltages from 0.925V to

2.00V.
The LSB (VID0) represents 50mV increments in the upper

voltage range (1.30V to 2.00V) and 25mV increments in
the lower voltage range (0.925V to 1.275V). The MSB is
VID4. When all bits are low, or grounded, the output
voltage is 2.00V.

Between the V
whose value is controlled by the five input pins (VID0 to
VID4). Another resistor, R2, between the V
VFB pins completes the resistive divider. The output volt­age is thus set by the ratio of (R1 + R2) to R1.

The LTC1736 has remote sense capability. The top of the
internal resistive divider is connected to V
referenced to the SGND pin. This allows a kelvin connec­tion for remotely sensing the output voltage directly across
the load, eliminating any PC board trace resistance errors.

Each VID digital input is pulled up by a 40k resistor in
series with a diode from VIDVCC. Therefore, it must be
grounded to get a digital low input, and can be either
floated or connected to VIDVCC to get a digital high input.
The series diode is used to prevent the digital inputs from
being damaged or clamped if they are driven higher than
VIDVCC. The digital inputs accept CMOS voltage levels.

VIDVCC is the supply voltage for the VID section. It is
normally connected to INTVCC but can be driven from
other sources such as a 3.3V supply. If it is driven from
another source, that source MUST be in the range of 2.7V
to 5.5V and MUST be alive prior to enabling the LTC1736.

pin and ground is a variable resistor, R1,

FB

OSENSE

OSENSE

and the

, and it is

15

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APPLICATIO S I FOR ATIO

Table 1. VID Output Voltage Programming

VID4 VID3 VID2 VID1 VID0 V

000002.000V

000011.950V

000101.900V

000111.850V

001001.800V

001011.750V

001101.700V

001111.650V

010001.600V

010011.550V

010101.500V

010111.450V

011001.400V

011011.350V

011101.300V
01111 *

100001.275V

100011.250V

100101.225V

100111.200V

101001.175V

101011.150V

101101.125V

101111.100V

110001.075V

110011.050V

110101.025V

110111.000V

111000.975V

111010.950V

111100.925V
11111 **

Note: *, ** represents codes without a defined output voltage as specified in
Intel specifications. The LTC1736 interprets these codes as valid inputs and
produces output voltages as follows: [01111] = 1.250V, [11111] = 0.900V.

OUT

(V)

Topside MOSFET Driver Supply (CB, DB)

An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
Capacitor CB in the Functional Diagram is charged though
external diode DB from INTVCC when the SW pin is low.
Note that the voltage across CB is about a diode drop below
INTVCC. When the topside MOSFET is to be turned on, the
driver places the CB voltage across the gate-source of the
MOSFET. This enhances the MOSFET and turns on the
topside switch. The switch node voltage SW rises to V

IN

and the BOOST pin rises to VIN + INTVCC. The value of the
boost capacitor CB needs to be 100 times greater than the
total input capacitance of the topside MOSFET. In most
applications 0.1µF to 0.33µF is adequate. The reverse
breakdown on DB must be greater than V

IN(MAX) .

When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If you make a change
and the input current decreases, then you improve the
efficiency. If there is no change in input current, then there
is no change in efficiency.

SENSE+/SENSE– Pins

The common mode input range of the current comparator
is from 0V to 1.1(INTVCC). Continuous linear operation is
guaranteed throughout this range allowing output volt­ages anywhere from 0.8V to 7V (although the VID control
pins only program a 0.925V to 2.00V output range). A
differential NPN input stage is used and is biased with
internal resistors from an internal 2.4V source as shown
in the Functional Diagram. This causes current to flow out
of both sense pins to the main output. This forces a
minimum load current which is sunk by the internal
resistive divider resistors R1 and R2. The maximum
current flowing out of the sense pins is:

I

SENSE+

+ I

SENSE–

= (2.4V – V

OUT

)/24k

Remember to take this current into account if resistance is
placed in series with the sense pins for filtering.

16

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APPLICATIO S I FOR ATIO

Soft-Start/Run Function

The RUN/SS pin is a multipurpose pin that provides a soft­start function and a means to shut down the LTC1736.
Soft-start reduces surge currents from VIN by gradually
increasing the controller’s current limit I

TH(MAX)

can also be used for power supply sequencing.
Pulling the RUN/SS pin below 1.5V puts the LTC1736 into

a low quiescent current shutdown (IQ < 25µA). This pin can
be driven directly from logic as shown in Figure 3. Releas­ing the RUN/SS pin allows an internal 1.2µA current
source to charge up the external soft-start capacitor C
If RUN/SS has been pulled all the way to ground there is
a delay before starting of approximately:

V

15

t

DELAY SS SS

=

12

.

.

CsFC

=µ

125

./

A

µ

()

When the voltage on RUN/SS reaches 1.5V the LTC1736
begins operating with a current limit at approximately
25mV/R

. As the voltage on RUN/SS increases from

SENSE

1.5V to 3.0V, the internal current limit is increased from

25mV/R

SENSE

to 75mV/R

. The output current limit

SENSE

ramps up slowly, taking an additional 1.25s/µF to reach
full current. The output current thus ramps up slowly
reducing the starting surge current required from the input
power supply.

Diode D1 in Figure 3 reduces the start delay while allowing
CSS to charge up slowly for the soft-start function. This
diode and C

can be deleted if soft-start is not needed.

SS

The RUN/SS pin has an internal 6V zener clamp (See
Functional Diagram).

. This pin

SS.

Fault Conditions: Overcurrent Latchoff

The RUN/SS pin also provides the ability to shut off the
controller and latchoff when an overcurrent condition is
detected. The RUN/SS capacitor C

is used initially to

SS

turn on and limit the inrush current of the controller. After
the controller has been started and given adequate time to
charge up the output capacitor and provide full load
current, CSS is used as a short-circuit timer. If the output
voltage falls to less than 70% of its nominal output voltage

after CSS reaches 4.1V

, the assumption is made that the
output is in a severe overcurrent and/or short-circuit
condition and CSS begins discharging. If the condition
lasts for a long enough period as determined by the size of
CSS, the controller will be shut down until the RUN/SS pin
voltage is recycled.

This built-in latchoff can be overridden by providing a
current >5µA at a compliance of 5V to the RUN/SS pin as
shown in Figure 4. This current shortens the soft-start
period but also prevents net discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
condition. When deriving the 5µA current from VIN as in
Figure 4a, current latchoff is always defeated. A diode
connecting this pull-up resistor to INTVCC , as in Figure 4b,
eliminates any extra supply current during controller shut­down while eliminating the INTV

loading from prevent-

CC

ing controller start-up. If the voltage on CSS does not exceed

4.1V, the overcurrent latch is not armed and the function
is disabled.

INTV

CC

3.3V OR 5V RUN/SS

D1

(a) (b)

Figure 3. RUN/SS Pin Interfacing

R

V

RUN/SS

C

C

SS

SS

1736 F03

3.3V OR 5V RUN/SS

Figure 4. RUN/SS Pin Interfacing with Latchoff Defeated

IN

R

D1

SS

C

SS

(a) (b)

SS

RUN/SS

D1

C

SS

1736 F04

17

LTC1736

I

mV

R

I

SC

SENSE

LSC

=+

30 1

2

∆

()

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APPLICATIO S I FOR ATIO

Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off. Defeating this feature will easily allow trouble­shooting of the circuit and PC layout. The internal short­circuit and foldback current limiting still remains active,
thereby protecting the power supply system from failure.
After the design is complete, a decision can be made
whether to enable the latchoff feature.

The value of the soft-start capacitor CSS will need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci­tance is given by:

CSS > (C

The minimum recommended soft-start capacitor of C

0.1µF will be sufficient for most applications.

Fault Conditions: Current Limit and Current Foldback

The LTC1736 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET current
of 75mV/R

The LTC1736 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is defeated. If the output
falls by more than half, then the maximum sense voltage
is progressively lowered from 75mV to 30mV. Under
short-circuit conditions with very low duty cycle, the
LTC1736 will begin cycle skipping in order to limit the
short-circuit current. In this situation the bottom MOSFET
will be conducting the peak current. The short-circuit
ripple current is determined by the minimum on-time
t

ON(MIN)

voltage, and inductor value:

∆I

L(SC)

)(V

OUT

SENSE

of the LTC1736 (less than 200ns), the input

= t

ON(MIN) VIN

OUT

.

)(10–4)(R

/L.

SENSE

)

=

SS

The resulting short circuit current is:

The current foldback function is always active and is not
effected by the current latchoff function.

Fault Conditions: Output Overvoltage Protection
(Crowbar)

The output overvoltage crowbar is designed to blow a
system fuse in the input lead when the output of the
regulator rises much higher than nominal levels. This
condition causes huge currents to flow, much greater than
in normal operation. This feature is designed to protect
against a shorted top MOSFET; it does not protect against
a failure of the controller itself.

The comparator (OV in the Functional Diagram) detects
overvoltage faults greater than 7.5% above the nominal
output voltage. When this condition is sensed, the top
MOSFET is turned off and the bottom MOSFET is forced
on. The bottom MOSFET remains on continuously for as
long as the OV condition persists; if V
level, normal operation automatically resumes. Note that
VID controlled output voltage decreases may cause the
overvoltage protection to be momentarily activated. This
will not cause permanent latchoff nor will it disrupt the
desired voltage change.

With soft-latch overvoltage protection, dynamic VID code
changes are allowed and the overvoltage protection tracks
the new VID code, always protecting the load (CPU). If
dynamic VID code changes are anticipated and the mini­mum load current is light, it may be necessary to either
force continuous operation by pulling FCB low during the
transition to maximize current sinking capability or con­nect PGOOD to FCB to automatically force continuous
operation during VID transitions.

returns to a safe

OUT

18

LTC1736

VV

R
R

SEC MIN()

.≈+











08 1

4
3

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APPLICATIO S I FOR ATIO

Minimum On-Time Considerations

Minimum on-time t

ON(MIN)

that the LTC1736 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum on­time limit and care should be taken to ensure that:

V

OUT

t

ON MIN

<

()

()

Vf

IN

If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1736 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and voltage will increase.

The minimum on-time for the LTC1736 in a properly
configured application is generally less than 200ns. How­ever, as the peak sense voltage decreases, the minimum
on-time gradually increases as shown in Figure 5. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre­spondingly larger current and voltage ripple.

If an application can operate close to the minimum on­time limit, an inductor must be chosen that is low enough
in value to provide sufficient ripple amplitude to meet the
minimum on-time requirement.

250

is the smallest amount of time

As a general rule keep the

inductor ripple current equal or greater than 30% of
I

OUT(MAX)

at V

IN(MAX)

.

FCB Pin Operation

When the DC voltage on the FCB pin drops below its 0.8V
threshold, continuous mode operation is forced. In this
case, the top and bottom MOSFETs continue to be driven
synchronously regardless of the load on the main output.
Burst Mode operation is disabled and current reversal is
allowed in the inductor.

In addition to providing a logic input to force continuous
synchronous operation and external synchronization, the
FCB pin provides a means to regulate a flyback winding
output. During continuous mode, current flows continu­ously in the transformer primary. The secondary winding(s)
draw current only when the bottom synchronous switch is
on. When primary load currents are low and/or the
VIN/V

ratio is low, the synchronous switch may not be

OUT

on for a sufficient amount of time to transfer power from
the output capacitor to the secondary load. Forced con­tinuous operation will support secondary windings pro­vided there is sufficient synchronous switch duty factor.
Thus, the FCB input pin removes the requirement that
power must be drawn from the inductor primary in order
to extract power from the auxiliary windings. With the loop
in continuous mode, the auxiliary output may nominally be
loaded without regard to the primary output load.

The secondary output voltage V

is normally set as

SEC

shown in the Functional Diagram by the turns ratio N of the
transformer:

200

150

100

MINIMUM ON-TIME (ns)

50

0

0

Figure 5. Minimum On-Time vs ∆I

10

∆IL/I

20

OUT(MAX)

(%)

V

≅ (N + 1) V

SEC

OUT

However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V
V

SEC

30

1736 F05

40

If V
continuous switching operation until V

L

its minimum.

will droop. An external resistive divider from

SEC

to the FCB pin sets a minimum voltage V

drops below this level, the FCB voltage forces

SEC

SEC

SEC(MIN)

is again above

:

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In order to prevent erratic operation if no external connec­tions are made to the FCB pin, the FCB pin has a 0.17µA
internal current source pulling the pin high. Remember to
include this current when choosing resistor values R3 and
R4.

The internal LTC1736 oscillator can be synchronized to an
external oscillator by clocking the FCB pin with a signal
above 1.5V
quency, Burst Mode operation is disabled, but cycle skip­ping is allowed at low load currents since current reversal
is inhibited. The bottom gate will come on every 10 clock
cycles to assure the boostrap cap, CB, is kept refreshed.
The rising edge of an external clock applied to the FCB pin
starts a new cycle.

The range of synchronization is from 0.9fO to 1.3fO, with
fO set by C
frequency than 1.3fO can result in inadequate slope
comensation and cause loop instability with high duty
cycles. If loop instability is observed while synchronized,
additional slope compensation can be obtained by simply
decreasing C

The following table summarizes the possible states avail­able on the FCB pin:

Table 2

FCB Pin Condition

DC Voltage: 0V to 0.7V Burst Disabled/Forced Continuous

DC Voltage: >0.9V Burst Mode Operation, No Current Reversal
Feedback Resistors Regulating a Secondary Winding
Ext Clock: (0V to V

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% - (L1 + L2 + L3 + ...)

. When synchronized to an external fre-

P-P

. Attempting to synchronize to a higher

OSC

.

OSC

Current Reversal Enabled

) Burst Mode Operation Disabled

FCBSYNC

(V

≥ 1.5V) No Current Reversal

FCBSYNC

where L1, L2, etc., are the individual losses as a percent­age of input power.

Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1736 circuits: 1) LTC1736 VIN current, 2)
INTVCC current, 3) I2R losses, 4) Topside MOSFET transi­tion losses.

1. The VIN current is the DC supply current given in the

electrical characteristics which excludes MOSFET driver
and control currents. VIN current results in a small
(<0.1%) loss that increases with VIN.

2. INTVCC current is the sum of the MOSFET driver and

control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, I

GATECHG

=
f(QT + QB), where QT and QB are the gate charges of the
topside and bottom-side MOSFETs.

Supplying INTVCC power through the EXTVCC switch
input from an output-derived or other high efficiency
source will scale the VIN current required for the driver
and control circuits by a factor of (Duty Cycle)/(Effi­ciency). For example, in a 15V to 1.8V application, 10mA
of INTVCC current results in approximately 1.2mA of V

IN

current. This reduces the low current loss from 10% or
more (if the driver was powered directly from VIN) to only
a few percent.

3. I2R Losses are predicted from the DC resistances of the
MOSFETs, inductor and current shunt. In continuous
mode the average output current flows through L and
R

, but is “chopped” between the topside main

SENSE

MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same R

DS(ON)

, then
the resistance of one MOSFET can simply be summed
with the resistances of L and R
losses. For example, if each R

0.03Ω, and R

= 0.01Ω, then the total resistance is

SENSE

DS(ON)

to obtain I2R

SENSE

= 0.02Ω, RL =

20

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0.06Ω. This results in losses ranging from 3% to 17%
as the output current increases from 1A to 5A for a 1.8V
output, or 4% to 20% for a 1.5V output. Efficiency
varies as the inverse square of V
external components and power level. I2R losses cause
the efficiency to drop at high output currents.

4. Transition losses apply only to the topside MOSFET(s),
and only become significant when operating at high
input voltages (typically 12V or greater). Transition
losses can be estimated from:

Transition Loss = (1.7)(V

Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and fuse resis­tance losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switch­ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having a maxi-
mum of 0.01Ω to 0.02Ω of ESR. Other losses including
Schottky conduction losses during dead-time and induc­tor core losses generally account for less than 2% total
additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem. OPTI­LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior but also provides a

OUT

OUT

generating the feedback error signal that

OUT

to its steady-state value. During this recovery

can be monitored for excessive overshoot or

(ESR), where ESR is the effective

LOAD

. ∆I

OUT

2

)(I

IN

also begins to charge or

LOAD

for the same

OUT

)(C

O(MAX)

shifts by an

OUT

RSS

)(f)

DC coupled and AC filtered closed-loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed-loop response. Assuming a pre­dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.

The I
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full-load current having a rise time of 1µs
to 10µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step
may not be within the bandwidth of the feedback loop, so
the standard second-order overshoot/DC ratio cannot be
used determine phase margin. The gain of the loop will be
increased by increasing RC and the bandwidth of the loop
will be increased by decreasing CC. If RC is increased by the
same factor that CC is decreased, the zero frequency will
be kept the same, thereby keeping the phase the same in
the most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability of
the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Application Note 76.

Improve Transient Response and Reduce Output
Capacitance with Active Voltage Positioning

Fast load transient response, limited board space and low
cost are requirements of microprocessor power supplies.
Active voltage positioning improves transient response
and reduces the output capacitance required to power a
microprocessor where a typical load step can be from 0.2A

series RC-CC filter sets the dominant pole-zero

TH

TH

21

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APPLICATIO S I FOR ATIO

to 15A in 100ns or 15A to 0.2A in 100ns. The voltage at the
microprocessor must be held to about ±0.1V of nominal
in spite of these load current steps. Since the control loop
cannot respond this fast, the output capacitors must
supply the load current until the control loop can respond.
Capacitor ESR and ESL primarily determine the amount of
droop or overshoot in the output voltage. Normally, sev­eral capacitors in parallel are required to meet micropro­cessor transient requirements.

Active voltage positioning is a form of deregulation. It
sets the output voltage high for light loads and low for
heavy loads. When load current suddenly increases, the
output voltage starts from a level higher than nominal so
the output voltage can droop more and stay within the
specified voltage range. When load current suddenly
decreases the output voltage starts at a level lower than
nominal so the output voltage can have more overshoot
and stay within the specified voltage range. Less output

capacitance is required when voltage positioning is used
because more voltage variation is allowed on the output
capacitors.

Active voltage positioning can be implemented using the
OPTI-LOOP architecture of the LTC1736 with two external
resistors. An input voltage offset is introduced when the
error amplifier has to drive a resistive load. This offset is
limited to ±30mV at the input of the error amplifier. The
resulting change in output voltage is the product of input
offset and the feedback voltage divider ratio.

Figure 6 shows a CPU-core-voltage regulator with active
voltage positioning. Resistors R1 and R5 force the input
voltage offset that sets the output voltage according to the
load current level. To select values for R1 and R5, first
determine the amount of output deregulation allowed. The
actual specification for a typical microprocessor allows
the output to vary ±0.112V. The LTC1736 output voltage

R2

VID0
VID1
VID2
VID3
VID4

VID

INPUT

R1

27k

C1 39pF

100k

C4 100pF

POWER

GOOD

0.1µF

C2

100pF

C3

C5

C6
47pF

C7 330pF

1000pF

C10, C18: TAIYO YUDEN JMK107BJ105
C11: KEMET T494A475M010AS
C12 TO C14: TAIYO YUDEN GMK325F106
C15 TO C17: PANASONIC EEFUE0G181R
D1: CENTRAL SEMI CMDSH-3

1
2
3
4
5
6
7
8

9
10
11
12

R5 100k

C

OSC

RUN/SS
I

TH

FCB
SGND
PGOOD
SENSE
SENSE
V

FB

V

OSENSE

VID0
VID1

R4 100k

LTC1736

–

+

R3 680k

24

TG

23

BOOST

22

SW

21

V

IN

20

INTV

CC

19

BG

18

PGND

17

EXTV

CC

16

VIDV

CC

15

VID4

14

VID3

13

VID2

D2: MOTOROLA MBRS340
L1: PANASONIC ETQP6F1R0SA
M1 TO M3: FAIRCHILD FDS6680A
R6: IRC LRF2512-01-R003-J
U1: LINEAR TECHNOLOGY LTC1736CG

C9

D1
CMDSH-3

5V (OPTIONAL)

C8

0.1µF

0.22µF

+

C10
1µF

C11

4.7µF
10V

M1
FDS6680A

M2, M3
FDS6680A
×2

L1

1µH

D2
MBRS340

R6

0.003Ω

+

1736 F06

C12 TO C14
10µF
35V

C15 TO C17
180µF/4V
×4

C18
1µF

V

IN

7.5V TO 24V

GND

V

OUT

0.9V TO 2V
15A

GND

22

Figure 6. CPU-Core-Voltage Regulator with Active Voltage Positioning

LTC1736

U

WUU

APPLICATIO S I FOR ATIO

accuracy is ±1%, so the output transient voltage cannot
exceed ±0.097V. At V
voltage change controlled by the ITH pin would be:

∆=

V

OSENSE

Input Offset V

003 15

±

=

With optimum resistor values at the ITH pin, the output
voltage will swing from 1.55V at minimum load to 1.44V
at full load. At this output voltage, active voltage position­ing provides an additional 56mV to the allowable transient
voltage on the output capacitors, a 58% improvement
over the 97mV allowed without active voltage positioning.

The next step is to calculate the ITH pin voltage, V
factor. The V

scale factor reflects the ITH pin voltage

ITH

required for a given load current. V
sense resistor voltage, which represents the DC output
current plus one half of the peak-to-peak inductor current.
The no load to full load V
which controls the sense resistor voltage from 0V to the
∆V

SENSE(MAX)

voltage of 75mV. The calculated V

factor with a 0.003Ω sense resistor is:

V Scale Factor

ITH

=

==

V

at any load current is:

ITH

= 1.5V, the maximum output

OUT

•

OUT

V

REF

.•.

V

.

08

V

ITH

V Range Sense sistor Value

ITH

(. – . )• .

24 03 0003

VV

56

=±

mV

, scale

ITH

controls the peak

ITH

range is from 0.3V to 2.4V,

scale

ITH

•Re

∆

.

0 075

V

()

SENSE MAX

V

./

0 084

VA

At minimum load current:



VAAVA V

ITH MIN

In this circuit, V

=+

02

=











040

.

ITH

()



2

.•./.

V

changes from 0.40V at light load to

−

PP

2



0 084 0 3







+






1.77V at full load, a 1.37V change. Notice that ∆IL, the
peak-to-peak inductor current, changes from light load to
full load. Increasing the DC inductor current decreases the
permeability of the inductor core material, which de­creases the inductance and increases ∆IL. The amount of
inductance change is a function of the inductor design.

To create the 30mV input offset, the gain of the error
amplifier must be limited. The desired gain is:

A

=

V

V

∆

ITH

Input Offset

==

V

137

.

2003

(. )

22 8

.

V

Connecting a resistor to the output of the transconductance
error amplifier will limit the voltage gain. The value of this
resistor is:

A

R

===

ITH

Error Amplifier g ms

V

To center the output voltage variation, V

22 8

.

13

.

m

17 54

.

ITH

k

must be
centered so that no ITH pin current flows when the output
voltage is nominal. V
tween V

at maximum output current and minimum

ITH

ITH(NOM)

is the average voltage be-

output current:



VI



=+



ITH OUT DC

()









+

V Offset

ITH



I

∆

L

V Scale Factor

•

ITH



2



At full load current:



VAAVA V

ITH MAX

=+

=











.

177

()

15



5

V



−

PP

•. / .

0 084 0 3



2









VV







V

ITH NOM

ITH MAX ITH MIN

=+

.–.

177 040

=+=

–

() ()

2

VV

VV

..

0 40 1 085

V

ITH MIN()

()

2

The Thevenin equivalent of the gain limiting resistance
value of 17.54k is made up of a resistor R5 that sources
current into the ITH pin and resistor R1 that sinks current

+

to SGND.

23

LTC1736

U

WUU

APPLICATIO S I FOR ATIO

To calculate the resistor values, first determine the ratio
between them:

VV

INTVCC ITH NOM

k

===

V

INTVCC

is equal to V

Resistor R5 is:

Rk R k k

4 1 3 79 1 17 54 84 0=+ = + =()• (. )•. .

Resistor R1 is:

()• (. )•.

R

1

Unfortunately, PCB noise can add to the voltage developed
across the sense resistor, R6, causing the ITH pin voltage
to be slightly higher than calculated for a given output
current. The amount of noise is proportional to the output
current level. This PCB noise does not present a serious
problem but it does change the effective value of R6 so the
calculated values of R1 and R5 may need to be adjusted to
achieve the required results. Since PCB noise is a function
of the layout, it will be the same on all boards with the same
layout.

Figures 7 and 8 show the transient response before and
after active voltage positioning is implemented. Notice
that the output voltage droop and overshoot levels don’t
change but the peak-to-peak output voltage reduces con­siderably with active voltage positioning.

–

()

V

ITH NOM

()

EXTVCC

ITH

kR

1 3 79 1 17 54

+

ITH

=

k

.–.

52 1085

or 5.2V if EXTVCC is not used.

+

379

VV

V

.

1 085

k

379

22 17=

=

.

.

.

k

VIN = 12V

= 1.5V

V

1.5V

15A

0A

OUT

OUTPUT

VOLTAGE

LOAD

CURRENT

50µs/DIV

1.582V

100mV/DIV

1.418V

10A/DIV

Figure 8. Transient Response with Active Voltage Positioning

FIGURE 6 CIRCUIT

1736 F08

Automotive Considerations:
Plugging into the Cigarette Lighter

As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main power line in an automobile
is the source of a number of nasty potential transients,
including load dump, reverse battery, and double battery.

Load dump is the result of a loose power cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.

Refer to Design Solutions 10 for more information about
active voltage positioning.

VIN = 12V
V

OUT

1.5V

100mV/DIV

15A

10A/DIV

0A

Figure 7. Normal Transient Response (Without R1, R5)

= 1.5V

OUTPUT

VOLTAGE

LOAD

CURRENT

50µs/DIV

FIGURE 6 CIRCUIT

1736 F07

24

The network shown in Figure 9 is the most straight forward
approach to protect a DC/DC converter from the ravages
of an automotive power line. The series diode prevents
current from flowing during reverse battery, while the
transient suppressor clamps the input voltage during load
dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the LTC1736 has a maximum input voltage of
36V, most applications will be limited to 30V by the
MOSFET BV

DSS

.

LTC1736

P

V

V

CC

V A pF kHz

mW

MAIN

=

()

+°°

[]

Ω

()

+

()()( )( )

=

16

22

12 1 0 005 50 25 0 03

1 7 22 12 80 275

571

2

2

.

( . )( – ) .

.

U

WUU

APPLICATIO S I FOR ATIO

50A IPK RATING

V

SENSE

IN

LTC1736

= 12V(nominal), V

IN

and C

can immediately

OSC

1736 F09

12V

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

Figure 9. Plugging into the Cigarette Lighter

1.5KA24A

Design Example

As a design example, assume V
22V(max), V

= 1.6V(nominal), 1.8V to 1.3V range, I

OUT

= 12A and f = 275kHz. R
be calculated:

R
C

= 50mV/12A = 0.0042Ω

SENSE

= 1.61(107)/(275kHz) – 11pF = 47pF

OSC

IN

MAX

in: R

DS(ON)

= 0.03Ω, C

= 80pF. At maximum input

RSS

voltage with T(estimated) = 50°C:

Because the duty cycle of the bottom MOSFET is much
greater than the top, two larger MOSFETs must be paral­leled. Choosing Fairchild FDS6680A MOSFETs yields a

=

parallel R

of 0.0065Ω. The total power dissipaton

DS(ON)

for both bottom MOSFETs, again assuming T = 50°C, is:

P

SYNC

–.

22 1 6

VV

=

22

=

955

mW

V

2

A

..

()

12 1 1 0 0065

()()

Ω

Assume a 1.2µH inductor and check the actual value of the
ripple current. The following equation is used :

∆I

V

OUT OUT

=

L

()()

fL



–1







V



V



IN

The highest value of the ripple current occurs at the
maximum input and output voltages:

∆I

L

=

kHz H

275 1 2

V

18

.

(. )



1

–



µ



18

.

22



V

V

A

=

5





The maximum ripple current is 42% of maximum output
current, which is about right.

Next, verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum VIN and mini­mum V

t

ON MIN

.

OUT

=

()

V

OUT

Vf

IN MAX

()

==

22 275

()

V

13

.

V kHz

()

215

ns

The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Fairchild FDS6612A results

Thanks to current foldback, the bottom MOSFET dissipaton
in short circuit will be less than under full-load conditions.

CIN is chosen for an RMS current rating of at least 6A at
temperature. C

is chosen with an ESR of 0.01Ω for low

OUT

output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:

V

ORIPPLE

= R

(∆IL) = 0.01Ω(5A) = 50mV

ESR

P-P

PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1736. These items are also illustrated graphically in
the layout diagram of Figure 10. Check the following in
your layout:

1. Are the signal and power grounds segregated? The

LTC1736 PGND pin should tie to the GND plane close to
the input capacitor. The SGND pin should then connect
to PGND and all components that connect to SGND
should make a single point tie to the SGND pin. The low
side FET source pins should connect directly to the
input capacitor ground.

25

LTC1736

U

WUU

APPLICATIO S I FOR ATIO

2. Does the V

OSENSE

the load? The optional 50pF to 100pF capacitor from
VFB to SGND should be as close as possible to the
LTC1736.

3. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor be­tween SENSE+ and SENSE– should be as close as
possible to the LTC1736. Ensure accurate current sens­ing with kelvin connections as shown in Figure 11.
Series resistance can be added to the SENSE lines to
increase noise rejection.

4. Does the (+) terminal of CIN connect to the drain of the
topside MOSFET(s) as closely as possible? This capaci­tor provides the AC current to the MOSFET(s).

pin connect as close as possible to

C

OSC

1

C

10
11
12

2
3
4
5
6
7
8
9

OSC

RUN/SS
I

TH

FCB
SGND
PGOOD
SENSE
SENSE
V

FB

V

OSENSE

VID0
VID1

LTC1736

–

+

C

SS

R

C

C

C1

C

C2

47pF

1000pF

BOOST

INTV

PGND
EXTV
VIDV

VID4
VID3
VID2

SW

V

TG

IN

CC

BG

CC

CC

5. Is the INTVCC decoupling capacitor connected closely
between INTVCC and the power ground pin? This ca­pacitor carries the MOSFET driver peak currents. An
additional 1µF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve
noise performance.

6. Keep the switching node (SW), Top Gate node (TG) and
Boost node (BOOST) away from sensitive small-signal
nodes, especially from the voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on the
“output side” (Pins 13 to 24) of the LTC1736 and
occupy minimum PC trace area.

+

24
23
22
21
20
19
18
17
16
15
14
13

D

B

+

4.7µF

EXTERNAL EXTV
CONNECTION

C

OUT

+

M1

C

B

C

IN

+

V

D1

M2

IN

–

CC

L1

–

V

R

SENSE

OUT

+

1736 F10

26

Figure 10. LTC1736 Layout Diagram

HIGH CURRENT PATH

CURRENT SENSE
RESISTOR
(R

SENSE+SENSE

–

Figure 11. Kelvin Sensing R

SENSE

SENSE

1736 F11

)

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

G Package

24-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

8.07 – 8.33*

(0.318 – 0.328)

2122 18 17 16 15 14

19202324

13

LTC1736

7.65 – 7.90

(0.301 – 0.311)

5.20 – 5.38**
(0.205 – 0.212)

° – 8°

0

0.13 – 0.22

(0.005 – 0.009)

NOTE: DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

*

SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

**

FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

0.55 – 0.95

(0.022 – 0.037)

12345678 9 10 11 12

0.65

(0.0256)

BSC

0.25 – 0.38

(0.010 – 0.015)

1.73 – 1.99

(0.068 – 0.078)

0.05 – 0.21

(0.002 – 0.008)

G24 SSOP 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC1736

TYPICAL APPLICATIO

12A Converter with FCB Tied to PGOOD for CPU Power; Optimized for Output Voltages of 1.3V to 1.6V

C

OSC

47pF

C

01.µF

SS

R

33k

C

C

47pF

C2

INTV

CC

47pF

C

OUT

C

IN

L1: PANASONIC ETQP6RZ1RZ0HFA

PGOOD

1

C

OSC

2

C

330pF

C1

100k

1000pF

: 4-180µF/4V PANASONIC EEFUEOG181R (AS SHOWN)

3-470µF/6.3V KEMIT T51CX447M006AS (ALTERNATE)
1-820µF/4V SANYO 4SP820M + 1-180µF/4V PANASONIC EEFUE0G181R (ALTERNATE)

: SANYO OS-CON 305C22M

3
4
5
6
7
8

9
10
11
12

RUN/SS
I

TH

FCB
SGND
PGOOD
SENSE
SENSE
V

FB

V

OSENSE

VID0
VID1

U

LTC1736

–

+

10Ω
10Ω

BOOST

INTV

PGND

EXTV

VIDV

VID4
VID3
VID2

TG

SW

V

BG

V

IN

24
23

0.22µF

D

B

CMDSH-3

+

4.7µF

OPTIONAL:
CONNECT
TO 5V

B

22
21

IN

20

CC

19
18
17

CC

16

CC

15
14

OUTPUT VOLTAGE

13

PROGRAMMING

1µF

M1
FDS6680A

L1

1.2µH

M2
FDS6680A
×2

+

D1
MBRS340T3

C

IN

22µF/30V
×2
OS-CONC

4.75V TO 24V

R

SENSE

0.004Ω

+

SGND

1736 TA02

V

1.35V TO 1.6V
12A

C

OUT

180µF/4V
×4

OUT

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Linear Technology Corporation

28

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

TM

Current Mode Synchronous Step-Down Controllers Up to 97% Efficiency, Burst Mode Operation,

SENSE

are trademarks of Linear Technology Corporaton.

●

www.linear-tech.com

16-Pin SSOP

SENSE

1736f LT/TP 1299 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1999