Datasheet LTC1735-1 Datasheet (Linear Technology)

FEATURES

LTC1735-1

High Efficiency

Synchronous Step-Down

Switching Regulator

U

DESCRIPTIO

■

Dual N-Channel MOSFET Synchronous Drive

■

Programmable/Synchronizable Fixed Frequency

■

V

Range: 0.8V to 7V

OUT

■

Wide VIN Range: 3.5V to 36V Operation

■

Very Low Dropout Operation: 99% Duty Cycle

■

OPTI-LOOPTM Compensation Minimizes C

■

±

1% Output Voltage Accuracy

■

Power Good Output Voltage Monitor

■

Internal Current Foldback

■

Output Overvoltage Crowbar Protection

■

Latched Short-Circuit Shutdown Timer

OUT

with Defeat Option

■

Optional Programmable Soft-Start

■

Remote Output Voltage Sense

■

Logic Controlled Micropower Shutdown: IQ < 25µA

■

Available in 16-Lead Narrow SSOP and SO Packages

U

APPLICATIO S

■

Notebook and Palmtop Computers, PDAs

■

Power Supply for Mobile Pentium® III Processor with
SpeedStepTM Technology

■

Cellular Telephones and Wireless Modems

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation. SpeedStep is a trademark of Intel
Corporation.

The LTC®1735-1 is a synchronous step-down switching
regulator controller optimized for CPU power. OPTI-LOOP
compensation allows the transient response to be opti­mized over a wide range of output capacitance and ESR
values.

The operating frequency (synchronizable up to 500kHz) is
set by an external capacitor allowing maximum flexibility
in optimizing efficiency. The output voltage is monitored
by a power good window comparator that indicates when
the output is within 7.5% of its programmed value, con­forming to Intel Mobile CPU Specifications.

Protection features include internal foldback current lim­iting, output overvoltage crowbar and optional short­circuit shutdown. Soft-start is provided by an external
capacitor that can be used to properly sequence supplies.
The operating current level is user-programmable via an
external current sense resistor. Wide input supply range
allows operation from 3.5V to 30V (36V maximum).

Pin defeatable Burst ModeTM operation provides high
efficiency at low load currents while 99% duty cycle
provides low dropout operation.

TYPICAL APPLICATIO

C

47pF

OSC

C

SS

C

47pF

C2

330pF

R

C

C1

Figure 1. CPU Core DC/DC Converter with Dynamic Voltage Selection from SpeedStep Enabled Processors

0.1µF

C1

47pF

33k

1000pF

1
2
3
4
5
6
7
8

C
RUN/SS
I

TH

PGOOD
SENSE
SENSE
V
SGND

OSC

OSENSE

U

LTC1735-1

–

+

10Ω
10Ω

BOOST

INTV

PGND

EXTV

SW
V

V

IN

4.5V TO 24VPGOOD

16

TG

15
14
13

IN

12

CC

11

BG

10
9

5V

CC

(OPTIONAL)

+

0.22µF

C

B

D1
CMDSH-3

4.7µF

Q1
FDS6680A

L1

1.2µH

MBRS340T3

Q2, Q3
FDS6680A
×2

D2

C

IN

22µF
50V
CERAMIC
×2

R

SENSE

0.004Ω

: MARCON THCR70E1H226ZT

C

IN

: PANASONIC EEFUE06181R

C

OUT

L1: PANASONIC ETQP6RZ1R20HFA

: IRC CRF2010-01-R004J

R

SENSE

R1
10k

47pF

0.5%

+

R3

33.2k

47pF

1%

Q4

R2

14.3k

0.5%

2N7002

1735-1 F01

V

OUT

1.35V TO 1.60V
12A

C

OUT

180µF
4V
PANASONIC SP
×4

V

= 1: V

SEL

OUT

= 0: V

V

SEL

OUT

GND

= 1.60V
= 1.35V

1

LTC1735-1

WW

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

Input Supply Voltage (VIN)........................ 36V to –0.3V

Topside Driver Supply Voltage (BOOST)... 42V to –0.3V

Switch Voltage (SW) ................................... 36V to –5V

INTVCC, EXTVCC (BOOST, SW) Voltages..... 7V to –0.3V

SENSE+, SENSE–,

PGOOD Voltages................ 1.1(INTV

ITH, V

OSENSE

, C

Voltages .....................2.7V to –0.3V

OSC

RUN/SS Voltage ....................(INTVCC + 0.3V) to –0.3V

Peak Driver Output Current <10µs (TG, BG) .............. 3A

INTVCC Output Current ......................................... 50mA

Operating Ambient Temperature Range

LTC1735C-1 ............................................ 0°C to 85°C

LTC1735I-1 ........................................ –40°C to 85°C

Junction Temperature (Note 2)............................. 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

+ 0.3V) to –0.3V

CC

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

1

C

OSC

2

RUN/SS

3

I

TH

4

PGOOD

–

5

SENSE

+

6

SENSE

7

V

OSENSE

8

SGND

GN PACKAGE

16-LEAD PLASTIC SSOP

T

= 125°C, θJA = 130°C/W (GN)

JMAX

T

= 125°C, θJA = 110°C/W (S)

JMAX

Consult factory for Military grade parts.

16

TG

15

BOOST

14

SW

13

V

IN

12

INTV

CC

11

BG

10

PGND

9

EXTV

CC

S PACKAGE

16-LEAD PLASTIC SO

ORDER PART

NUMBER

LTC1735CGN-1
LTC1735CS-1
LTC1735IGN-1
LTC1735IS-1

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop

I

VOSENSE

V

OSENSE

∆V

LINEREG

∆V

LOADREG

DF Max Maximum Duty Factor In Dropout 98 99.4 %
g

m

V

OVL

I

Q

V

RUN/SS

I

RUN/SS

I

SCL

UVLO Undervoltage Lockout Measured at VIN Pin (Ramping Negative) ● 3.5 3.9 V
∆V

SENSE(MAX)

I

SENSE

t

ON(MIN)

Feedback Current (Note 3) –4 –25 nA
Feedback Voltage (Note 3) ● 0.792 0.8 0.808 V
Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 3) 0.001 0.02 %/V
Output Voltage Load Regulation (Note 3)

Transconductance Amplifier g
Feedback Overvoltage Lockout ● 0.84 0.86 0.88 V
Input DC Supply Current (Note 5)

Normal Mode 3.6V < V

Shutdown V
Run Pin Start Threshold V
Run Pin Begin Latchoff Threshold V
Soft-Start Charge Current V
RUN/SS Discharge Current Soft Short Condition, V

Maximum Current Sense Threshold V
SENSE Pins Total Source Current V
Minimum On-Time Tested with a Square Wave (Note 4) 160 200 ns

m

The ● denotes specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

Measured in Servo Loop; V
Measured in Servo Loop; V

< 30V 450 µA

IN

= 0V 15 25 µA

RUN/SS

, Ramping Positive 1.0 1.5 1.9 V

RUN/SS

, Ramping Positive 4.1 4.5 V

RUN/SS

= 0V –0.7 –1.2 µA

RUN/SS

= 4.5V

V

RUN/SS

= 0.7V ● 60 75 85 mV

OSENSE

SENSE

–

= V

+

= 0V 60 80 µA

SENSE

= 0.7V ● 0.1 0.3 %

ITH

= 2V ● –0.1 –0.3 %

ITH

1.3 mmho

= 0.5V, 0.5 2 4 µA

OSENSE

2

LTC1735-1

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

TG Transition Time: (Note 7)

TG t
TG t

r
f

Rise Time C
Fall Time C

= 3300pF 50 90 ns

LOAD

= 3300pF 50 90 ns

LOAD

BG Transition Time: (Note 7)

BG t
BG t

r
f

Rise Time C
Fall Time C

TG/BG T1D Top Gate Off to Synchronous C

= 3300pF 50 90 ns

LOAD

= 3300pF 40 80 ns

LOAD

= 3300pF Each Driver 100 ns

LOAD

Gate-On Delay Time

TG/BG T2D Synchronous Gate Off to Top C

= 3300pF Each Driver 70 ns

LOAD

Gate-On Delay Time

Internal VCC Regulator

V

INTVCC

V

LDO(INT)

V

LDO(EXT)

V

EXTVCC

V

EXTVCC(HYS)

Internal VCC Voltage 6V < VIN < 30V, V
INTVCC Load Regulation ICC = 0mA to 20mA, V
EXTVCC Drop Voltage ICC = 20mA, V

EXTVCC

= 4V 5.0 5.2 5.4 V

EXTVCC

= 4V 0.2 1 %

EXTVCC

= 5V 130 200 mV
EXTVCC Switchover Voltage ICC = 20mA, EXTVCC Ramping Positive ● 4.5 4.7 V
EXTVCC Hysteresis 0.2 V

Oscillator

f

OSC

fH/f

OSC

Oscillator Frequency (Note 6), C

= 43pF 265 300 335 kHz

OSC

Maximum Sync Frequency Ratio 1.3

PGOOD Pin

V

PG(SYNC)

V

PG(FC)

V

PGL

I

PGOOD

V

PG

Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.

Note 2: T
dissipation P

LTC1735CS-1, LTC1735IS-1: TJ = TA + (PD • 110 °C/W)
LTC1735CGN-1, LTC1735IGN-1: T

Note 3: The LTC1735-1 is tested in a feedback loop that servos V
to the balance point for the error amplifier (V

Note 4: The minimum on-time condition corresponds to an inductor
peak-to-peak ripple current >40% of I

PGOOD Threshold for Sync Ramping Negative 0.9 1.2 V
PGOOD Threshold for Force Cont. 0.76 0.8 0.84 V
PGOOD Voltage Low I
PGOOD Pull-Up Current V
PGOOD Trip Level V

= 2mA 110 200 mV

PGOOD

= 0.85V –0.17 µA

PGOOD

With Respect to Set Output Voltage

OSENSE

V
V

Ramping Negative –6.0 –7.5 –9.5 %

OSENSE

Ramping Positive 6.0 7.5 9.5 %

OSENSE

Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.

is calculated from the ambient temperature TA and power

J

according to the following formulas:

D

= TA + (PD • 130°C/W)

J

= 1.2V).

ITH

OSENSE

Note 6: Oscillator frequency is tested by measuring the C
current (I

) and applying the formula:

OSC



.()

f kHz

()

OSC

8 477 10

=



CpF I I



OSC CHG DIS

()

–

8





11





+

11





1



+





Note 7: Rise and fall times are measured using 10% to 90% levels.
Delay times are measured using 50% levels.

(see Minimum On-Time

MAX

OSC

charge

Considerations in the Applications Information section).

3

LTC1735-1

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Load Current
(3 Operating Modes)

100

EXTVCC OPEN

90

BURST

80

70

60

50

EFFICIENCY (%)

40

30

20

0.001

0.01

SYNC

CONT

0.1

LOAD CURRENT (A)

VIN = 10V
V

= 3.3V

OUT

= 0.01Ω

R

S

f

= 300kHz

O

1

1735-1 G01

10

Efficiency vs Load Current

100

EXTVCC = 5V

= 1.6V

V

OUT

90

VIN = 5V

80

70

EFFICIENCY (%)

60

50

40

10mA 100mA 1A 10A

VIN = 24V

LOAD CURRENT (A)

VIN = 15V

1735-1 G02

Efficiency vs Input Voltage

100

EXTVCC = 5V

= 1.6V

V

OUT

95

FIGURE 1

90

85

EFFICIENCY (%)

80

75

70

0

10 15 20

5

INPUT VOLTAGE (V)

I

OUT

I

= 0.5A

= 5A

OUT

25 30

1735-1 G03

100

EXTVCC OPEN

= 1.6V

V

OUT

95

FIGURE 1

90

85

I

EFFICIENCY (%)

80

75

70

0

5

OUT

10 15 20

INPUT VOLTAGE (V)

Input and Shutdown Currents
vs Input Voltage

500

EXTVCC OPEN

400

300

200

INPUT CURRENT (µA)

100

0

05

SHUTDOWN

EXTVCC = 5V

20

15

10

INPUT VOLTAGE (V)

= 0.5A

25

I

OUT

= 5A

25 30

1735-1 G04

30

1735-1 G07

VIN – V

Dropout Voltage

OUT

vs Load CurrentLoad RegulationEfficiency vs Input Voltage

0

–0.1

(%)

OUT

–0.2

NORMALIZED V

–0.3

–0.4

0

2

4

LOAD CURRENT (A)

FCB = 0V

= 15V

V

IN

FIGURE 1

6

8

10

1735-1 G05

500

400

300

(mV)

OUT

– V

200

IN

V

100

R

SENSE

V

OUT

0

0

= 0.005Ω

= 5V – 5% DROP

2468

LOAD CURRENT (A)

10

1735-1 G06

EXTVCC Switch Drop

INTVCC Line Regulation

100

SHUTDOWN CURRENT (µA)

80

60

40

20

0

35

6

1mA LOAD

5

4

3

VOLTAGE (V)

CC

2

INTV

1

0

0

510

INPUT VOLTAGE (V)

20 30 35

15 25

1735-1 G08

vs INTVCC Load Current

500

400

(mV)

300

CC

– INTV

200

CC

EXTV

100

0

10

0

INTVCC LOAD CURRENT (mA)

30

40

20

50

1735-1 G09

4

UW

V

RUN/SS

(V)

0

0

V

ITH

(V)

0.5

1.0

1.5

2.0

2.5

1

234

1735-1 G15

56

V

OSENSE

= 0.7V

TYPICAL PERFOR A CE CHARACTERISTICS

Maximum Current Sense Threshold
vs Normalized Output Voltage
(Foldback)

80

70

60

50

40

30

20

10

MAXIMUM CURRENT SENSE THRESHOLD (mV)

0

0

25

NORMALIZED OUTPUT VOLTAGE (%)

50

75

100

1735-1 G10

Maximum Current Sense Threshold
vs V

RUN/SS

80

V

60

40

20

MAXIMUM CURRENT SENSE THRESHOLD (mV)

0

0

= 1.6V

SENSE(CM)

1234

V

(V)

RUN/SS

56

1735-1 G11

LTC1735-1

Maximum Current Sense Threshold
vs Sense Common Mode Voltage

80

76

72

68

64

MAXIMUM CURRENT SENSE THRESHOLD (mV)

60

1

0

2

COMMON MODE VOLTAGE (V)

3

4

5

1735-1 G12

Maximum Current Sense Voltage
vs ITH Voltage

90
80
70
60
50
40

30
20
10

0
–10
–20

MAXIMUM CURRENT SENSE VOLTAGE (V)

–30

0.5

0

1

V

ITH

SENSE Pins Total Source Current

100

50

(µA)

0

SENSE

I

–50

–100

0

24

V

COMMON MODE VOLTAGE (V)

SENSE

(V)

1.5

2

1735-1 G13

1735-1 G16

2.5

Maximum Current Sense Threshold
vs Temperature

80

V

75

70

65

MAXIMUM CURRENT SENSE THRESHOLD (mV)

60

–40

= 1.6V

SENSE(CM)

–15 10 35 60

TEMPERATURE (°C)

85 110 135

1735-1 G18

ITH Voltage vs Load Current

2.5
VIN = 10V

= 3.3V

V

OUT

= 0.01Ω

R

SENSE

2.0

= 300kHz

f

O

CONTINUOUS

1.5

VOLTAGE (V)

1.0

TH

I

0.5

6

0

MODE

SYNCHRONIZED f = f

Burst Mode
OPERATION

0

234

1

LOAD CURRENT (A)

O

56

1735-1 G17

V

vs V

ITH

RUN/SS

Output Current vs Duty Cycle

100

(%)

MAX

80

/I

OUT

60

40

20

f

SYNC

AVERAGE OUTPUT CURRENT I

0

0

I

OUT/IMAX

(SYNCHRONIZED)

= f

O

40 60 80

20

DUTY CYCLE (%)

(FREE RUN)

I

OUT/IMAX

100

1735-1 G14

5

LTC1735-1

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Oscillator Frequency
vs Temperature

300

C

= 47pF

OSC

290

280

270

FREQUENCY (kHz)

260

250

–40 –15

10

TEMPERATURE (°C)

Start-Up

V

OUT

1V/DIV

V

RUN/SS

5V/DIV

RUN/SS Pin Current
vs Temperature

0

V

= 0V

RUN/SS

–1

–2

–3

RUN/SS CURRENT (µA)

–4

60

35

85

110

1735-1 G19

135

–5

V

OUT

10mV/DIV

–40 –15

V

10

TEMPERATURE (°C)

OUT(RIPPLE)

I

= 10mA I

LOAD

60

35

85

(Synchronized)

110

1735-1 G20

FIGURE 1

135

PGOOD Pin Current
vs Temperature

0

V

PGOOD

–0.2

–0.4

–0.6

PGOOD PIN CURRENT (µA)

–0.8

–1.0

–40 –15

V

OUT(RIPPLE)

(Burst Mode Operation)

LOAD

V

OUT

20mV/DIV

= 0.85V

35

10

TEMPERATURE (°C)

= 50mA

60

85

110

1735-1 G21

FIGURE 1

135

5A/DIV

V

OUT

20mV/DIV

5A/DIV

I

L

V

= 15V 5ms/DIV 1735-1 G22

IN

V

= 1.6V

OUT

R

= 0.16Ω

LOAD

V

OUT(RIPPLE)

(Burst Mode Operation)

I

= 1.5A

LOAD

I

L

= 15V 5µs/DIV 1735-1 G25

V

IN

V

= 1.6V

OUT

I

L

5A/DIV

= 15V 50µs/DIV 1735-1 G24

V

IN

V

= 1.6V

OUT

5A/DIV

I

L

EXT SYNC f = f
VIN = 15V
V

= 1.6V

OUT

10µs/DIV 1735-1 G23

O

Load Step
(Burst Mode Operation)

FIGURE 1 FIGURE 1 FIGURE 1

V

OUT

50mV/DIV

5A/DIV

I

L

10mA TO 10µs/DIV
11A LOAD STEP
V

= 15V

IN

= 1.6V

V

OUT

1735-1 G26

50mV/DIV

Load Step (Continuous Mode)

V

OUT

I

L

5A/DIV

0A TO 10µs/DIV
11A LOAD STEP
PGOOD = 0V

= 15V

V

IN

V

= 1.6V

OUT

1735-1 G27

6

UUU

PI FU CTIO S

C

(Pin 1): External capacitor C

OSC

ground sets the operating frequency.
RUN/SS (Pin 2): Combination of Soft-Start and Run

Control Inputs. A capacitor to ground at this pin sets the
ramp time to full current output. The time is approximately

1.25s/µF. Forcing this pin below 1.5V causes the device to
be shut down. In shutdown all functions are disabled.
Latchoff overcurrent protection is also invoked via this pin
as described in the Applications Information section.

ITH (Pin 3): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 2.4V.

PGOOD (Pin 4): Open-Drain Logic Output and Forced
Continuous/Synchronization Input. The PGOOD pin is
pulled to ground when the voltage on the V
not within ±7.5% of its nominal set point. If power good
indication is not needed, this pin can be tied to ground to
force continuous synchronous operation. Clocking this
pin with a signal above 1.5V
oscillator to the external clock. Synchronization only
occurs while the main output is in regulation (PGOOD not
internally pulled low). When synchronized, Burst Mode
operation is disabled but cycle skipping is allowed at low
load currents. This pin requires a pull-up resistor for
power good indication. Do not connect this pin directly to
an external source (or INTVCC). Do not exceed INTVCC on
this pin.

SENSE– (Pin 5): The (–) Input to the Current Comparator.
SENSE+ (Pin 6): The (+) Input to the Current Comparator.

Built-in offsets between SENSE+ and SENSE– pins in
conjunction with R
threshold.

V

OSENSE

external resistive divider across the output.

(Pin 7): Receives the feedback voltage from an

SENSE

synchronizes the internal

P-P

set the inductor current trip

from this pin to

OSC

OSENSE

pin is

LTC1735-1

SGND (Pin 8): Small-Signal Ground. All small-signal
components such as C
the loop compensation resistors and capacitor(s) should
single-point tie to this pin. This pin should, in turn, connect
to PGND.

EXTVCC (Pin 9): Input to the Internal Switch Connected to
INTVCC. This switch closes and supplies VCC power when­ever EXTVCC is higher than 4.7V. See EXTVCC connection
in Applications Information section. Do not exceed 7V on
this pin and ensure EXTVCC is ≤ VIN.

PGND (Pin 10): Driver Power Ground. This pin connects
to the source of the bottom N-channel MOSFET, the anode
of the Schottky diode and the (–) terminal of CIN.

BG (Pin 11): High Current Gate Drive for the Bottom
N-Channel MOSFET. Voltage swing at this pin is from
ground to INTV

INTVCC (Pin 12): Output of the Internal 5.2V Low Dropout
Regulator and EXTVCC Switch. The driver and control
circuits are powered from this voltage. Decouple to power
ground with a 1µF ceramic capacitor placed directly adja-
cent to the IC together with a minimum of 4.7µF tantalum
or other low ESR capacitor.

V

(Pin 13): Main Supply Pin. This pin must be closely

IN

decoupled to power ground.
SW (Pin 14): Switch Node Connection to Inductor and

Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground to
VIN.

BOOST (Pin 15): Supply to Topside Floating Driver. The
bootstrap capacitor is returned to this pin. Voltage swing
at this pin is from a diode drop below INTVCC to VIN +
INTVCC.

TG (Pin 16): High Current Gate Drive for Top N-Channel
MOSFET. This is the output of a floating driver with a
voltage swing equal to INTVCC superimposed on the
switch node voltage SW.

CC

.

, CSS, the feedback divider plus

OSC

7

LTC1735-1

UU

W

FU CTIO AL DIAGRA

INTV

CC

100k

PGOOD

4 8

–
+

0.74V

V

OSENSE

7

R1

R2

1.2µA

6V

RUN/SS

C

0.8V

SS

0.86V

V

FB

2

+
–

–

EA

+

CURRENT

LATCHOFF

OSC

g

=1.3m

m

SD

RUN

SOFT-

START

OVER-

C

C

OV

+

C

OSC

SGNDC

1

SYNC

OSC

Ω

0.86V

)

4(V

FB

SLOPE COMP

R

C

I

TH

C

ICMP

BURST
DISABLE
FC

A

2.4V

I

1

–
+

1.2V

FORCE BOT

S

R

–
+

BUFFERED

SENSE

Q

2k

I

TH

0.17µA

DROP

OUT
DET

TOP ON

45k

+– –+

30k 30k

+

3mV

INTV

0.55V

0.8V

CC

BOT

–
+

+
–

45k

–

I

+

SENSE

V

IN

V

13

IN

UVL

0.8V
REF

FC

F

TOP

SWITCH

LOGIC

B

SD

IREV

2

INTV

–

4.8V

BOT

V

IN

CC

5.2V
LDO
REG

+
–

EXTV

CC

BOOST

15

TG
16

SW

14

9563

INTV

CC

D

B

C

B

D

1

INTV

CC

12

C

INTVCC

BG

11

PGND

10

+

C

IN

R

L

SENSE

V

OUT

+

C

OUT

+

U

OPERATIO

Main Control Loop:
The LTC1735-1 uses a constant frequency, current mode

step-down architecture. During normal operation, the top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator I1 resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on Pin ITH, which is the output of error amplifier
EA. Pin V

OSENSE

to receive an output feedback voltage VFB from the external
resistive divider. When the load current increases, it
causes a slight decrease in VFB relative to the 0.8V refer­ence, which in turn causes the ITH voltage to increase until

, described in the Pin Functions, allows EA

(Refer to Functional Diagram)

1735-1 FD

the average inductor current matches the new load cur­rent. While the top MOSFET is off, the bottom MOSFET is
turned on until either the inductor current starts to reverse,
as indicated by current comparator I2, or the beginning of
the next cycle.

The top MOSFET driver is powered from a floating boot­strap capacitor CB. This capacitor is normally recharged
from INTVCC through an external Schottky diode when the
top MOSFET is turned off. As VIN decreases towards V

OUT

,
the converter will attempt to turn on the top MOSFET con­tinuously (“dropout’’). A dropout counter detects this con­dition and forces the top MOSFET to turn off for about 500ns
every tenth cycle to recharge the bootstrap capacitor.

8

OPERATIO

LTC1735-1

U

(Refer to Functional Diagram)

The main control loop is shut down by pulling Pin 2 (RUN/
SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with the
ITH voltage clamped at approximately 30% of its maximum
value. As CSS continues to charge, ITH is gradually re­leased allowing normal operation to resume. If V
not reached 70% of its final value when CSS has charged
to 4.1V, latchoff can be invoked as described in the
Applications Information section.

The internal oscillator can be synchronized to an external
clock applied though a series resistor to the PGOOD pin
and can lock to a frequency between 90% and 130% of its
nominal rate set by capacitor C

An overvoltage comparator OV guards against transient
overshoots (>7.5%) as well as other more serious
conditions that may overvoltage the output. In this case,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.

Foldback current limiting for an output shorted to ground
is provided by amplifier A. As V
the buffered ITH input to the current comparator is gradually
pulled down to a 0.86V clamp. This reduces peak inductor
current to about 1/4 of its maximum value.

Low Current Operation

The LTC1735-1 has three low current modes controlled
by the PGOOD pin. Burst Mode operation is selected when
the PGOOD pin is above 0.8V (typically tied through a
resistor to INTVCC). During Burst Mode operation, if the
error amplifier drives the ITH voltage below 0.86V, the
buffered ITH input to the current comparator will be
clamped at 0.86V. The inductor current peak is then held
at approximately 20mV/R
output current). If ITH then drops below 0.5V, the Burst
Mode comparator B will turn off both MOSFETs to maxi­mize efficiency. The load current will be supplied solely by
the output capacitor until ITH rises above the 60mV
hysteresis of the comparator and switching is resumed.
Burst Mode operation is disabled by comparator F when
the PGOOD pin is brought below 0.8V. This forces

SENSE

.

OSC

drops below 0.6V,

OSENSE

(about 1/4 of maximum

OUT

has

continuous operation and assists in controlling voltage
regulation. If the output voltage is not within 7.5% of its
nominal value the PGOOD open-drain output will be
pulled low and Burst Mode operation will be disabled.

Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff

The RUN/SS capacitor, CSS, is used initially to limit the
inrush current of the switching regulator. After the con­troller has been started and been given adequate time to
charge up the output capacitors and provide full load
current, CSS is used as a short-circuit time-out circuit. If
the output voltage falls to less than 70% of its nominal
output voltage, CSS begins discharging on the assumption
that the output is in an overcurrent and/or short-circuit
condition. If the condition lasts for a long enough period
as determined by the size of the CSS, the controller will be
shut down until the RUN/SS pin voltage is recycled. This
built-in latchoff can be overridden by providing a current
>5µA at a compliance of 5V to the RUN/SS pin. This
current shortens the soft-start period but also prevents net
discharge of C
circuit condition. Foldback current limiting is activated
when the output voltage falls below 70% of its nominal
level whether or not the short-circuit latchoff circuit is
enabled.

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and most
of the internal circuitry of the LTC1735-1 is derived from
the INTVCC pin. When the EXTVCC pin is left open, an
internal 5.2V low dropout regulator supplies the INTV
power from VIN. If EXTVCC is raised above 4.7V, the
internal regulator is turned off and an internal switch
connects EXTVCC to INTVCC. This allows a high efficiency
source, such as the primary or a secondary output of the
converter itself, to provide the INTVCC power. Voltages up
to 7V can be applied to EXTVCC for additional gate drive
capability.

To provide clean start-up and to protect the MOSFETs,
undervoltage lockout is used to keep both MOSFETs off
until the input voltage is above 3.5V.

during an overcurrent and/or short-

SS

CC

9

LTC1735-1

OPERATIO

U

(Refer to Functional Diagram)

POWER GOOD

A window comparator monitors the output voltage and its
open-drain output is pulled low when the divided down
output voltage (appearing at the V
±7.5% of the reference voltage of 0.8V.

During a programmed output voltage transition (i.e., a
transition from 1.55V to 1.3V) the PGOOD open-drain
output will be pulled low and Burst Mode operation will be
disabled until the output voltage is within 7.5% of its newly
programmed value.

When the PGOOD pin is driven by an external oscillator
through a series resistor, cycle-skipping operation is
invoked and the internal oscillator is synchronized to the
external clock by comparator C. In this mode, the 25%
minimum inductor current clamp is removed, providing
low noise, constant frequency discontinuous operation

OSENSE

U

pin) is not within

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APPLICATIO S I FOR ATIO

over the widest possible output current range. This con­stant frequency operation is not quite as efficient as Burst
Mode operation, but does provide a lower noise, constant
frequency operation. When the power good window com­parator indicates the output is not in regulation, the
PGOOD pin is pulled to ground and synchronization is
inhibited. Obviously when driving the PGOOD pin with an
external clock the power good indication is not available
unless additional circuitry is added.

If the PGOOD pin is tied to ground, continuous operation
is forced. This operation is the least efficient mode, but is
desirable in certain applications. The output can source
or sink current in this mode. When forcing continuous
operation and sinking current, current will be forced back
into the main power supply potentially boosting the input
supply to dangerous voltage levels—BEWARE.

The basic LTC1735-1 application circuit is shown in
Figure 1 on the first page of this data sheet. External
component selection is driven by the load requirement
and begins with the selection of R
is known, C
MOSFETs and D1 are selected. The operating frequency
and the inductor are chosen based largely on the desired
amount of ripple current. Finally, CIN is selected for its
ability to handle the large RMS current into the converter
and C

OUT

output voltage ripple and transient specifications. The
circuit shown in Figure 1 can be configured for operation
up to an input voltage of 28V (limited by the external
MOSFETs).

R

R
The LTC1735-1 current comparator has a maximum
threshold of 75mV/R
range of SGND to 1.1(INTVCC). The current comparator
threshold sets the peak of the inductor current, yielding a
maximum average output current I
value less half the peak-to-peak ripple current, ∆IL.

Selection For Output Current

SENSE

is chosen based on the required output current.

SENSE

and L can be chosen. Next, the power

OSC

is chosen with low enough ESR to meet the

and an input common mode

SENSE

. Once R

SENSE

equal to the peak

MAX

SENSE

Allowing a margin for variations in the LTC1735-1 and
external component values yields:

mV

R

SENSE

C

Selection for Operating Frequency

OSC

and Synchronization

The choice of operating frequency and inductor value is
a trade-off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses, both gate charge loss and
transition loss. However, lower frequency operation
requires more inductance for a given amount of ripple
current.

The LTC1735-1 uses a constant frequency architecture
with the frequency determined by an external oscillator
capacitor C
the voltage on C
C

is charged by a fixed current. When the voltage on the

OSC

capacitor reaches 1.19V, C
process then repeats.

50

=

I

MAX

. Each time the topside MOSFET turns on,

OSC

is reset to ground. During the on-time,

OSC

is reset to ground. The

OSC

10

LTC1735-1

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APPLICATIO S I FOR ATIO

The value of C
frequency assuming no external clock input on the PGOOD
pin:

CpF

()

OSC

A graph for selecting C
Figure 2. The maximum recommended switching fre­quency is 550kHz .

The internal oscillator runs at its nominal frequency (fO)
when the PGOOD pin is pulled high (to INTVCC) though a
series resistor or connected to ground. Clocking the
PGOOD pin above and below 1.2V will cause the internal
oscillator to injection-lock to an external clock signal
applied to the PGOOD pin with a frequency between 0.9f
and 1.3fO. The clock high level must exceed 1.3V for at
least 0.3µs, and the clock low level must be less than 0.3V
for at least 0.3µs. The top MOSFET turn-on will synchro-
nize with the rising edge of the external clock.

Attempting to synchronize to too high of an external
frequency (above 1.3fO) can result in inadequate slope
compensation and possible loop instability at high duty
cycles. If this condition exists, simply lower the value of
C

so (f

OSC

EXT

100.0

87.5

75.0

62.5

50.0

VALUE (pF)

37.5

OSC

C

25.0

12.5

When synchronized to an external clock, Burst Mode
operation is disabled but the inductor current is not
allowed to reverse. The 25% minimum inductor current

is calculated from the desired operating

OSC



16110



Frequency





7

.( )

versus frequency is given in

OSC



–=

11






= fO) according to Figure 2.

0

0 100 200 300 400 500 600

OPERATING FREQUENCY (kHZ)

1735-1 F02

Figure 2. Timing Capacitor Value

O

clamp present in Burst Mode operation is removed,
providing constant frequency discontinuous operation
over the widest possible output current range. In this
mode the synchronous MOSFET is forced on once every
10 clock cycles to recharge the bootstrap capacitor. This
minimizes audible noise while maintaining reasonably
high efficiency.

Inductor Value Calculation

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic trade
off, the effect of inductor value on ripple current and low
current operation must also be considered.

The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL decreases with higher induc­tance or frequency and increases with higher VIN or V

∆I

1

=

L OUT

fL

()()



V

1

–




V

OUT

V

IN






OUT

:

Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.3 to 0.4(I

). Remember,

MAX

the maximum ∆IL occurs at the maximum input voltage.
The inductor value also has an effect on low current

operation. The transition to low current operation begins
when the inductor current reaches zero while the bottom
MOSFET is on. Burst Mode operation begins when the
average inductor current required results in a peak current
below 25% of the current limit determined by R

SENSE

.
Lower inductor values (higher ∆IL) will cause this to occur
at higher load currents, which can cause a dip in efficiency
in the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.

11

LTC1735-1

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APPLICATIO S I FOR ATIO

Inductor Core Selection

Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford
the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will increase.

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Because
they generally lack a bobbin, mounting is more difficult.
However, designs for surface mount are available that do
not increase the height significantly.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for use
with the LTC1735-1: an N-channel MOSFET for the top
(main) switch, and an N-channel MOSFET for the bottom
(synchronous) switch.

The peak-to-peak gate drive levels are set by the INTV
voltage. This voltage is typically 5.2V during start-up (see
EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most LTC1735-1
applications. The only exception is when low input voltage
is expected (V
MOSFETs (V
attention to the BV

< 5V); then, sub-logic level threshold

IN

GS(TH)

< 3V) should be used. Pay close

specification for the MOSFETs as

DSS

well; most of the logic level MOSFETs are limited to 30V or
less.

Kool Mµ is a registered trademark of Magnetics, Inc.

CC

Selection criteria for the power MOSFETs include the “ON”
resistance R

, reverse transfer capacitance C

DS(ON)

RSS

,
input voltage and maximum output current. When the
LTC1735-1 is operating in continuous mode the duty
cycles for the top and bottom MOSFETs are given by:

V

Main SwitchDuty Cycle

Synchronous SwitchDuty Cycle

OUT

=

V

IN

VV

–

IN OUT

=

V

IN

The MOSFET power dissipations at maximum output
current are given by:

V

P

MAIN

P

SYNC

OUT

=

V

IN

kV I C f

()( )( )()

IN MAX RSS

VV

–

IN OUT

=

V

IN

where δ is the temperature dependency of R

2

IR

()

MAX DS ON

2

+

11δ

()

2

IR

()

MAX DS ON

+

()

()

δ

+

()

DS(ON)

and k

is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the topside

N-channel equation includes an additional term for transi­tion losses, which are highest at high input voltages. For
V

< 20V the high current efficiency generally improves

IN

with larger MOSFETs, while for V

> 20V the transition

IN

losses rapidly increase to the point that the use of a higher
R

DS(ON)

device with lower C

actually provides higher

RSS

efficiency. The synchronous MOSFET losses are greatest
at high input voltage or during a short circuit when the duty
cycle in this switch is nearly 100%.

The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R

vs Temperature curve, but

DS(ON)

δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C

is usually specified in the

RSS

MOSFET characteristics. The constant k = 1.7 can be used
to estimate the contributions of the two terms in the main
switch dissipation equation.

The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom

12

LTC1735-1

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APPLICATIO S I FOR ATIO

MOSFET from turning on and storing charge during the
dead-time, which could cost as much as 1% in efficiency.
A 3A Schottky is generally a good size for 10A to 12A regu­lators due to the relatively small average current. Larger
diodes result in additional transition losses due to their
larger junction capacitance. The diode may be omitted if the
efficiency loss can be tolerated.

CIN Selection

In continuous mode, the source current of the top
N-channel MOSFET is a square wave of duty cycle V
VIN. To prevent large voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS capacitor current is given by:

12

II

≅

RMS O MAX

()

V

OUT

V

V



V



ININOUT



This formula has a maximum at V
= I

/2. This simple worst-case condition is commonly

OUT

–1

IN






= 2V

/

, where I

OUT

used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the manufacturer if there is any question.

C

Selection

OUT

The selection of C

is primarily determined by the

OUT

effective series resistance (ESR) to minimize voltage ripple.
The output ripple (∆V

) in continuous mode is deter-

OUT

mined by:

∆∆V I ESR

≈+

OUT L





8

where f = operating frequency, C



fC

1

OUT






= output capacitance,

OUT

and ∆IL= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. Typically, once the ESR requirement
for C
far exceeds the I

0.3I

has been met, the RMS current rating generally

OUT

requirement. With ∆IL =

OUT(MAX)

RIPPLE(P-P)

and allowing for 2/3 of the ripple due to ESR,

OUT

RMS

/

the output ripple will be less than 50mV at max V

IN

assuming:
C

C

required ESR < 2.2 R

OUT

> 1/(8fR

OUT

SENSE

SENSE

)

The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran­tees that the output voltage does not significantly dis­charge during the operating frequency period due to ripple
current. The choice of using smaller output capacitance
increases the ripple voltage due to the discharging term
but can be compensated for by using capacitors of very
low ESR to maintain the ripple voltage at or below 50mV.
The I

pin OPTI-LOOP compensation components can be

TH

optimized to provide stable, high performance transient
response regardless of the output capacitors selected.

The selection of output capacitors for CPU or other appli­cations with large load current transients is primarily de­termined by the voltage tolerance specifications of the load.
The resistive component of the capacitor, ESR, multiplied
by the load current change plus any output voltage ripple
must be within the voltage tolerance of the load (CPU).

The required ESR due to a load current step is:

R

< ∆V/∆I

ESR

where ∆I is the change in current from full load to zero load
(or minimum load) and ∆V is the allowed voltage deviation
(not including any droop due to finite capacitance).

The amount of capacitance needed is determined by the
maximum energy stored in the inductor. The capacitance
must be sufficient to absorb the change in inductor current
when a high current to low current transition occurs. The
opposite load current transition is generally determined by
the control loop OPTI-LOOP components, so make sure
not to over compensate and slow down the response. The
minimum capacitance to assure the inductors’ energy is
adequately absorbed is:

2

LI

∆

C

OUT

()

>

∆

2

VV

OUT

()

where ∆I is the change in load current.

13

LTC1735-1

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APPLICATIO S I FOR ATIO

Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance through­hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.

In surface mount applications, multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Special
polymer surface mount capacitors offer very low ESR but
have much lower capacitive density per unit volume than
other capacitor types. These capacitors offer a very cost­effective output capacitor solution and are an ideal choice
when combined with a controller having high loop
bandwidth. Tantalum capacitors offer the highest
capacitance density and are often used as output capacitors
for switching regulators having controlled soft-start.
Several excellent surge-tested choices are the AVX TPS,
AVX TPSV or the KEMET T510 series of surface mount
tantalums, available in case heights ranging from 2mm to
4mm. Aluminum electrolytic capacitors can be used in
cost-driven applications providing that consideration is
given to ripple current ratings, temperature and long-term
reliability. A typical application will require several to many
aluminum electrolytic capacitors in parallel. A combination
of the above mentioned capacitors will often result in
maximizing performance and minimizing overall cost.
Other capacitor types include Sanyo OS-CON, Nichicon PL
series and Sprague 595D series. Consult manufacturers
for other specific recommendations.

INTVCC Regulator

An internal P-channel low dropout regulator produces the

5.2V supply that powers the drivers and internal circuitry
within the LTC1735-1. The INTVCC pin can supply a
maximum RMS current of 50mA and must be bypassed
to ground with a minimum of 4.7µF tantalum, 10µF
special polymer or low ESR type electrolytic capacitor. A
1µF ceramic capacitor placed directly adjacent to the

INTVCC and PGND IC pins is highly recommended. Good
bypassing is required to supply the high transient cur­rents required by the MOSFET gate drivers.

Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi­mum junction temperature rating for the LTC1735-1 to be
exceeded. The system supply current is normally domi­nated by the gate charge current. Additional loading of
INTVCC also needs to be taken into account for the power
dissipation calculations. The total INTVCC current can be
supplied by either the 5.2V internal linear regulator or by
the EXTVCC input pin. When the voltage applied to the
EXTVCC pin is less than 4.7V, all of the INTVCC current is
supplied by the internal 5.2V linear regulator. Power
dissipation for the IC in this case is highest, (VIN)(I
and overall efficiency is lowered. The gate charge current
is dependant on operating frequency as discussed in the
Efficiency Consideration section. The junction tempera­ture can be estimated by using the equations given in Note
2 of the Electrical Characteristics. For example, the
LTC1735CS-1 is limited to less than 17mA from a 30V
supply when not using the EXTVCC pin as follows:

TJ = 70°C + (17mA)(30V)(110°C/W) = 126°C
Use of the EXTVCC input pin reduces the junction tempera-

ture to:

TJ = 70°C + (17mA)(5V)(110°C/W) = 79°C

To prevent maximum junction temperature from being
exceeded, the input supply current must be checked
operating in continuous mode at maximum VIN.

EXTVCC Connection

The LTC1735-1 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
Whenever the EXTVCC pin is above 4.7V the internal 5.2V
regulator shuts off, the switch closes and INTVCC power is
supplied via EXTVCC until EXTVCC drops below 4.5V. This
allows the MOSFET gate drive and control power to be
derived from the output or other external source during
normal operation. When the output is out of regulation
(start-up, short circuit) power is supplied from the internal
regulator. Do not apply greater than 7V to the EXTVCC pin
and ensure that EXTVCC < VIN.

INTVCC

),

14

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APPLICATIO S I FOR ATIO

Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
simply means connecting the EXTVCC pin directly to V
However, for dynamic (VID-like) programmed regulators
and other lower voltage regulators, additional circuitry is
required to derive INTVCC power from the output.

The following list summarizes the four possible connec­tions for EXTV

CC:

1. EXTVCC Left Open (or Grounded). This will cause INTV
to be powered from the internal 5.2V regulator resulting
in an efficiency penalty of up to 10% at high input
voltages.

2. EXTVCC connected directly to V

. This is the normal

OUT

connection for a 5V to 7V output regulator and provides
the highest efficiency. For output voltages > 5V, EXTV
is required to connect to V

so the SENSE pins

OUT

absolute maximum ratings are not exceeded.

3. EXTVCC Connected to an External Supply (This Option
is the Most Likely Used). If an external supply is
available in the 5V to 7V range, such as notebook main
5V system power, it may be used to power EXTV
providing it is compatible with the MOSFET gate drive
requirements. This is the typical case as the 5V power
is almost always present and is derived by another high
efficiency regulator.

4. EXTVCC Connected to an Output-Derived Boost Net­work. For low output voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with either the inductive
boost winding or capacitive charge pump circuits.
Refer to the LTC1735 data sheet for details. The charge
pump has the advantage of simple magnetics.

Output Voltage Programming

The output voltage is set by an external resistive divider
according to the following formula:

R

2

VV

=+

OUT



08 1

.










R

1

OUT

CC

CC

CC

.

V

OUT

R2

V

OSENSE

LTC1735-1

SGND

1735-1 F03

Figure 3. Setting the LTC1735-1 Output Voltage

47pF

R1

The resistive divider is connected to the output as shown
in Figure 3 allowing remote voltage sensing.

The output voltage can be digitally set to voltages between
any two levels with the addition of a resistor and small
signal N-channel MOSFET as shown in the circuit of
Figure 1. Dynamic output voltage selection can be accom­plished with this technique. Output voltages of 1.30V and

1.55V are set by the resistors R1 to R3. With the gate of
the MOSFET low, (VG = 0), the output voltage is set by the
ratio of R1 to R2. When the MOSFET is on (VG = high), the
output voltage is the ratio of R1 to the parallel combina­tion of R2 and R3. With the available power good output
(PGOOD), the circuit in Figure 1 creates a low cost Intel
Pentium III mobile processor compliant supply.

The LTC1735-1 has remote sense capability. The top of the
internal resistive divider is connected to V

OSENSE

and is
referenced to the SGND pin. This allows a kelvin connec­tion for remotely sensing the output voltage directly across
the load, eliminating any PC board trace resistance errors.

Topside MOSFET Driver Supply (CB, DB)

An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside
MOSFET. Capacitor CB in the Functional Diagram is charged
though external diode DB from INTVCC when the SW pin is
low. Note that the voltage across CB is about a diode drop
below INTVCC. When the topside MOSFET is to be turned
on, the driver places the CB voltage across the gate-source
of the MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage SW rises to
VIN and the BOOST pin rises to VIN + INTVCC. The value of
the boost capacitor CB needs to be 100 times greater than
the total input capacitance of the topside MOSFET. In most
applications 0.1µF to 0.33µF is adequate. The reverse
breakdown on DB must be greater than V

IN(MAX) .

15

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APPLICATIO S I FOR ATIO

When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If you make a change
and the input current decreases, then you improved the
efficiency. If there is no change in input current, then there
is no change in efficiency.

SENSE+/SENSE– Pins

The common mode input range of the current comparator
is from 0V to 1.1(INTVCC). Continuous linear operation is
guaranteed throughout this range allowing output volt­ages anywhere from 0.8V to 7V. A differential NPN input
stage is used and is biased with internal resistors from an
internal 2.4V source as shown in the Functional Diagram.
This causes current either to be sourced or sunk by these
pins depending on the output voltage. If the output voltage
is below 2.4V, current will flow out of both SENSE pins to
the main output. This forces a minimum load current that
can be fulfilled by the V
mum current flowing out of the SENSE pins is:

I

SENSE+

Since V

+ I

SENSE–

OSENSE

= (2.4V – V

is servoed to the 0.8V reference voltage, we
can choose R1 in Figure 3 to have a maximum value to
absorb this current:

resistive divider. The maxi-

OUT

)/24k

OUT

capacitor C

If RUN/SS has been pulled all the way to

SS.

ground there is a delay before starting of approximately:

15

.

T

DELAY SS SS

V

=

12

CsFC

.

A

µ

125

./

=µ

()

When the voltage on RUN/SS reaches 1.5V the
LTC1735-1 begins operating with a current limit at ap­proximately 25mV/R

. As the voltage on RUN/SS

SENSE

increases from 1.5V to 3V, the internal current limit is
increased from 25mV/R

SENSE

to 75mV/R

SENSE

. The out-

put current limit ramps up slowly, taking an additional

1.25s/µF to reach full current. Ramping the output cur-
rent slowly reduces the starting surge current
required from the input supply.

Diode D1 in Figure 4 and Figure 5 reduces the start delay
while allowing CSS to charge up slowly for the soft-start
function. This diode and C

can be deleted if soft-start is

SS

not needed. The RUN/SS pin has an internal 6V zener
clamp (see Functional Diagram).

3.3V OR 5V RUN/SS RUN/SS

D1

C

C

SS

SS

R Max k



124

()

=



24



08

.

VV

.–

V

OUT






Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that for output voltages above

2.4V no maximum value of R1 is necessary to absorb the
sense currents; however, R1 is still bounded by the
V

OSENSE

feedback current.

Soft-Start/Run Function

The RUN/SS pin is a multipurpose pin that provides a soft­start function and a means to shut down the LTC1735-1.
Soft-start reduces surge currents from VIN by gradually
increasing the controller’s current limit I

TH(MAX)

. This pin

can also be used for power supply sequencing.
Pulling the RUN/SS pin below 1.5V puts the LTC1735-1

into a low quiescent current shutdown (IQ < 25µA). This
pin can be driven directly from logic as shown in Figures
4 and 5. Releasing the RUN/SS pin allows an internal

1.2µA current source to charge up the external soft-start

1735-1 F04

Figure 4. RUN/SS Pin Interfacing

V

3.3V OR 5V RUN/SS

Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated

IN

R

D1

SS

C

SS

(a) (b)

INTV

CC

R

SS

RUN/SS

D1

C

SS

1735-1 F05

Fault Conditions: Overcurrent Latchoff

The RUN/SS pin also provides the ability to shut off the
controller and latchoff when an overcurrent condition is
detected. The RUN/SS capacitor C

is used initially to

SS

turn on and limit the inrush current of the controller. After
the controller has been started and given adequate time to
charge up the output capacitor and provide full load

16

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APPLICATIO S I FOR ATIO

current, CSS is used as a short-circuit timer. If the output
voltage falls to less than 70% of its nominal output voltage

after

CSS reaches 4.1V, the assumption is made that the
output is in a severe overcurrent and/or short-circuit
condition and CSS begins discharging. If the condition
lasts for a long enough period as determined by the size of
CSS, the controller will be shut down until the RUN/SS pin
voltage is recycled.

This built-in latchoff can be overridden by providing a
current >5µA at a compliance of 5V to the RUN/SS pin as
shown in Figure 5a. This current shortens the soft-start
period but also prevents net discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
conditions. When deriving the 5µA current from VIN as in
Figure 5a, current latchoff is always defeated. The diode
connecting this pull-up resistor to INTVCC , as in Figure 5b,
eliminates any extra supply current during shutdown
while eliminating the INTV
controller start-up. If the voltage on CSS does not exceed

4.1V, the overcurrent latch is not armed and the function
is disabled.

Why should you defeat current latchoff? During the
prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off. Defeating this feature will easily allow trouble­shooting of the circuit and PC layout. The internal short
circuit and foldback current limiting still remains active,
thereby protecting the power supply system from failure.
After the design is complete, a decision can be made
whether to enable the latchoff feature.

The value of the soft-start capacitor CSS will need to be
scaled with output current, output capacitance and load
current characteristics. The minimum soft-start capaci­tance is given by:

CSS > (C

The minimum recommended soft-start capacitor of
C

= 0.1µF will be sufficient for most applications.

SS

Fault Conditions: Current Limit and Current Foldback

The LTC1735-1 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET current
of 75mV/R

)(V

OUT

SENSE

OUT

.

) (10–4) (R

loading from preventing

CC

)

SENSE

The LTC1735-1 includes current foldback to help further
limit load current when the output is shorted to ground. If
the output falls by more than half, then the maximum
sense voltage is progressively lowered from 75mV to
30mV. Under short-circuit conditions with very low duty
cycles, the LTC1735-1 will begin cycle skipping in order to
limit the short-circuit current. In this situation the bottom
MOSFET will be conducting the peak current. The short­circuit ripple current is determined by the minimum on­time t

ON(MIN)

input voltage, and inductor value:

∆I

L(SC)

The resulting short circuit-current is:

I

SC

The current foldback function is always active and is not
effected by the current latchoff function.

Fault Conditions: Output Overvoltage Protection
(Crowbar)

The output overvoltage crowbar is designed to blow a
system fuse in the input lead when the output of the
regulator rises much higher than nominal levels. This
condition causes huge currents to flow, much greater than
in normal operation. This feature is designed to protect
against a shorted top MOSFET; it does not protect against
a failure of the controller itself.

The comparator (OV in the Functional Diagram) detects
overvoltage faults greater than 7.5% above the nominal
output voltage. When this condition is sensed the top
MOSFET is turned off and the bottom MOSFET is forced
on. The bottom MOSFET remains on continuously for as
long as the OV condition persists; if V
level, normal operation automatically resumes. Note that
dynamically changing the output voltage may cause over­voltage protection to be momentarily activated during
output voltage decreases. This will not cause permanent
latchoff nor will it disrupt the desired voltage change.

With soft-latch overvoltage protection, dynamically chang­ing the output voltage is allowed and the overvoltage
protection tracks the newly programmed output voltage,
always protecting the load (CPU).

of the LTC1735-1 (less than 200ns), the

= t

ON(MIN)(VIN

mV

30 1

=+

R

SENSE

/L)

I

∆

LSC

()

2

returns to a safe

OUT

17

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Minimum On-Time Considerations

Minimum on-time t

ON(MIN)

that the LTC1735-1 is capable of turning the top MOSFET
on and off again. It is determined by internal timing delays
and the gate charge required to turn on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:

V

t

ON MIN

()

<

Vf

OUT

IN

()

If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1735-1 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.

The minimum on-time for the LTC1735-1 in a properly
configured application is less than 200ns. However, as the
peak sense voltage decreases, the minimum on-time
gradually increases as shown in Figure 6. This is of
particular concern in forced continuous applications with
low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre­spondingly larger current and voltage ripple.

If an application can operate close to the minimum on­time limit, an inductor must be chosen that is low enough
to provide sufficient ripple amplitude to meet the mini­mum on-time requirement.

inductor ripple current equal or greater than 30% of
I

OUT(MAX)

at V

IN(MAX)

250

200

150

100

MINIMUM ON-TIME (ns)

50

is the smallest amount of time

As a general rule keep the

.

PGOOD Pin Operation

The PGOOD pin is a multifunction pin intended primarily to
indicate when the output voltage is within ±7.5% of its
nominal set point. A window comparator monitors the
V

OSENSE

pin and activates an open-drain internal MOSFET
that pulls down the PGOOD pin when the output voltage is
out of regulation. Normally a 10k to 100k pull-up resistor
is connected to this pin from a voltage source such as
INT

. Do not apply a voltage greater than INTVCC to this

VCC

pin. Dynamically changing the output voltage between two
voltage levels greater that 7.5% apart from each other will
invoke the power good indication, causing the PGOOD
output to go low until the new output voltage is reached.

When the DC voltage on the PGOOD pin drops below its

0.8V threshold, continuous mode operation is forced. In
this case, the top and bottom MOSFETs continue to be
driven synchronously regardless of the load on the main
output. Burst Mode operation is disabled and current
reversal is allowed in the inductor. This mode is forced
whenever the output voltage is not within its 7.5%
window.

In addition to providing a power good output, the PGOOD
pin provides a logic input to force continuous synchro­nous operation and allow synchronization to an external
clock.

The internal LTC1735-1 oscillator can be synchronized to
an external oscillator by applying a clock signal to the
PGOOD pin though a series resistor with a signal ampli­tude above 1.5V

. When synchronized to an external

P-P

frequency, Burst Mode operation is disabled but cycle
skipping is allowed at low load currents since current
reversal is inhibited. The bottom gate will come on every
10 clock cycles to assure the bootstrap capacitor is kept
refreshed. The rising edge of an external clock applied to
the PGOOD pin starts a new cycle. If the output voltage is
not within the 7.5% window around its nominal set point,
the open-drain PGOOD output will pull low, disabling the
external synchronization.

18

0

0

Figure 6. Minimum On-Time vs ∆I

10

∆IL/I

20

OUT(MAX)

30

(%)

1736-1 F06

The following table summarizes the possible states avail-

40

L

able on the PGOOD pin.

LTC1735-1

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APPLICATIO S I FOR ATIO

Table 1

PGOOD PIN CONDITION

DC Voltage: 0V to 0.7V No Power Good Indication

Resistor Pull-Up to Power Good Indication

(or Other DC Burst Mode, No Current Reversal

INT

VCC

Voltage Less Than INTV
Resistor to Ext Clock: No Power Good Indication

(0V to 1.5V) Burst Mode Operation Disabled

The circuit shown in Figure 7 provides a power good
output and forces continuous operation. Transistor Q1
keeps the voltage at the PGOOD pin below 0.8V thus
disabling Burst Mode operation. When the window com­parator indicates the output voltage is not within its 7.5%
window, the base of Q1 is pulled to ground and the power
good output appearing at the collector of Q2 goes low.

PGOOD

PIN 4

Figure 7. Forced Continuous Operation with Power Good Indication

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-

age of input power.
Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the
losses in LTC1735-1 circuits: 1) LTC1735-1 VIN current,

2) INTVCC current, 3) I2R losses, 4) Topside MOSFET
transition losses.

1. The VIN current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver

Burst Mode Operation Disabled/Forced
Continuous Current Reversal Enabled

) When Power is Good

CC

No Current Reversal

INTV

CC

470k

100k

10k

POWER
GOOD

Q2

Q1

1735-1 F07

and control currents. VIN current results in a small
(<0.1%) loss that increases with VIN.

2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, I

GATECHG

=
f(QT + QB), where QT and QB are the gate charges of the
topside and bottom-side MOSFETs.

By powering EXTVCC from an output-derived source (or
other high efficiency source), the additional V

current

IN

resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Efficiency). For
example, in a 15V to 1.8V application, 10mA of INTV

CC

current results in approximately 1.2mA of VIN current.
This reduces the midcurrent loss from 10% or more (if
the driver was powered directly from VIN) to only a few
percent.

3. I2R losses are predicted from the DC resistances of the
MOSFETs, inductor and current shunt. In continuous
mode, the average output current flows through L and
R

, but is “chopped” between the topside main

SENSE

MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same R

DS(ON)

, then
the resistance of one MOSFET can simply be summed
with the resistances of L and R
losses. For example, if each R

0.03Ω, and R

= 0.01Ω, then the total resistance is

SENSE

DS(ON)

to obtain I2R

SENSE

= 0.02Ω, RL =

0.06Ω. This results in losses ranging from 3% to 17%
as the output current increases from 1A to 5A for a 1.8V
output, or 4% to 20% for a 1.5V output. Efficiency
varies as the inverse square of V

for the same

OUT

external components and power level. I2R losses cause
the efficiency to drop at high output currents.

4. Transition losses apply only to the topside MOSFET(s),
and only become significant when operating at high
input voltages (typically 12V or greater). Transition
losses can be estimated from:

Transition Loss = (1.7) V

2

I

IN

O(MAX) CRSS

f

19

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Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has
adequate charge storage and a very low ESR at the
switching frequency. A 25W supply will typically require
a minimum of 20µF to 40µF of capacitance having a
maximum of 0.01Ω to 0.02Ω of ESR. Other losses
including Schottky conduction losses during dead-time
and inductor core losses generally account for less than
2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior but also
provides a DC coupled and AC filtered closed-loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.

The I
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been

OUT

OUT

series RC-CC filter sets the dominant pole-zero

TH

generating the feedback error signal that

OUT

to its steady-state value. During this recovery

can be monitored for excessive overshoot or

(ESR), where ESR is the effective

LOAD

OUT

. ∆I

also begins to charge or

LOAD

shifts by an

OUT

TH

determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise time
of 1µs to 10µs will produce output voltage and ITH pin
waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The initial
output voltage step may not be within the bandwidth of the
feedback loop, so the standard second order overshoot/
DC ratio cannot be used to determine phase margin. The
gain of the loop will be increased by increasing RC and the
bandwidth of the loop will be increased by decreasing CC.
If RC is increased by the same factor that CC is decreased,
the zero frequency will be kept the same, thereby keeping
the phase shift the same in the most critical frequency
range of the feedback loop. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.

Improve Transient Response and Reduce Output
Capacitance with Active Voltage Positioning

Fast load transient response, limited board space and low
cost are normal requirements of microprocessor power
supplies. Active voltage positioning improves transient
response and reduces the output capacitance required to
power a microprocessor where a typical load step can be
from 0.2A to 15A in 100ns or 15A to 0.2A in 100ns. The
voltage at the microprocessor must be held to about
±0.1V of nominal in spite of these load current steps.
Since the control loop cannot respond this fast, the output
capacitors must supply the load current until the control
loop can respond. Capacitor ESR and ESL primarily deter­mine the amount of droop or overshoot in the output
voltage. Normally, several capacitors in parallel are re­quired to meet microprocessor transient requirements.

Active voltage positioning is a form of deregulation. It
sets the output voltage high for light loads and low for
heavy loads. When load current suddenly increases, the
output voltage starts from a level higher than nominal so
the output voltage can droop more and stay within the
specified voltage range. When load current suddenly

20

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APPLICATIO S I FOR ATIO

decreases the output voltage starts at a level lower than
nominal so the output voltage can have more overshoot
and stay within the specified voltage range. Less output
capacitance is required when voltage positioning is used
because more voltage variation is allowed on the output
capacitors.

Active voltage positioning can be implemented using the
OPTI-LOOP architecture of the LTC1735-1 and two resis­tors connected to the ITH pin. An input voltage offset is
introduced when the error amplifier has to drive a resistive
load. This offset voltage is limited to ±30mV at the input
of the error amplifier. The resulting change in output
voltage is the product of input offset voltage and the
feedback voltage divider ratio.

Figure 8 shows a CPU-core-voltage regulator with active
voltage positioning. Resistors R1 and R5 force the input
voltage offset that adjusts the output voltage according to
the load current level. To select values for R1 and R5, first
determine the amount of output deregulation allowed. The
actual specification for a typical microprocessor allows
the output to vary ±0.112V. The LTC1735-1 reference

accuracy is ±1%. Using 1% tolerance resistors, the total
feedback divider accuracy is about 1% because both
feedback resistors are close to the same value. The result­ing setpoint accuracy is ±2% so the output transient
voltage cannot exceed ±0.082V. For V

= 1.5V, the

OUT

maximum output voltage change controlled by the ITH pin
would be:

56

•

mV

OUT

∆=

V

OSENSE

Input Offset Voltage V

.•.

003 15

±

=

.

08

V

REF

V

=±

V

With optimum resistor values at the ITH pin, the output
voltage will swing from 1.55V at minimum load to 1.44V
at full load. At this output voltage, active voltage position­ing provides an additional ±56mV to the allowable tran­sient voltage on the output capacitors, a 68% improvement
over the ±82mV allowed without active voltage
positioning.

C2

0.1µF

C4

100pF

C6

47pF

R1

27k

R2

100k

PGOOD

C1

39pF

C3

100pF

1000pF

R3 680k

C15 TO
C18
180µF
4V

C12 TO C14
10µF
35V

R4 100k

R5 100k

BOOST

INTV

PGND

EXTV

TG

SW

V

BG

IN

CC

CC

16

15

14

13

12

11

10

9

5V (OPTIONAL)

1

C

OSC

2

RUN/SS

3

I

TH

U1

LTC1735-1

4

PGOOD

5

–

6

7

8

SENSE

SENSE

V

OSENSE

SGND

+

C5

C7

0.1µF

C8

0.22µF

D1
CMDSH-3

+

C9
1µF

C10

4.7µF
10V

Q1
FDS6680A

MBRS340

Q2, Q3
FDS6680A
×2

C9, C19: TAIYO YUDEN JMK107BJ105
C10: KEMET T494A475M010AS
C12 TO C14: TAIYO YUDEN GMK325F106
C15 TO C18: PANASONIC EEFUE0G181R
D1: CENTRAL SEMI CMDSH-3
D2: MOTOROLA MBRS340
L1: PANASONIC ETQP6F1R0SA
Q1 TO Q3: FAIRCHILD FDS6680A
R5: IRC LRF2512-01-R003-J
U1: LINEAR TECHNOLOGY LTC1735CS-1

L1

1µH

D2

R6

0.003Ω

C11
330pF

11.5k

1735-1 F08

10k

R7

+

R8

C19
1µF

V

IN

7.5V TO
24V

GND

V

OUT

1.5V
15A

GND

Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning

21

LTC1735-1

k

VV

V

VV

V

INTVCC ITH NOM

ITH NOM

===

–

.–.

.

.

()

()

52 1085

1 085

379

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APPLICATIO S I FOR ATIO

The next step is to calculate the ITH pin voltage, V
factor. The V

scale factor reflects the ITH pin voltage

ITH

required for a given load current in continuous inductor
current operation. V

controls the peak sense resistor

ITH

voltage, which represents the DC output current plus one
half of the peak-to-peak inductor current. The no load to
full load V

range is from 0.3V to 2.4V, which controls

ITH

the sense resistor voltage from 0V to the ∆V
voltage of 75mV. For the circuit shown in Figure 8, the
calculated V

V Scale Factor

ITH

Assuming continuous inductor current, V

scale factor is:

ITH

V Range Sense sistor Value

ITH

=

(. – . )• .

24 03 0003

VV

==

•Re

∆

V

SENSE MAX

.

0 075

V

()

ITH

, scale

ITH

SENSE(MAX)

./

0 084

VA

is:

V

from 0.40V at light load to 1.77V at full load, a 1.37V

ITH

change. During Burst Mode operation, the LTC1735-1
output voltage is controlled by a comparator, not the error
amplifier. Even though the error amplifier is not used in
Burst Mode operation, it is necessary to assume linear
operation for all error amplifier gain calculations.

To create the ±30mV input offset error, the voltage gain of
the error amplifier must be limited. The desired gain is:

A

=

V

Input Offset Error

V

∆

ITH

==

V

137

.

2003

(. )

22 8

.

V

Connecting a resistor to the output of the transconductance
error amplifier will limit the voltage gain. The value of this
resistor is:

A

R

===

ITH

Error Amplifier g ms

V

22 8

.

13

.

m

17 54

.

k



VI

ITH OUTDC



=+









V Offset

+

ITH

I

∆



L

V Scale Factor

•



ITH



2






At full load current:



VAAVA V

ITH MAX

=+

=











.

177

()

15



5

V



−

PP

•. / .

0 084 0 3



2





+






At minimum load current:



VAAVA V

ITH MIN

=+

02

=











.

040

()



2

.•./.

V

−

PP

2



0 084 0 3







+






Notice that ∆IL, the peak-to-peak inductor current, changes
from light load to full load. Increasing the DC inductor
current decreases the permeability of the inductor core
material, which decreases the inductance and increases
∆IL. The amount of inductance change is a function of the
inductor design.

If the circuit shown in Figure 8 sustained continuous in­ductor current operation, the error amplifier would control

To center the output voltage variation, V

must be

ITH

centered so that no ITH pin current flows when the output
voltage is nominal. V
tween V

at maximum output current and minimum

ITH

ITH(NOM)

is the average voltage be-

output current:

V

ITH NOM

VV

ITH MAX ITH MIN

=+

.–.

177 040

=+=

–

() ()

2

VV

..

0 40 1 085

VV

V

ITH MIN()

()

2

The Thevenin equivalent of the gain limiting resistance
value of 17.54k is made up of a resistor R5 that sources
current into the ITH pin and resistor R1 that sinks current
to SGND.

To calculate the resistor values, first determine the ratio
between them:

V

INTVCC

is equal to V

or 5.2V if EXTVCC is not used.

EXTVCC

Resistor R5 is:

Rk R k k

5 1 3 79 1 17 54 84 0=+ = + =()• (. )•. .

ITH

22

LTC1735-1

U

WUU

APPLICATIO S I FOR ATIO

Resistor R1 is:

kR

1 3 79 1 17 54

+

()• (. )•.

R

1

ITH

=

k

+

379

.

Unfortunately, PCB noise can add to the voltage developed
across the sense resistor, R6, causing the ITH pin voltage
to be slightly higher than calculated for a given output
current. The amount of noise is proportional to the output
current level. This PCB noise does not present a serious
problem but it does change the effective value of R6 so the
calculated values of R1 and R5 may need to be adjusted to
achieve the required results. Since PCB noise is a function
of the layout, it will be the same on all boards with the same
layout.

Figures 9 and 10 show the transient response before and
after active voltage positioning is implemented. Notice
that active voltage positioning reduced the transient re­sponse from almost 200mV

to a little over 100mV

P-P

Refer to Design Solutions 10 for more information about
active voltage positioning.

VIN = 12V

= 1.5V

V

1.50V

15A

0.2A

1.50V

15A

0A

OUT

VIN = 12V

= 1.5V

V

OUT

LOAD

CURRENT

OUTPUT

VOLTAGE

LOAD

CURRENT

50µs/DIV

1.582V

100mV/DIV

1.418V

5A/DIV

Figure 9. Transient Response Without Active Voltage Positioning

1.582V

100mV/DIV

1.418V

FIGURE 8 CIRCUIT

OUTPUT

VOLTAGE

FIGURE 8 CIRCUIT

k

=

1735-1 F09

k

22 17=

.

.

P-P

Automotive Considerations: Plugging Into the
Cigarette Lighter

As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main power line in an auto is the
source of a number of nasty potential transients, including
load dump, reverse battery and double battery.

Load dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.

The network shown in Figure 11 is the most straight
forward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse battery,
while the transient suppressor clamps the input voltage
during load dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC1735-1 has a maximum input
voltage of 36V, most applications will be limited to 30V by
the MOSFET BV

12V

TRANSIENT VOLTAGE

GENERAL INSTRUMENT

Figure 11. Plugging Into the Cigarette Lighter

.

DSS

50A IPK RATING

SUPPRESSOR

1.5KA24A

V

IN

LTC1735-1

1735-1 F11

0.2A

5A/DIV

Figure 10. Transient Response with Active Voltage Positioning

0A

50µs/DIV

1735-1 F10

23

LTC1735-1

U

WUU

APPLICATIO S I FOR ATIO

Design Example

As a design example, assume VIN = 12V (nominal), V
22V (max), V
R

and C

SENSE

R
C

= 50mV/12A = 0.042Ω

SENSE

= 1.61(107)/(300kHz) – 11pF = 43pF

OSC

= 1.5V, I

OUT

can immediately be calculated:

OSC

= 12A and f = 300kHz,

MAX

Assume a 1.2µH inductor and check the actual value of the
ripple current. The following equation is used :

∆I

V

OUT OUT

=

L

fL

()()



–1







V



V



IN

The highest value of the ripple current occurs at the
maximum input and output voltages:

∆I

L

=

kHz H

300 1 2

V

15

.

(. )






µ

V

15

.

22






V

1

–

=

39

.

A

The maximum ripple current is 32% of maximum output
current, which is about right.

IN

=

P

SYNC

=
=

959

–.

22

V

mW

2

12 1 1 0 0065

A

()()

..

()

Ω

22 1 5

VV

Thanks to current foldback, the bottom MOSFET dissipa­tion in short circuit will be less than under full-load
conditions.

CIN is chosen for an RMS current rating of at least 6A at
temperature. C

is chosen with an ESR of 0.01Ω for low

OUT

output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:

V

ORIPPLE

= R

(∆IL) = 0.01Ω(3.9A) = 39mV

ESR

P-P

Since the output voltage is below 2.4V, the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins specified input
current.

R MAX k



08

.



VV

24 15

.–.





V





k124

21 3()

.=

=

Next, verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum VIN and mini­mum V

t

ON MIN

.

OUT

.

V

OUT

== =

()

VfVV kHz

IN MAX

()

15

()

22 300

227

ns

The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Fairchild FDS6612A results
in; R

DS(ON)

= 0.03Ω, C

= 80pF. At maximum input

RSS

voltage with T(estimated) = 50°C:

P

MAIN

15

=

22

.

1 7 22 12 80 300

+

=

568

2

+°°

12 1 0 005 50 25 0 03

()

V

()()( )( )

( . )( – ) .

[]

2

V A pF kHz

CC

mW

Ω

()

V

.

Because the duty cycle of the bottom MOSFET is much
greater than the top, two larger MOSFETs must be paral­leled. Choosing Fairchild FDS6680A MOSFETs yields a
parallel R

of 0.0065Ω. The total power dissipation

DS(ON)

for both bottom MOSFETs, again assuming T = 50°C, is:

Choosing 1% resistors: R1 = 21k and R2 = 18.7k yields an
output voltage of 1.512V.

PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1735-1. These items are also illustrated graphically in
the layout diagram of Figure 12. Check the following in
your layout:

1. Are the signal and power grounds segregated? The
LTC1735-1 PGND pin should tie to the ground plane
close to the input capacitor(s). The SGND pin should
then connect to PGND and all components that connect
to SGND should make a single-point tie to the SGND
pin. The synchronous MOSFET source should connect
to the input capacitor(s) ground.

2.

Does the V

OSENSE

pin connect directly to the feedback
resistors? The resistive divider R1, R2 must be con­nected between the (+) plate of C
The 47pF capacitor from V

OSENSE

and signal ground.

OUT

to SGND should be
as close as possible to the LTC1735-1. Be careful
locating the feedback resistors too far away from the

24

LTC1735-1

U

WUU

APPLICATIO S I FOR ATIO

LTC1735-1. The V

OSENSE

close to any other nodes with high slew rates.

3. Are the SENSE+ and SENSE– leads routed together with
minimum PC trace spacing? The filter capacitor be­tween SENSE+ and SENSE– should be as close as
possible to the LTC1735-1. Ensure accurate current
sensing with kelvin connections to the SENSE resistors
shown in Figure 13. Series resistance can be added to
the SENSE lines to increase noise rejection.

4. Does the (+) terminal of CIN connect to the drain of the
topside MOSFET(s) as closely as possible? This capaci­tor provides the AC current to the MOSFET(s).

C

SS

R

C

C2

line should not be routed

INTV

CC

C

C

C

OSC

C

1000pF

47pF

1
2
3
4
5
6
7
8

C

OSC

RUN/SS
I

TH

PGOOD
SENSE
SENSE
V

OSENSE

SGND

LTC1735-1

–

+

BOOST

INTV

PGND

EXTV

SW

V

BG

16

TG

15
14
13

IN

12

CC

11
10
9

CC

5. Is the INTVCC decoupling capacitor connected closely
between INTVCC and the power ground pin? This capaci­tor carries the MOSFET driver peak currents. An addi­tional 1µF ceramic placed immediately next to the INTV
and PGND pins can help improve noise performance.

6. Keep the switching node (SW), Top Gate node (TG), and
Boost node (BOOST) away from sensitive small-signal
nodes, especially from the voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on the
“output side” (Pins 9 to 16) of the LTC1735-1 and
occupy minimum PC trace area.

+

Q1

C

IN

D

+

4.7µF

C

B

B

D1

Q2

+

V

IN

–

CC

R1

C

OUT

+

R2

Figure 12. LTC1735-1 Layout Diagram

HIGH CURRENT PATH

CURRENT SENSE
RESISTOR
(R

SENSE+SENSE

–

Figure 13. Kelvin Sensing R

SENSE

SENSE

L1

R

SENSE

1735-1 F13

)

1735-1 F12

–

V

OUT

+

25

LTC1735-1

U

TYPICAL APPLICATIONS

INTV

CC

C

100k

OSC

C

47pF

C

0.1µF

C2

SS

220pF

R

33k

C

POWER

43pF

C

470pF

GOOD

1000pF

1

C

OSC

2

3

4

5

6

7

8

RUN/SS

I

TH

LTC1735-1

PGOOD

SENSE

SENSE

V

OSENSE

SGND

C

1.8V/5A Converter with Power Good

4.5V TO 22V

16

TG

15

BOOST

14

SW

13

V

IN

INTV

PGND

EXTV

CC

BG

CC

12

11

10

9

OPTIONAL:
CONNECT TO 5V

–

+

+

C

B

0.1µF

D

B

CMDSH-3

4.7µF

V

IN

Q1
Si4412DY

Q2
Si4410DY

L1

3.3µH

MBRS140T3

C

IN

22µF
50V
CER

R

SENSE

0.01Ω

V

OUT

1.8V

R2

32.4k
1%

+

R1

25.5k
1%

SGND

: PANASONIC EEFUEOG151R

C

OUT

C

: MARCON THCR70LE1H226ZT

IN

L1: PANASONIC ETQP6F3R3HFA

: IRC LR 2010-01-R010F

R

SENSE

1735-1 TA02

5A

C

OUT

150µF

6.3V
×2
PANASONIC SP

POWER

GOOD

CPU Core Voltage Regulator for 2-Step Applications (VIN = 5V) with Burst Mode Operation Disabled

V

IN

C

B

0.22µF

B

5V

Q1
FDS6680A

Q2, Q3
FDS6680A
×2

L1

0.78µH

MBRD835L

C

IN

150µF

6.3V
×2

R

SENSE

0.004Ω

1735-1 TA03

R2

32.4k

100pF

1%
R1

25.5k
1%

: PANASONIC EEFUEOG181R

C

OUT

: PANASONIC EEFUEOJ151R

C

IN

: TAIYO YUDEN LMK550BJ476MM-B

C

O

L1: COILCRAFT 1705022P-781HC
Q4, Q5: 2N2222

: IRC LRF 2512-01-R004-J

R

SENSE

+

SGND

C

OUT

180µF
4V
×3

C

O

47µF
10V

V

1.5V
12A

OUT

100k*

C

39pF

OSC

1

C

2

3

4

5

6

7

8

OSC

RUN/SS

I

TH

PGOOD

SENSE

SENSE

V

OSENSE

SGND

LTC1735-1

–

+

C

SS

0.1µF

INTV

CC

10k

100k

470k

Q5

Q4

C

220pF

47pF

C

C

R

C

220pF

20k

C2

1000pF

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

BOOST

INTV

PGND

EXTV

SW

V

16

TG

15

14

13

IN

12

CC

11

BG

10

9

CC

D
MBR0530

+

4.7µF

1µF

V

IN

5V

26

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

GN Package

16-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.189 – 0.196*
(4.801 – 4.978)

16

15

14

12 11 10

13

9

LTC1735-1

0.009

(0.229)

REF

0.015

± 0.004

(0.38 ± 0.10)

0.007 – 0.0098

(0.178 – 0.249)

0.016 – 0.050

(0.406 – 1.270)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0° – 8° TYP

× 45°

S Package

16-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.229 – 0.244

(5.817 – 6.198)

(1.351 – 1.727)

0.008 – 0.012

(0.203 – 0.305)

16

15

0.053 – 0.068

14

12

3

0.386 – 0.394*

(9.804 – 10.008)

13

12

0.150 – 0.157**
(3.810 – 3.988)

5

4

678

0.004 – 0.0098

(0.102 – 0.249)

0.0250
(0.635)

BSC

GN16 (SSOP) 1098

11

10

9

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

× 45°

0.016 – 0.050

(0.406 – 1.270)

0° – 8° TYP

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.228 – 0.244

(5.791 – 6.197)

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

TYP

0.150 – 0.157**
(3.810 – 3.988)

4

5

0.050

(1.270)

BSC

3

2

1

7

6

8

0.004 – 0.010

(0.101 – 0.254)

S16 1098

27

LTC1735-1

TYPICAL APPLICATIO

High Efficiency Dynamic Output Voltage Selectable CPU Power Supply for SpeedStep Enabled Processors

U

PGOOD RUN

R7

100k

INTV

CC

C

C

C1

47pF

OSC

C2

47pF

330pF

C

SS

R

C1

C

C1

1000pF

0.1µF

33k

47pF

C

1
2
3
4
5
6

S1

7
8

RELATED PARTS

C

OSC

RUN/SS
I

TH

PGOOD
SENSE
SENSE
V

OSENSE

SGND

JP1

LATCH-OFF

DISABLE

LTC1735-1

–

+

R5 10Ω
R4 10Ω

R6

680k

BOOST

INTV

PGND

EXTV

TG

SW
V

BG

0.1µF

IN

CC

CC

C

F1

16
15
14
13
12
11
10
9

+

C2

4.7µF

5V
INPUT
(OPTIONAL)

R8

4.7Ω

0.22µF

C

B

D1
CMDSH-3

C4
1µF

V

IN

4.5V TO 24V

Q1
FDS6680A

MBRS340T3

Q2, Q3
FDS6680A
×2

L1

1.2µH

C

IN

22µF
50V
CERAMIC
×2

R

SENSE

0.004Ω

D2

CIN: MARCON THCR70E1H226ZT

: PANASONIC EEFVE06181R

C

OUT

L1: PANASONIC ETQP6F1R2HFA

: IRC CRF2512-01-R004F

R

SENSE

R1

C2

10k

47pF

0.5%

+

R3

C3

33.2k

47pF

1%

Q4

R2

14.3k

0.5%

2N7002

1735-1 TA01

V

OUT

1.35V OR 1.60V
12A

C

OUT

180µF
4V
SP
×4

V

= 1: V

SEL

OUT

= 0: V

V

SEL

OUT

GND

= 1.60V
= 1.35V

PART NUMBER DESCRIPTION COMMENTS

LTC1149 High Efficiency Synchronous Step-Down Controller 100% DC, Std Threshold MOSFETs, VIN < 48V
LTC1159 High Efficiency Synchronous Step-Down Controller 100% DC, Logic Level MOSFETs, VIN < 40V
LT1375/LT1376 1.5A 500kHz Step-Down Switching Regulator High Efficiency
LTC1435A High Efficiency Low Noise Synchronous Step-Down Controller, N-Ch Drive Burst Mode Operation, 16-Pin Narrow SO
LTC1436A/LTC1436A-PLL High Efficiency Low Noise Synchronous Step-Down Converter, N-Ch Drive Adaptive PowerTM Mode 20-Pin, 24-Pin SSOP
LTC1474/LTC1475 Ultralow Quiescent Current Step-Down Monolithic Switching Regulator 100% DC, 8-Pin MSOP, IQ = 10µA
LTC1628 Dual High Efficiency 2-Phase Step-Down Controller Antiphase Drive, 28-Pin SSOP, 3.5V ≤ VIN ≤ 36V
LTC1702 550kHz Dual Output Synchronous Step-Down Controller Antiphase Drive, 24-Pin SSOP, VIN ≤ 7V
LTC1709 PolyPhaseTM Synchronous Controller with 5-Bit VID Up to 42A, Minimum Input Capacitors,

OUT

≤ 3.5V

1.3V ≤ V

LTC1735 High Efficiency Synchronous Step-Down Contoller, N-Channel Drive Burst Mode Opertion, 16-Pin Narrow SSOP
LTC1736 High Efficiency Synchronous Step-Down Controller with 5-Bit VID Control Output Fault Protection, 24-Pin SSOP
LTC1772 SOT-23 High Efficiency Constant Frequency Step-Down Controller 100% DC, 550kHz, SOT-23, Current Mode
Adaptive Power and PolyPhase are trademarks of Linear Technology Corporation.

28

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

17351f LT/TP 0100 4K • PRINTED IN USA

 LINEAR TE CHNOLOGY CORPORATION 1999