Datasheet LTC1735 Datasheet (Linear Technology)

FEATURES

LTC1735

High Efficiency

Synchronous Step-Down

Switching Regulator

U

DESCRIPTIO

■

Dual N-Channel MOSFET Synchronous Drive

■

Synchronizable/Programmable Fixed Frequency

■

Wide VIN Range: 3.5V to 36V Operation

■

V

Range: 0.8V to 6V

OUT

■

OPTI-LOOPTM Compensation Minimizes C

■

±

1% Output Voltage Accuracy

■

Internal Current Foldback

■

Output Overvoltage Crowbar Protection

■

Latched Short-Circuit Shutdown Timer

OUT

with Defeat Option

■

Very Low Dropout Operation: 99% Duty Cycle

■

Forced Continuous Control Pin

■

Optional Programmable Soft-Start

■

Remote Output Voltage Sense

■

Logic Controlled Micropower Shutdown: IQ < 25µA

■

LTC1435 Pin Compatible with
Minor Component Changes

■

Available in 16-Lead Narrow SSOP and SO Packages

U

APPLICATIO S

■

Notebook and Palmtop Computers, PDAs

■

Cellular Telephones and Wireless Modems

■

DC Power Distribution Systems

The LTC®1735 is a synchronous step-down switching
regulator controller that drives external N-channel power
MOSFETs using a fixed frequency architecture. Burst
ModeTM operation provides high efficiency at low load
currents. The precision 0.8V reference is compatible with
future microprocessor generations. OPTI-LOOP compen­sation allows the transient response to be optimized over
a wide range of output capacitance and ESR values.

The operating frequency (synchronizable up to 500kHz) is
set by an external capacitor allowing maximum flexibility
in optimizing efficiency. A forced continuous control pin
reduces noise and RF interference and can assist second­ary winding regulation by disabling Burst Mode operation
when the main output is lightly loaded.

Protection features include internal foldback current lim­iting, output overvoltage crowbar and optional short­circuit shutdown. Soft-start is provided by an external
capacitor that can be used to properly sequence supplies.
The operating current level is user-programmable via an
external current sense resistor. Wide input supply range
allows operation from 3.5V to 30V (36V maximum).

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

C

OSC

47pF

C

SS

0.1µF

C

C

330pF

C

100pF

1000pF

C
100pF

R
33k

U

C

OSC

RUN/SS

I

TH

C2

SGND

V

OSENSE

SENSE

SENSE

LTC1735

–

+

BOOST

INTV

PGND

TG

SW

V

IN

CC

BG

C

0.22µF

D
CMDSH-3

+

4.7µF

Figure 1. High Efficiency Step-Down Converter

M1
FDS6680A

B

B

M2
FDS6680A

L1

2µH

D1
MBRS340T3

V

IN

5V TO 24V

C

IN

22µF
50V

: PANASONIC EEFUEOG181R

C

OUT

: MARCON THCR70E1H226ZT

C

IN

L1: PANASONIC ETQP6FZR0HFA
R

SENSE

R

SENSE

0.005Ω

: IRC LRF2010-01-R005J

R1
20k
1%

R2
20k
1%

1735 F01

V

OUT

1.6V
9A

C

OUT

180µF

+

4V
×4
SP

1

LTC1735

WW

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

Input Supply Voltage (VIN).........................36V to –0.3V

Topside Driver Supply Voltage (BOOST)....42V to –0.3V

Switch Voltage (SW) ....................................36V to – 5V

EXTVCC Voltage ...........................................7V to –0.3V

Boosted Driver Voltage (BOOST – SW) .......7V to –0.3V

SENSE+, SENSE– Voltages ..........1.1 (INTVCC) to –0.3V

FCB Voltage ............................(INTVCC + 0.3V) to –0.3V

ITH, V

OSENSE

RUN/SS Voltages.........................................7V to – 0.3V

Peak Driver Output Current <10µs (TG, BG) .............. 3A

INTVCC Output Current ......................................... 50mA

Operating Ambient Temperature Range

LTC1735C ............................................... 0°C to 85°C

LTC1735I............................................ –40°C to 85°C

Junction Temperature (Note 2).............................125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

Voltages ...............................2.7V to –0.3V

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

1

C

OSC

2

RUN/SS

3

I

TH

4

FCB

5

SGND

6

V

OSENSE

–

7

SENSE

+

8

SENSE

GN PACKAGE

16-LEAD NARROW

PLASTIC SSOP

T

= 125°C, θJA = 130°C/W (GN)

JMAX

= 125°C, θJA = 110°C/W (S)

T

JMAX

Consult factory for Military grade parts.

16

TG

15

BOOST

14

SW

13

V

IN

12

INTV

CC

11

BG

10

PGND

9

EXTV

CC

S PACKAGE

16-LEAD PLASTIC SO

ORDER PART

NUMBER

LTC1735CGN
LTC1735CS
LTC1735IGN
LTC1735IS

GN PART MARKING

1735
1735I

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop

I

VOSENSE

V

OSENSE

∆V

LINEREG

∆V

LOADREG

DF Max Maximum Duty Factor In Dropout 98 99.4 %
g

m

V

FCB

I

FCB

V

OVL

I

Q

V

RUN/SS

V

RUN/SS

I

RUN/SS

I

SCL

UVLO Undervoltage Lockout Measured at VIN Pin (VIN Ramping Down) ● 3.5 3.9 V
∆V

SENSE(MAX)

Feedback Current (Note 3) –4 –25 nA
Feedback Voltage (Note 3) ● 0.792 0.8 0.808 V
Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 3) 0.001 0.02 %/V
Output Voltage Load Regulation (Note 3)

Transconductance Amplifier g
Forced Continuous Threshold ● 0.76 0.8 0.84 V
Forced Continuous Current V
Feedback Overvoltage Lockout ● 0.84 0.86 0.88 V
Input DC Supply Current (Note 4)

Normal Mode 450 µA

Shutdown V
Run Pin Start Threshold V
Run Pin Begin Latchoff Threshold V
Soft-Start Charge Current V
RUN/SS Discharge Current Soft Short Condition, V

Maximum Current Sense Threshold V

m

The ● denotes specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

Measured in Servo Loop; V
Measured in Servo Loop; V

= 0.85V – 0.17 –0.3 µA

FCB

= 0V 15 25 µA

RUN/SS

, Ramping Positive 1.0 1.5 1.9 V

RUN/SS

, Ramping Positive 4.1 4.5 V

RUN/SS

= 0V –0.7 – 1.2 µA

RUN/SS

= 4.5V

V

RUN/SS

= 0.7V ● 60 75 85 mV

OSENSE

= 0.7V ● 0.1 0.3 %

ITH

= 2V ● –0.1 –0.3 %

ITH

1.3 mmho

= 0.5V, 0.5 2 4 µA

OSENSE

2

LTC1735

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

SENSE

t

ON(MIN)

Sense Pins Total Source Current V

SENSE

–

= V

Minimum On-Time Tested with a Square Wave (Note 6) 160 200 ns

+

= 0V 60 80 µA

SENSE

TG Transition Time: (Note 7)

TG t
TG t

r
f

Rise Time C
Fall Time C

= 3300pF 50 90 ns

LOAD

= 3300pF 50 90 ns

LOAD

BG Transition Time: (Note 7)

BG t

r

BG t

f

TG/BG t

Rise Time C
Fall Time C

1D

Top Gate Off to Synchronous C

= 3300pF 50 90 ns

LOAD

= 3300pF 40 80 ns

LOAD

= 3300pF Each Driver 100 ns

LOAD

Gate On Delay Time

TG/BG t

2D

Synchronous Gate Off to Top C

= 3300pF Each Driver 70 ns

LOAD

Gate On Delay Time

Internal VCC Regulator

V

INTVCC

V

LDO(INT)

V

LDO(EXT)

V

EXTVCC

V

EXTVCC(HYS)

Internal VCC Voltage 6V < VIN < 30V, V
Internal V
EXTVCC Drop Voltage ICC = 20mA, V

Load Regulation ICC = 0 to 20mA, V

CC

EXTVCC

= 4V 5.0 5.2 5.4 V

EXTVCC

= 4V 0.2 1 %

EXTVCC

= 5V 130 200 mV
EXTVCC Switchover Voltage ICC = 20mA, EXTVCC Ramping Positive ● 4.5 4.7 V
EXTVCC Hysteresis 0.2 V

Oscillator

f

OSC

fH/f

OSC

f

FCB(SYNC)

Oscillator Frequency C

= 43pF (Note 5) 265 300 335 kHz

OSC

Maximum Sync Frequency Ratio 1.3
FCB Pin Threshold For Sync Ramping Negative 0.9 1.2 V

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: T
dissipation P

LTC1735CS, LTC1735IS: T

is calculated from the ambient temperature TA and power

J

according to the following formulas:

D

= TA + (PD • 110 °C/W)

J

LTC1735CGN, LTC1735IGN: TJ = TA + (PD • 130°C/W)
Note 3: The LTC1735 is tested in a feedback loop that servos V

the balance point for the error amplifier (V

ITH

= 1.2V).

OSENSE

to

Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.

Note 5: Oscillator frequency is tested by measuring the C
current (I

) and applying the formula:

OSC



f

OSC

8 477 10

=





CpF I I

OSC CHG DIS



11

.( )

+

()

11















–

11



+





1

OSC

charge

Note 6: The minimum on-time condition corresponds to an inductor peak­to-peak ripple current ≥40% of I

(see Minimum On-Time

MAX

Considerations in the Applications Information section).
Note 7: Rise and fall times are measured using 10% and 90% levels.

Delay times are measured using 50% levels.

3

LTC1735

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Load Current
(3 Operating Modes) Efficiency vs Load Current

100

EXTVCC OPEN

90

BURST

80

70

60

50

EFFICIENCY (%)

40

30

20

0.001

SYNC

0.01

0.1

LOAD CURRENT (A)

CONT

VIN = 10V

= 3.3V

V

OUT

R

= 0.01Ω

S

= 300kHz

f

O

1

10

1735 G01

100

EXTV

= 5V

CC

FIGURE 1

90

VIN = 5V

80

70

EFFICIENCY (%)

60

50

40

0.01 0.1 1 10

= 15V

V

IN

VIN = 24V

LOAD CURRENT (A)

1735 G02

Efficiency vs Input Voltage

100

EXTVCC = 5V

= 1.6V

V

OUT

95

FIGURE 1

90

85

I

EFFICIENCY (%)

80

75

70

0

5

OUT

10 15 20

INPUT VOLTAGE (V)

I

OUT

= 0.5A

= 5A

25 30

1735 G03

Efficiency vs Input Voltage

100

EXTVCC OPEN

= 1.6V

V

OUT

95

FIGURE 1

90

85

I

= 0.5A

EFFICIENCY (%)

80

75

70

OUT

0

10 15 20

5

INPUT VOLTAGE (V)

Input and Shutdown Currents
vs Input Voltage

500

EXTVCC OPEN

400

300

200

INPUT CURRENT (µA)

100

0

05

SHUTDOWN

EXTVCC = 5V

20

15

10

INPUT VOLTAGE (V)

I

OUT

= 5A

25

25 30

1735 G04

30

1735 G07

Load Regulation

0

–0.1

(%)

OUT

–0.2

NORMALIZED V

–0.3

–0.4

0

2

4

LOAD CURRENT (A)

VIN – V
vs Load Current

500

400

300

(mV)

OUT

– V

200

IN

V

100

R

SENSE

V

OUT

0

0

FCB = 0V

= 15V

V

IN

FIGURE 1

6

8

10

1735 G05

Dropout Voltage

OUT

= 0.005Ω

= 5V – 5% DROP

2468

LOAD CURRENT (A)

10

1735 G06

EXTVCC Switch Drop

INTVCC Line Regulation

100

SHUTDOWN CURRENT (µA)

80

60

40

20

0

35

6

1mA LOAD

5

4

3

VOLTAGE (V)

CC

2

INTV

1

0

0

510

INPUT VOLTAGE (V)

20 30 35

15 25

1735 G08

vs INTVCC Load Current

500

400

(mV)

300

CC

– INTV

200

CC

EXTV

100

0

10

0

INTVCC LOAD CURRENT (mA)

30

40

20

50

1735 G09

4

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Maximum Current Sense Threshold
vs Normalized Output Voltage
(Foldback)

80

70

60

50

40

30

20

10

MAXIMUM CURRENT SENSE THRESHOLD (mV)

0

0

25

NORMALIZED OUTPUT VOLTAGE (%)

50

75

100

1735 G10

Maximum Current Sense Threshold
vs V

RUN/SS

80

V

60

40

20

MAXIMUM CURRENT SENSE THRESHOLD (mV)

0

0

= 1.6V

SENSE(CM)

1234

V

(V)

RUN/SS

56

1735 G11

LTC1735

Maximum Current Sense Threshold
vs Sense Common Mode Voltage

80

76

72

68

64

MAXIMUM CURRENT SENSE THRESHOLD (mV)

60

1

0

COMMON MODE VOLTAGE (V)

3

2

4

5

1735 G12

Maximum Current Sense Threshold
vs ITH Voltage

90
80
70
60
50
40
30
20
10

0
–10
–20

MAXIMUM CURRENT SENSE THRESHOLD (mV)

–30

0.5

0

1.5

1

V

(V)

ITH

SENSE Pins Total Source Current

100

50

(µA)

0

SENSE

I

–50

–100

0

24

V

COMMON MODE VOLTAGE (V)

SENSE

Maximum Current Sense Threshold

V

vs Temperature

80

V

75

70

65

MAXIMUM CURRENT SENSE THRESHOLD (mV)

2

2.5

1735 G13

60

–40

= 1.6V

SENSE(CM)

–15 10 35 60

TEMPERATURE (°C)

85 110 135

1735 G18

(V)

ITH

V

ITH Voltage vs Load Current

1735 G16

2.5
VIN = 10V

= 3.3V

V

OUT

= 0.01Ω

R

SENSE

2.0
= 300kHz

f

O

CONTINUOUS

1.5

VOLTAGE (V)

1.0

TH

I

0.5

6

0

MODE

SYNCHRONIZED f = f

Burst Mode
OPERATION

0

234

1

LOAD CURRENT (A)

O

56

1735 G17

100

(%)

MAX

/I

OUT

AVERAGE OUTPUT CURRENT I

vs V

ITH

RUN/SS

2.5
V

= 0.7V

OSENSE

2.0

1.5

1.0

0.5

0

0

234

1

V

RUN/SS

(V)

Output Current vs Duty Cycle

I

(SYNC)

OUT/IMAX

80

60

40

20

f

= f

SYNC

0

O

0

20

DUTY CYCLE (%)

I

OUT/IMAX

(FREE RUN)

40 60 80

56

1735 G15

100

1735 G14

5

LTC1735

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Oscillator Frequency
vs Temperature

300

C

= 47pF

OSC

290

280

270

FREQUENCY (kHz)

260

250

–40 –15

10

TEMPERATURE (°C)

Start-Up

V

OUT

1V/DIV

V

RUN/SS

5V/DIV

RUN/SS Pin Current
vs Temperature

0

V

= 0V

RUN/SS

–1

–2

–3

RUN/SS CURRENT (µA)

–4

60

35

85

110

135

1735 G19

–5

V

OUT

10mV/DIV

–40 –15

V

OUT(RIPPLE)

I

LOAD

60

35

10

TEMPERATURE (°C)

85

110

135

1735 G20

(Synchronized)

= 10mA I

FIGURE 1 FIGURE 1

FCB Pin Current vs Temperature

0

V

= 0.85V

FCB

–0.2

–0.4

–0.6

FCB CURRENT (µA)

–0.8

–1.0

–40 –15

V

OUT(RIPPLE)

35

10

TEMPERATURE (°C)

(Burst Mode Operation)

= 50mA

LOAD

V

OUT

20mV/DIV

60

85

110

135

1735 G21

5A/DIV

V

OUT

20mV/DIV

5A/DIV

I

L

= 15V 5ms/DIV

V

IN

V

= 1.6V

OUT

= 0.16Ω

R

LOAD

V

OUT(RIPPLE)

(Burst Mode Operation)

I

= 1.5A

LOAD

I

L

FCB = 5V 5µs/DIV
V

= 15V

IN

= 1.6V

V

OUT

I

L

I

L

5A/DIV

1735 G22 1735 G23 1735 G24

EXT SYNC f = f
V

= 15V

IN

= 1.6V

V

OUT

O

10µs/DIV

5A/DIV

FCB = 5V 50µs/DIV

= 15V

V

IN

V

= 1.6V

OUT

Load Step (Burst Mode Operation) Load Step (Continuous Mode)

FIGURE 1 FIGURE 1 FIGURE 1

V

OUT

V

OUT

50mV/DIV

I

L

5A/DIV

1735 G27 1735 G26 1735 G25

10mA TO 10µs/DIV
9A LOAD STEP
FCB = 5V

= 15V

V

IN

= 1.6V

V

OUT

50mV/DIV

5A/DIV

I

L

0A TO 10µs/DIV
9A LOAD STEP
FCB = 0V

= 15V

V

IN

= 1.6V

V

OUT

6

UUU

PI FU CTIO S

C

(Pin 1): External capacitor C

OSC

ground sets the operating frequency.
RUN/SS (Pin 2): Combination of Soft-Start and Run

Control Inputs. A capacitor to ground at this pin sets the
ramp time to full output current. The time is approximately

1.25s/µF. Forcing this pin below 1.5V causes the device to
be shutdown. In shutdown all functions are disabled.
Latchoff overcurrent protection is also invoked via this pin
as described in the Applications Information section.

ITH (Pin 3): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 2.4V.

FCB (Pin 4): Forced Continuous/Synchronization Input.
Tie this pin to ground for continuous synchronous opera­tion, to a resistive divider from the secondary output when
using a secondary winding or to INTVCC to enable Burst
Mode operation at low load currents. Clocking this pin with
a signal above 1.5V
allows cycle-skipping at low load currents and synchro­nizes the internal oscillator with the external clock.

SGND (Pin 5): Small-Signal Ground. All small-signal
components such as C
the loop compensation resistors and capacitor(s) should
single-point tie to this pin. This pin should, in turn, connect
to PGND.

V

OSENSE

external resistive divider across the output.

SENSE– (Pin 7): The (–) Input to the Current Comparator.
SENSE+ (Pin 8): The (+) Input to the Current Comparator.

Built-in offsets between SENSE– and SENSE+ pins in
conjunction with R

(Pin 6): Receives the feedback voltage from an

disables Burst Mode operation but

P–P

, CSS, the feedback divider plus

OSC

set the current trip threshold.

SENSE

from this pin to

OSC

LTC1735

EXTVCC (Pin 9): Input to the Internal Switch Connected to
INTVCC. This switch closes and supplies VCC power when­ever EXTVCC is higher than 4.7V. See EXTVCC connection
in the Applications Information section. Do not exceed 7V
on this pin and ensure EXTVCC ≤ VIN.

PGND (Pin 10): Driver Power Ground. Connects to the
source of bottom N-channel MOSFET, the anode of the
Schottky diode, and the (–) terminal of CIN.

BG (Pin 11): High Current Gate Drive for Bottom
N-Channel MOSFET. Voltage swing at this pin is from
ground to INTVCC.

INTVCC (Pin 12): Output of the Internal 5.2V Regulator and
EXTVCC Switch. The driver and control circuits are pow­ered from this voltage. Decouple to power ground with a
1µF ceramic capacitor placed directly adjacent to the IC
together with a minimum of 4.7µF tantalum or other low
ESR capacitor.

VIN (Pin 13): Main Supply Pin. Must be closely decoupled
to power ground.

SW (Pin 14): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground to
VIN.

BOOST (Pin 15): Supply to Topside Floating Driver. The
bootstrap capacitor is returned to this pin. Voltage swing
at this pin is from a diode drop below INTVCC to (VIN +
INTVCC).

TG (Pin 16): High Current Gate Drive for Top N-Channel
MOSFET. This is the output of a floating driver with a
voltage swing equal to INTVCC superimposed on the
switch node voltage SW.

7

LTC1735

UU

W

FU CTIO AL DIAGRA

C

OSC

1 5 4

OSC

SYNC

OSC

OV

+
–

0.86V

V

OSENSE

V

FB

6

0.8V

R2

R1

1.2µA

6V

RUN/SS

C

SS

2

gm =1.3m

–

EA

+

CURRENT

LATCHOFF

SD

RUN

SOFT-

START

+

OVER-

C

C

Ω

R

C

0.86V

4(V

)

FB

SLOPE COMP

I

TH

ICMP

BURST
DISABLE
FC

0.17µA

C

–
+

1.2V 0.8V

FORCE BOT

S

R

2.4V

–

I

1

+

A

BUFFERED
I

TH

SENSE

Q

2k

+– –+

+

FCBSGNDC

DROP

OUT

DET

TOP ON

45k

3mV

30k 30k

0.55V

BOT

–
+

+
–

45k

–
+

SENSE

V

IN

V

13

IN

UVL

0.8V
REF

FC

F

TOP

SWITCH

LOGIC

B

SD

IREV

I

2

INTV

4.7V

–

BOT

V

IN

CC

5.2V
LDO
REG

+
–

EXTV

CC

BOOST

15

TG

16

SW

14

9783

INTV

CC

D

B

C

B

D

1

INTV

C

INTVCC

PGND

CC

12

BG

11

10

+

C

IN

V

SEC

+

C

SEC

V

OUT

+

C

OUT

+

8

R

SENSE

1735 FD

OPERATIO

LTC1735

U

(Refer to Functional Diagram)

Main Control Loop

The LTC1735 uses a constant frequency, current mode
step-down architecture. During normal operation, the top
MOSFET is turned on each cycle when the oscillator sets
the RS latch and turned off when the main current com­parator I1 resets the RS latch. The peak inductor current at
which I1 resets the RS latch is controlled by the voltage on
Pin 3 (ITH), which is the output of error amplifier EA. Pin␣ 6
(V

OSENSE

receive an output feedback voltage VFB from an external
resistive divider. When the load current increases, it
causes a slight decrease in VFB relative to the 0.8V refer­ence, which in turn causes the ITH voltage to increase until
the average inductor current matches the new load cur­rent. While the top MOSFET is off, the bottom MOSFET is
turned on until either the inductor current starts to reverse,
as indicated by current comparator I2, or the beginning of
the next cycle.

The top MOSFET driver is powered from a floating boot­strap capacitor CB. This capacitor is normally recharged
from INTVCC through an external diode when the top
MOSFET is turned off. As VIN decreases towards V
converter will attempt to turn on the top MOSFET continu­ously (“dropout’’). A dropout counter detects this condi­tion and forces the top MOSFET to turn off for about 500ns
every tenth cycle to recharge the bootstrap capacitor.

), described in the pin functions, allows EA to

, the

OUT

conditions that may overvoltage the output. In this case,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.

Foldback current limiting for an output shorted to ground
is provided by amplifier A. As V
the buffered ITH input to the current comparator is gradu­ally pulled down to a 0.86V clamp. This reduces peak
inductor current to about 1/4 of its maximum value.

Low Current Operation

The LTC1735 has three low current modes controlled by
the FCB pin. Burst Mode operation is selected when the
FCB pin is above 0.8V (typically tied to INTVCC). In Burst
Mode operation, if the error amplifier drives the ITH voltage
below 0.86V, the buffered ITH input to the current com­parator will be clamped at 0.86V. The inductor current
peak is then held at approximately 20mV/R
1/4 of maximum output current). If ITH then drops below

0.5V, the Burst Mode comparator B will turn off both
MOSFETs to maximize efficiency. The load current will be
supplied solely by the output capacitor until ITH rises
above the 60mV hysteresis of the comparator and switch­ing is resumed. Burst Mode operation is disabled by
comparator F when the FCB pin is brought below 0.8V.
This forces continuous operation and can assist second­ary winding regulation.

OSENSE

drops below 0.6V,

(about

SENSE

The main control loop is shut down by pulling Pin 2
(RUN/SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with the
ITH voltage clamped at approximately 30% of its maximum
value. As CSS continues to charge, ITH is gradually re­leased allowing normal operation to resume. If V
not reached 70% of its final value when CSS has charged
to 4.1V, latchoff can be invoked as described in the
Applications Information section.

The internal oscillator can be synchronized to an external
clock applied to the FCB pin and can lock to a frequency
between 90% and 130% of its nominal rate set by capaci­tor C

An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious

OSC

.

OUT

has

When the FCB pin is driven by an external oscillator, a low
noise cycle-skipping mode is invoked and the internal
oscillator is synchronized to the external clock by com­parator C. In this mode the 25% minimum inductor
current clamp is removed, providing constant frequency
discontinuous operation over the widest possible output
current range. This constant frequency operation is not
quite as efficient as Burst Mode operation, but provides a
lower noise, constant frequency spectrum.

The FCB pin is tied to ground when forced continuous
operation is desired. This is the least efficient mode, but is
desirable in certain applications. The output can source or
sink current in this mode. When sinking current while in
forced continuous operation, current will be forced back
into the main power supply potentially boosting the input
supply to dangerous voltage levels—BEWARE.

9

LTC1735

OPERATIO

U

(Refer to Functional Diagram)

Foldback Current, Short-Circuit Detection and
Short-Circuit Latchoff

The RUN/SS capacitor, CSS, is used initially to limit the
inrush current of the switching regulator. After the con­troller has been started and been given adequate time to
charge up the output capacitors and provide full load cur­rent, CSS is used as a short-circuit time-out circuit. If the
output voltage falls to less than 70% of its nominal output
voltage, CSS begins discharging on the assumption that
the output is in an overcurrent and/or short-circuit condi­tion. If the condition lasts for a long enough period as
determined by the size of CSS, the controller will be shut
down until the RUN/SS pin voltage is recycled. This built­in latchoff can be overridden by providing a current >5µA
at a compliance of 5V to the RUN/SS pin. This current
shortens the soft-start period but also prevents net dis­charge of C
condition. Foldback current limiting is activated when the

during an overcurrent and/or short-circuit

SS

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APPLICATIO S I FOR ATIO

output voltage falls below 70% of its nominal level whether
or not the short-circuit latchoff circuit is enabled.

INTVCC/EXTVCC POWER

Power for the top and bottom MOSFET drivers and most
of the internal circuitry of the LTC1735 is derived from the
INTVCC pin. When the EXTVCC pin is left open, an internal

5.2V low dropout regulator supplies the INTVCC power
from VIN. If EXTVCC is raised above 4.7V, the internal
regulator is turned off and an internal switch connects
EXTVCC to INTVCC. This allows a high efficiency source,
such as the primary or a secondary output of the converter
itself, to provide the INTVCC power. Voltages up to 7V can
be applied to EXTVCC for additional gate drive capability.

To provide clean start-up and to protect the MOSFETs,
undervoltage lockout is used to keep both MOSFETs off
until the input voltage is above 3.5V.

The basic LTC1735 application circuit is shown in Figure␣ 1
on the first page. External component selection is driven
by the load requirement and begins with the selection of
R
Next, the power MOSFETs and D1 are selected. The
operating frequency and the inductor are chosen based
largely on the desired amount of ripple current. Finally, C
is selected for its ability to handle the large RMS current
into the converter and C
ESR to meet the output voltage ripple and transient speci­fications. The circuit shown in Figure 1 can be configured
for operation up to an input voltage of 28V (limited by the
external MOSFETs).

R

R
The LTC1735 current comparator has a maximum thresh­old of 75mV/R
SGND to 1.1(INTVCC). The current comparator threshold
sets the peak of the inductor current, yielding a maximum
average output current I
half the peak-to-peak ripple current, ∆IL.

. Once R

SENSE

Selection for Output Current

SENSE

is chosen based on the required output current.

SENSE

is known, C

SENSE

is chosen with low enough

OUT

and an input common mode range of

SENSE

equal to the peak value less

MAX

and L can be chosen.

OSC

IN

Allowing a margin for variations in the LTC1735 and
external component values yields:

mV

R

SENSE

C

Selection for Operating Frequency and

OSC

Synchronization

The choice of operating frequency and inductor value is a
trade-off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses, both gate charge loss and
transition loss. However, lower frequency operation re­quires more inductance for a given amount of ripple
current.

The LTC1735 uses a constant frequency architecture with
the frequency determined by an external oscillator capaci­tor C

OSC

voltage on C
C

is charged by a fixed current. When the voltage on the

OSC

50

=

I

MAX

. Each time the topside MOSFET turns on, the

is reset to ground. During the on-time,

OSC

10

LTC1735

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APPLICATIO S I FOR ATIO

capacitor reaches 1.19V, C
process then repeats.

The value of C

is calculated from the desired operating

OSC

frequency assuming no external clock input on the FCB
pin:



16110

CpF

()

OSC



Frequency





A graph for selecting C

7

.( )

OSC

Figure 2. The maximum recommended switching fre­quency is 550kHz .

The internal oscillator runs at its nominal frequency (fO)
when the FCB pin is pulled high to INTVCC or connected to
ground. Clocking the FCB pin above and below 0.8V will
cause the internal oscillator to injection lock to an external
clock signal applied to the FCB pin with a frequency
between 0.9fO and 1.3fO. The clock high level must exceed

1.3V for at least 0.3µs and the clock low level must be less
than 0.3V for at least 0.3µs. The top MOSFET turn-on will
synchronize with the rising edge of the clock.

Attempting to synchronize to too high an external fre­quency (above 1.3fO) can result in inadequate slope com­pensation and possible loop instability. If this condition
exists simply lower the value of C
to Figure 2.

When synchronized to an external clock, Burst Mode
operation is disabled but the inductor current is not

100.0

87.5

75.0

62.5

50.0

VALUE (pF)

37.5

OSC

C

25.0

12.5

0

0 100 200 300 400 500 600

OPERATING FREQUENCY (kHZ)

is reset to ground. The

OSC




11

–=





versus frequency is shown in

OSC

so f

= fO according

EXT

1735 F02

allowed to reverse. The 25% minimum inductor current
clamp present in Burst Mode operation is removed,
providing constant frequency discontinuous operation
over the widest possible output current range. In this
mode the synchronous MOSFET is forced on once every
10 clock cycles to recharge the bootstrap capacitor. This
minimizes audible noise while maintaining reasonably
high efficiency.

Inductor Value Calculation

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic trade
off, the effect of inductor value on ripple current and low
current operation must also be considered.

The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL decreases with higher induc­tance or frequency and increases with higher VIN or V

∆I

1

=

L OUT

fL

()()



V

1

–




V

OUT

V

IN





OUT

:

Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.3 to 0.4(I

). Remember,

MAX

the maximum ∆IL occurs at the maximum input voltage.
The inductor value also has an effect on low current

operation. The transition to low current operation begins
when the inductor current reaches zero while the bottom
MOSFET is on. Burst Mode operation begins when the
average inductor current required results in a peak current
below 25% of the current limit determined by R

SENSE

.

Lower inductor values (higher ∆IL) will cause this to occur
at higher load currents, which can cause a dip in efficiency
in the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.

Figure 2. Timing Capacitor Value

11

LTC1735

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APPLICATIO S I FOR ATIO

Inductor Core Selection

Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af­ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. Actual core loss is independent of
core size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance re­quires more turns of wire and therefore copper losses will
increase.

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con­centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc­tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!

Selection criteria for the power MOSFETs include the “ON”
resistance R
input voltage and maximum output current. When the
LTC1735 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:

Main SwitchDuty Cycle

Synchronous Switch Duty Cycle

The MOSFET power dissipations at maximum output
current are given by:

P

MAIN

V

=

kV I C f

()( )( )()

, reverse transfer capacitance C

DS(ON)

V

OUT

=

V

IN

VV

=

OUT

V

IN

2

IN MAX RSS

2

IR

()

MAX DS ON

+

1

δ

()

()

–

IN OUT

V

IN

+

RSS

,

Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu­facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be­cause they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
that do not increase the height significantly.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for use
with the LTC1735: An N-channel MOSFET for the top
(main) switch and an N-channel MOSFET for the bottom
(synchronous) switch.

The peak-to-peak gate drive levels are set by the INTV
voltage. This voltage is typically 5.2V during start-up (see
EXTVCC pin connection). Consequently, logic-level thresh­old MOSFETs must be used in most LTC1735 applica­tions. The only exception is when low input voltage is
expected (VIN < 5V); then, sub-logic level threshold
MOSFETs (V
attention to the BV
well; many of the logic level MOSFETs are limited to 30V
or less.

< 3V) should be used. Pay close

GS(TH)

specification for the MOSFETs as

DSS

CC

–

VV

P

SYNC

where δ is the temperature dependency of R
is a constant inversely related to the gate drive current.

Both MOSFETs have I2R losses while the topside
N-channel equation includes an additional term for transi­tion losses, which are highest at high input voltages. For
VIN < 20V the high current efficiency generally improves
with larger MOSFETs, while for VIN > 20V the transition
losses rapidly increase to the point that the use of a higher
R

DS(ON)

efficiency. The synchronous MOSFET losses are greatest
at high input voltage or during a short-circuit when the
duty cycle in this switch is nearly 100%.

The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
δ␣ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C
MOSFET characteristics. The constant k = 1.7 can be
used to estimate the contributions of the two terms in the
main switch dissipation equation.

Kool Mµ is a registered trademark of Magnetics, Inc.

IN OUT

=

V

IN

device with lower C

DS(ON)

RSS

2

IR

()

MAX DS ON

is usually specified in the

+

1

δ

()

actually provides higher

RSS

vs Temperature curve, but

()

DS(ON)

and k

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APPLICATIO S I FOR ATIO

The Schottky diode D1 shown in Figure 1 conducts during the
dead-time between the conduction of the two power MOSFETs.
This prevents the body diode of the bottom MOSFET from
turning on and storing charge during the dead-time, which
could cost as much as 1% in efficiency. A 3A Schottky is
generally a good size for 10A to 12A regulators due to the
relatively small average current. Larger diodes can result in
additional transition losses due to their larger junction capaci­tance. The diode may be omitted if the efficiency loss can be
tolerated.

CIN Selection

In continuous mode, the source current of the top
N-channel MOSFET is a square wave of duty cycle V
VIN. To prevent large voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS capacitor current is given by:

12

II

≅

RMS O MAX

()



V

OUT



V



ININOUT

V

V

–1

/






OUT

/

increases with input voltage. Typically, once the ESR
requirement for C
rating generally far exceeds the I
With ∆IL = 0.3I

OUT(MAX)

to ESR the output ripple will be less than 50mV at max V

has been met, the RMS current

OUT

RIPPLE(P–P)

requirement.

and allowing 2/3 of the ripple due

IN

assuming:

C

required ESR < 2.2 R

C

OUT

OUT

> 1/(8fR

SENSE

)

SENSE

The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran­tees that the output capacitance does not significantly
discharge during the operating frequency period due to
ripple current. The choice of using smaller output capaci­tance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage at or below
50mV. The ITH pin OPTI-LOOP compensation compo­nents can be optimized to provide stable, high perfor­mance transient response regardless of the output capaci­tors selected.

This formula has a maximum at VIN = 2V
I

RMS

␣=␣I

/2. This simple worst case condition is com-

O(MAX)

OUT

, where

monly used for design because even significant deviations do
not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours of
life. This makes it advisable to further derate the capacitor or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult the
manufacturer if there is any question.

C

Selection

OUT

The selection of C

is primarily determined by the

OUT

effective series resistance (ESR) to minimize voltage
ripple. The output ripple (∆V

) in continuous mode is

OUT

determined by:

∆∆V I ESR

≈+

OUT L





8

Where f = operating frequency, C



fC

1

OUT






= output capaci-

OUT

tance and ∆IL = ripple current in the inductor. The output
ripple is highest at maximum input voltage since ∆I

L

The selection of output capacitors for CPU or other appli­cations with large load current transients is primarily
determined by the voltage tolerance specifications of the
load. The resistive component of the capacitor, ESR,
multiplied by the load current change plus any output
voltage ripple must be within the voltage tolerance of the
load (CPU).

The required ESR due to a load current step is:

R

< ∆V/∆I

ESR

where ∆I is the change in current from full load to zero load
(or minimum load) and ∆V is the allowed voltage deviation
(not including any droop due to finite capacitance).

The amount of capacitance needed is determined by the
maximum energy stored in the inductor. The capacitance
must be sufficient to absorb the change in inductor current
when a high current to low current transition occurs. The
opposite load current transition is generally determined by
the control loop OPTI-LOOP components, so make sure
not to over compensate and slow down the response. The
minimum capacitance to assure the inductors’ energy is
adequately absorbed is:

13

LTC1735

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APPLICATIO S I FOR ATIO

LI

()

C

>

OUT

where ∆I is the change in load current.
Manufacturers such as Nichicon, United Chemicon and

Sanyo can be considered for high performance through­hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.

In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Spe­cial polymer surface mount capacitors offer very low ESR
but have much lower capacitive density per unit volume
than other capacitor types. These capacitors offer a very
cost-effective output capacitor solution and are an ideal
choice when combined with a controller having high loop
bandwidth. Tantalum capacitors offer the highest capaci­tance density and are often used as output capacitors for
switching regulators having controlled soft-start. Several
excellent surge-tested choices are the AVX TPS, AVX
TPSV or the KEMET T510 series of surface mount
tantalums, available in case heights ranging from 2mm to
4mm. Aluminum electrolytic capacitors can be used in
cost-driven applications providing that consideration is
given to ripple current ratings, temperature and long-term
reliability. A typical application will require several to many
aluminum electrolytic capacitors in parallel. A combina­tion of the above mentioned capacitors will often result in
maximizing performance and minimizing overall cost.
Other capacitor types include Nichicon PL series, NEC
Neocap, Panasonic SP and Sprague 595D series. Consult
manufacturers for other specific recommendations.

Like all components, capacitors are not ideal. Each ca­pacitor has its own benefits and limitations. Combina­tions of different capacitor types have proven to be a very
cost effective solution. Remember also to include high
frequency decoupling capacitors. They should be placed

∆

VV

()

∆22

OUT

as close as possible to the power pins of the load. Any
inductance present in the circuit board traces negates
their usefulness.

INTVCC Regulator

An internal P-channel low dropout regulator produces the

5.2V supply that powers the drivers and internal circuitry
within the LTC1735. The INTVCC pin can supply a maxi­mum RMS current of 50mA and must be bypassed to
ground with a minimum of 4.7µF tantalum, 10µF special
polymer or low ESR type electrolytic capacitor. A 1µF
ceramic capacitor placed directly adjacent to the INTV
and PGND IC pins is highly recommended. Good bypass­ing is required to supply the high transient currents
required by the MOSFET gate drivers.

Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi­mum junction temperature rating for the LTC1735 to be
exceeded. The system supply current is normally domi­nated by the gate charge current. Additional loading of
INTVCC also needs to be taken into account for the power
dissipation calculations. The total INTVCC current can be
supplied by either the 5.2V internal linear regulator or by
the EXTVCC input pin. When the voltage applied to the
EXTVCC pin is less than 4.7V, all of the INTVCC current is
supplied by the internal 5.2V linear regulator. Power
dissipation for the IC in this case is highest: (VIN)(I
and overall efficiency is lowered. The gate charge is
dependent on operating frequency as discussed in the
Efficiency Considerations section. The junction tempera­ture can be estimated by using the equations given in
Note␣ 2 of the Electrical Characteristics. For example, the
LTC1735CS is limited to less than 17mA from a 30V
supply when not using the EXTVCC pin as follows:

TJ = 70°C + (17mA)(30V)(110°C/W) = 126°C

Use of the EXTVCC input pin reduces the junction tempera­ture to:

TJ = 70°C + (17mA)(5V)(110°C/W) = 79°C

To prevent maximum junction temperature from being
exceeded, the input supply current must be checked
operating in continuous mode at maximum VIN.

CC

INTVCC

)

14

LTC1735

EXTV

CC

FCB

SGND

V

IN

TG

SW

BG

PGND

LTC1735

R

SENSE

V

OUT

V

SEC

6.8V

+

C

OUT

+

1µF

1735 F03a

N-CH

N-CH

R4

+

C

IN

V

IN

L1

1:N

1N4148

OPTIONAL EXTV

CC

CONNECTION
5V ≤ V

SEC

≤ 7V

R3

EXTV

CC

V

IN

TG

SW

BG

PGND

LTC1735

R

SENSE

V

OUT

VN2222LL

+

C

OUT

1735 F03b

N-CH

N-CH

+

C

IN

+

1µF

V

IN

L1

BAT85 BAT85

BAT85

0.22µF

VV

R
R

OUT

=+











08 1

2
1

.

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APPLICATIO S I FOR ATIO

EXTVCC Connection

The LTC1735 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
Whenever the EXTVCC pin is above 4.7V the internal 5.2V
regulator shuts off, the switch closes and INTVCC power is
supplied via EXTVCC until EXTVCC drops below 4.5V. This
allows the MOSFET gate drive and control power to be
derived from the output or other external source during
normal operation. When the output is out of regulation
(start-up, short circuit) power is supplied from the internal
regulator. Do not apply greater than 7V to the EXTVCC pin
and ensure that EXTVCC ≤ VIN.

Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
simply means connecting the EXTVCC pin directly to V
However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTVCC power
from the output.

OUT

.

MOSFET gate drive requirements. This is the typical case
as the 5V power is almost always present and is derived by
another high efficiency regulator.

Figure 3a. Secondary Output Loop and EXTVCC Connection

The following list summarizes the four possible connec­tions for EXTV

1. EXTVCC left open (or grounded). This will cause INTV
to be powered from the internal 5.2V regulator resulting in
an efficiency penalty of up to 10% at high input voltages.

2. EXTVCC connected directly to V
connection for a 5V output regulator and provides the
highest efficiency. For output voltages higher than 5V,
EXTVCC is required to connect to V
absolute maximum ratings are not exceeded.

3. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency gains
can still be realized by connecting EXTVCC to an output­derived voltage that has been boosted to greater than

4.7V. This can be done with either the inductive boost
winding as shown in Figure 3a or the capacitive charge
pump shown in Figure 3b. The charge pump has the
advantage of simple magnetics.

4. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 7V range (EXTV
such as notebook main 5V system power, it may be used
to power EXTVCC providing it is compatible with the

CC:

. This is the normal

OUT

so the SENSE pins’

OUT

CC

CC

≤ VIN),

Figure 3b. Capacitive Charge Pump for EXTV

CC

Output Voltage Programming

The output voltage is set by an external resistive divider
according to the following formula:

The resistive divider is connected to the output as shown
in Figure 4 allowing remote voltage sensing.

15

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APPLICATIO S I FOR ATIO

V

OUT

R2

V

OSENSE

R1

LTC1735

SGND

Figure 4. Setting the LTC1735 Output Voltage

Topside MOSFET Driver Supply (CB, DB)

An external bootstrap capacitor CB connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFET. Capacitor CB in the Functional Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. Note that the voltage across CB is about a diode
drop below INTVCC. When the topside MOSFET is to be
turned on, the driver places the CB voltage across the
gate-source of the MOSFET. This enhances the MOSFET
and turns on the topside switch. The switch node voltage
SW rises to VIN and the BOOST pin rises to VIN + INTVCC.
The value of the boost capacitor CB needs to be 100 times
greater than the total input capacitance of the topside
MOSFET. In most applications 0.1µF to 0.33µF is ad-
equate. The reverse breakdown on DB must be greater
than V

IN(MAX)

.

When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If you make a change
and the input current decreases, then you improved the
efficiency. If there is no change in input current, then there
is no change in efficiency.

47pF

1735 F04

V

resistive divider. The maximum current flowing out

OUT

of the sense pins is:

I

SENSE

Since V

+

+ I

OSENSE

–

SENSE

= (2.4V – V

OUT

)/24k

is servoed to the 0.8V reference voltage, we
can choose R1 in Figure 4 to have a maximum value to
absorb this current:



08

Rk

124

=

MAX

()





.

VV

24

.–

V

OUT






Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that at output voltages above

2.4V no maximum value of R1 is necessary to absorb the
sense pin currents; however, R1 is still bounded by the
V

OSENSE

feedback current.

Soft-Start/Run Function

The RUN/SS pin is a multipurpose pin that provides a soft­start function and a means to shut down the LTC1735.
Soft-start reduces surge currents from VIN by gradually
increasing the controller’s current limit I

TH(MAX)

. This pin

can also be used for power supply sequencing.
Pulling the RUN/SS pin below 1.5V puts the LTC1735 into

a low quiescent current shutdown (IQ < 25µA). This pin can
be driven directly from logic as shown in Figure 5. Releas­ing the RUN/SS pin allows an internal 1.2µA current
source to charge up the external soft-start capacitor C

SS.

If RUN/SS has been pulled all the way to ground there is
a delay before starting of approximately:

SENSE+/SENSE– Pins

The common mode input range of the current comparator
is from 0V to 1.1(INTVCC). Continuous linear operation in
step-down applications is guaranteed throughout this
range allowing output voltages anywhere from 0.8V to 7V.
A differential NPN input stage is used and is biased with
internal resistors from an internal 2.4V source as shown
in the Functional Diagram. This causes current to either be
sourced or sunk by the sense pins depending on the
output voltage. If the output voltage is below 2.4V current
will flow out of both sense pins to the main output. This
forces a minimum load current that can be fulfilled by the

16

15

.

t

DELAY SS SS

=

12

.

V

CsFC

A

µ

125

./

=µ

()

When the voltage on RUN/SS reaches 1.5V the LTC1735
begins operating with a current limit at approximately
25mV/R

. As the voltage on the RUN/SS pin increases

SENSE

from 1.5V to 3.0V, the internal current limit is increased
from 25mV/R

SENSE

to 75mV/R

. The output current

SENSE

limit ramps up slowly, taking an additional 1.25s/µF to
reach full current. The output current thus ramps up
slowly, reducing the starting surge current required from
the input power supply.

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APPLICATIO S I FOR ATIO

Diode D1 in Figure 5 reduces the start delay while allowing
CSS to charge up slowly for the soft-start function. This
diode and C
The RUN/SS pin has an internal 6V zener clamp (See
Functional Diagram).

3.3V OR 5V RUN/SS RUN/SS

Fault Conditions: Overcurrent Latchoff

The RUN/SS pin also provides the ability to shut off the
controller and latch off when an overcurrent condition is
detected. The RUN/SS capacitor, CSS, is used initially to
turn on and limit the inrush current of the controller. After
the controller has been started and given adequate time to
charge up the output capacitor and provide full load
current, CSS is used as a short-circuit timer. If the output
voltage falls to less than 70% of it’s nominal output voltage

after CSS reaches 4.1V

output is in a severe overcurrent and/or short-circuit
condition and CSS begins discharging. If the condition
lasts for a long enough period as determined by the size of
CSS, the controller will be shut down until the RUN/SS pin
voltage is recycled.

This built-in latchoff can be overridden by providing a
current >5µA at a compliance of 5V to the RUN/SS pin as
shown in Figure␣ 6. This current shortens the soft-start
period but also prevents net discharge of the RUN/SS

3.3V OR 5V RUN/SS

Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated

can be deleted if soft-start is not needed.

SS

D1

C

SS

Figure 5. RUN/SS Pin Interfacing

C

1735 F05

, the assumption is made that the

V

IN

R

D1

SS

C

SS

(a) (b)

INTV

CC

R

SS

RUN/SS

D1

C

1735 F06

SS

SS

capacitor during a severe overcurrent and/or short-circuit
condition. When deriving the 5µA current from VIN as in
Figure␣ 6a, current latchoff is always defeated. Diode con­necting this pull-up resistor to INTVCC , as in Figure␣ 6b,
eliminates any extra supply current during controller shut­down while eliminating the INTV

loading from prevent-

CC

ing controller start-up. If the voltage on CSS does not
exceed 4.1V the overcurrent latch is not armed and the
function is disabled.

Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off. Defeating this feature will easily allow trouble­shooting of the circuit and PC layout. The internal short­circuit and foldback current limiting still remains active,
thereby protecting the power supply system from failure.
After the design is complete, a decision can be made
whether to enable the latchoff feature.

The value of the soft-start capacitor CSS will need to be
scaled with output current, output capacitance and load
current characteristics. The minimum soft-start capaci­tance is given by:

CSS > (C

OUT

)(V

)(10–4)(R

OUT

SENSE

)

The minimum recommended soft-start capacitor of
CSS␣=␣0.1µF will be sufficient for most applications.

Fault Conditions: Current Limit and Current Foldback

The LTC1735 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET current
of 75mV/R

SENSE

.

The LTC1735 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is defeated. If the output
falls by more than half, then the maximum sense voltage
is progressively lowered from 75mV to 30mV. Under
short-circuit conditions with very low duty cycle, the
LTC1735 will begin cycle skipping in order to limit the
short-circuit current. In this situation the bottom MOSFET
will be conducting the peak current. The short-circuit
ripple current is determined by the minimum on-time

17

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t

ON(MIN)

voltage and inductor value:

The resulting short-circuit current is:

The current foldback function is always active and is not
effected by the current latchoff function.

Fault Conditions: Output Overvoltage Protection
(Crowbar)

The output overvoltage crowbar is designed to blow a
system fuse in the input lead when the output of the
regulator rises much higher than nominal levels. This
condition causes huge currents to flow, much greater than
in normal operation. This feature is designed to protect
against a shorted top MOSFET; it does not protect against
a failure of the controller itself.

The comparator (OV in the Functional Diagram) detects
overvoltage faults greater than 7.5% above the nominal
output voltage. When this condition is sensed the top
MOSFET is turned off and the bottom MOSFET is forced
on. The bottom MOSFET remains on continuously for as
long as the 0V condition persists; if V
level, normal operation automatically resumes.

Note that dynamically changing the output voltage may
cause overvoltage protection to be momentarily activated
during programmed output voltage decreases. This will
not cause permanent latchoff nor will it disrupt the desired
voltage change. With soft-latch overvoltage protection,
dynamically changing the output voltage is allowed and
the overvoltage protection tracks the newly programmed
output voltage, always protecting the load.

of the LTC1735 (approximately 200ns), the input

∆I

= t

I

SC

L(SC)

ON(MIN)VIN

mV

30 1

=+

R

SENSE

/L

I

∆

LSC

()

2

returns to a safe

OUT

the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum on­time limit and care should be taken to ensure that:

V

t

ON MIN

()

<

Vf

OUT

()

IN

If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1735 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and voltage will increase.

The minimum on-time for the LTC1735 in a properly
configured application is generally less than 200ns. How­ever, as the peak sense voltage decreases, the minimum
on-time gradually increases as shown in Figure 7. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre­spondingly larger current and voltage ripple.

If an application can operate close to the minimum on­time limit, an inductor must be chosen that is low enough
to provide sufficient ripple amplitude to meet the mini­mum on-time requirement.

As a general rule keep the
inductor ripple current equal or greater than 30% of
I

OUT(MAX)

at V

IN(MAX)

250

200

150

100

MINIMUM ON-TIME (ns)

50

.

Minimum On-Time Considerations

Minimum on-time t

ON(MIN)

is the smallest amount of time
that the LTC1735 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and

18

0

0

10

Figure 7. Minimum On-Time vs ∆I

∆IL/I

20

OUT(MAX)

30

(%)

40

1735 F07

L

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APPLICATIO S I FOR ATIO

FCB Pin Operation

When the FCB pin drops below its 0.8V threshold, continu­ous mode operation is forced. In this case, the top and
bottom MOSFETs continue to be driven synchronously
regardless of the load on the main output. Burst Mode
operation is disabled and current reversal is allowed in the
inductor.

In addition to providing a logic input to force continuous
synchronous operation and external synchronization, the
FCB pin provides a means to regulate a flyback winding
output. During continuous mode, current flows continu­ously in the transformer primary. The secondary winding(s)
draw current only when the bottom, synchronous switch
is on. When primary load currents are low and/or the VIN/
V

ratio is low, the synchronous switch may not be on

OUT

for a sufficient amount of time to transfer power from the
output capacitor to the secondary load. Forced continuous
operation will support secondary windings providing there
is sufficient synchronous switch duty factor. Thus, the
FCB input pin removes the requirement that power must
be drawn from the inductor primary in order to extract
power from the auxiliary windings. With the loop in
continuous mode, the auxiliary outputs may nominally be
loaded without regard to the primary output load.

The secondary output voltage V
shown in Figure␣ 3a by the turns ratio N of the transformer:

V

≅ (N + 1)V

SEC

OUT

However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V
V

SEC

If V

will droop. An external resistive divider from

SEC

to the FCB pin sets a minimum voltage V

VV

SEC MIN()

drops below this level, the FCB voltage forces

SEC

.≈+

08 1









R

4



R

3



continuous switching operation until V
its minimum.

In order to prevent erratic operation if no external connec­tions are made to the FCB pin, the FCB pin has a 0.17µA

is normally set as

SEC

SEC(MIN)

is again above

SEC

:

internal current source pulling the pin high. Remember to
include this current when choosing resistor values R3 and
R4.

The internal LTC1735 oscillator can be synchronized to an
external oscillator by applying and clocking the FCB pin
with a signal above 1.5V

. When synchronized to an

P–P

external frequency, Burst Mode operation is disabled but
cycle skipping is allowed at low load currents since current
reversal is inhibited. The bottom gate will come on every
10 clock cycles to assure the bootstrap cap is kept re­freshed. The rising edge of an external clock applied to the
FCB pin starts a new cycle.

The range of synchronization is from 0.9fO to 1.3fO, with
fO set by C

. Attempting to synchronize to a higher

OSC

frequency than 1.3fO can result in inadequate slope com­pensation and cause loop instability with high duty cycles
(duty cycle > 50%). If loop instability is observed while
synchronized, additional slope compensation can be ob­tained by simply decreasing C

OSC

.

The following table summarizes the possible states avail­able on the FCB pin:

Table 1

FCB Pin Condition

DC Voltage: 0V to 0.7V Burst Disabled/Forced Continuous

Current Reversal Enabled

DC Voltage: ≥ 0.9V Burst Mode Operation,

No Current Reversal
Feedback Resistors Regulating a Secondary Winding
Ext Clock: (0V to V

(V

FCBSYNC

) Burst Mode Operation Disabled

FCBSYNC

> 1.5V) No Current Reversal

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + …)

where L1, L2, etc. are the individual losses as a percentage
of input power.

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Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC1735 circuits: 1) LTC1735 VIN current,

2)␣ INTVCC current, 3) I2R losses, 4) Topside MOSFET
transition losses.

1) The VIN current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. VIN current results in a small (<0.1%)
loss that increases with VIN.

2) INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTVCC to
ground. The resulting dQ/dt is a current out of INTVCC that
is typically much larger than the control circuit current. In
continuous mode, I

GATECHG

are the gate charges of the topside and bottom-side
MOSFETs.

Supplying INTV

power through the EXTVCC switch input

CC

from an output-derived or other high efficiency source will
scale the V

current required for the driver and control

IN

circuits by a factor of (Duty Cycle)/(Efficiency). For ex­ample, in a 20V to 5V application, 10mA of INTVCC current
results in approximately 3mA of VIN current. This reduces
the mid-current loss from 10% or more (if the driver was
powered directly from VIN) to only a few percent.

3) I2R losses are predicted from the DC resistances of the
MOSFET, inductor and current shunt. In continuous mode
the average output current flows through L and R
but is “chopped” between the topside main MOSFET and
the synchronous MOSFET. If the two MOSFETs have
approximately the same R
one MOSFET can simply be summed with the resistances
of L and R
R

= 0.03Ω, RL = 0.05Ω and R

DS(ON)

to obtain I2R losses. For example, if each

SENSE

the total resistance is 0.09Ω. This results in losses ranging
from 2% to 9% as the output current increases from 1A to
5A for a 5V output, or a 3% to 14% loss for a 3.3V output.
Effeciency varies as the inverse square of V
same external components and output power level. I2R
losses cause the efficiency to drop at high output currents.

= f(QT+QB), where QT and Q

SENSE

, then the resistance of

DS(ON)

= 0.01Ω, then

SENSE

for the

OUT

B

,

4) Transition losses apply only to the topside MOSFET(s)
and only become significant when operating at high input
voltages (typically 12V or greater). Transition losses can
be estimated from:

Transition Loss = (1.7) V

2

I

IN

O(MAX) CRSS

f

Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and fuse resis­tance losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switch­ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having a maxi-
mum of 0.01Ω to 0.02Ω of ESR. Other losses including
Schottky conduction losses during dead-time and induc­tor core losses generally account for less than 2% total
additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in load current.
When a load step occurs, V
to ∆I
tance of C
C

OUT

(ESR), where ESR is the effective series resis-

LOAD

OUT

. ∆I

also begins to charge or discharge

LOAD

generating the feedback error signal that forces the
regulator to adapt to the current change and return V
to its steady-state value. During this recovery time V

shifts by an amount equal

OUT

OUT
OUT

can be monitored for excessive overshoot or ringing,
which would indicate a stability problem. OPTI-LOOP
compensation allows the transient response to be opti­mized over a wide range of output capacitance and ESR
values. The availability of the ITH pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response. Assuming a pre­dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I

TH

external components shown in the Figure␣ 1 circuit will
provide an adequate starting point for most applications.

20

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The I
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1µs
to 10µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step
may not be within the bandwidth of the feedback loop, so
the standard second-order overshoot/DC ratio cannot be
used to determine phase margin. The gain of the loop will
be increased by increasing RC and the bandwidth of the
loop will be increased by decreasing CC. If RC is increased
by the same factor that CC is decreased, the zero frequency
will be kept the same, thereby keeping the phase the same
in the most critical frequency range of the feedback loop.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Applica­tion Note 76.

A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C

LOAD

should be controlled so that the load rise time is limited to
approximately (25)(C
require a 250µs rise time, limiting the charging current to
about 200mA.

Improve Transient Response and Reduce Output
Capacitance with Active Voltage Positioning

Fast load transient response, limited board space and low
cost are requirements of microprocessor power supplies.

series RC–CC filter sets the dominant pole-zero

TH

, causing a rapid drop in V

OUT

to C

is greater than1:50, the switch rise time

OUT

). Thus a 10µF capacitor would

LOAD

. No regulator can

OUT

Active voltage positioning improves transient response
and reduces the output capacitance required to power a
microprocessor where a typical load step can be from 0.2A
to 15A in 100ns or 15A to 0.2A in 100ns. The voltage at the
microprocessor must be held to about ±0.1V of nominal
in spite of these load current steps. Since the control loop
cannot respond this fast, the output capacitors must
supply the load current until the control loop can respond.
Capacitor ESR and ESL primarily determine the amount of
droop or overshoot in the output voltage. Normally, sev­eral capacitors in parallel are required to meet micropro­cessor transient requirements.

Active voltage positioning is a form of deregulation. It sets
the output voltage high for light loads and low for heavy
loads. When load current suddenly increases, the output
voltage starts from a level higher than nominal so the
output voltage can droop more and stay within the speci­fied voltage range. When load current suddenly decreases
the output voltage starts at a level lower than nominal so
the output voltage can have more overshoot and stay
within the specified voltage range. Less output capaci­tance is required when voltage positioning is used be­cause more voltage variation is allowed on the output
capacitors.

Active voltage positioning can be implemented using the
OPTI-LOOP architecture of the LTC1735 and two resistors
connected to the ITH pin. An input voltage offset is intro­duced when the error amplifier has to drive a resistive load.
This offset is limited to ±30mV at the input of the error
amplifier. The resulting change in output voltage is the
product of input offset and the feedback voltage divider
ratio.

Figure 8 shows a CPU-core-voltage regulator with active
voltage positioning. Resistors R1 and R4 force the input
voltage offset that adjusts the output voltage according to
the load current level. To select values for R1 and R4, first
determine the amount of output deregulation allowed. The
actual specification for a typical microprocessor allows
the output to vary ±0.112V. The LTC1735 reference accu­racy is ±1%. Using 1% tolerance resistors, the total
feedback divider accuracy is about 1% because both
feedback resistors are close to the same value. The result­ing setpoint accuracy is ±2% so the output transient

21

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APPLICATIO S I FOR ATIO

R3

680k

C2

0.1µF

C4

100pF

C5

47pF

R1

27k

R2

100k

C1

39pF

C3

100pF

1000pF

1

2

3

4

5

6

7

C6

8

C

OSC

RUN/SS

I

TH

FCB

SGND

V

OSENSE

SENSE

SENSE

R4

100k

U1

LTC1735

–

+

BOOST

INTV

PGND

EXTV

SW

V

BG

TG

IN

CC

CC

16

15

14

13

12

11

10

9

5V (OPTIONAL)

D1
CMDSH-3

C9
1µF

C7

0.1µF

C8

0.22µF

+

C10

4.7µF
10V

M1
FDS6680A

D2

MBRS340

M2, M3
FDS6680A
×2

C9, C19: TAIYO YUDEN JMK107BJ105
C10: KEMET T494A475M010AS
C12 TO C14: TAIYO YUDEN GMK325F106
C15 TO C18: PANASONIC EEFUE0G181R
D1: CENTRAL SEMI CMDSH-3
D2: MOTOROLA MBRS340
L1: PANASONIC ETQP6F1R0SA
M1 TO M3: FAIRCHILD FDS6680A
R5: IRC LRF2512-01-R003-J
U1: LINEAR TECHNOLOGY LTC1735CS

L1

1µH

R5

0.003Ω

C11
330pF

R6

10k

R7

11.5k

V

IN

C19
1µF

7.5V TO
24V

GND

V

OUT

1.5V
15A

GND

C12 TO C14
10µF
35V

C15 TO

+

C18
180µF
4V

Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning

voltage cannot exceed ±0.082V. At V

= 1.5V, the

OUT

maximum output voltage change controlled by the ITH pin
would be:

∆=

V

OSENSE

Input Offset V

.•.

003 15

±

=

.

08

•

OUT

V

REF

V

=±

56

mV

V

With the optimum resistor values at the ITH pin, the output
voltage will swing from 1.55V at minimum load to 1.44V
at full load. At this output voltage, active voltage position­ing provides an additional ±56mV to the allowable tran­sient voltage on the output capacitors, a 68% improve­ment over the ±82mV allowed without active voltage
positioning.

The next step is to calculate the ITH pin voltage, V
factor. The V

scale factor reflects the ITH pin voltage

ITH

ITH

, scale

1735 F08

required for a given load current. V

controls the peak

ITH

sense resistor voltage, which represents the DC output
current plus one half of the peak-to-peak inductor current.
The no load to full load V

range is from 0.3V to 2.4V,

ITH

which controls the sense resistor voltage from 0V to the
∆V

SENSE(MAX)

voltage of 75mV. The calculated V

ITH

scale

factor with a 0.003Ω sense resistor is:

V Scale Factor

ITH

V

at any load current is:

ITH



VI

ITH OUTDC



=+









V Offset

+

ITH

V Range Sense sistor Value

ITH

=

24 03 0003

(. – . )• .

VV

==

I

∆



L





2

•Re

∆

V

0 075

.

V Scale Factor

•

ITH

()

SENSE MAX

V

0 084

./

VA






22

LTC1735

k

VV

V

VV

V

INTVCC ITH NOM

ITH NOM

===

–

.–.

.

.

()

()

52 1085

1 085

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APPLICATIO S I FOR ATIO

At full load current:



VAAVA V

ITH MAX

=+

15

=











177

.

()



5

V



−

PP

2

0 084 0 3

•. / .





At minimum load current:



VAAVA V

ITH MIN

In this circuit, V

=+

02

=











.

040

ITH

()



2

.•./.

V

changes from 0.40V at light load to

−

PP

2



0 084 0 3





1.77V at full load, a 1.37V change. Notice that ∆IL, the
peak-to-peak inductor current, changes from light load to
full load. Increasing the DC inductor current decreases the
permeability of the inductor core material, which de­creases the inductance and increases ∆IL. The amount of
inductance change is a function of the inductor design.

To create the ±30mV input offset, the gain of the error
amplifier must be limited. The desired gain is:

A

=

V

Input Offset Error

V

∆

ITH

==

V

137

.

2003

(. )

V

Connecting a resistor to the output of the transconductance
error amplifier will limit the voltage gain. The value of this
resistor is:

A

R

===

ITH

Error Amplifier g ms

V

22 8

.

13

.

m

To center the output voltage variation, V
centered so that no ITH pin current flows when the output
voltage is nominal. V
tween V

at maximum output current and minimum

ITH

ITH(NOM)

is the average voltage be-

output current:







22 8

.

17 54

.

ITH

+



+






k

must be

The Thevenin equivalent of the gain limiting resistance
value of 17.54k is made up of a resistor R4 that sources
current into the ITH pin and resistor R1 that sinks current
to SGND.

To calculate the resistor values, first determine the ratio
between them:

V

INTVCC

is equal to V

or 5.2V if EXTV

EXTVCC

is not used.

CC

Resistor R4 is:

Rk R k

4 1 3 79 1 17 54 84 0=+ = + =()• (. )•. .

ITH

Resistor R1 is:

kR

1 3 79 1 17 54

+

()• (. )•.

R

1

ITH

=

k

+

379

.

k

=

k

22 17=

.

Unfortunately, PCB noise can add to the voltage developed
across the sense resistor, R5, causing the ITH pin voltage
to be slightly higher than calculated for a given output
current. The amount of noise is proportional to the output
current level. This PCB noise does not present a serious
problem but it does change the effective value of R5 so the
calculated values of R1 and R4 may need to be adjusted to
achieve the required results. Since PCB noise is a function
of the layout, it will be the same on all boards with the same
layout.

Figures 9 and 10 show the transient response before and
after active voltage positioning is implemented. Notice
that active voltage positioning reduced the transient re­sponse from almost 200mV

to a little over 100mV

P-P

P-P

.

Refer to Design Solutions 10 for more information about
active voltage positioning.

V

ITH NOM

VV

ITH MAX ITH MIN

=+

.–.

177 040

=+=

–

() ()

2

VV

..

0 40 1 085

VV

V

ITH MIN()

()

2

23

LTC1735

U

WUU

APPLICATIO S I FOR ATIO

VIN = 12V
V

OUT

1.5V

100mV/DIV

15A

10A/DIV

0A

Figure 9. Normal Transient Response (Without R1, R4)

VIN = 12V
V

1.582V

100mV/DIV

1.418V

10A/DIV

OUT

1.5V

15A

0A

= 1.5V

= 1.5V

OUTPUT

VOLTAGE

LOAD

CURRENT

OUTPUT

VOLTAGE

LOAD

CURRENT

50µs/DIV

FIGURE 8 CIRCUIT

1735 F09

FIGURE 8 CIRCUIT

The network shown in Figure␣ 11 is the most straight
forward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse-battery,
while the transient suppressor clamps the input voltage
during load-dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC1735 has a maximum input
voltage of 36V, most applications will be limited to 30V by
the MOSFET BV

50A IPK RATING

12V

TRANSIENT VOLTAGE

GENERAL INSTRUMENT

Figure 11. Plugging into the Cigarette Lighter

.

DSS

SUPPRESSOR

1.5KA24A

V

IN

LTC1735

1735 F11

50µs/DIV

Figure 10. Transient Response with Active Voltage Positioning

1735 F10

Automotive Considerations: Plugging into the
Cigarette Lighter

As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging
into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery and
double-battery.

Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.

Design Example

As a design example, assume VIN = 12V(nominal),
VIN = 22V(max), V
R

SENSE

R

SENSE

C

OSC

and C

OSC

= 50mV/5A = 0.01Ω

= 1.61(107)/(300kHz) – 11pF = 43pF

= 1.8V, I

OUT

= 5A and f = 300kHz.

MAX

can immediately be calculated:

Assume a 3.3µH inductor and check the actual value of the
ripple current. The following equation is used:

∆I

V

OUT OUT

=

L

()()

fL



–1







V



V



IN

The highest value of the ripple current occurs at the
maximum input voltage:

∆I

L

=

18

kHz H

300 3 3

V

.

µ

(. )



1

–





18

.

22



V



V



=

23

.

A

The maximum ripple current is 33% of maximum output
current, which is about right.

24

LTC1735

U

WUU

APPLICATIO S I FOR ATIO

Next verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum VIN:

V

t

ON MIN

()

Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the sense pin current.

Rk

124

MAX

()

Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.

The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results in
R
voltage with T(estimated) = 50°C:

P

Because the duty cycle of the bottom MOSFET is much
greater than the top, a larger MOSFET, Siliconix Si4410DY,
(R
bottom MOSFET, again assuming TA = 50°C, is:

DS(ON)

MAIN

DS(ON)

P

SYNC

=

=

= 0.042Ω, C

18

.

22

1 7 22 5 100 300

+

.

220

= 0.02Ω) is chosen. The power dissipation in the

=
=

OUT

== =

VfVV kHz

IN MAX

()



=





=

K

24

V

5 1 0 005 50 25 0 042

()

V

V A pF kHz

()()( )( )

mW

–.

22 1 8

VV

22

500

mW

.

08

.–

VV

24



.

08



.–.

VV

24 18



= 100pF. At maximum input

RSS

2

+°°

( . )( – ) .

[]

2

511002

()()

V

.

18
()

22 300



V





OUT



V

A

=

32





CC

2

..

()

ns

273

k

()

Ω

Ω

CIN is chosen for an RMS current rating of at least 2.5A at
temperature. C
output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The worst-case
output voltage ripple due to ESR is approximately:

VRI AmV

ORIPPLE ESR L P P

PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1735. These items are also illustrated graphically in
the layout diagram of Figure␣ 12. Check the following in
your layout:

1) Are the signal and power grounds segregated? The
LTC1735 PGND pin should tie to the ground plane close to
the input capacitor(s). The SGND pin should then connect
to PGND and all components that connect to SGND should
make a single point tie to the SGND pin. The synchronous
MOSFET source pins should connect to the input
capacitor(s) ground.

2) Does the V
resistors? The resistive divider R1, R2 must be connected
between the (+) plate of C
to 100pF capacitor should be as close as possible to the
LTC1735. Be careful locating the feedback resistors too far
away from the LTC1735. The V
routed close to any other nodes with high slew rates.

3) Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible to the
LTC1735. Ensure accurate current sensing with Kelvin
connections as shown in Figure 13. Series resistance can
be added to the SENSE lines to increase noise rejection.

4) Does the (+) terminal of CIN connect to the drain of the
topside MOSFET(s) as closely as possible? This capacitor
provides the AC current to the MOSFET(s).

is chosen with an ESR of 0.02Ω for low

OUT

==Ω=

OSENSE

(). (.)∆ 002 23 46

pin connect directly to the feedback

and signal ground. The 47pF

OUT

OSENSE

line should not be

−

Thanks to current foldback, the bottom MOSFET dissipa­tion in short-circuit will be less than under full load
conditions.

5) Is the INTVCC decoupling capacitor connected closely
between INTVCC and the power ground pin? This capaci­tor carries the MOSFET driver peak currents. An addi­tional 1µF ceramic capacitor placed immediately next to

25

LTC1735

U

WUU

APPLICATIO S I FOR ATIO

the INTVCC and PGND pins can help improve noise
performance.

6) Keep the switching node (SW), top gate node (TG) and
boost node (BOOST) away from sensitive small-signal
nodes, especially from the voltage and current sensing

C

C

R

C

SS

C

C2

C

47pF

1000pF

OSC

1

C

OSC

2

RUN/SS

C

3

4

5

6

7

8

I

TH

FCB

SGND

V

OSENSE

SENSE

SENSE

LTC1735

–

+

BOOST

INTV

PGND

EXTV

SW

V

TG

BG

16

15

14

13

IN

12

CC

+

11

10

9

CC

feedback pins. All of these nodes have very large and fast
moving signals and therefore should be kept on the
“output side” (Pin 9 to Pin 16) of the LTC1735 and occupy
minimum PC trace area.

+

M1

C

IN

+

V

IN

D

4.7µF

C

B

B

D1

M2

–

L1

R1

C

OUT

+

R2

R

Figure 12. LTC1735 Layout Diagram

HIGH CURRENT PATH

CURRENT SENSE
RESISTOR
(R

SENSE+SENSE

–

Figure 13. Kelvin Sensing R

SENSE

SENSE

SENSE

1735 F13

)

1735 F12

–

V

OUT

+

26

U

TYPICAL APPLICATIO S

1.8V/5A Converter from Design Example with Burst Mode Operation Disabled

C

OSC

43pF

1

C

0.1µF

220pF

47pF

C

SS

C

C

R

C

470pF

33k

C

C2

1000pF

2

3

4

5

6

7

8

OSC

RUN/SS

I

TH

FCB

SGND

V

OSENSE

SENSE

SENSE

LTC1735

–

+

BOOST

INTV

PGND

EXTV

SW

V

BG

TG

IN

CC

CC

16

15

14

13

12

11

10

9

OPTIONAL:
CONNECT TO 5V

+

C

B

0.1µF

D

B

CMDSH-3

4.7µF

V

IN

4.5V TO 22V

M1
Si4412DY

M2
Si4410DY

MBRS140T3

L1

3.3µH

C

IN

22µF
50V
CER

R

SENSE

0.01Ω

LTC1735

V

OUT

1.8V

R2

32.4k
1%

+

R1

25.5k
1%

SGND

: PANASONIC EEFUEOG151R

C

OUT

: MARCON THCR70LE1H226ZT

C

IN

L1: PANASONIC ETQP6F3R3HFA

: IRC LR 2010-01-R010F

R

SENSE

1735 TA02

5A

C

OUT

150µF

6.3V
×2
PANASONIC SP

CPU Core Voltage Regulator for 2-Step Applications (VIN = 5V)

100k*

C

39pF

OSC

1

C

2

3

4

5

6

7

8

OSC

RUN/SS

I

TH

FCB

SGND

V

OSENSE

SENSE

SENSE

LTC1735

–

+

C

SS

0.1µF

C

C

R

C

220pF

20k

C

C2

220pF

47pF

1000pF

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

BOOST

INTV

PGND

EXTV

SW

V

TG

BG

V

IN

5V

C

IN

150µF

16

C

1µF

+

0.22µF

D

B

MBR0530

4.7µF

15

14

13

IN

12

CC

11

10

9

V

CC

IN

M1
FDS6680A

B

0.78µH

M2, M3
FDS6680A
×2

MBRD835L

6.3V
×2

L1

R

SENSE

0.004Ω

R2

32.4k

100pF

1%
R1

25.5k
1%

: PANASONIC EEFUEOG181R

C

OUT

: PANASONIC EEFUEOJ151R

C

IN

: TAIYO YUDEN LMK550BJ476MM-B

C

O

L1: COILCRAFT 1705022P-781HC

: IRC LRF 2512-01-R004-J

R

SENSE

1735 TA03

+

SGND

C
180µF
4V
×3

OUT

C

O

47µF
10V

V

OUT

1.5V
12A

27

LTC1735

U

TYPICAL APPLICATIO S

Selectable Output Voltage Converter with Burst Mode Operation Disabled for CPU Power

C

OSC

43pF

1

C

10Ω
10Ω

2

3

4

5

6

7

8

OSC

RUN/SS

I

TH

FCB

SGND

V

OSENSE

SENSE

SENSE

LTC1735

–

+

BOOST

INTV

PGND

EXTV

47pF

C

0.1µF

C

47pF

SS

C

C

R

C

330pF

33k

C2

1000pF

SW

V

TG

IN

CC

BG

CC

0.1µF

16

15

14

13

12

11

10

9

4.7Ω

0.22µF

D

B

CMDSH-3

+

4.7µF

1µF
CER

OPTIONAL:
CONNECT TO 5V

4.5V TO 24V

C

B

V

IN

M1
FDS6680A

M2
FDS6680A
×2

L1

1.2µH

MBRS340T3

C

IN

+

22µF
×2
CER

C

: MARCON THCR70EIH226ZT

IN

: KEMET T510X447M006AS

C

OUT

L1: PANASONIC ETQP6F1R2HFA

: IRC LRF2512-01-R004F

R

SENSE

R

SENSE

0.004Ω

1735 TA05

R3

33.2k
1%

47pF

VN2222

10k

47pF

R2
10k
1%

R1

14.3k
1%

+

SGND

C

OUT

470µF

6.3V
×3
KEMET

ON: V
OFF: V

V

OUT

1.35V/1.60V
12A

= 1.60V

OUT

= 1.35V

OUT

C

OSC

150pF

C

C

2200pF

R

3.3k

0.1µF

C

47pF

3300pF

C

SS

C

C2

100pF

V

OUT

100Ω

CMDSH-3

1M

1

C

OSC

2

RUN/SS

3

I

TH

4

FCB

5

SGND

6

V

OSENSE

7

SENSE

8

SENSE

FMMT625

LTC1735

–

+

BOOST

INTV

PGND

EXTV

SW

V

4V to 40V Input to 12V Flyback Converter

V

IN

4V TO 40V

C

10k

6.2V

16

TG

15

14

13

IN

12

CC

11

BG

10

9

CC

IN

22µF
50V
×2

+

0.1µF

4.7µF

T1

•

6

10

•

7

3

M1
IR2910

R

SENSE

0.004Ω

22Ω

1nF
100V

M2
Si4450DY

C

: MARCON THCR70EIH226ZT

IN

: AVX TPSV227M016R0150

C

OUT

T1: COILTRONICS VP5-0155
R

SENSE

MBRS1100

: IRC LRF2512-01-R004F

47Ω

1nF
100V

R2
113k
1%

R1

8.06k
1%

V

OUT

12V
3A

C

OUT

+

470µF
16V
×4

28

1735 TA07

U

TYPICAL APPLICATIO S

5V/3.5A Converter with 12V/200mA Auxiliary Output

C

OSC

51pF

1

C

0.1µF

220pF

100pF

C

SS

C

C

R

C

470pF

33k

C

C2

1000pF

10k

2

3

4

5

6

7

8

OSC

RUN/SS

I

TH

FCB

SGND

V

OSENSE

SENSE

SENSE

100Ω

90.9k

LTC1735

–

+

BOOST

INTV

PGND

EXTV

100Ω

SW

V

LTC1735

V

IN

5.5V TO 28V

C

IN

+

22µF

T1

1:1.8
10µH

30V
OS-CON

22Ω

MBRS1100T3

R

SENSE

0.012Ω

1000pF

C

SEC

+

22µF
35V
AVX

R2
105k
1%

+

R1
20k
1%

SGND

: SANYO OS-CON 305C22M

C

IN

: AVX TPSD107M010R0068

C

OUT

T1: 1:8 DALE LPE6562-A262

C

OUT

100µF
10V
×3
AVX

V

OUT

5V

3.5A

1735 TA04

V

OUT2

12V
120mA
UNREG

16

TG

+

0.1µF

D

B

CMDSH-3

4.7µF

15

14

13

IN

12

CC

11

BG

10

9

CC

M1
IRF7803

C

B

M2
IRF7803

MBRS140T3

R

33k

100pF

Dual Output 15W 3.3V/5V Power Supply

V

IN

4.5V TO 28V

C

OSC

47pF

1

C

C

SS

0.1µF

470pF

C

C

C2

100pF

1000pF

OSC

2

RUN/SS

C

C

3

I

TH

LTC1735

4

FCB

5

SGND

6

V

OSENSE

7

–

SENSE

8

+

SENSE

BOOST

INTV

PGND

EXTV

SW

V

16

TG

15

14

13

IN

12

CC

+

11

BG

10

9

V

OUT2

CC

D

B

CMDSH-3

4.7µF

C

0.1µF

M1
Si4412DY

B

M2
Si4412DY

+

T1A T1B

•

•

18

27

MBRS140T3

C

IN

22µF
50V

0.01µF

R

SENSE

0.01Ω

CMDSH-3

T1C

•

36

M3
Si4412DY

4.7k

MBRS140T3

R2

62.6k
1%

+

R1
20k
1%

SGND

: MARCON THCR70EIH226ZT

C

IN

: AVX TPSD107M010R0065

C

OUT1, 2

T1: BI TECHNOLOGIES HM00-93839

: IRC LRF2512-01-R010 F

R

1735 TA08

SENSE

C

OUT1

100µF
10V
×2

V

OUT2

5V

1.5A

C

OUT2

+

100µF
10V
×2

V

OUT1

3.3V

2.5A

29

LTC1735

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

GN Package

16-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.189 – 0.196*
(4.801 – 4.978)

16

15

14

12 11 10

13

9

0.009

(0.229)

REF

0.015

± 0.004

(0.38 ± 0.10)

0.007 – 0.0098
(0.178 – 0.249)

0.016 – 0.050

(0.406 – 1.270)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0° – 8° TYP

× 45°

0.229 – 0.244

(5.817 – 6.198)

0.053 – 0.068

(1.351 – 1.727)

0.008 – 0.012

(0.203 – 0.305)

12

0.150 – 0.157**
(3.810 – 3.988)

5

4

3

678

0.004 – 0.0098
(0.102 – 0.249)

0.0250

(0.635)

BSC

GN16 (SSOP) 1098

30

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

S Package

16-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.386 – 0.394*

(9.804 – 10.008)

13

16

14

15

12

11

LTC1735

10

9

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

×

°

45

0.016 – 0.050

(0.406 – 1.270)

0° – 8° TYP

0.228 – 0.244

(5.791 – 6.197)

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

TYP

0.150 – 0.157**
(3.810 – 3.988)

4

5

0.050

(1.270)

BSC

3

2

1

7

6

8

0.004 – 0.010

(0.101 – 0.254)

S16 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

LTC1735

TYPICAL APPLICATIO

3.3V to 2.5V/5A Converter with External Clock Synchronization Operating at 500kHz

C

OSC

20pF

1

0.1µF

R

33k

47pF

C

SS

C

C

330pF

C

EXT

CLOCK

C

C2

500kHz

51pF

1000pF

2

3

4

5

6

7

8

C

RUN/SS

I

FCB

SGND

V

SENSE

SENSE

OSC

TH

OSENSE

U

LTC1735

–

+

BOOST

INTV

PGND

EXTV

SW

V

TG

BG

V

IN

C

0.1µF

B

3.3V

C

IN

+

100µF

M1
Si4410DY

B

1.5µH

M2
Si4410DY

MBRS140T3

10V
OS-CON

C

: SANYO OS-CON 10SL100M

IN

: AVX TPSD107M010R0065

C

OUT

L1: COILCRAFT DO3316P-152

: IRC LR2010-01-R010-F

R

SENSE

L1

R

SENSE

0.01Ω

47pF

R2

43.2k
1%

R1
20k
1%

+

SGND

C

OUT

100µF
10V
AVX
×3

V

OUT

2.5V
5A

5V

0.1µF

16

15

14

13

IN

12

CC

11

10

9

CC

+

D
CMDSH-3

4.7µF

1735 TA06

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SENSE

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No R

is trademark of Linear Technology Corporation. *DC = Duty Cycle

SENSE

Q

IN

IN

32

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

1735f LT/TP 1199 4K • PRINTED IN USA

 LINEAR TE CHNOLOGY CORPORATION 1998