Datasheet LTC1709-9, LTC1709-8 Datasheet (Linear Technology)

LTC1709-8/LTC1709-9

Final Electrical Specifications

2-Phase, 5-Bit VID,

Current Mode, High Efficiency,

Synchronous Step-Down Switching Regulators

FEATURES

■

Single Controller Operates Two Output Stages:
Antiphase Reducing Required Input Capacitance
and Power Supply Induced Noise

■

Two 5-Bit Desktop VID Codes:

LTC1709-8 For VRM8.4 (V
LTC1709-9 For VRM9.0 (V

■

Current Mode Control Ensures Best Current Sharing

■

True Remote Sensing Differential Amplifier

■

Power Good Output Indicator

■

OPTI-LOOPTM Compensation Minimizes C

■

Programmable Fixed Frequency: 150kHz to 300kHz

■

±1% Output Voltage Accuracy

■

Wide VIN Range: 4V to 36V Operation

■

Adjustable Soft-Start Current Ramping

■

Internal Current Foldback and Short-Circuit Shutdown

■

Overvoltage Soft Latch Eliminates Nuisance Trips

■

Low Shutdown Current: 20µA

■

Available in 36-Lead SSOP Package

from 1.3V to 3.5V)

OUT

from 1.1V to 1.85V)

OUT

OUT

U

APPLICATIO S

■

Workstations

■

Internet Servers

■

Large Memory Arrays

■

DC Power Distribution Systems

U

May 2000

DESCRIPTIO

The LTC®1709-8/LTC1709-9 are 2-phase, VID program­mable, synchronous step-down switching regulator con­trollers that drive two all N-channel external power MOSFET
stages in a fixed frequency architecture. The 2-phase
controller drives its two output stages out of phase at
frequencies up to 300kHz to minimize the RMS ripple
currents in both input and output capacitors. The 2-phase
technique effectively multiplies the fundamental frequency
by two, improving transient response while operating
each channel at an optimum frequency for efficiency.
Thermal design is also simplified.

An internal differential amplifier provides true remote
sensing of the regulated supply’s positive and negative
output terminals as required for high current applications.

The RUN/SS pin provides soft-start and optional timed,
short-circuit shutdown. Current foldback limits MOSFET
dissipation during short-circuit conditions when the
overcurrent latchoff is disabled. OPTI-LOOP compensa­tion allows the transient response to be optimized for a
wide range of output capacitors and ESR values. The
LTC1709-8/LTC1709-9 implement two different VID
tables compliant with VRM8.4 and VRM9.0 respectively.

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP is a trademark of Linear Technology Corporation.

TYPICAL APPLICATIO

0.1µF

3.3k

220pF

5 VID BITS

U

+

10µF

1µH

35V
×4

0.002Ω

1µH

0.002Ω

+

V

IN

TG1

RUN/SS

LTC1709-8

I

TH

SGND
PGOOD

VID0–VID4

EAIN
ATTENOUT
ATTENIN
V

DIFFOUT

–

V

OS

+

V

OS

BOOST1

SENSE1
SENSE1

BOOST2

INTV
SENSE2
SENSE2

SW1

BG1

PGND

TG2

SW2

BG2

S

0.47µF

S

+
–

0.47µF

CC

+
–

10µF

+

Figure 1. High Current Dual Phase Step-Down Converter

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

V

IN

5V TO 28V

V

OUT

1.3V TO 3.5V
40A

C

OUT

1000µF
4V
×2

17097 F01

1

LTC1709-8/LTC1709-9

WW

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

Input Supply Voltage (VIN).........................36V to –0.3V

Topside Driver Voltages (BOOST1,2).........42V to –0.3V

Switch Voltage (SW1, 2) .............................36V to –5 V

SENSE1+, SENSE2+, SENSE1–,

SENSE2– Voltages........................ (1.1)INTVCC to –0.3V

EAIN, V
V

BIAS

VID0–VID4, Voltages ...................................7V to –0.3V

Boosted Driver Voltage (BOOST-SW) ..........7V to –0.3V

PLLFLTR, PLLIN, V

ITH Voltage................................................2.7V to –0.3V

Peak Output Current <1µs(TGL1,2, BG1,2)................ 3A

INTVCC RMS Output Current................................ 50mA

Operating Ambient Temperature Range

(Note 2) ................................................ – 40°C to 85°C

Junction Temperature (Note 3)............................. 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

+

–

, V

OS

, EXTVCC, INTVCC, RUN/SS,

OS

, ATTENIN, ATTENOUT, PGOOD,

DIFFOUT

Voltages .... INTVCC to –0.3V

UUW

PACKAGE/ORDER I FOR ATIO

RUNN/SS
SENSE1
SENSE1

EAIN

PLLFLTR

PLLIN

NC
I

SGND

V

DIFFOUT

VOS–
V

OS

SENSE2
SENSE2

ATTENOUT

ATTENIN

VID0
VID1

TOP VIEW

1

+

2

–

3
4
5
6
7
8

TH

9
10
11
12

+

–

13

+

14
15
16
17
18

G PACKAGE

36-LEAD PLASTIC SSOP

T

= 125°C, θJA = 85°C/W

JMAX

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

NC
TG1
SW1
BOOST1
V

IN

BG1
EXTV

CC

INTV

CC

PGND
BG2
BOOST2
SW2
TG2
PGOOD
V

BIAS

VID4
VID3
VID2

ORDER PART

NUMBER

LTC1709EG-8
LTC1709EG-9

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes the specifications which apply over the full operating

BIAS

= 5V, V

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop

V

EAIN

V

SENSEMAX

I

INEAIN

V

LOADREG

V

REFLNREG

V

OVL

Regulated Feedback Voltage ITH Voltage = 1.2V (Note 4) ● 0.792 0.800 0.808 V
Maximum Current Sense Threshold V

–

= 5V ● 62 75 88 mV

SENSE

Feedback Current (Note 4) –5 –50 nA
Output Voltage Load Regulation (Note 4)

Measured in Servo Loop, ∆I
Measured in Servo Loop, ∆I

Voltage: 1.2V to 0.7V ● 0.1 0.5 %

TH

Voltage: 1.2V to 2V ● –0.1 –0.5 %

TH

Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 4) 0.002 0.02 %/V
Output Overvoltage Threshold Measured at V

EAIN

● 0.84 0.86 0.88 V

UVLO Undervoltage Lockout VIN Ramping Down 3 3.5 4 V
g

m

g

mOL

I

Q

I

RUN/SS

V

RUN/SS

Transconductance Amplifier g

m

ITH = 1.2V, Sink/Source 5µA (Note 4) 3 mmho
Transconductance Amplifier Gain ITH = 1.2V, (gmxZL; No Ext Load) (Note 4) 1.5 V/mV
Input DC Supply Current (Note 5)

Normal Mode EXTV

Shutdown V
Soft-Start Charge Current V
RUN/SS Pin ON Arming V

Tied to V

CC

= 0V 20 40 µA

RUN/SS

= 1.9V –0.5 –1.2 µA

RUN/SS

Rising 1.0 1.5 1.9 V

RUN/SS

OUT

, V

= 5V 470 µA

OUT

2

LTC1709-8/LTC1709-9

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes the specifications which apply over the full operating

BIAS

= 5V, V

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

RUN/SSLO

I

SCL

I

SDLHO

I

SENSE

DF

MAX

RUN/SS Pin Latchoff Arming V
RUN/SS Discharge Current Soft Short Condition V
Shutdown Latch Disable Current V
Total Sense Pins Source Current Each Channel: V

Rising from 3V 4.1 4.5 V

RUN/SS

= 0.5V, V

EAIN

= 0.5V 1.6 5 µA

EAIN

SENSE1–, 2

– = V

SENSE1+, 2

= 4.5V 0.5 2 4 µA

RUN/SS

+ = 0V –85 –60 µA

Maximum Duty Factor In Dropout 98 99.5 %
Top Gate Transition Time: (Note 6)

TG1, 2 t
TG1, 2 t

Rise Time C

r

Fall Time C

f

= 3300pF 30 90 ns

LOAD

= 3300pF 40 90 ns

LOAD

Bottom Gate Transition Time: (Note 6)

BG1, 2 t
BG1, 2 t

TG/BG t

Rise Time C

r

Fall Time C

f

Top Gate Off to Bottom Gate On Delay C

1D

= 3300pF 30 90 ns

LOAD

= 3300pF 20 90 ns

LOAD

= 3300pF Each Driver (Note 6) 90 ns

LOAD

Synchronous Switch-On Delay Time

BG/TG t

Bottom Gate Off to Top Gate On Delay C

2D

= 3300pF Each Driver (Note 6) 90 ns

LOAD

Top Switch-On Delay Time

t

ON(MIN)

Minimum On-Time Tested with a Square Wave (Note 7) 180 ns

Internal VCC Regulator

V

INTVCC

V

LDO

V

LDO

V

EXTVCC

V

LDOHYS

Internal VCC Voltage 6V < VIN < 30V, V

INT INTVCC Load Regulation ICC = 0 to 20mA, V
EXT EXTVCC Voltage Drop ICC = 20mA, V

EXTVCC

EXTVCC Switchover Voltage ICC = 20mA, EXTV
EXTVCC Switchover Hysteresis ICC = 20mA, EXTV

= 4V 4.8 5.0 5.2 V

EXTVCC

= 4V 0.2 1.0 %

EXTVCC

= 5V 80 160 mV
Ramping Positive ● 4.5 4.7 V

CC

Ramping Negative 0.2 V

CC

VID Parameters

V

BIAS

R

ATTEN

Operating Supply Voltage Range 2.7 5.5 V
Resistance Between ATTENIN LTC1709-8 20 kΩ

and ATTENOUT Pins LTC1709-9 10 kΩ

ATTEN

R

PULLUP

VID

THLOW

VID

THHIGH

VID

LEAK

Resistive Divider Error LTC1709-8: VID4 = 0; LTC1709-9 ● –0.25 0.25 %

ERR

LTC1709-8: VID4 = 1

● –0.35 0.35 %

VID0–VID4 Pull-Up Resistance (Note 8) 40 kΩ
VID0–VID4 Logic Threshold Low 0.4 V
VID0–VID4 Logic Threshold High 1.6 V
VID0–VID4 Leakage V

< VID0–VID4 < 7V 1 µA

BIAS

Oscillator and Phase-Locked Loop

f

NOM

f

LOW

f

HIGH

R

PLLIN

I

PLLFLTR

R

RELPHS

Nominal Frequency V
Lowest Frequency V
Highest Frequency V

= 1.2V 190 220 250 kHz

PLLFLTR

= 0V 120 140 160 kHz

PLLFLTR

≥ 2.4V 280 320 360 kHz

PLLFLTR

PLLIN Input Resistance 50 kΩ
Phase Detector Output Current

Sinking Capability f

Sourcing Capability f

PLLIN
PLLIN

< f
> f

OSC
OSC

–15 µA
15 µA

Controller 2-Controller 1 Phase 180 Deg

3

LTC1709-8/LTC1709-9

VIN (V)

5

EFFICIENCY (%)

100

90

80

70

170989 G03

10 15 20

V

OUT

= 3.3V

V

EXTVCC

= 5V

I

OUT

= 20A

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PGOOD Output

V

PGL

I

PGOOD

V

PG

PGOOD Voltage Low I
PGOOD Leakage Current V
PGOOD Trip Level, Either Controller V

= 2mA 0.1 0.3 V

PGOOD

= 5V ±1 µA

PGOOD

with Respect to Set Output Voltage

EAIN

Ramping Negative –6 –7.5 –9.5 %

V

EAIN

Ramping Positive 6 7.5 9.5 %

V

EAIN

Differential Amplifier/Op Amp Gain Block

A

DA

CMRR
R

IN

Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.

Note 2: The LTC1709EG is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: T
dissipation P

LTC1709EG: T

Note 4: The LTC1709-8/LTC1709-9 are tested in a feedback loop that
servos V

Gain 0.995 1 1.005 V/V
Common Mode Rejection Ratio 0V < VCM < 5V 46 55 dB

DA

Input Resistance Measured at VOS+ Input 80 kΩ

Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.

Note 7: The minimum on-time condition corresponds to the on inductor

(see Minimum On-Time

MAX

CC

is calculated from the ambient temperature TA and power

J

according to the following formula:

D

= TA + (PD • 85°C/W)

J

peak-to-peak ripple current ≥40% I
Considerations in the Applications Information section).

Note 8: Each built-in pull-up resistor attached to the VID inputs also has a
series diode to allow input voltages higher than the VIDV
damage or clamping (see the Applications Information section).

to a specified voltage and measures the resultant V

ITH

EAIN

.

supply without

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Output Current
(Figure 12)

100

80

VIN = 5V

60

40

EFFICIENCY (%)

20

0

0.1
OUTPUT CURRENT (A)

VIN = 8V
VIN = 12V
VIN = 20V

1 10 100

V

= 2V

OUT

V

= 0V

EXTVCC

FREQ = 200kHz

170989 G01

Efficiency vs Output Current
(Figure 12)

100

V

= 5V

EXTVCC

80

V

EXTVCC

60

40

EFFICIENCY (%)

20

0

0.1
OUTPUT CURRENT (A)

= 0V

VIN = 12V

= 2V

V

OUT

FREQ = 200kHz

101 100

Efficiency vs Output Current
(Figure 12)

170989 G02

4

UW

TEMPERATURE (°C)

–50

INTV

CC

AND EXTV

CC

SWITCH VOLTAGE (V)

4.95

5.00

5.05

25 75

170989 G06

4.90

4.85

–25 0

50 100 125

4.80

4.70

4.75

INTVCC VOLTAGE

EXTVCC SWITCHOVER THRESHOLD

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1709-8/LTC1709-9

Supply Current vs Input Voltage
and Mode (Figure 12) EXTVCC Voltage Drop

1000

800

600

400

SUPPLY CURRENT (µA)

200

0

05

ON

SHUTDOWN

10

INPUT VOLTAGE (V)

20

15

25

30

170989 G04

35

250

200

150

100

VOLTAGE DROP (mV)

CC

EXTV

50

0

10

0

Maximum Current Sense Threshold
vs Duty Factor

5.1
I

LOAD

5.0

4.9

4.8

VOLTAGE (V)

4.7

CC

INTV

4.6

4.5

4.4

0

= 1mA

510

INPUT VOLTAGE (V)

20 30 35

15 25

170989 G07

75

50

(mV)

SENSE

V

25

0

0

20 40 60 80

30

20

CURRENT (mA)

DUTY FACTOR (%)

40

170989 G05

170989 G08

50

100

INTVCC and EXTVCC Switch
Voltage vs Temperature

Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)Internal 5V LDO Line Reg

80

70

60

50

(mV)

40

SENSE

V

30

20

10

0

0

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

25

50

75

100

170989 G09

80

60

(mV)

40

SENSE

V

20

0

0

Maximum Current Sense Threshold
vs V

V

SENSE(CM)

(Soft-Start)

RUN/SS

= 1.6V

1234

V

(V)

RUN/SS

56

170989 G10

Maximum Current Sense Threshold
vs Sense Common Mode Voltage

80

76

72

(mV)

SENSE

68

V

64

60

1

0

COMMON MODE VOLTAGE (V)

3

2

4

170989 G11

Current Sense Threshold
vs ITH Voltage

90
80
70
60
50
40

(mV)

30
20

SENSE

V

10

0
–10
–20

5

–30

0.5

0

1.5

2

1

V

(V)

ITH

2.5

170989 G12

5

LTC1709-8/LTC1709-9

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Load Regulation V

0.0

–0.1

(%)

OUT

–0.2

NORMALIZED V

–0.3

–0.4

0

1

2

LOAD CURRENT (A)

FCB = 0V
V

= 15V

IN

FIGURE 1

3

4

5

1629 G13

Maximum Current Sense
Threshold vs Temperature

80

78

76

(mV)

SENSE

74

V

72

70

–50 –25

25

0

TEMPERATURE (°C)

SENSE Pins Total Source Current

100

50

(µA)

0

SENSE

I

–50

–100

0

24

V

COMMON MODE VOLTAGE (V)

SENSE

6

1629 G15

(V)

ITH

V

2.5

2.0

1.5

1.0

0.5

vs V

ITH

RUN/SS

V

= 0.7V

OSENSE

0

0

234

1

V

RUN/SS

(V)

56

1629 G14

RUN/SS Current vs Temperature

1.8

1.6

1.4

1.2

1.0

0.8

0.6

RUN/SS CURRENT (µA)

0.4

0.2

50

75

100

170989 G16

125

0

–50 –25

0 25 125

TEMPERATURE (°C)

75 10050

170989 G17

6

Soft-Start (Figure 12) Load Step (Figure 12)

V

1V/DIV

V

2V/DIV

V

RUN/SS

2V/DIV

OUT

ITH

100ms/DIV

170989 G18

V

OUT

50mV/DIV

I

OUT

0/20A

20µs/DIV

170989 G19

UW

TEMPERATURE (°C)

–50

200

250

350

25 75

170989 G22

150

100

–25 0

50 100 125

50

0

300

FREQUENCY (kHz)

V

FREQSET

= 5V

V

FREQSET

= OPEN

V

FREQSET

= 0V

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1709-8/LTC1709-9

Current Sense Pin Input Current
vs Temperature

35

V

= 5V

OUT

33

31

29

27

CURRENT SENSE INPUT CURRENT (µA)

25

–50 –25

0

TEMPERATURE (°C)

50

25

Undervoltage Lockout
vs Temperature

3.50

3.45

3.40

3.35

3.30

UNDERVOLTAGE LOCKOUT (V)

3.25

3.20
–50

75

–25 0

125

100

170989 G20

50 100 125

25 75

TEMPERATURE (°C)

EXTVCC Switch Resistance
vs Temperature

10

8

6

4

SWITCH RESISTANCE (Ω)

CC

2

EXTV

0

–50 –25

170989 G23

25

0

TEMPERATURE (°C)

50

75

100

170989 G21

125

Shutdown Latch Thresholds
vs Temperature

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

SHUTDOWN LATCH THRESHOLDS (V)

0

–50 –25

Oscillator Frequency
vs Temperature

LATCH ARMING

LATCHOFF

THRESHOLD

0 25 125

TEMPERATURE (°C)

75 10050

170989 G24

PI FU CTIO S

RUN/SS (Pin 1): Combination of Soft-Start, Run Control
Input and Short-Circuit Detection Timer. A capacitor to
ground at this pin sets the ramp time to full current output.
Forcing this pin below 0.8V causes the IC to shut down all
internal circuitry. All functions are disabled in shutdown.

SENSE1+, SENSE2+ (Pins 2,14): The (+) Input to Each
Differential Current Comparator. The ITH pin voltage and
built-in offsets between SENSE– and SENSE+ pins in
conjunction with R

UUU

set the current trip threshold.

SENSE

SENSE1–, SENSE2– (Pins 3, 13): The (–) Input to the
Differential Current Comparators.

EAIN (Pin 4): Input to the error amplifier that compares the
feedback voltage to the internal 0.8V reference voltage.
This pin is normally connected to a resistive divider from
the output of the differential amplifier (DIFFOUT).

PLLFLTR (Pin 5): The phase-locked loop’s lowpass filter
is tied to this pin. Alternatively, this pin can be driven with
an AC or DC voltage source to vary the frequency of the
internal oscillator.

7

LTC1709-8/LTC1709-9

UUU

PI FU CTIO S

PLLIN (Pin 6): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with
50kΩ. The phase-locked loop will force the rising top gate
signal of controller 1 to be synchronized with the rising
edge of the PLLIN signal.

NC (Pins 7, 36): Do not connect.
ITH (Pin 8): Error Amplifier Output and Switching Regula-

tor Compensation Point. Both current comparator’s thresh­olds increase with this control voltage. The normal voltage
range of this pin is from 0V to 2.4V

SGND (Pin 9): Signal Ground. This pin is common to both
controllers. Route separately to the PGND pin.

V

DIFFOUT

pin provides true remote output voltage sensing. V
normally drives an external resistive divider that sets the
output voltage.

V

OS

fier. Internal precision resistors capable of being elec­tronically switched in or out can configure it as a differential
amplifier or an uncommitted op amp.

ATTENOUT (Pin 15): Voltage Feedback Signal Resistively
Divided According to the VID Programming Code.

ATTENIN (Pin 16): The Input to the VID Controlled Resis­tive Divider.

VID0–VID4 (Pins 17,18, 19, 20, 21): VID Control Logic
Input Pins.

V

BIAS

PGOOD (Pin 23): Open-Drain Logic Output. PGOOD is

pulled to ground when the voltage on the EAIN pin is not
within ±7.5% of its set point.

(Pin 10): Output of a Differential Amplifier. This

DIFFOUT

–

+

, V

(Pins 11, 12): Inputs to an Operational Ampli-

OS

(Pin 22): Supply Pin for the VID Control Circuit.

TG2, TG1 (Pins 24, 35): High Current Gate Drives for Top

N-Channel MOSFETS. These are the outputs of floating
drivers with a voltage swing equal to INTVCC superim­posed on the switch node voltage SW.

SW2, SW1 (Pins 25, 34): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to VIN.

BOOST2, BOOST1 (Pins 26, 33): Bootstrapped Supplies
to the Topside Floating Drivers. External capacitors are
connected between the BOOST and SW pins, and Schottky
diodes are connected between the BOOST and INTV
pins.

BG2, BG1 (Pins 27, 31): High Current Gate Drives for
Bottom N-Channel MOSFETS. Voltage swing at these pins
is from ground to INTVCC.

PGND (Pin 28): Driver Power Ground. Connect to sources
of bottom N-channel MOSFETS and the (–) terminals of
CIN.

INTVCC (Pin 29): Output of the Internal 5V Linear Low
Dropout Regulator and the EXTVCC Switch. The driver and
control circuits are powered from this voltage source.
Decouple to power ground with a 1µF ceramic capacitor
placed directly adjacent to the IC and minimum of 4.7µF
additional tantalum or other low ESR capacitor.

EXTVCC (Pin 30): External Power Input to an Internal
Switch. This switch closes and supplies INTV
ing the internal low dropout regulator whenever EXTVCC is
higher than 4.7V. See EXTVCC Connection in the Applica­tions Information section. Do not exceed 7V on this pin
and ensure V

VIN (Pin 32): Main Supply Pin. Should be closely decoupled
to the IC’s signal ground pin.

EXTVCC

≤ VIN.

CC,

CC

bypass-

8

LTC1709-8/LTC1709-9

UU

W

FU CTIO AL DIAGRA

PLLIN

f

IN

PLLLPF

R

LP

C

LP

PGOOD

V

OS

V

OS

DIFFOUT

V

IN

V

IN

EXTV

INTV

5V

+

SGND

ATTENIN

ATTENOUT

50k

–

+

CC

CC

20k (LTC1709-8)
10k (LTC1709-9)

PHASE DET

OSCILLATOR

–
+

+

4.7V
–

R1

A1

0.80V

CLK1
CLK2

–
+

–
+

V

REF

5V
LDO
REG

INTERNAL

SUPPLY

0.86V

EAIN

0.74V

DUPLICATE FOR SECOND
CONTROLLER CHANNEL

0.86V

4(VFB)

SLOPE

COMP

1.2µA

6V

5-BIT VID DECODER

SRQ

I

1

DROP

OUT
DET

Q

–

+

45k

TYPICAL ALL

VID PINS

40k

+–

SHDN

RST

4(VFB)

BOT

FORCE BOT

SHDN

45k

2.4V

OV

RUN

SOFT

START

EA

SWITCH

LOGIC

–
+

+
–

TOP

BOT

INTV

0.80V

0.86V

INTV

CC

30k

30k

CC

BOOST

TG

SW

BG

PGND

SENSE

SENSE

EAIN

I

TH

RUN/SS

INTV

+

–

R

SENSE

V

CC

IN

D

B

C

B

L

+

C

IN

C

OUT

+

V

OUT

C

C

R

C

C

SS

VID1 VID2 VID3 VID4

VID0

V

BIAS

170989 FBD

9

LTC1709-8/LTC1709-9

U

OPERATIO

(Refer to Functional Diagram)

Main Control Loop

The LTC1709 uses a constant frequency, current mode
step-down architecture with inherent current sharing.
During normal operation, the top MOSFET is turned on
each cycle when the oscillator sets the RS latch, and
turned off when the main current comparator, I1, resets
the RS latch. The peak inductor current at which I1 resets
the RS latch is controlled by the voltage on the ITH pin,
which is the output of the error amplifier EA. The differen­tial amplifier, A1, produces a signal equal to the differen­tial voltage sensed across the output capacitor but
re-references it to the internal signal ground (SGND)
reference. The EAIN pin receives a portion of this voltage
feedback signal at the DIFFOUT as determined by VID
logic input pins (VID0 to VID4) and is compared to the
internal reference voltage by the EA. When the load
current increases, it causes a slight decrease in the EAIN
pin voltage relative to the 0.8V reference, which in turn
causes the ITH voltage to increase until the average
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on for the rest of the period.

The top MOSFET drivers are biased from floating boot­strap capacitor CB, which normally is recharged during
each off cycle through an external Schottky diode. When
VIN decreases to a voltage close to V
may enter dropout and attempt to turn on the top MOSFET
continuously. A dropout detector detects this condition
and forces the top MOSFET to turn off for about 400ns
every 10th cycle to recharge the bootstrap capacitor, CB.

The main control loop is shut down by pulling Pin 1 (RUN/
SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with
the ITH voltage clamped at approximately 30% of its
maximum value. As CSS continues to charge, ITH is
gradually released allowing normal operation to resume.
When the RUN/SS pin is low, all LTC1709 functions are
shut down. If V
value when CSS has charged to 4.1V, an overcurrent
latchoff can be invoked as described in the Applications
Information section.

has not reached 70% of its nominal

OUT

, however, the loop

OUT

Low Current Operation

The LTC1709 operates in a continuous, PWM control
mode. The resulting operation at low output currents
optimizes transient response at the expense of substantial
negative inductor current during the latter part of the
period. The level of ripple current is determined by the
inductor value, input voltage, output voltage and fre­quency of operation.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
DC frequency control input of the oscillator that operates
over a 140kHz to 310kHz range corresponding to a DC
voltage input from 0V to 2.4V. When locked, the PLL aligns
the turn on of the top MOSFET to the rising edge of the
synchronizing signal. When PLLIN is left open, the PLLFLTR
pin goes low, forcing the oscillator to minimum frequency.

Input capacitance ESR requirements and efficiency losses
are substantially reduced because the peak current drawn
from the input capacitor is effectively divided by two and
power loss is proportional to the RMS current squared. A
two stage, single output voltage implementation can
reduce input path power loss by 75% and radically reduce
the required RMS current rating of the input capacitor(s).

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and most
of the IC circuitry is derived from INTVCC. When the
EXTVCC pin is left open, an internal 5V low dropout
regulator supplies INTVCC power. If the EXTVCC pin is
taken above 4.7V, the 5V regulator is turned off and an
internal switch is turned on connecting EXTVCC to INTVCC.
This allows the INTVCC power to be derived from a high
efficiency external source such as the output of the regu­lator itself or a secondary winding, as described in the
Applications Information section. An external Schottky
diode can be used to minimize the voltage drop from
EXTVCC to INTV
the specified INTVCC current. Voltages up to 7V can be
applied to EXTVCC for additional gate drive capability.

in applications requiring greater than

CC

10

OPERATIO

LTC1709-8/LTC1709-9

U

(Refer to Functional Diagram)

Differential Amplifier

This amplifier provides true differential output voltage
sensing. Sensing both V
tion in high current applications and/or applications hav­ing electrical interconnection losses. The AMPMD pin
allows selection of internal, precision feedback resistors
for high common mode rejection differencing applica­tions, or direct access to the actual amplifier inputs
without these internal feedback resistors for other applica­tions. The AMPMD pin is grounded to connect the internal
precision resistors in a unity-gain differencing application,
or tied to the INTVCC pin to bypass the internal resistors
and make the amplifier inputs directly available. The
amplifier is a unity-gain stable, 2MHz gain bandwidth,
>120dB open-loop gain design. The amplifier has an
output slew rate of 5V/µs and is capable of driving capaci-
tive loads with an output RMS current typically up to
35mA. The amplifier is not capable of sinking current and
therefore must be resistively loaded to do so.

Power Good (PGOOD)

The PGOOD pin is connected to the drain of an internal
MOSFET. The MOSFET turns on when the output voltage
is not within ±7.5% of its nominal output level as deter­mined by the feedback divider. When the output is within

OUT

+

and V

–

benefits regula-

OUT

±7.5% of its nominal value, the MOSFET is turned off
within 10µs and the PGOOD pin should be pulled up by an
external resistor to a source of up to 7V.

Short-Circuit Detection

The RUN/SS capacitor is used initially to limit the inrush
current from the input power source. Once the controllers
have been given time, as determined by the capacitor on
the RUN/SS pin, to charge up the output capacitors and
provide full-load current, the RUN/SS capacitor is then
used as a short-circuit timeout circuit. If the output voltage
falls to less than 70% of its nominal output voltage the
RUN/SS capacitor begins discharging assuming that the
output is in a severe overcurrent and/or short-circuit
condition. If the condition lasts for a long enough period
as determined by the size of the RUN/SS capacitor, the
controller will be shut down until the RUN/SS pin voltage
is recycled. This built-in latchoff can be overidden by
providing a current >5µA at a compliance of 5V to the
RUN/SS pin. This current shortens the soft-start period
but also prevents net discharge of the RUN/SS capacitor
during a severe overcurrent and/or short-circuit condi­tion. Foldback current limiting is activated when the output
voltage falls below 70% of its nominal level whether or not
the short-circuit latchoff circuit is enabled.

U

WUU

APPLICATIO S I FOR ATIO

The basic LTC1709 application circuit is shown in Fig­ure␣ 1 on the first page. External component selection
begins with the selection of the inductor(s) based on
ripple current requirements and continues with the
R

SENSE1, 2

inductor current and/or maximum current limit. Next, the
power MOSFETs and D1 and D2 are selected. The oper­ating frequency and the inductor are chosen based mainly
on the amount of ripple current. Finally, CIN is selected for
its ability to handle the input ripple current (that
PolyPhaseTM operation minimizes) and C
with low enough ESR to meet the output ripple voltage
and load step specifications (also minimized with
PolyPhase). Current mode architecture provides inherent

resistor selection using the calculated peak

is chosen

OUT

current sharing between output stages. The circuit shown
in Figure␣ 1 can be configured for operation up to an input
voltage of 28V (limited by the external MOSFETs).

R

R
current. The LTC1709 current comparator has a maxi­mum threshold of 75mV/R
mode range of SGND to 1.1(INTVCC). The current com­parator threshold sets the peak inductor current, yielding
a maximum average output current I
value less half the peak-to-peak ripple current, ∆IL.

PolyPhase is a trademark of Linear Technology Corporation.

Selection For Output Current

SENSE

SENSE1, 2

are chosen based on the required peak output

and an input common

SENSE

equal to the peak

MAX

11

LTC1709-8/LTC1709-9

∆I

V

fL

V

V

L

OUT OUT

IN

=−











1

U

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APPLICATIO S I FOR ATIO

Allowing a margin for variations in the LTC1709 and
external component values yields:

R

Operating Frequency

The LTC1709 uses a constant frequency, phase-lockable
architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current
plus an additional current which is proportional to the
voltage applied to the PLLFLTR pin. Refer to Phase­Locked Loop and Frequency Synchronization for addi­tional information.

A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure␣ 2. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 310kHz.

SENSE

= 2(50mV/I

2.5

MAX

)

effect of inductor value on ripple current and low current
operation must also be considered. The PolyPhase ap­proach reduces both input and output ripple currents
while optimizing individual output stages to run at a lower
fundamental frequency, enhancing efficiency.

The inductor value has a direct effect on ripple current.
The inductor ripple current ∆IL per individual section, N,
decreases with higher inductance or frequency and
increases with higher VIN or V

OUT

:

where f is the individual output stage operating frequency.
In a 2-phase converter, the net ripple current seen by the

output capacitor is much smaller than the individual
inductor ripple currents due to ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.

2.0

1.5

1.0

PLLFLTR PIN VOLTAGE (V)

0.5

0

120 170 220 270 320

OPERATING FREQUENCY (kHz)

1709 F02

Figure 2. Operating Frequency vs V

PLLFLTR

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
MOSFET gate charge and transition losses increase di­rectly with frequency. In addition to this basic tradeoff, the

Figure 3 shows the net ripple current seen by the output
capacitors for the 1- and 2- phase configurations. The
output ripple current is plotted for a fixed output voltage as
the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations, simplifying the
design process.

1.0

OUT/VIN

1-PHASE
2-PHASE

)

O(P–P)

1709 F03

)]

0.9

0.8

0.7

0.6

/fL

0.5

O

O(P-P)

V

∆I

0.4

0.3

0.2

0.1
0

0.1 0.2 0.3 0.4

Figure 3. Normalized Output Ripple Current
vs Duty Factor [I

DUTY FACTOR (V

0.5 0.6 0.7 0.8 0.9

≈ 0.3 (∆I

RMS

12

LTC1709-8/LTC1709-9

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APPLICATIO S I FOR ATIO

Accepting larger values of ∆IL allows the use of low
inductances, but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is ∆I
= 0.4(I
ber, the maximum ∆IL occurs at the maximum input
voltage. The individual inductor ripple currents are deter­mined by the inductor, input and output voltages.

Inductor Core Selection

Once the values for L1 and L2 are known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ® cores. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As induc­tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con­centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc­tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple.

)/2, where I

OUT

is the total load current. Remem-

OUT

not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space effi­cient, especially when you can use several layers of wire.
Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.

L

Do

(see EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(VIN < 5V); then, sublogic-level threshold MOSFETs
(V
BV
logic-level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “ON”
resistance R
input voltage and maximum output current. When the
LTC1709 is operating in continuous mode the duty factors
for the top and bottom MOSFETs of each output stage are
given by:

The MOSFET power dissipations at maximum output
current are given by:

where δ is the temperature dependency of R
is a constant inversely related to the gate drive current.

< 1V) should be used. Pay close attention to the

GS(TH)

specification for the MOSFETs as well; most of the

DSS

, reverse transfer capacitance C

DS(ON)

V

Main SwitchDuty Cycle

Synchronous SwitchDuty Cycle



P

MAIN

P

SYNC

V

OUTINMAX

=

V

2

kV

IN

()

–

VVVI

IN OUTINMAX

=










I

I

MAX




2






2








OUT

=

V

IN



VV

IN OUT

=





2

1

R

+

δ

()

Cf

RSS

()()

2

DS ON

2



1

+

()





()

R

δ

+

DS ON

()

–

V

IN

DS(ON)

RSS






and k

,

Power MOSFET, D1 and D2 Selection

Two external power MOSFETs must be selected for each
controller with the LTC1709: one N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTV
voltage. This voltage is typically 5V during start-up

CC

Both MOSFETs have I2R losses but the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
high current efficiency generally improves with larger
MOSFETs, while for V
increase to the point that the use of a higher R
with lower C

Kool Mµ is a registered trademark of Magnetics, Inc.

RSS

> 20V the transition losses rapidly

IN

actual provides higher efficiency. The

< 20V the

IN

DS(ON)

device

13

LTC1709-8/LTC1709-9

U

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APPLICATIO S I FOR ATIO

synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.

The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C

RSS

MOSFET characteristics. The constant k = 1.7 can be
used to estimate the contributions of the two terms in the
main switch dissipation equation.

The Schottky diodes, D1 and D2 shown in Figure 1
conduct during the dead-time between the conduction of
the two large power MOSFETs. This helps prevent the
body diode of the bottom MOSFET from turning on,
storing charge during the dead-time, and requiring a
reverse recovery period which would reduce efficiency. A
1A to 3A Schottky (depending on output current) diode is
generally a good compromise for both regions of opera­tion due to the relatively small average current. Larger
diodes result in additional transition losses due to their
larger junction capacitance.

CIN and C

Selection

OUT

In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V
VIN. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a closed form
equation can be found in Application Note 77. Figure 4
shows the input capacitor ripple current for a 2-phase
configuration with the output voltage fixed and input
voltage varied. The input ripple current is normalized
against the DC output current. The graph can be used in
place of tedious calculations. The minimum input ripple
current can be achieved when the input voltage is twice the
output voltage

In the graph of Figure 4, the 2-phase local maximum input
RMS capacitor currents are reached when:

V

OUT

V

IN

−21

k

=

4

where k = 1, 2

vs temperature curve, but

DS(ON)

is usually specified in the

OUT

/

0.6

0.5

0.4

0.3

0.2

DC LOAD CURRENT

RMS INPUT RIPPLE CURRNET

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Figure 4. Normalized RMS Input Ripple Current
vs Duty Factor for 1 and 2 Output Stages

1-PHASE
2-PHASE

DUTY FACTOR (V

OUT/VIN

0.9

)

170989 F04

These worst-case conditions are commonly used for
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the capacitor manufacturer if there is any
question.

It is important to note that the efficiency loss is propor­tional to the input RMS current

squared

and therefore a
2-phase implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the
reduction of the input ripple current in a 2-phase system.
The required amount of input capacitance is further
reduced by the factor, 2, due to the effective increase in
the frequency of the current pulses.

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically once the ESR require­ment has been met, the RMS current rating generally far
exceeds the I
output ripple (∆V

∆∆V I ESR

OUT RIPPLE

RIPPLE(P-P)

OUT

≈+

requirements. The steady state

) is determined by:






16

fC

1

OUT






14

LTC1709-8/LTC1709-9

U

WUU

APPLICATIO S I FOR ATIO

Where f = operating frequency of each stage, C
output capacitance and ∆I
ripple currents.

The output ripple varies with input voltage since ∆IL is a
function of input voltage. The output ripple will be less than
50mV at max VIN with ∆IL = 0.4I

C
C
The emergence of very low ESR capacitors in small,

surface mount packages makes very physically small
implementations possible. The ability to externally com­pensate the switching regulator loop using the I
pin(OPTI-LOOP compensation) allows a much wider se­lection of output capacitor types. OPTI-LOOP compensa­tion effectively removes constraints on output capacitor
ESR. The impedance characteristics of each capacitor
type are significantly different than an ideal capacitor and
therefore require accurate modeling or bench evaluation
during design.

Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
dielectric capacitor available from Sanyo and the Panasonic
SP surface mount types have the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON type capacitors is recommended to reduce
the inductance effects.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum elec­trolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer sur­face mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV or the KEMET T510
series of surface mount tantalums, available in case heights
ranging from 2mm to 4mm. Other capacitor types include
Sanyo OS-CON, Nichicon PL series and Sprague 595D

required ESR < 4(R

OUT

> 1/(16f)(R

OUT

SENSE

RIPPLE

SENSE

)

= combined inductor

OUT(MAX)

) and

/2 assuming:

OUT

=

TH

series. Consult the manufacturer for other specific recom­mendations. A combination of capacitors will often result
in maximizing performance and minimizing overall cost
and size.

INTVCC Regulator

An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. The INTV
regulator powers the drivers and internal circuitry of the
LTC1709. The INTVCC pin regulator can supply up to 50mA
peak and must be bypassed to power ground with a
minimum of 4.7µF tantalum or electrolytic capacitor. An
additional 1µF ceramic capacitor placed very close to the
IC is recommended due to the extremely high instanta­neous currents required by the MOSFET gate drivers.

High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi­mum junction temperature rating for the LTC1709 to be
exceeded. The supply current is dominated by the gate
charge supply current, in addition to the current drawn
from the differential amplifier output. The gate charge is
dependent on operating frequency as discussed in the
Efficiency Considerations section. The supply current can
either be supplied by the internal 5V regulator or via the
EXTVCC pin. When the voltage applied to the EXTVCC pin
is less than 4.7V, all of the INTVCC load current is supplied
by the internal 5V linear regulator. Power dissipation for
the IC is higher in this case by (IIN)(VIN – INTVCC) and
efficiency is lowered. The junction temperature can be
estimated by using the equations given in Note 1 of the
Electrical Characteristics. For example, the LTC1709 V
current is limited to less than 24mA from a 24V supply:

TJ = 70°C + (24mA)(24V)(85°C/W) = 119°C

Use of the EXTVCC pin reduces the junction temperature
to:

TJ = 70°C + (24mA)(5V)(85°C/W) = 80.2°C

The input supply current should be measured while the
controller is operating in continuous mode at maximum
V

and the power dissipation calculated in order to

IN

prevent the maximum junction temperature from being
exceeded.

CC

IN

15

LTC1709-8/LTC1709-9

1709 F05b

V

IN

TG1

N-CH

N-CH

BG1

PGND

LTC1709

SW1

EXTV

CC

L1

R

SENSE

BAT85

BAT85

BAT85 0.22µF

V

OUT

V

IN

+

C

IN

+

+

C

OUT

VN2222LL

U

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APPLICATIO S I FOR ATIO

EXTVCC Connection

The LTC1709 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
When the voltage applied to EXTV
internal regulator is turned off and an internal switch
closes, connecting the EXTV
thereby supplying internal and MOSFET gate driving power
to the IC. The switch remains closed as long as the voltage
applied to EXTVCC remains above 4.5V. This allows the
MOSFET driver and control power to be derived from the
output during normal operation (4.7V < V
from the internal regulator when the output is out of
regulation (start-up, short-circuit). Do not apply greater
than 7V to the EXTVCC pin and ensure that EXTV

0.3V when using the application circuits shown. If an
external voltage source is applied to the EXTVCC pin when
the VIN supply is not present, a diode can be placed in
series with the LTC1709’s V
between the EXTV

and the V

CC

IN

from backfeeding VIN.
Significant efficiency gains can be realized by powering

INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by the
ratio: (Duty Factor)/(Efficiency). For 5V regulators this
means connecting the EXTVCC pin directly to V
ever, for 3.3V and other lower voltage regulators, addi­tional circuitry is required to derive INTVCC power from the
output.

rises above 4.7V, the

CC

pin to the INTV

CC

EXTVCC

pin

CC

< 7V) and

< V

CC

IN

pin and a Schottky diode

pin, to prevent current

IN

. How-

OUT

+

The following list summarizes the four possible connec­tions for EXTV

1. EXTVCC left open (or grounded). This will cause INTV

CC:

CC

to be powered from the internal 5V regulator resulting in
a significant efficiency penalty at high input voltages.

2. EXTVCC connected directly to V

. This is the normal

OUT

connection for a 5V regulator and provides the highest
efficiency.

3. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 7V range, it may be used to
power EXTVCC providing it is compatible with the MOSFET
gate drive requirements.

4. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency gains
can still be realized by connecting EXTVCC to an output­derived voltage which has been boosted to greater than

4.7V but less than 7V. This can be done with either the
inductive boost winding as shown in Figure 5a or the
capacitive charge pump shown in Figure 5b. The charge
pump has the advantage of simple magnetics.

Topside MOSFET Driver Supply (CB,DB) (Refer to
Functional Diagram)

External bootstrap capacitors CB1 and CB2 connected to
the BOOST1 and BOOST2 pins supply the gate drive
voltages for the topside MOSFETs. Capacitor CB in the
Functional Diagram is charged though diode DB from

OPTIONAL EXTVCC
CONNECTION

< 7V

5V < V

SEC

LTC1709

EXTV

CC

SW1

BG1

PGND

Figure 5a. Secondary Output Loop with EXTVCC Connection Figure 5b. Capacitive Charge Pump for EXTV

16

+

C

IN

V

IN

TG1

N-CH

N-CH

V

IN

1N4148

T1

R

SENSE

V

SEC

+

1µF

V

OUT

+

C

OUT

1709 F05a

CC

LTC1709-8/LTC1709-9

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APPLICATIO S I FOR ATIO

INTVCC when the SW pin is low. When the topside MOSFET
turns on, the driver places the CB voltage across the gate­source of the desired MOSFET. This enhances the MOSFET
and turns on the topside switch. The switch node voltage,
SW, rises to VIN and the BOOST pin rises to VIN + V
The value of the boost capacitor CB needs to be 30 to 100
times that of the total input capacitance of the topside
MOSFET(s). The reverse breakdown of DB must be greater
than V

IN(MAX).

The final arbiter when defining the best gate drive ampli­tude level will be the input supply current. If a change is
made that decreases input current, the efficiency has
improved. If the input current does not change then the
efficiency has not changed either.

Output Voltage

The LTC1709 has a true remote voltage sense capablity.
The sensing connections should be returned from the load
back to the differential amplifier’s inputs through a com­mon, tightly coupled pair of PC traces. The differential
amplifier corrects for DC drops in both the power and
ground paths. The differential amplifier output signal is
divided down and compared with the internal precision

0.8V voltage reference by the error amplifier.

Output Voltage Programming

The output voltage is digitally programmed as defined in
Table 1 using the VID0 to VID4 logic input pins. The VID
logic inputs program a precision, 0.25% internal feedback
resistive divider. The LTC1709-8 has an output voltage
range of 1.30V to 3.5V in 50mV and 100mV steps. The
LTC1709-9 has an output voltage range of 1.10V to 1.85V
in 25mV steps.

Between the ATTENOUT pin and ground is a variable
resistor, R1, whose value is controlled by the five VID input
pins (VID0 to VID4). Another resistor, R2, between the
ATTENIN and the ATTENOUT pins completes the resistive
divider. The output voltage is thus set by the ratio of
(R1␣ +␣ R2) to R1.

INTVCC

.

Table 1. VID Output Voltage Programming

LTC1709-8 LTC1709-9

VID4 VID3 VID2 VID1 VID0 VRM8.4 VRM9.0

00000 2.05V 1.850V
00001 2.00V 1.825V
00010 1.95V 1.800V
00011 1.90V 1.775V
00100 1.85V 1.750V
00101 1.80V 1.725V
00110 1.75V 1.700V
00111 1.70V 1.675V
01000 1.65V 1.650V
01001 1.60V 1.625V
01010 1.55V 1.600V
01011 1.50V 1.575V
01100 1.45V 1.550V
01101 1.40V 1.525V
01110 1.35V 1.500V
01111 1.30V 1.475V
10000 3.50V 1.450V
10001 3.40V 1.425V
10010 3.30V 1.400V
10011 3.20V 1.375V
10100 3.10V 1.350V
10101 3.00V 1.325V
10110 2.90V 1.300V
10111 2.80V 1.275V
11000 2.70V 1.250V
11001 2.60V 1.225V
11010 2.50V 1.200V
11011 2.40V 1.175V
11100 2.30V 1.150V
11101 2.20V 1.125V
11110 2.10V 1.100V
11111No_CPU/ No_CPU/

Shutdown* Shutdown*

*Represents codes without a defined output voltage as specified in Intel
specifications. The LTC1709 interprets these codes as a valid input and
produces an output voltage as follows:

LTC1709-8 (11111) = 2V
LTC1709-9 (11111) = 1.075V

17

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APPLICATIO S I FOR ATIO

Each VID digital input is pulled up by a 40k resistor in
series with a diode from V
grounded to get a digital low input, and can be either
floated or connected to V

BIAS

series diode is used to prevent the digital inputs from
being damaged or clamped if they are driven higher than
V

. The digital inputs accept CMOS voltage levels.

BIAS

V

is the supply voltage for the VID section. It is

BIAS

normally connected to INTVCC but can be driven from
other sources. If it is driven from another source, that
source

must

be in the range of 2.7V to 5.5V and

alive prior to enabling the LTC1709.

Soft-Start/Run Function

The RUN/SS pin provides three functions: 1) Run/Shut­down, 2) soft-start and 3) a defeatable short-circuit latchoff
timer. Soft-start reduces the input power sources’ surge
currents by gradually increasing the controller’s current
limit I

TH(MAX)

. The latchoff timer prevents very short,

extreme load transients from tripping the overcurrent
latch. A small pull-up current (>5µA) supplied to the RUN/
SS pin will prevent the overcurrent latch from operating.
The following explanation describes how the functions
operate.

. Therefore, it must be

BIAS

to get a digital high input. The

must

be

The time for the output current to ramp up is then:

t

IRAMP SS SS

315

=

.

VV

−

12

.

CsFC

A

µ

125

./

=µ

()

By pulling the RUN/SS pin below 0.8V the LTC1709 is put
into low current shutdown (IQ < 40µA). The RUN/SS pins
can be driven directly from logic as shown in Figure 6.
Diode D1 in Figure 6 reduces the start delay but allows
CSS to ramp up slowly providing the soft-start function.
The RUN/SS pin has an internal 6V zener clamp (see
Functional Diagram).

D1*

INTV

CC

RSS*

RUN/SS

170989 F06

C

SS

V

3.3V OR 5V RUN/SS

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

IN

RSS*

D1

C

SS

Figure 6. RUN/SS Pin Interfacing

Fault Conditions: Overcurrent Latchoff

An internal 1.2µA current source charges up the soft-start
capacitor, CSS. When the voltage on RUN/SS reaches

1.5V, the controller is permitted to start operating. As the
voltage on RUN/SS increases from 1.5V to 3.0V, the
internal current limit is increased from 25mV/R
75mV/R

. The output current limit ramps up slowly,

SENSE

SENSE

to

taking an additional 1.4s/µF to reach full current. The
output current thus ramps up slowly, reducing the starting
surge current required from the input power supply. If
RUN/SS has been pulled all the way to ground there is a
delay before starting of approximately:

V

15

t

DELAY SS SS

=

.

12

.

CsFC

=µ

125

./

A

µ

()

The RUN/SS pin also provides the ability to latch off the
controllers when an overcurrent condition is detected. The
RUN/SS capacitor, CSS, is used initially to limit the inrush
current of both controllers. After the controllers have been
started and been given adequate time to charge up the
output capacitors and provide full load current, the RUN/
SS capacitor is used for a short-circuit timer. If the output
voltage falls to less than 70% of its nominal value after C

SS

reaches 4.1V, CSS begins discharging on the assumption
that the output is in an overcurrent condition. If the
condition lasts for a long enough period as determined by
the size of the CSS, the controller will be shut down until the
RUN/SS pin voltage is recycled. If the overload occurs
during start-up, the time can be approximated by:

t

≈ (CSS • 0.6V)/(1.2µA) = 5 • 105 (CSS)

LO1

18

LTC1709-8/LTC1709-9

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APPLICATIO S I FOR ATIO

If the overload occurs after start-up, the voltage on CSS will
continue charging and will provide additional time before
latching off:

t

≈ (CSS • 3V)/(1.2µA) = 2.5 • 106 (CSS)

LO2

This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, RSS, to the RUN/SS pin as
shown in Figure 6. This resistance shortens the soft-start
period and prevents the discharge of the RUN/SS capaci­tor during a severe overcurrent and/or short-circuit con­dition. When deriving the 5µA current from VIN as in the
figure, current latchoff is always defeated. The diode
connecting this pull-up resistor to INTVCC, as in Figure␣ 6,
eliminates any extra supply current during shutdown
while eliminating the INTV

loading from preventing

CC

controller start-up.
Why should you defeat current latchoff? During the

prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is com­plete whether to rely solely on foldback current limiting or
to enable the latchoff feature by removing the pull-up
resistor.

The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci­tance is given by:

CSS > (C

OUT

)(V

)(10-4)(R

OUT

SENSE

)

The minimum recommended soft-start capacitor of CSS =

0.1µF will be sufficient for most applications.

Phase-Locked Loop and Frequency Synchronization

The LTC1709 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the
center frequency fO. A voltage applied to the PLLFLTR pin Figure 7. Phase-Locked Loop Block Diagram

of 1.2V corresponds to a frequency of approximately
220kHz. The nominal operating frequency range of the
LTC1709 is 140kHz to 310kHz.

The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec­tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆fH, is equal to the capture range, ∆f

C:

∆fH = ∆fC = ±0.5 fO (150kHz-300kHz)

The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 7.

If the external frequency (f
lator frequency f

, current is sourced continuously,

0SC

) is greater than the oscil-

PLLIN

pulling up the PLLFLTR pin. When the external frequency
is less than f

, current is sunk continuously, pulling

0SC

down the PLLFLTR pin. If the external and internal fre­quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond­ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor CLP holds the voltage. The
LTC1709 PLLIN pin must be driven from a low impedance
source such as a logic gate located close to the pin.

PLLIN

EXTERNAL

OSC

50k

PHASE

DETECTOR

DIGITAL

PHASE/

FREQUENCY

DETECTOR

2.4V
R

LP

10k

PLLFLTR

1709 F07

OSC

C

LP

19

LTC1709-8/LTC1709-9

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APPLICATIO S I FOR ATIO

The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically R

0.1µF.

Minimum On-Time Considerations

Minimum on-time, t

ON(MIN)

that the LTC1709 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that:

V

t

ON MIN

()

<

Vf

IN

OUT

()

If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1709 will begin to skip
cycles resulting in variable frequency operation. The out­put voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.

The minimum on-time for the LTC1709 is generally less
than 200ns. However, as the peak sense voltage de­creases, the minimum on-time gradually increases. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre­spondingly larger ripple current and voltage ripple.

If an application can operate close to the minimum
on-time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement.

rule, keep the inductor ripple current of each phase equal
to or greater than 15% of I

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak
output voltage excursion under worst-case transient load­ing conditions. The open-loop DC gain of the control loop

=10k and CLP is 0.01µF to

LP

, is the smallest time duration

As a general

OUT(MAX)

at V

IN(MAX)

.

is reduced depending upon the maximum load step speci­fications. Voltage positioning can easily be added to the
LTC1709 by loading the ITH pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage of the error amplifier, or 1.2V
(see Figure 8).

The resistive load reduces the DC loop gain while main­taining the linear control range of the error amplifier. The
worst-case peak-to-peak output voltage deviation due to
transient loading can theoretically be reduced to half or
alternatively the amount of output capacitance can be
reduced for a particular application. A complete explana­tion is included in Design Solutions 10 or the LTC1736
data sheet. (See www.linear-tech.com)

INTV

CC

R

T2

I

TH

R

R

Figure 8. Active Voltage Positioning Applied to the LTC1709

C

T1

C

C

LTC1709

1709 F08

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1709 circuits: 1) I2R losses, 2) Topside
MOSFET transition losses, 3) INTVCC regulator current
and 4) LTC1709 VIN current (including loading on the
differential amplifier output).

20

LTC1709-8/LTC1709-9

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APPLICATIO S I FOR ATIO

1) I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi­mately the same R

, then the resistance of one

DS(ON)

MOSFET can simply be summed with the resistances of L,
R
R

and ESR to obtain I2R losses. For example, if each

SENSE
DS(ON)

= 10mΩ, RL = 10mΩ, and R

= 5mΩ, then the

SENSE

total resistance is 25mΩ. This results in losses ranging
from 2% to 8% as the output current increases from 3A to
15A per output stage for a 5V output, or a 3% to 12% loss
per output stage for a 3.3V output. Efficiency varies as the
inverse square of V

for the same external components

OUT

and output power level. The combined effects of increas­ingly lower output voltages and higher currents required
by high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!

2) Transition losses apply only to the topside MOSFET(s),
and are significant only when operating at high input
voltages (typically 12V or greater). Transition losses can
be estimated from:

Transition Loss = (1.7) V

2

I

IN

O(MAX) CRSS

f

3) INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTVCC to
ground. The resulting dQ/dt is a current out of INTVCC that
is typically much larger than the control circuit current. In
continuous mode, I

GATECHG

= (QT + QB), where QT and Q
are the gate charges of the topside and bottom side
MOSFETs.

Supplying INTV
from an output-derived source will scale the V

power through the EXTVCC switch input

CC

IN

required for the driver and control circuits by the ratio
(Duty Factor)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTVCC current results in approxi­mately 3mA of VIN current. This reduces the mid-current

SENSE

current

,

B

loss from 10% or more (if the driver was powered directly
from VIN) to only a few percent.

4) The VIN current has two components: the first is the
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control cur­rents; the second is the current drawn from the differential
amplifier output. VIN current typically results in a small
(<0.1%) loss.

Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and input fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and a very low ESR at
the switching frequency. A 50W supply will typically
require a minimum of 200µF to 300µF of capacitance
having a maximum of 10mΩ to 20mΩ of ESR. The
LTC1709 2-phase architecture typically halves this input
capacitance requirement over competing solutions. Other
losses including Schottky conduction losses during dead­time and inductor core losses generally account for less
than 2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C

generating the feedback error signal that

OUT

(ESR), where ESR is the effective

LOAD

OUT

(∆I

) also begins to charge or

LOAD

shifts by an

OUT

forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem.

to its steady-state value. During this recovery

OUT

can be monitored for excessive overshoot or

OUT

The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response.

Assuming a predominantly second

order system, phase margin and/or damping factor can be

21

LTC1709-8/LTC1709-9

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APPLICATIO S I FOR ATIO

estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin. The ITH external components
shown in the Figure 1 circuit will provide an adequate
starting point for most applications.

The I
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop gain and phase. An output current pulse of 20% to
80% of full-load current having a rise time of <2µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step resulting
from the step change in output current may not be within
the bandwidth of the feedback loop, so this signal cannot
be used to determine phase margin. This is why it is
better to look at the Ith pin signal which is in the feedback
loop and is the filtered and compensated control loop
response. The gain of the loop will be increased by
increasing RC and the bandwidth of the loop will be
increased by decreasing CC. If RC is increased by the
same factor that CC is decreased, the zero frequency will
be kept the same, thereby keeping the phase the same in
the most critical frequency range of the feedback loop.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.

series RC-CC filter sets the dominant pole-zero

TH

Automotive Considerations: Plugging into the
Cigarette Lighter

As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during opera­tion. But before you connect, be advised: you are plugging
into the supply from hell. The main battery line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery, and
double-battery.

Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.

The network shown in Figure 9 is the most straightfor­ward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse-battery,
while the transient suppressor clamps the input voltage
during load-dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LT1709 has a maximum input
voltage of 36V, most applications will be limited to 30V by
the MOSFET BV

DSS

.

22

50A I

RATING

PK

12V

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

1.5KA24A

Figure 9. Automotive Application Protection

V

IN

LTC1709

170989 F09

LTC1709-8/LTC1709-9

DF

V

V

V

V

O

IN

== =

18

5

036..

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APPLICATIO S I FOR ATIO

Design Example

As a design example, assume VIN = 5V (nominal), VIN␣ =␣ 5.5V
(max), V

The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the FREQSET pin
to the INTVCC pin for 300kHz operation. The minimum
inductance for 30% ripple current is:

L

≥

≥

≥µ

A 1.5µH inductor will produce 27% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 11.4A. The minimum on­time occurs at maximum VIN:

t

ON MIN

The R
maximum current sense voltage specification with some
accomodation for tolerances:

= 1.8V, I

OUT



V

OUT OUT

fI

()

300 30 10

()()()

135

.

()

SENSE

−

1





∆

18

.

kHz A

H

V

OUT

==

Vf

IN

resistors value can be calculated by using the

= 20A, TA = 70°C and f␣ =␣ 300kHz.

MAX



V



V



IN

V

%

()( )



−

1





V

18

.

V kHz

5 5 300

.

18

.

55

.



V



V



=µ

11

.

s

The worst-case power disipated by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem­perature rise is:

..

VV

−

=

=
=

25

0 004

.

=
=

55 18

.

V

55

.

W

129

mV

Ω

..

55 18

564



1



+



2



VV

−

.

V

55
mW

200 5 5

P

SYNC

A short-circuit to ground will result in a folded back current
of about:

I

SC

The worst-case power disipated by the synchronous
MOSFET under short-circuit conditions at elevated ambi­ent temperature and estimated 50°C junction temperature
rise is:

P

SYNC

which is less than half of the normal, full-load dissipation.
Incidentally, since the load no longer dissipates power in
the shorted condition, total system power dissipation is
decreased by over 99%.

2

..

A

10 1 48 0 013

()()

ns V

()

H

µ

15

.

...

A

66 148 0013

()()

()



.



=



2

Ω

A

66

.

()

Ω

R

SENSE

The power dissipation on the topside MOSFET can be
easily estimated. Using a Siliconix Si4420DY for example;
R

DS(ON)

voltage with TJ (estimated) = 110°C at an elevated ambient
temperature:

P

MAIN

mV

50

=≈Ω

11 4

= 0.013Ω, C

.

18

V

=

.

55

V

...

0 013 1 7 5 5 10 300

300 0 65

kHz W

()

0 004

.

A

.

= 300pF. At maximum input

RSS

2

10 1 0 005 110 25

()+()

Ω

+

=

.

[]

()()( )

.

()

2

VApF

CC

°− °

The duty factor for this application is:

Using Figure 4, the RMS ripple current will be:

I

= (20A)(0.23) = 4.6A

INRMS

An input capacitor(s) with a 4.6A
is required.

The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
and multiplying by the factor obtained from Figure␣ 3
along with the calculated duty factor. The output ripple in

RMS

ripple current rating

RMS

23

LTC1709-8/LTC1709-9

U

WUU

APPLICATIO S I FOR ATIO

con

tinuous mode will be highest at the maximum input
voltage since the duty factor is <50%. The maximum
output current ripple is:

V

OUT

03 33

∆∆I

VmAmV

OUTRIPPLE RMS RMS

PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1709. These items are also illustrated graphically in
the layout diagram of Figure␣ 10. Check the following in
your layout:

1) Are the signal and power grounds segregated? The
LTC1709 signal ground pin should return to the (–) plate
of C
sources of the bottom N-channel MOSFETs, anodes of the
Schottky diodes, and (–) plates of CIN, which should have
as short lead lengths as possible.

2) Does the LTC1709 V
load? Does the LTC1709 V
return?

3) Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitors between
SENSE+ and SENSE– pin pairs should be as close as
possible to the LTC1709. Ensure accurate current sensing
with Kelvin connections at the current sense resistor.

4) Does the (+) plate of CIN connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the AC current to the MOSFETs. Keep the input

=

COUT

I

COUTMAX

separately. The power ground returns to the

OUT

.%

at DF

()

fL

18

.

=

300 1 5

()

12

.

=

20 1 2 24

=Ω

V

kHz H

()

A

RMS

.

()

+

pin connect to the point of

OS

OS

03

.

.

µ

=

–

pin connect to the load

current path formed by the input capacitor, top and bottom
MOSFETs, and the Schottky diode on the same side of the
PC board in a tight loop to minimize conducted and
radiated EMI.

5) Is the INTVCC 1µF ceramic decoupling capacitor con-
nected closely between INTVCC and the power ground pin?
This capacitor carries the MOSFET driver peak currents. A
small value is recommended to allow placement immedi­ately adjacent to the IC.

6) Keep the switching nodes, SW1 (SW2), away from
sensitive small-signal nodes. Ideally the switch nodes
should be placed at the furthest point from the LTC1709.

7) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.

The diagram in Figure 10 illustrates all branch currents in
a 2-phase switching regulator. It becomes very clear after
studying the current waveforms why it is critical to keep
the high-switching-current paths to a small physical size.
High electric and magnetic fields will radiate from these
“loops” just as radio stations transmit signals. The output
capacitor ground should return to the negative terminal of
the input capacitor and not share a common ground path
with any switched current paths. The left half of the circuit
gives rise to the “noise” generated by a switching regula­tor. The ground terminations of the sychronous MOSFETs
and Schottky diodes should return to the negative plate(s)
of the input capacitor(s) with a short isolated PC trace
since very high switched currents are present. A separate
isolated path from the negative plate(s) of the input
capacitor(s) should be used to tie in the IC power ground
pin (PGND) and the signal ground pin (SGND). This
technique keeps inherent signals generated by high cur­rent pulses from taking alternate current paths that have
finite impedances during the total period of the switching
regulator. External OPTI-LOOP compensation allows over­compensation for PC layouts which are not optimized but
this is not the recommended design procedure.

24

LTC1709-8/LTC1709-9

U

WUU

APPLICATIO S I FOR ATIO

SW1

V

IN

R

IN

+

C

IN

SW2

L1

D1

L2

R

SENSE1

R

SENSE2

V

OUT

C

OUT

+

R

L

BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.

D2

Figure 10. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator

Simplified Visual Explanation of How a 2-Phase
Controller Reduces Both Input and Output RMS Ripple
Current

A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is divided by, and
the effective ripple frequency is multiplied up by the
number of phases used (assuming that the input voltage
is greater than the number of phases used times the output
voltage). The output ripple amplitude is also reduced by,
and the effective ripple frequency is increased by the
number of phases used. Figure 11 graphically illustrates
the principle.

SW V

I

CIN

I

COUT

SW1 V

SW2 V

I

I

I

CIN

I

COUT

L1

L2

Figure 11. Single and 2-Phase Current Waveforms

170989 F10

DUAL PHASESINGLE PHASE

RIPPLE

1709 F11

25

LTC1709-8/LTC1709-9

U

WUU

APPLICATIO S I FOR ATIO

The worst-case RMS ripple current for a single stage
design peaks at an input voltage of twice the output
voltage. The worst-case RMS ripple current for a two stage
design results in peak outputs of 1/4 and 3/4 of input
voltage. When the RMS current is calculated, higher
effective duty factor results and the peak current levels are
divided as long as the currents in each stage are balanced.
Refer to Application Note 19 for a detailed description of
how to calculate RMS current for the single stage switch­ing regulator. Figures 3 and 4 help to illustrate how the
input and output currents are reduced by using an addi­tional phase. The input current peaks drop in half and the
frequency is doubled for this 2-phase converter. The input
capacity requirement is thus reduced theoretically by a
factor of four! Ceramic input capacitors with their
unbeatably low ESR characteristics can be used.

Figure 4 illustrates the RMS input current drawn from the
input capacitance vs the duty cycle as determined by the
ratio of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 50%
in a 2-phase solution due to the current splitting between
the two stages.

An interesting result of the 2-phase solution is that the V
which produces worst-case ripple current for the input
capacitor, V
duces zero input current ripple in the 2-phase design.

The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V
term from the stage that has its bottom MOSFET on
subtracts current from the (VIN - V
resulting from the stage which has its top MOSFET on. The
output ripple current is:

∆I

RIPPLE

where D is duty factor.
The input and output ripple frequency is increased by the

number of stages used, reducing the output capacity
requirements. When VIN is approximately equal to 2(V
as illustrated in Figures 3 and 4, very low input and output
ripple currents result.

= VIN/2, in the single phase design pro-

OUT

/L discharge current

OUT

)/L charging current

OUT



12 1

−−

DD

2

V

OUT

fL






=

()

−+

12 1

D







OUT

IN

)

26

PACKAGE DESCRIPTIO

5.20 – 5.38**
(0.205 – 0.212)

LTC1709-8/LTC1709-9

U

Dimensions in inches (millimeters) unless otherwise noted.

G Package

36-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

12.67 – 12.93*
(0.499 – 0.509)

2526 22 21 20 19232427282930313233343536

12345678 9 10 11 12 14 15 16 17 1813

7.65 – 7.90

(0.301 – 0.311)

1.73 – 1.99

(0.068 – 0.078)

° – 8°

0

0.13 – 0.22

(0.005 – 0.009)

NOTE: DIMENSIONS ARE IN MILLIMETERS

*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

0.55 – 0.95

(0.022 – 0.037)

0.65

(0.0256)

BSC

0.25 – 0.38

(0.010 – 0.015)

0.05 – 0.21

(0.002 – 0.008)

G36 SSOP 1098

27

LTC1709-8/LTC1709-9

U

TYPICAL APPLICATIO

LTC1709-8

1

RUNN/SS

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

SENSE1

SENSE1

EAIN

PLLFLTR

PLLIN

NC

I

TH

SGND

V

DIFFOUT

VOS–

V

+

OS

SENSE2

SENSE2

ATTENOUT

ATTENIN

VID0

VID1

INTV

47k

2.7k

CC

15k

3.3nF

0.1µF

1000pF

1000pF

10k

51k

100pF

470pF

+

–

–

+

TG1

SW1

BOOST1

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

PGOOD

V

BIAS

VID4

VID3

VID2

36

NC

35

34

0.22µF

33

32

V

IN

31

30

5V (OPT)

CC

29

CC

10µF

28

27

26

0.22µF

25

24

23

22

0.1µF

21

20

19

100k

10Ω

10Ω

0.1µF

PGOOD

L1

0.004Ω

M1 M2

C

IN

47µF 35V

+

M3

M4

0.004Ω

L2

D1
MBRS140T3

+

C

OUT

D2
MBRS140T3

SWITCHING FREQUENCY = 200kHz
C

: 5A RIPPLE CURRENT RATING REQUIRED

IN

C

: 4 × 180µF/4V PANASONIC SP

OUT

L1 TO L2: 1.5µH SUMIDA CEP125-1R5MC
M1 TO M4: FAIRCHILD FDS7760A

V

IN

5V TO 28V

V

OUT

1.3V TO 3.5V
20A

VID INPUTS

170989 F12

Figure 12. 1.3V to 2.5V/20A CPU Power Supply with Active Voltage Positioning

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Adaptive Power and Burst Mode are trademarks of Linear Technology Corporation.

≤ 3.5V, Current Mode Ensures

OUT

≤ 3.5V, Current Mode Ensures

OUT

IN

≤ 36V

IN

≤ 2V

OUT

≤ 36V

28

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone] ● www.linear-tech.com

170989i LT/TP 0500 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2000