Datasheet LTC1708-PG Datasheet (Linear Technology)

LTC1708-PG

Final Electrical Specifications

Dual Adjustable 5-Bit VID

High Efficiency, 2-Phase Current Mode

Synchronous Buck Regulator Controller

FEATURES

■

Out-of-Phase Controllers Reduce Input Capacitance
and Power Supply Induced Noise

■

OPTI-LOOPTM Compensation Minimizes C

■

Power Good Output Monitors Both Outputs

■

5-Bit Mobile VID Control, V

■

Dual N-Channel MOSFET Synchronous Drive

■

±1% Output Voltage Accuracy

■

DC Programmed Fixed Frequency 150kHz to 300kHz

■

Wide VIN Range: 3.5V to 36V Operation

■

Very Low Dropout Operation: 99% Duty Cycle

■

Adjustable Soft-Start Current Ramping

■

Foldback Output Current Limiting

■

Latched Short-Circuit Shutdown with Defeat Option

■

Output Overvoltage Protection

■

Remote Output Voltage Sense

■

Low Shutdown Current: 20µA

■

5V and 3.3V Standby Regulators

■

Selectable Constant Frequency, Burst ModeTM and

: 0.9V to 2.0V

OUT

OUT

Continuous Operation

U

APPLICATIO S

■

Notebook and Palmtop Computers, PDAs

■

Portable Instruments

U

February 2000

DESCRIPTIO

The LTC®1708 is a dual adjustable 5-bit VID program­mable step-down switching regulator controller that drives
all N-Channel power MOSFET stages. A constant fre­quency current mode architecture allows adjustment of
the frequency up to 300kHz. Power loss and noise due to
the ESR of the input capacitance are minimized by oper­ating the two main controller output stages out of phase.

OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The precision 0.8V reference is compat­ible with future microprocessor generations, and a wide

3.5V to 30V (36V maximum) input supply range that
encompasses all battery chemistries. A power good out­put indicates when the output voltages are within 7.5% of
their programmed value.

A RUN/SS pin for each controller provides both soft-start
and an optional timed, short-circuit shutdown. Other
protection features include: internal foldback current lim­iting and an output overvoltage crowbar. The force con­tinuous control pin (FCB) can be used to inhibit Burst
Mode operation or to regulate a third, flyback output.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

R

SENSE1

0.003Ω

V

OUT1

0.925V TO

2.00V

14.1A

C
10µF

6.3V
CERAMIC

U

+

4.7µF

D3

1µH

OUT1a

VINVIDVCCINTV

L1

M1

M2

D1

C

OUT1

+

270µF
2V
SP
×4

C

B1

0.47µF

5 VID BITS

1000pF

C
1500pF

R

C1

22k

C1

TG1 TG2

BOOST1 BOOST2
SW1 SW2

LTC1708-PG

BG1 BG2

VID0 TO VID4 PGND

+

SENSE1

–

SENSE1
ATTNIN V
I

TH1

RUN/SS1 RUN/SS2SGND

C

SS1

0.1µF

SENSE2

PGOOD

SENSE2

OSENSE2

CC

+

–

I

TH2

C

SS2

0.1µF

Figure 1. High Efficiency VID Controlled, 2-Output Step-Down Converter

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

D4

C

220pF

C2

R
15k

C

B2

C2

1µF
CERAMIC

0.1µF

1000pF

20k
1%

V

IN

L2

R

SENSE2

C

180µF

0.01Ω

OUT

4V
SP

4.75V TO 28V

V

OUT2

1.5V
4A

M1: IRF7811

+

M2: 1RF7809
M3a, M3b: FDS6982
L1: VISHAY 5050CE
ATTNOUT CONNECTED TO EAIN1

1628 F01

C

IN

10µF
50V
CERAMIC

M3a

×4

2.2µH

M3b

D2

R4

63.4k
1%

R3

1

LTC1708-PG

WW

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

Input Supply Voltage (VIN).........................36V to –0.3V

Topside Driver Voltages

(BOOST1, BOOST2) ...................................42V to –0.3V

Switch Voltage (SW1, SW2) .........................36V to – 5V

INTV

(BOOST1-SW1), (BOOST2-SW2), ...............7V to –0.3V

SENSE1+, SENSE2+, SENSE1–,

SENSE2– Voltages....................... (1.1)INTVCC to –0.3V

FREQSET, STBYMD, FCB, VIDVCC, VID0-4,

PGOOD Voltages..........................................7V to –0.3V

I

TH1, ITH2

ATTNOUT Voltages ...................................2.7V to –0.3V

Peak Output Current <10µs (TG1, TG2, BG1, BG2) ... 3A

INTVCC Peak Output Current ................................ 50mA

Operating Ambient Temperature Range

(Note 2) ...................................................–40°C to 85°C

Junction Temperature (Note 3)............................. 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

EXTVCC, RUN/SS1, RUN/SS2,

CC,

, EAIN1, EAIN2, ATTNIN,

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

RUN/SS1

SENSE1
SENSE1

EAIN1

FREQSET

STBYMD

FCB

I

TH1

SGND

3.3V

OUT

I

TH2

EAIN2
SENSE2
SENSE2

ATTNOUT

ATTNIN

VID0
VID1

1

+

2

–

3
4
5
6
7
8

9
10
11
12

–

13

+

14
15
16
17
18

G PACKAGE

36-LEAD PLASTIC SSOP

T

= 125°C, θJA = 85°C/W

JMAX

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

PGOOD
TG1
SW1
BOOST1
V

IN

BG1
EXTV

CC

INTV

CC

PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
VIDV

CC

VID4
VID3
VID2

Consult factory for Industrial and Military grade parts.

ORDER PART

NUMBER

LTC1708EG-PG

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes the specifications which apply over the full operating

RUN/SS1, 2

= 5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops

V

EAIN1, 2

Regulated Feedback Voltage (Note 4); I

Voltage = 1.2V ● 0.792 0.800 0.808 V

TH1, 2

at EAIN Pin

I

EAIN1, 2

V

REFLNREG

V

LOADREG

g

m1, 2

g

mOL1, 2

I

Q

V

FCB

I

FCB

V

BINHIBIT

Feedback Current (Note 4) –5 – 50 nA
Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 4) 0.002 0.02 %/V
Output Voltage Load Regulation (Note 4)

Transconductance Amplifier g

m

Transconductance Amplifier GBW I

Measured in Servo Loop; I
Measured in Servo Loop; I

I

= 1.2V; Sink/Source 5µA; (Note 4) 1.3 mmho

TH1, 2

= 1.2V; (gm • ZL, No Ext Load) (Note 4) 3 MHz

TH1, 2

Voltage = 1.2V to 0.7V ● 0.1 0.5 %

TH1, 2

Voltage = 1.2V to 2.0V ● –0.1 –0.5 %

TH1, 2

Input DC Supply Current (Note 5)

Normal Mode EXTV
Standby V
Shutdown V

Tied to GND; VID Inputs Open Circuit 850 µA

CC
RUN/SS1, 2
RUN/SS1, 2

= 0V, V
= 0V, V

> 2V 125 µA

STBYMD

= Open 20 35 µA

STBYMD

Forced Continuous Threshold ● 0.760 0.800 0.840 V
Forced Continuous Current V

= 0.85V –0.3 – 0.18 – 0.1 µA

FCB

Burst Inhibit Threshold Measured at FCB pin 4.3 4.8 V

UVLO Undervoltage Lockout VIN Ramping Down 3.5 4 V

2

LTC1708-PG

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes the specifications which apply over the full operating

RUN/SS1, 2

= 5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

OV

I

SENSE

V

STBYMD

V

STBYMD

DF

MAX

I

RUN/SS1, 2

V

RUN/SS1, 2

V

RUN/SS1, 2

I

SCL1, 2

I

SDLHO

V

SENSE(MAX)

Output Overvoltage Threshold Measured at EAIN1, 2 0.84 0.86 0.88 V

Sense Pins Total Source Current (Each Channel); V
MS Master Shutdown Threshold V
KA Keep-Alive Power On-Threshold V

SENSE1–, 2–

Ramping Down 0.4 0.6 V

STBYMD

Ramping Up, RUN

STBYMD

= V

SENSE1+, 2+

= 0V 1.5 2 V

SS1, 2

= 0V –85 –60 µA

Maximum Duty Factor In Dropout 98 99.4 %

Soft-Start Charge Current V

ON RUN/SS Pin ON Threshold V
LT RUN/SS Pin Latchoff Threshold V

RUN/SS1, 2

RUN/SS1, VRUN/SS2

RUN/SS1, VRUN/SS2

RUN/SS Discharge Current Soft Short Condition E

V

RUN/SS1, 2

= 1.9V 0.5 1.2 µA

Rising 1.0 1.5 1.9 V
Rising from 3V 4.1 4.5 V

= 0.5V; 0.5 2 4 µA

AIN1, 2

= 4.5V
Shutdown Latch Disable Current EAIN1, 2 = 0.5V 1.6 5 µA
Maximum Current Sense Threshold V

EAIN1, 2

V

EAIN1, 2

= 0.7V; V
= 0.7V; V

= 5V 65 75 85 mV

SENSE1, 2

= 5V ● 62 75 88 mV

SENSE1, 2

TG Transition Time:

TG1, 2 t
TG1, 2 t

r
f

Rise Time C
Fall Time C

= 3300pF (Note 10) 50 90 ns

LOAD

= 3300pF (Note 10) 50 90 ns

LOAD

BG Transition Time:

BG1, 2 t
BG1, 2 t

TG/BG t

r
f

1D

Rise Time C
Fall Time C

Top Gate Off to Bottom Gate On Delay C

= 3300pF (Note 10) 40 90 ns

LOAD

= 3300pF (Note 10) 40 80 ns

LOAD

= 3300pF Each Driver (Note 10) 90 ns

LOAD

Synchronous Switch-On Delay Time

BG/TG t

2D

Bottom Gate Off to Top Gate On Delay C

= 3300pF Each Driver (Note 10) 90 ns

LOAD

Top Switch-On Delay Time

t

ON(MIN)

Minimum On-Time Tested with a Square Wave (Notes 6, 10) 160 200 ns

INTVCC Linear Regulator

V

INTVCC

V

INT INTVCC Load Regulation ICC = 0 to 20mA, V

LDO

V

EXT EXTVCC Voltage Drop ICC = 20mA, V

LDO

V

EXTVCC

V

LDOHYS

Internal VCC Voltage 6V < VIN < 30V, V

EXTVCC

EXTVCC Switchover Voltage ICC = 20mA, EXTV

= 4V 4.8 5.0 5.2 V

EXTVCC

= 4V 0.2 1.0 %

EXTVCC

= 5V 120 240 mV
Ramping Positive ● 4.5 4.7 V

CC

EXTVCC Hysteresis 0.2 V

Oscillator

f

OSC

f

LOW

f

HIGH

I

FREQSET

Oscillator Frequency V
Lowest Frequency V
Highest Frequency V
FREQSET Input Current V

= Open (Note 7) 190 220 250 kHz

FREQSET

= 0V 120 140 170 kHz

FREQSET

= 2.4V 280 310 350 kHz

FREQSET

= 0V –2 – 1 µA

FREQSET

3.3V Linear Regulator

V

3.3OUT

V

3.3IL

V

3.3VL

3.3V Regulator Output Voltage No Load ● 3.25 3.35 3.45 V

3.3V Regulator Load Regulation I

3.3V Regulator Line Regulation 6V < V

= 0 to 10mA 0.5 2 %

3.3

< 30V 0.05 0.2 %

IN

PGOOD Output

V

PGL

I

PGOOD

V

PG

PGOOD Voltage Low I
PGOOD Leakage Current V

= 2mA 0.1 0.3 V

PGOOD

= 5V 1 µA

PGOOD

PGOOD Trip Level Relative to the 0.8V Regulated Feedback Voltage

EAIN1, 2 Ramping Negative from 0.8V – 10 –7.5 – 5 %
EAIN1, 2 Ramping Positive from 0.8V 5 7.5 10 %

3

LTC1708-PG

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes the specifications which apply over the full operating

RUN/SS1, 2

= 5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VID Parameters

VIDV

CC

I

VIDVCC

R

FBOUT1/SENSE1

R

RATIO

R

PULL-UP

V

IDT

I

VIDLEAK

V

PULL-UP

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The LTC1708EG-PG is guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.

Note 3: T
dissipation P

LTC1708EG-PG: T

Note 4: The LTC1708-PG is tested in a feedback loop that servos V
to a specified voltage and measures the resultant EAIN1, 2.

Note 5: The supply current is higher due to the gate charge being delivered
at the switching frequency. See Applications Information.

VID Operating Supply Voltage 2.7 5.5 V
VID Supply Current VIDVCC = 3.3V (Note 8) 0.01 5 µA
Resistance Between ATTNIN/ATTNOUT 10 5 kΩ
Resistor Ratio Accuracy Programmed from 0.925V to 2.00V 0.25 %
VID0 to VID4 Pull-Up Resistance (Note 9) V

= 0.7V 40 kΩ

DIODE

VID Voltage Threshold 0.4 1.0 1.6 V
VID Input Leakage Current (Note 9) VIDVCC < VIDVCC < 7V 0.1 1 µA
VID Pull-Up Voltage VIDVCC = 3V 2.5 2.8 3.1 V

Note 6: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current ≥40% of I

(see minimum on-time

MAX

considerations in the Applications Information section).
Note 7: V

pin internally tied to 1.19V reference through a large

FREQSET

resistance.
Note 8: With all five VID inputs floating (or tied to VIDV

is calculated from the ambient temperature TA and power

J

according to the following formulas:

D

= TA + (PD • 85°C/W)

J

ITH1, 2

current is typically <1µA. However, the VIDVCC current will rise and be
approximately equal to the number of grounded VID input pins times

– 0.6V)/40k. (See the Applications Information section.)

(VIDV

CC

Note 9: Each built-in pull-up resistor attached to the VID inputs also has a
series diode to allow input voltages higher than the VIDV
damage or clamping. (See Applications Information section.)

Note 10: Rise and fall times are measured at 20% to 80% levels. Delay

) the VIDV

CC

supply without

CC

CC

and nonoverlap times are measured using 50% levels.

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Output Current
and Mode (Figure 12)

100

90

Burst Mode

OPERATION

80
70
60

50
40

EFFICIENCY (%)

30
20
10

0

0.1

CONSTANT FREQUENCY
MODE

PWM MODE

1

OUTPUT CURRENT (A)

10

15A

VIN = 15V

= 1.6V

V

OUT

100

1708 G01

Efficiency vs Output Current
(Figure 12)

100

90
80
70
60
50
40

EFFICIENCY (%)

30
20
10

0

0.01

EXTV

V

IN

= 0V

CC

= 5V

VIN = 10V

V

= 15V

IN

VIN = 20V

0.1
OUTPUT CURRENT (A)

1

V
V

FCB
OUT

10

15A

= OPEN
= 1.6V

1708 G02

100

Efficiency vs Input Voltage
(Figure 12)

100

V

= 1.6V

OUT

= 0V

EXTV

CC

90

80

70

EFFICIENCY (%)

60

50

510

15 20

INPUT VOLTAGE (V)

I

I

OUT

OUT

= 7A

= 12A

25

1708 G03

28

4

UW

TEMPERATURE (°C)

–50

INTV

CC

AND EXTV

CC

SWITCH VOLTAGE (V)

4.95

5.00

5.05

25 75

1708 G06

4.90

4.85

–25 0

50 100 125

4.80

4.70

4.75

INTVCC VOLTAGE

EXTVCC SWITCHOVER THRESHOLD

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1708-PG

Supply Current vs Input Voltage
and Mode (Figure 12)

1000

800

600

400

SUPPLY CURRENT (µA)

200

0

05

BOTH
CONTROLLERS ON

STANDBY

SHUTDOWN

10

INPUT VOLTAGE (V)

20

15

Internal 5V LDO Line Reg

5.1
I

= 1mA

LOAD

5.0

4.9

4.8

VOLTAGE (V)

4.7

CC

INTV

4.6

4.5

4.4

0

510

INPUT VOLTAGE (V)

20 30 35

15 25

INTVCC and EXTVCC Switch

EXTVCC Voltage Drop

250

200

150

100

VOLTAGE DROP (mV)

CC

EXTV

50

30

35

1708 G04

25

0

10

0

CURRENT (mA)

30

40

20

50

1708 G05

Voltage vs Temperature

Maximum Current Sense Threshold

1708 G07

Maximum Current Sense Threshold
vs Duty Factor

75

50

(mV)

SENSE

V

25

0

0

20 40 60 80

DUTY FACTOR (%)

100

1708 G08

vs Percent of Nominal Output
Voltage (Foldback)

80

70

60

50

(mV)

40

SENSE

V

30

20

10

0

0

25

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

50

75

100

1708 G09

80

60

(mV)

40

SENSE

V

20

0

Maximum Current Sense Threshold
vs V

V

SENSE(CM)

0

(Soft-Start)

RUN/SS

= 1.6V

1234

V

(V)

RUN/SS

56

1708 G10

Maximum Current Sense Threshold
vs Sense Common Mode Voltage

80

76

72

(mV)

SENSE

68

V

64

60

1

0

2

COMMON MODE VOLTAGE (V)

3

Current Sense Threshold
vs ITH Voltage

90
80
70
60
50
40

(mV)

30
20

SENSE

V

10

0
–10
–20

4

5

1708 G11

–30

0.5

0

1.5

2

1

V

(V)

ITH

2.5

1708 G12

5

LTC1708-PG

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Load Regulation

0.0

–0.1

(%)

OUT

–0.2

NORMALIZED V

–0.3

–0.4

0

1

2

LOAD CURRENT (A)

FCB = 0V

= 15V

V

IN

FIGURE 1
V

OUT2

3

4

5

1708 G13

(V)

ITH

V

2.5

2.0

1.5

1.0

0.5

V

vs V

ITH

RUN/SS

V

= 0.7V

EAIN

0

0

234

1

V

RUN/SS

(V)

Maximum Current Sense
Threshold vs Temperature Dropout Voltage vs Output Current

80

78

76

(mV)

SENSE

74

V

72

70

–50 –25

50

25

0

TEMPERATURE (°C)

100

125

1708 G17

75

4

V

= 5V

OUT

3

2

DROPOUT VOLTAGE (V)

1

0

0

0.5 1.0 1.5 2.0
OUTPUT CURRENT (A)

R

SENSE

R

= 0.015Ω

SENSE

= 0.010Ω

2.5 3.0 3.5 4.0

56

1708 G14

1708 G18

SENSE Pins Total Source Current

100

50

(µA)

0

SENSE

I

–50

–100

0

24

V

COMMON MODE VOLTAGE (V)

SENSE

RUN/SS Current vs Temperature

1.8

1.6

1.4

1.2

1.0

0.8

0.6

RUN/SS CURRENT (µA)

0.4

0.2

0

–50 –25

0 25 125

TEMPERATURE (°C)

6

1708 G15

75 10050

1708 G25

V

OUT

100mV/DIV

I

OUT

5A/DIV

6

Load Step (Figure 12)

= 15V 10µs/DIV 1708 G22

V

IN

V

= 1.6V

OUT2

LOAD STEP = 100mA – 15A
CONSTANT FREQUENCY MODE: V
ACTIVE VOLTAGE POSITIONING CIRCUIT

FCB

= V

INTVCC

V

OUT

100mV/DIV

I

OUT

5A/DIV

Load Step (Figure 12)

V

= 15V 10µs/DIV 1708 G20

IN

V

= 1.6V

OUT2

LOAD STEP = 100mA – 15A
Burst Mode OPERATION: V
ACTIVE VOLTAGE POSITIONING CIRCUIT

FCB

= OPEN

V

OUT

100mV/DIV

I

OUT

5A/DIV

Load Step (Figure 12)

VIN = 15V 10µs/DIV 1708 G21
V

= 1.6V

OUT2

LOAD STEP = 100mA – 15A
CONTINUOUS MODE: V
ACTIVE VOLTAGE POSITIONING CIRCUIT

FCB

= 0V

UW

TEMPERATURE (°C)

–50

200

250

350

25 75

1708 G28

150

100

–25 0

50 100 125

50

0

300

FREQUENCY (kHz)

V

FREQSET

= 5V

V

FREQSET

= OPEN

V

FREQSET

= 0V

TYPICAL PERFOR A CE CHARACTERISTICS

Soft-Start Up (Figure 12)

V

RUN/SS

2V/DIV

V

OUT

1V/DIV

I

OUT

5A/DIV

20mV/DIV

Burst Mode Operation (Figure 12)

V

OUT

I

OUT

5A/DIV

V

OUT

20mV/DIV

I

OUT

2A/DIV

LTC1708-PG

Constant Frequency (Burst Inhibit)
Operation (Figure 12)

CURRENT SENSE INPUT CURRENT (µA)

V

= 15V 100ms/DIV 1708 G19

IN

V

= 1.6V

OUT2

Current Sense Input Current
vs Temperature

35

33

31

29

27

25

–50 –25

0

TEMPERATURE (°C)

50

25

Undervoltage Lockout
vs Temperature

3.50

3.45

3.40

3.35

3.30

UNDERVOLTAGE LOCKOUT (V)

3.25

3.20
–50

–25 0

75

100

1708 G26

25 75

TEMPERATURE (°C)

10

8

6

4

SWITCH RESISTANCE (Ω)

CC

2

EXTV

125

50 100 125

0

V

= 15V 20µs/DIV 1708 G23

IN

V

= 1.6V

OUT2

= OPEN

V

FCB

I

= 250mA

OUT

EXTVCC Switch Resistance
vs Temperature

50

25

–50 –25

1708 G29

0

TEMPERATURE (°C)

75

V

IN

V

OUT2

V

FCB

I

OUT

Oscillator Frequency
vs Temperature

125

100

1708 G27

Shutdown Latch Thresholds
vs Temperature

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

SHUTDOWN LATCH THRESHOLDS (V)

0

–50 –25

LATCH ARMING

LATCHOFF

THRESHOLD

0 25 125

TEMPERATURE (°C)

= 15V 20µs/DIV 1708 G24

= 1.6V

= V

INTVCC

= 250mA

75 10050

1708 G30

7

LTC1708-PG

UUU

PI FU CTIO S

RUN/SS1, RUN/SS2 (Pins 1, 23): Combination of soft­start, run control inputs and short-circuit detection timers.
A capacitor to ground at each of these pins sets the ramp
time to full output current. Forcing either of these pins
back below 1.0V causes the IC to shut down the circuitry
required for that particular controller. Latchoff overvolt­age protection is also invoked via this pin as described in
the Applications Information section.

SENSE1+, SENSE2+ (Pins 2, 14): The (+) Input to the
Differential Current Comparators. The Ith pin voltage and
built-in offsets between the SENSE– and SENSE+ pins in
conjunction with R

SENSE1–, SENSE2– (Pins 3, 13): The (–) Input to the
Differential Current Comparators.

EAIN1, EAIN2 (Pins 4, 12): Receives the remotely sensed
feedback voltage for each controller from a resistive
divider across the output. The VID section may be used for
one resistive divider.

FREQSET (Pin 5): Frequency Control Input to the Oscilla­tor. This pin can be left open, tied to ground, tied to INTV
or driven by an external voltage source. This pin can also
be used with an external phase detector to build a true
phase-locked loop.

STBYMD (Pin 6): Control pin that determines which cir­cuitry remains active when the controllers are shut down
and/or provides a common control point to shut down
both controllers. See the Operation section for details.

FCB (Pin 7): Forced Continuous Control Input. This input
acts on both controllers and is normally used to regulate
a secondary winding using a resistive divider. An applied
input voltage below 0.8V will force continuous synchro­nous operation on both controllers. Do not leave this pin
floating.

I

TH1, ITH2

ing Regulator Compensation Point. Each associated chan­nels’ current comparator trip point increases with this
control voltage.

SGND (Pin 9): Small-Signal Ground. Common to both
controllers, this pin must be routed separately from high
current grounds to the common (–) terminals of the
C

OUT

(Pins 8, 11): Error Amplifier Output and Switch-

capacitors.

sets the current trip threshold.

SENSE

CC

3.3V

supplying 10mA DC with peak currents as high as 50mA.
ATTNOUT (Pin 15): Divided down output voltage feeding

the EAIN pin of the regulator. The VID inputs program a
resistive divider between ATTNIN and SGND. ATTNOUT is
the tap point on the divider. The voltage on ATTNOUT is

0.8V when the output is in regulation. This pin can be
bypassed to SGND with 50pF.

ATTNIN (Pin 16): Receives the remotely sensed feedback
voltage from the output.

VID0 to VID4 (Pins 17 to 21): Digital inputs for controlling
the output voltage from 0.925V to 2.0V. Table 1 specifies
the output voltage for the 32 combinations of digital
inputs. The LSB (VID0) represents 50mV increments in
the upper voltage range (2.00V to 1.30V) and 25mV
increments in the lower voltage range (1.275V to 0.925V).
Logic Low = GND, Logic High = VIDVCC or Float.

VIDVCC (Pin 22): VID Input Supply Voltage. Range from

2.7V to 5.5V. Typically this pin is tied to INTVCC.
PGND (Pin 28): Driver Power Ground. Connects to the

sources of bottom (synchronous) N-channel MOSFETs, an­ode of the Schottky rectifier and the (–) terminal(s) of CIN.

INTVCC (Pin 29): Output of the Internal 5V Linear Low
Dropout Regulator and the EXTVCC Switch. The driver and
control circuits are powered from this voltage source. Must
be decoupled to power ground with a minimum of 4.7µF
tantalum or other low ESR capacitor. The INTVCC regulator
standby function is determined by the STBYMD pin.

EXTVCC (Pin 30): External Power Input to an Internal
Switch Connected to INTVCC. This switch closes and
supplies VCC power, bypassing the internal low dropout
regulator, whenever EXTVCC is higher than 4.7V. See
EXTVCC connection in Applications Information section.
Do not exceed 7V on this pin.

BG1, BG2 (Pins 31, 27): High Current Gate Drives for
Bottom (Synchronous) N-Channel MOSFETs. Voltage
swing at these pins is from ground to INTVCC.

VIN (Pin 32): Main Supply Pin. A bypass capacitor should
be tied between this pin and the signal ground pin.

(Pin 10): Output of a linear regulator capable of

OUT

8

UUU

PI FU CTIO S

LTC1708-PG

BOOST1, BOOST2 (Pins 33, 26): Bootstrapped Supplies
to the Topside Floating Drivers. Capacitors are connected
between the boost and switch pins and Schottky diodes
are tied between the boost and INTV
at the boost pins is from INTV

CC

pins. Voltage swing

CC

to (VIN + INTVCC).

SW1, SW2 (Pins 34, 25): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to VIN.

UU

W

FU CTIO AL DIAGRA

V

V

SEC

IN

+

FREQSET

PGOOD

3.3V

EXTV

INTV

5V

STBYMD

ATTNIN

ATTNOUT

VARIABLE

FCB

V

SGND

0.17µA

OUT

IN

CC

CC

R1

1M

OSCILLATOR

4.5V

0.8V

+
–

4.8V

R2
10k

1.19V
CLK1

CLK2

–
+

–
+

–
+

–
+

–
+

+
–

V

REF

+
–

5-BIT VID DECODER

5V
LDO
REG

INTERNAL

SUPPLY

0.86V

V

0.74V

0.86V

V

0.74V

BINH

FCB

DUPLICATE FOR SECOND
CONTROLLER CHANNEL

DROP

OUT

FB1

SRQ

FB2

0.86V

4(VFB)

SLOPE

COMP

1.2µA

6V

40k

EACH VID
INPUT

DET

Q

+

0.6V
–

I

1

+

+– –+

–

45k

2.4V

4(VFB)

TG1, TG2 (Pins 35, 24): High Current Gate Drives for Top
N-Channel MOSFETs. These are the outputs of floating
drivers with a voltage swing equal to INTV

CC

– 0.5V

superimposed on the switch node voltage SW.
PGOOD (Pin 36): Open-Drain Logic Output. PGOOD is

pulled to ground when the voltage at either EAIN pin is not
within 7.5% of the setpoint.

V

CC

IN

D

B

C

B

D

SEC

C

C

R

C

C

C2

C

SS

D

R

1

SENSE

+

C

IN

C

OUT

+

+

C

SEC

SHDN

RST

BOT

3mV

TOP ON

FCB

SHDN

–
+

45k

OV

RUN
SOFT­START

I

2

EA

SWITCH

LOGIC

–

+

+

–

V

FB

0.800V

0.860V

TOP

BOT

INTV

INTV

CC

30k

30k

CC

BOOST

TG

SW

BG

PGND

SENSE

SENSE

EAIN

I

TH

RUN/SS

INTV

+

–

V

OUT

VID0

VID1 VID2 VID3 VID4

VIDV

CC

1708 F02

Figure 2

9

LTC1708-PG

U

OPERATIO

(Refer to Functional Diagram)

Main Control Loop

The LTC1708 uses a constant frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out of phase. During normal opera­tion, each top MOSFET is turned on when the clock for that
channel sets the RS latch, and turned off when the main
current comparator, I1, resets the RS latch. The peak
inductor current at which I1 resets the RS latch is con­trolled by the voltage on the I
each error amplifier EA. The EAIN pin receives the voltage
feedback signal, which is compared to the internal refer­ence voltage by the EA. When the load current increases,
it causes a slight decrease in EAIN relative to the 0.8V
reference, which in turn causes the ITH voltage to increase
until the average inductor current matches the new load
current. After the top MOSFET has turned off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by current comparator I2, or
the beginning of the next cycle.

The top MOSFET drivers are biased from floating boot­strap capacitor CB, which normally is recharged during
each off cycle through an external diode when the top
MOSFET turns off. As VIN decreases to a voltage close to
V

, the loop may enter dropout and attempt to turn on

OUT

the top MOSFET continuously. The dropout detector de­tects this and forces the top MOSFET off for about 500ns
every tenth cycle to allow CB to recharge.

The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with the
ITH voltage clamped at approximately 30% of its maximum
value. As CSS continues to charge, the I
gradually released allowing normal, full-current opera­tion. When both RUN/SS1 and RUN/SS2 are low, all
LTC1708 controller functions are shut down, and the
STBYMD pin determines if the standby 5V and 3.3V
regulators are kept alive.

Low Current Operation

The FCB pin is a multifunction pin providing two func­tions: 1) to provide regulation for a secondary winding by
temporarily forcing continuous PWM operation on

pin, which is the output of

TH

pin voltage is

TH

controller 1 and 2) select between
current operation. When the FCB pin voltage is below

0.8V, the controller forces continuous PWM current
mode operation. In this mode, the top and bottom
MOSFETs are alternately turned on to maintain the output
voltage independent of direction of inductor current.
When the FCB pin is below V

0.8V, the controller enters Burst Mode operation. Burst
Mode operation sets a minimum output current level
before inhibiting the top switch and turns off the synchro­nous MOSFET(s) when the inductor current goes nega­tive. This combination of requirements will, at low cur­rents, force the ITH pin below a voltage threshold that will
temporarily inhibit turn-on of both output MOSFETs until
the output voltage drops. There is 60mV of hysteresis in
the burst comparator B tied to the ITH pin. This hysteresis
produces output signals to the MOSFETs that turn them
on for several cycles, followed by a variable “sleep”
interval depending upon the load current. The resultant
output voltage ripple is held to a very small value by
having the hysteretic comparator after the error amplifier
gain block.

Constant Frequency Operation

When the FCB pin is tied to INTVCC, Burst Mode operation
is disabled and the forced minimum output current re­quirement is removed. This provides constant frequency,
discontinuous (preventing reverse inductor current) cur­rent operation over the widest possible output current
range. This constant frequency operation is not as efficient
as Burst Mode operation, but does provide a lower noise,
constant frequency operating mode down to approxi­mately 1% of designed maximum output current.

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be
forced back into the main power supply potentially boost­ing the input supply to dangerous voltage levels—
BEWARE!

INTVCC

two

modes of low

␣ –␣ 2V but greater than

10

OPERATIO

LTC1708-PG

U

(Refer to Functional Diagram)

Frequency Setting

The FREQSET pin provides frequency adjustment of the
internal oscillator from approximately 140kHz to 310kHz.
This input is nominally biased through an internal resistor
to the 1.19V reference, setting the oscillator frequency to
approximately 220kHz. This pin can be driven from an
external AC or DC signal source to control the instanta­neous frequency of the oscillator.

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV
When the EXTVCC pin is left open, an internal 5V low
dropout linear regulator supplies INTVCC power. If EXTV
is taken above 4.7V, the 5V regulator is turned off and an
internal switch is turned on connecting EXTVCC to INTVCC.
This allows the INTVCC power to be derived from a high
efficiency external source such as the output of the regu­lator itself or a secondary winding, as described in the
Applications Information.

Standby Mode Pin

The STBYMD pin is a three-state input that controls
common circuitry within the IC as follows: When the
STBYMD pin is held at ground, both controller RUN/SS
pins are pulled to ground providing a single control pin to
shut down both controllers. When the pin is left open, the
internal RUN/SS currents are enabled to charge the
RUN/SS capacitor(s), allowing the turn-on of either con­troller and activating necessary common internal biasing.
When the STBYMD pin is taken above 2V, both internal
linear regulators are turned on independent of the state on
the RUN/SS pins of the two switching regulator control­lers, providing an output power source for “wake-up”
circuitry. Decouple the pin with a small capacitor (0.01µF)
to ground if the pin is not connected to a DC potential.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi­tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned on
until the overvoltage condition is cleared.

CC

pin.

CC

VID Control

Logic inputs VID0 to VID4 program an internal resistive
divider. The output voltage can be programmed in 50mV
and 25mV increments from 0.925V to 2.0V (see Table 1).
These logic input pins are internally pulled up to the
VIDVCC pin using separate internal series resistor/diode
paths. The diodes provide electrical isolation when the
logic pins are externally pulled up to a higher voltage
supply than VIDVCC.

Power Good (PGOOD)

The PGOOD pin is connected to an open drain of an internal
MOSFET. The MOSFET turns on when the outputs are not
both within ±7.5% of their nominal output levels as
determined by their feedback dividers. When both outputs
are within ±7.5% of their nominal values, the MOSFET is
turned off within 10µs and the pin is pulled up by an
external source

Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff

The RUN/SS capacitors are used initially to limit the inrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used in a short-circuit time-out
circuit. If the output voltage falls to less than 70% of its
nominal output voltage, the RUN/SS capacitor begins
discharging on the assumption that the output is in an
overcurrent and/or short-circuit condition. If the condition
lasts for a long enough period as determined by the size of
the RUN/SS capacitor, both controllers will be shut down
until the RUN/SS pin’s voltages are recycled. This built-in
latchoff can be overridden by providing a >5µA pull-up at
a compliance of 5V to the RUN/SS pin(s). This current
shortens the soft-start period but also prevents net dis­charge of the RUN/SS capacitor(s) during an overcurrent
and/or short-circuit condition. Foldback current limiting is
also activated when the output voltage falls below 70% of
its nominal level whether or not the short-circuit latchoff
circuit is enabled. Even if a short is present and the short­circuit latchoff is not enabled, a safe, low output current is
provided due to internal current foldback and actual power

11

LTC1708-PG

U

OPERATIO

(Refer to Functional Diagram)

wasted is low due to the efficient nature of the current
mode switching regulator.

THEORY AND BENEFITS OF 2-PHASE OPERATION

The LTC1708 dual high efficiency DC/DC controller, like the
LTC1628, brings the considerable benefits of 2-phase
operation to portable applications for the first time. Note­book computers, PDAs, handheld terminals and automo­tive electronics will all benefit from the lower input filtering
requirement, reduced electromagnetic interference (EMI)
and increased efficiency associated with 2-phase operation.

Why the need for 2-phase operation? Up until the LTC1628,
constant-frequency dual switching regulators operated
both channels in phase (i.e., single-phase operation). This
means that both switches turned on at the same time,
causing current pulses of up to twice the amplitude of
those for one regulator to be drawn from the input capaci­tor and battery. These large amplitude current pulses
increased the total RMS current flowing from the input
capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.

With 2-phase operation, the two channels of the dual­switching regulator are operated 180 degrees out of
phase. This effectively interleaves the current pulses
drawn by the switches, greatly reducing the overlap time
where they add together.

The result is a significant reduc-

tion in total RMS input current, which in turn allows less

expensive input capacitors to be used, reduces shielding
requirements for EMI and improves real world operating
efficiency.

Figure 3 compares the input waveforms for a representa­tive single-phase dual switching regulator to the new
LTC1628 2-phase dual switching regulator. An actual
measurement of the RMS input current under these con­ditions shows that 2-phase operation dropped the input
current from 2.53A

to 1.55A

RMS

. While this is an

RMS

impressive reduction in itself, remember that the power
losses are proportional to I

2

, meaning that the actual

RMS

power wasted is reduced by a factor of 2.66. The reduced
input ripple voltage also means less power is lost in the
input power path, which could include batteries, switches,
trace/connector resistances and protection circuitry. Im­provements in both conducted and radiated EMI also
directly accrue as a result of the reduced RMS input
current and voltage.

Of course, the improvement afforded by 2-phase opera­tion is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
voltage VIN (Duty Cycle = V

OUT/VIN

). Figure 4 shows how
the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.

It can readily be seen that the advantages of 2-phase
operation are not just limited to a narrow operating range,
but in fact extend over a wide region. A good rule of thumb

12

5V SWITCH

20V/DIV

3.3V SWITCH
20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

I

I

= 2.53A

IN(MEAS)

(a)

Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation
for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The
Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows Less Expensive
Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency

DC236 F03a

RMS

IN(MEAS)

= 1.55A

(b)

DC236 F03b

RMS

OPERATIO

LTC1708-PG

U

(Refer to Functional Diagram)

for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.

A final question: If 2-phase operation offers such an
advantage over single-phase operation for dual switching
regulators, why hasn’t it been done before? The answer is
that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators
require an oscillator derived “slope compensation” signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in single­phase dual switching regulators, but required the develop­ment of a new and proprietary technique to allow 2-phase
operation. In addition, isolation between the two channels
becomes more critical with 2-phase operation because
switch transitions in one channel could potentially disrupt
the operation of the other channel.

U

WUU

APPLICATIO S I FOR ATIO

Figure 1 on the first page is a basic LTC1708 application
circuit. External component selection is driven by the load
requirement, and begins with the selection of R
Once R
MOSFETs and D1 are selected. Finally, CIN and C

is known, L can be chosen. Next, the power

SENSE

OUT

selected . The circuit shown in Figure 1 can be configured
for operation up to an input voltage of 28V (limited by the
external MOSFETs).

SENSE

are

.

The LTC1708 is proof that these hurdles have been sur­mounted. The new device offers unique advantages for the
ever-expanding number of high efficiency power supplies
required in portable electronics.

15.0
SINGLE PHASE

12.5

10.0

7.5

5.0

INPUT RMS CURRENT (A)

2.5
VO1 = 5V/15A

= 3.3V/15A

V

O2

0

0

Figure 4. RMS Input Current Comparison

DUAL CONTROLLER

2-PHASE

DUAL CONTROLLER

10 20 30 40

INPUT VOLTAGE (V)

1708 F04

When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability crite­rion for buck regulators operating at greater than 50%
duty factor. A curve is provided to estimate this reducton
in peak output current level depending upon the operating
duty factor.

Selection of Operating Frequency

R

R

Selection For Output Current

SENSE

is chosen based on the required output current.

SENSE

The LTC1708 current comparator has a maximum thresh­old of 75mV/R

and an input common mode range of

SENSE

SGND to 1.1(INTVCC). The current comparator threshold
sets the peak of the inductor current, yielding a maximum
average output current I

equal to the peak value less

MAX

half the peak-to-peak ripple current, ∆IL.
Allowing a margin for variations in the LTC1708 and

external component values yields:

mV

R

SENSE

50

=

I

MAX

The LTC1708 uses a constant frequency architecture with
the frequency determined by an internal oscillator capaci­tor. This internal capacitor is charged by a fixed current
plus an additional current that is proportional to the
voltage applied to the FREQSET pin.

A graph for the voltage applied to the FREQSET pin vs
frequency is given in Figure 5. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 310kHz.

13

LTC1708-PG

U

WUU

APPLICATIO S I FOR ATIO

2.5

2.0

1.5

1.0

FREQSET PIN VOLTAGE (V)

0.5

0

120 170 220 270 320

OPERATING FREQUENCY (kHz)

1708 F05

Figure 5. FREQSET Pin Voltage vs Frequency

Inductor Value Calculation

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.

The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL decreases with higher induc­tance or frequency and increases with higher VIN:

∆I

1

=

L OUT

fL

()()



V

1

–





Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL=0.3(I
maximum ∆IL occurs at the maximum input voltage.

V

OUT

V

IN






). Remember, the

MAX

the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.

Inductor Core Selection

Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af­ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will in­crease.

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con­centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc­tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu­facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be­cause they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
that do not increase the height significantly.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for each
controller with the LTC1708: One N-channel MOSFET for
each top (main) switch, and one N-channel MOSFET for
each bottom (synchronous) switch.

The inductor value also has secondary effects. The transi­tion to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by R

SENSE

. Lower

inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in

14

The peak-to-peak drive levels are set by the INTVCC volt­age. This voltage is typically 5V during start-up (see
EXTVCC Pin Connection). Consequently, logic-level thresh­old MOSFETs must be used in most applications. The only
exception is if low input voltage is expected (VIN < 5V);

Kool Mµ is a registered trademark of Magnetics, Inc.

LTC1708-PG

U

WUU

APPLICATIO S I FOR ATIO

then, sub-logic level threshold MOSFETs (V
should be used. Pay close attention to the BV
cation for the MOSFETs as well; most of the logic level
MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “ON”
resistance R
input voltage and maximum output current. When the
LTC1708 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:

Main SwitchDuty Cycle

Synchronous SwitchDuty Cycle

The MOSFET power dissipations at maximum output
current are given by:

P

MAIN

P

SYNC

where δ is the temperature dependency of R
is a constant inversely related to the gate drive current.

Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V the
high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher R
with lower C
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.

V

=

kV I C f

()( )( )()

=

, reverse transfer capacitance C

DS(ON)

V

OUT

=

V

IN

VV

–

IN OUT

=

V

OUT

()

V

IN

2

IN MAX RSS

–

VV

IN OUT

V

IN

actually provides higher efficiency. The

RSS

2

IR

MAX DS ON

+

1

δ

()

2

IR

()

MAX DS ON

+

1

()

()

δ

+

()

GS(TH)

specifi-

DSS

IN

DS(ON)

DS(ON)

< 3V)

RSS

and k

device

,

δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C
MOSFET characteristics. The constant k = 1.7 can be used
to estimate the contributions of the two terms in the main
switch dissipation equation.

The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead­time and requiring a reverse recovery period that could
cost as much as 3% in efficiency at high VIN. A 1A to 3A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.

CIN and C

The selection of CIN is simplified by the multiphase archi­tecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (V
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease
the input RMS ripple current from this maximum value
(see Figure 4). The out-of-phase technique typically re­duces the input capacitor’s RMS ripple current by a factor
of 30% to 70% when compared to a single phase power
supply solution.

The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selec­tion process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20µF to 40µF is usually sufficient
for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.

Selection

OUT

OUT

)(I

is usually specified in the

RSS

) product needs to be used in the

OUT

The term (1+δ) is generally given for a MOSFET in the
form of a normalized R

vs Temperature curve, but

DS(ON)

Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as

15

LTC1708-PG

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APPLICATIO S I FOR ATIO

input capacitors, but each has drawbacks: ceramic voltage
coefficients are very high and may have audible piezoelec­tric effects; tantalums need to be surge-rated; OS-CONs
suffer from higher inductance, larger case size and limited
surface-mount applicability; electrolytics’ higher ESR and
dryout possibility require several to be used. Multiphase
systems allow the lowest amount of capacitance overall.
As little as one 22µF or two to three 10µF ceramic capaci-
tors are an ideal choice in a 20W to 35W power supply due
to their extremely low ESR. Even though the capacitance
at 20V is substantially below their rating at zero-bias, very
low ESR loss makes ceramics an ideal candidate for
highest efficiency battery operated systems. Also con­sider parallel ceramic and high quality electrolytic capaci­tors as an effective means of achieving ESR and bulk
capacitance goals.

In continuous mode, the source current of the top N-chan­nel MOSFET is a square wave of duty cycle V
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current of one channel must
be used. The maximum RMS capacitor current is given by:

VVV

()

OUT IN OUT

C quiredI I

Re

IN RMS MAX

This formula has a maximum at VIN = 2V
I

= I

RMS

monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.

The benefit of the LTC1708 multiphase can be calculated
by using the equation above for the higher power control­ler and then calculating the loss that would have resulted
if both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are
operating due to the interleaving of current pulses through

/2. This simple worst case condition is com-

OUT

≈

[]

V

OUT/VIN

−

IN

OUT

. To

/

12

, where

the input capacitor’s ESR. This is why the input capacitor’s
requirement calculated above for the worst-case control­ler is adequate for the dual controller design. Remember
that input protection fuse resistance, battery resistance
and PC board trace resistance losses are also reduced due
to the reduced peak currents in a multiphase system.

The
overall benefit of a multiphase design will only be fully
realized when the source impedance of the power supply/
battery is included in the efficiency testing.

the two top MOSFETS should be placed within 1cm of each
other and share a common CIN(s). Separating the drains
and CIN may produce undesirable voltage and current
resonances at VIN.

The selection of C
series resistance (ESR). Typically once the ESR require­ment is satisfied the capacitance is adequate for filtering.
The output ripple (∆V

∆∆V I ESR

Where f = operating frequency, C
and ∆IL= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3I
ripple will typically be less than 50mV at max VIN assum­ing:

C
and C

The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran­tees that the output capacitance does not significantly
discharge during the operating frequency period due to
ripple current. The choice of using smaller output capaci­tance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage at or below
50mV. The ITH pin OPTI-LOOP compensation compo­nents can be optimized to provide stable, high perfor­mance transient response regardless of the output
capacitors selected.

≈+

OUT L

Recommended ESR < 2 R

OUT

> 1/(8fR

OUT

is driven by the required effective

OUT

) is determined by:

OUT






8

SENSE

fC

)

1

OUT






= output capacitance,

OUT

SENSE

The drains of

OUT(MAX)

the output

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APPLICATIO S I FOR ATIO

Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance through­hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.

In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Spe­cial polymer surface mount capacitors offer very low ESR
but have lower storage capacity per unit volume than other
capacitor types. These capacitors offer a very cost-effec­tive output capacitor solution and are an ideal choice when
combined with a controller having high loop bandwidth.
Tantalum capacitors offer the highest capacitance density
and are often used as output capacitors for switching
regulators having controlled soft-start. Several excellent
surge-tested choices are the AVX TPS, AVX TPSV or the
KEMET T510 series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. Aluminum
electrolytic capacitors can be used in cost-driven applica­tions providing that consideration is given to ripple current
ratings, temperature and long term reliability. A typical
application will require several to many aluminum electro­lytic capacitors in parallel. A combination of the above
mentioned capacitors will often result in maximizing per­formance and minimizing overall cost. Other capacitor
types include Nichicon PL series, NEC Neocap, Pansonic
SP and Sprague 595D series. Consult manufacturers for
other specific recommendations.

recommended. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between channels.

Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi­mum junction temperature rating for the LTC1708 to be
exceeded. The system supply current is normally domi­nated by the gate charge current. Additional external
loading of the INTVCC and 3.3V linear regulators also
needs to be taken into account for the power dissipation
calculations. The total INTVCC current can be supplied by
either the 5V internal linear regulator or by the EXTV
input pin. When the voltage applied to the EXTVCC pin is
less than 4.7V, all of the INTVCC current is supplied by the
internal 5V linear regulator. Power dissipation for the IC in
this case is highest: (VIN)(I
is lowered. The gate charge current is dependent on
operating frequency as discussed in the Efficiency Consid­erations section. The junction temperature can be esti­mated by using the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC1708 V
current is limited to less than 24mA from a 24V supply
when not using the EXTVCC pin as follows:

TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C

Use of the EXTVCC input pin reduces the junction tempera­ture to:

TJ = 70°C + (24mA)(5V)(95°C/W) = 81°C

Dissipation should be calculated to also include any added
current drawn from the internal 3.3V linear regulator. To
prevent maximum junction temperature from being ex­ceeded, the input supply current must be checked operat­ing in continuous mode at maximum VIN.

), and overall efficiency

INTVCC

CC

IN

INTVCC Regulator

An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. INTVCC powers
the drivers and internal circuitry within the LTC1708. The
INTVCC pin regulator can supply a peak current of 50mA
and must be bypassed to ground with a minimum of

4.7µF tantalum, 10µF special polymer, or low ESR type
electrolytic capacitor. A 1µF ceramic capacitor placed
directly adjacent to the INTVCC and PGND IC pins is highly

EXTVCC Connection

The LTC1708 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
When the voltage applied to EXTV
internal regulator is turned off and the switch closes,
connecting the EXTV
supplying internal power. The switch remains closed as
long as the voltage applied to EXTVCC remains above 4.5V.
This allows the MOSFET driver and control power to be

pin to the INTV

CC

rises above 4.7V, the

CC

pin thereby

CC

17

LTC1708-PG

EXTV

CC

V

IN

TG1

SW

BG1

PGND

LTC1708-PG

R

SENSE

V

OUT

VN2222LL

+

C

OUT

1708 F06b

N-CH

N-CH

+

C

IN

+

1µF

V

IN

L1

BAT85 BAT85

BAT85

0.22µF

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APPLICATIO S I FOR ATIO

derived from the output during normal operation (4.7V <
V

< 7V) and from the internal regulator when the output

OUT

is out of regulation (start-up, short-circuit). If more cur­rent is required through the EXTVCC switch than is speci­fied, an external Schottky diode can be added between the
EXTVCC and INTVCC pins. Do not apply greater than 7V to
the EXTVCC pin and ensure that EXTV

Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
supply means connecting the EXTVCC pin directly to V
However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTVCC power
from the output.

The following list summarizes the four possible connec­tions for EXTV

CC:

1. EXTVCC Left Open (or Grounded). This will cause INTV
to be powered from the internal 5V regulator resulting in
an efficiency penalty of up to 10% at high input voltages.

2. EXTVCC Connected directly to V
connection for a 5V regulator and provides the highest
efficiency.

3. EXTVCC Connected to an External supply. If an external
supply is available in the 5V to 7V range, it may be used to
power EXTVCC providing it is compatible with the MOSFET
gate drive requirements.

<␣ VIN.

CC␣

. This is the normal

OUT

OUT

CC

.

4. EXTVCC Connected to an Output-Derived Boost Net­work. For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with either the inductive boost
winding as shown in Figure 6a or the capacitive charge
pump shown in Figure 6b. The charge pump has the
advantage of simple magnetics.

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitors CB connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor CB in the functional diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: V
VIN + V

. The value of the boost capacitor CB needs

INTVCC

BOOST

=

to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the exter­nal Schottky diode must be greater than V

IN(MAX)

. When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.

V

N-CH

N-CH

IN

+

C

IN

T1

1:N

R

OPTIONAL EXTV
CONNECTION
5V < V

LTC1708-PG

EXTV

R6

FCB

R5

SGND

Figure 6a. Secondary Output Loop & EXTVCC Connection

18

CC

< 7V

SEC

V

IN

TG1

CC

SW

BG1

PGND

V

SEC

SENSE

+

1µF

V

OUT

+

C

OUT

1708 F06a

Figure 6b. Capacitive Charge Pump for EXTV

CC

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APPLICATIO S I FOR ATIO

Output Voltage Programming

The LTC1708 output voltages are set by the VID logic
inputs for the first controller and by an external feedback
resistive divider carefully placed across the output capaci­tor for the second controller. The resultant feedback signal
is compared with the internal precision 0.800V voltage
reference by the error amplifier. The output voltage is
given by the equation:

VV

=+

08 1

OUT

.





The output voltage of the first controller is digitally set to
levels between 0.925V and 2.00V using the voltage iden­tification (VID) inputs VID0 to VID4. The internal 5-bit DAC
configured as a precision resistive voltage divider sets the
output voltage in 50mV or 25mV increments according to
Table 1.

The VID codes (00000-11110) are engineered to be com­patible with Intel Mobile Pentium® II and Pentium III
processor specifications for output voltages from 0.925V
to 2.00V.

The LSB (VID0) represents 50mV increments in the upper
voltage range (1.30V to 2.00V) and 25mV increments in
the lower voltage range (0.925V to 1.275V). The MSB is
VID4. When all bits are low, or grounded, the output
voltage is 2.00V.

Between the ATTNOUT pin and ground is a variable resis­tor, R1, whose value is controlled by the five input pins (VID0
to VID4). Another resistor, R2, between the ATTNIN and
the ATTNOUT pins completes the resistive divider. The
output voltage is thus set by the ratio of (R1 + R2) to R1.

The LTC1708 has remote sense capability. The top of the
internal resistive divider is connected to ATTNIN, and it is
referenced to the SGND pin. This allows a Kelvin connec­tion for remotely sensing the output voltage directly across
the load, eliminating any PC board trace resistance errors.

Each VID digital input is pulled up by a 40k resistor in
series with a diode from VIDVCC. Therefore, it must be
grounded to get a digital low input, and can be either
floated or connected to VIDVCC to get a digital high input.
The series diode is used to prevent the digital inputs from

Pentium is a registered trademark of Intel Corporation.





R

2



R

1



being damaged or clamped if they are driven higher than
VIDVCC. The digital inputs accept CMOS voltage levels.

VIDVCC is the supply voltage for the VID section. It is
normally connected to INTVCC but can be driven from
other sources such as a 3.3V supply. If it is driven from
another source, that source MUST be in the range of 2.7V
to 5.5V and MUST be alive prior to enabling the LTC1708.

Table 1. VID Output Voltage Programming

VID4 VID3 VID2 VID1 VID0 V

0 0 0 0 0 2.000V
0 0 0 0 1 1.950V
0 0 0 1 0 1.900V
0 0 0 1 1 1.850V
0 0 1 0 0 1.800V
0 0 1 0 1 1.750V
0 0 1 1 0 1.700V
0 0 1 1 1 1.650V
0 1 0 0 0 1.600V
0 1 0 0 1 1.550V
0 1 0 1 0 1.500V
0 1 0 1 1 1.450V
0 1 1 0 0 1.400V
0 1 1 0 1 1.350V
0 1 1 1 0 1.300V
01111 *
1 0 0 0 0 1.275V
1 0 0 0 1 1.250V
1 0 0 1 0 1.225V
1 0 0 1 1 1.200V
1 0 1 0 0 1.175V
1 0 1 0 1 1.150V
1 0 1 1 0 1.125V
1 0 1 1 1 1.100V
1 1 0 0 0 1.075V
1 1 0 0 1 1.050V
1 1 0 1 0 1.025V
1 1 0 1 1 1.000V
1 1 1 0 0 0.975V
1 1 1 0 1 0.950V
1 1 1 1 0 0.925V
11111 **

Note: *, ** represent codes without a defined output voltage as specified in
Intel specifications. The LTC1708 interprets these codes as valid inputs and
produces output voltages as follows: [01111] = 1.250V, [11111] = 0.900V.

OUT

(V)

19

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SENSE+/SENSE– Pins

The common mode input range of the current comparator
sense pins is from 0V to (1.1)INTVCC. Continuous linear
operation is guaranteed throughout this range allowing
output voltage setting from 0.8V to 7.7V, depending upon
the voltage applied to EXTVCC. A differential NPN input
stage is biased with internal resistors from an internal

2.4V source as shown in the Functional Diagram. This
requires that current either be sourced or sunk from the
SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
pins to the main output. The output can be easily preloaded
by the V
comparator’s negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:

I

SENSE

Since V
can choose R1 in Figure 8 to have a maximum value to
absorb this current.

Rk

124

for V

Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32K. Note that for an output voltage above

2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the V
feedback current.

resistive divider to compensate for the current

OUT

+

+ I

is servoed to the 0.8V reference voltage, we

EAIN

=

MAX

()

< 2.4V

OUT

SENSE

–

= (2.4V – V



08

.



VV

24

.–



V

OUT

OUT






)/24k

EAIN

R

SENSE

to 75mV/R

. The output current limit ramps

SENSE

up slowly, taking an additional 1.25s/µF to reach full
current. The output current thus ramps up slowly, reduc­ing the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:

15

.

t

DELAY SS SS

t

IRAMP SS SS

V

=

12

315

=

CsFC

.

A

µ

.

VV

−

12

.

A

µ

125

./

=µ

()

125

CsFC

./

=µ

()

By pulling both RUN/SS pins below 1V and/or pulling the
STBYMD pin below 0.2V, the LTC1708 is put into low
current shutdown (IQ = 20µA). The RUN/SS pins can be
driven directly from logic as shown in Figure 7. Diode D1
in Figure 7 reduces the start delay but allows CSS to ramp
up slowly providing the soft-start function. Each RUN/SS
pin has an internal 6V zener clamp (See Functional
Diagram).

V

3.3V OR 5V RUN/SS

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

IN

RSS*

D1

C

SS

(a) (b)

INTV

CC

RSS*

RUN/SS

C

1708 F07

SS

Soft-Start/Run Function

The RUN/SS1 and RUN/SS2 pins are multipurpose pins
that provide a soft-start function and a means to shut
down the LTC1708. Soft-start reduces the input power
source’s surge currents by gradually increasing the
controller’s current limit (proportional to V

). This pin

ITH

can also be used for power supply sequencing.
An internal 1.2µA current source charges up the C

SS

capacitor. When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 25mV/

20

Figure 7. RUN/SS Pin Interfacing

Fault Conditions: Overcurrent Latchoff

The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected.
The RUN/SS capacitor, CSS, is used initially to turn on and
limit the inrush current. After the controller has been
started and been given adequate time to charge up the
output capacitor and provide full load current, the RUN/SS
capacitor is used for a short-circuit timer. If the regulator’s
output voltage falls to less than 70% of its nominal value
after CSS reaches 4.1V, CSS begins discharging on the
assumption that the output is in an overcurrent condition.

LTC1708-PG

I

mV

R

I

SC

SENSE

LSC

=+

25 1

2

∆

()

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APPLICATIO S I FOR ATIO

If the condition lasts for a long enough period as deter­mined by the size of the CSS and the specified discharge
current, the controller will be shut down until the RUN/SS
pin voltage is recycled. If the overload occurs during start­up, the time can be approximated by:

t

≈ [CSS(4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA)

LO1

= 2.7 • 106 (CSS)

If the overload occurs after start-up the voltage on CSS will
begin discharging from the zener clamp voltage:

t

≈ [CSS (6 – 3.5)]/(1.2µA) = 2.1 • 106 (CSS)

LO2

This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin as shown
in Figure 7. This resistance shortens the soft-start period
and prevents the discharge of the RUN/SS capacitor
during an over current condition. Tying this pull-up resis­tor to VIN as in Figure 7a, defeats overcurrent latchoff.
Diode-connecting this pull-up resistor to INTVCC , as in
Figure 7b, eliminates any extra supply current during
controller shutdown while eliminating the INTV
from preventing controller start-up.

loading

CC

of 75mV/R
generally occurs with the largest VIN at the highest ambi­ent temperature, conditions that cause the highest power
dissipation in the top MOSFET.

The LTC1708 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is overridden. If the
output falls below 70% of its nominal output level, then the
maximum sense voltage is progressively lowered from
75mV to 25mV. Under short-circuit conditions with very
low duty cycles, the LTC1708 will begin cycle skipping in
order to limit the short-circuit current. In this situation the
bottom MOSFET will be dissipating most of the power but
less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time t
the LTC1708 (less than 200ns), the input voltage and
inductor value:

∆I

The resulting short-circuit current is:

L(SC)

= t

. The maximum value of current limit

SENSE

ON(MIN)

(VIN/L)

ON(MIN)

of

Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.

The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci­tance is given by:

CSS > (C

The minimum recommended soft-start capacitor of
C

= 0.1µF will be sufficient for most applications.

SS

Fault Conditions: Current Limit and Current Foldback

The LTC1708 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET current

OUT

)(V

) (10–4) (R

OUT

SENSE

)

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.

A comparator monitors the output for overvoltage condi­tions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottom MOSFET is turned on until the overvolt­age condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if V

returns to a safe level,

OUT

21

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APPLICATIO S I FOR ATIO

normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regu­late properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.

The Standby Mode (STBYMD) Pin Function

The Standby Mode (STBYMD) pin provides several choices
for start-up and standby operational modes. If the pin is
pulled to ground, the RUN/SS pins for both controllers are
internally pulled to ground, preventing start-up and thereby
providing a single control pin for turning off both control­lers at once. If the pin is left open or decoupled with a
capacitor to ground, the RUN/SS pins are each internally
provided with a starting current enabling external control
for turning on each controller independently. If the pin is
provided with a current of >3µA at a voltage greater than
2V, both internal linear regulators (INTVCC and 3.3V) will
be on even when both controllers are shut down. In this
mode, the onboard 3.3V and 5V linear regulators can
provide power to keep-alive functions such as a keyboard
controller. This pin can also be used as a latching “on” and/
or latching “off” power switch if so designed.

Frequency of Operation

The LTC1708 has an internal voltage controlled oscillator.
The frequency of this oscillator can be varied over a 2 to 1
range. The pin is internally self-biased at 1.19V, resulting
in a free-running frequency of approximately 220kHz. The
FREQSET pin can be grounded to lower this frequency to
approximately 140kHz or tied to the INTVCC pin to yield
approximately 310kHz. The FREQSET pin may be driven
with a voltage from 0 to INTVCC to fix or modulate the
oscillator frequency as shown in Figure 5.

V

OUT

t

ON MIN

If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1708 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.

The minimum on-time for the LTC1708 is generally less
than 200ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
300ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.

FCB Pin Operation

The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced
when the FCB pin drops below 0.8V. During continuous
mode, current flows continuously in the transformer pri­mary. The secondary winding(s) draw current only when
the bottom, synchronous switch is on. When primary load
currents are low and/or the VIN/V
synchronous switch may not be on for a sufficient amount
of time to transfer power from the output capacitor to the
secondary load. Forced continuous operation will support
secondary windings providing there is sufficient synchro­nous switch duty factor. Thus, the FCB input pin removes
the requirement that power must be drawn from the
inductor primary in order to extract power from the
auxiliary windings. With the loop in continuous mode, the
auxiliary outputs may nominally be loaded without regard
to the primary output load.

<

()

()

Vf

IN

ratio is low, the

OUT

Minimum On-Time Considerations

Minimum on-time t
that the LTC1708 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that

ON(MIN)

is the smallest time duration

22

The secondary output voltage V
shown in Figure 6a by the turns ratio N of the transformer:

V

≅ (N + 1) V

SEC

However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V
V

SEC

will droop. An external resistive divider from

SEC

to the FCB pin sets a minimum voltage V

OUT

is normally set as

SEC

SEC(MIN)

:

LTC1708-PG

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APPLICATIO S I FOR ATIO

VV

SEC MIN()

If V

drops below this level, the FCB voltage forces

SEC

.≈+

08 1





temporary continuous switching operation until V
again above its minimum.

In order to prevent erratic operation if no external connec­tions are made to the FCB pin, the FCB pin has a 0.18µA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.

The following table summarizes the possible states avail­able on the FCB pin:



Table 1

FCB Pin Condition

0V to 0.75V Forced Continuous (Current Reversal

0.85V < V

Feedback Resistors Regulating a Secondary Winding
>4.8V Burst Mode Operation Disabled

< 4.3V Minimum Peak Current Induces

FCB

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak
output voltage excursion under worst-case transient load­ing conditions. The open-loop DC gain of the control loop
is reduced depending upon the maximum load step speci­fications. Voltage positioning can easily be added to the
LTC1708 by loading the ITH pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage of the error amplifier, or 1.2V
(see Figure 8).

The resistive load reduces the DC loop gain while main­taining the linear control range of the error amplifier. The
worst-case peak-to-peak output voltage deviation due to
transient loading can theoretically be reduced to half or
alternatively the amount of output capacitance can be
reduced for a particular application. A complete explana­tion is included in Design Solutions 10 or the LTC1736
data sheet. (See www.linear-tech.com)



R

6



R

5



Allowed—Burst Inhibited)

Burst Mode Operation
No Current Reversal Allowed

Constant Frequency Mode Enabled
No Current Reversal Allowed

No Minimum Peak Current

SEC

is

EAIN

1708 F08

V

OUT

R2

R1

INTV

CC

R

T2

I

TH

R

R

C

T1

C

Figure 8. Active Voltage Positioning Applied to the LTC1708

LTC1708-PG

C

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1708 circuits: 1) LTC1708 VIN current (in­cluding loading on the 3.3V internal regulator), 2) INTV

CC

regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.

1. The VIN current has two components: the first is the DC
supply current given in the Electrical Characteristics table,
which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output. VIN current typically results in a small (<0.1%) loss.

2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTVCC to
ground. The resulting dQ/dt is a current out of INTVCC that
is typically much larger than the control circuit current. In
continuous mode, I

GATECHG

=f(QT+QB), where QT and Q

B

are the gate charges of the topside and bottom side
MOSFETs.

Supplying INTV
from an output-derived source will scale the V

power through the EXTVCC switch input

CC

current

IN

23

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APPLICATIO S I FOR ATIO

required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTVCC current results in approxi­mately 2.5mA of VIN current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from VIN) to only a few percent.

3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi­mately the same R

, then the resistance of one

DS(ON)

MOSFET can simply be summed with the resistances of
L, R
each R
R

ESR

and ESR to obtain I2R losses. For example, if

SENSE

= 10mΩ, RL = 5mΩ, R

DS(ON)

SENSE

= 3mΩ and

= 10mΩ (sum of both input and output capacitance

losses), then the total resistance is 28mΩ. This results in
losses ranging from 3% to 8% as the output current
increases from 5A to 15A for a 5V output, or an 8% to 20%
loss for a 1.6V output. Efficiency varies as the inverse
square of V

for the same external components and

OUT

output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!

4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:

Transition Loss = (1.7) V

2

I

IN

O(MAX) CRSS

f

Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switch­ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having a

SENSE

,

maximum of 20mΩ to 50mΩ of ESR. The LTC1708 2­phase architecture typically halves this input capacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead-time
and inductor core losses generally account for less than
2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C

generating the feedback error signal that

OUT

(ESR), where ESR is the effective

LOAD

OUT

. ∆I

also begins to charge or

LOAD

shifts by an

OUT

forces the regulator to adapt to the current change and
return V
time V

to its steady-state value. During this recovery

OUT

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem. OPTI­LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values.

The availability of the ITH pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response

. Assuming a pre­dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I

TH

external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.

The I

series RC-CC filter sets the dominant pole-zero

TH

loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 100%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and ITH pin waveforms that will

24

LTC1708-PG

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APPLICATIO S I FOR ATIO

give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step resulting
from the step change in output current may not be within
the bandwidth of the feedback loop, so this signal cannot
be used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
and is the filtered and compensated control loop re­sponse. The gain of the loop will be increased by increas­ing RC and the bandwidth of the loop will be increased by
decreasing CC. If RC is increased by the same factor that
CC is decreased, the zero frequency will be kept the same,
thereby keeping the phase the same in the most critical
frequency range of the feedback loop. The output voltage
settling behavior is related to the stability of the closed­loop system and will demonstrate the actual overall supply
performance.

A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C

LOAD

should be controlled so that the load rise time is limited to
approximately 25 • C
require a 250µs rise time, limiting the charging current to
about 200mA.

, causing a rapid drop in V

OUT

to C

is greater than1:50, the switch rise time

OUT

. Thus a 10µF capacitor would

LOAD

. No regulator can

OUT

Automotive Considerations: Plugging into the
Cigarette Lighter

As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during opera­tion. But before you connect, be advised: you are plug­ging into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery and
double-battery.

Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.

The network shown in Figure 9 is the most straight forward
approach to protect a DC/DC converter from the ravages
of an automotive power line. The series diode prevents
current from flowing during reverse-battery, while the
transient suppressor clamps the input voltage during
load-dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the LTC1708 has a maximum input voltage of
36V, most applications will be limited to 30V by the
MOSFET BVDSS.

RATING

A I

PK

VOLTAGE

OR

STRUMENT

Figure 9. Automotive Application Protection

V

IN

LTC1708-PG

25

LTC1708-PG

P

V

V

CC

VApFkHz

W

MAIN

=

()

+°°

[]

Ω

()

+

()()( )( )

=

16

22

14 1 0 005 50 25

0 011 1 7 22 14 240 300

10

2

2

.

(. )( – )

..

.

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APPLICATIO S I FOR ATIO

Design Example

As a design example for one channel, assume VIN =
12V(nominal), VIN = 22V(max), V
and f = 300kHz, R

R

Tie the FREQSET pin to the INTVCC pin for 300kHz opera­tion, or use a resistive divider from INTVCC according to
Figure 5 to reduce the operating frequency.

Assume a 1µH inductor and check the actual value of the
ripple current. The following equation is used:

∆I

The highest value of the ripple current occurs at the
maximum input voltage:

= 50mV/14A ≈ 0.0035Ω → 0.003Ω

SENSE



V

OUT OUT

=

L

()()

fL





can immediately be calculated:

SENSE



V

–1



V



IN

OUT

= 1.6V, I

MAX

= 14A,

continuous mode is not selected and the programmed
voltage is less than 1.4V with no external load, it is
necessary to preload the output in order to prevent the
current comparator input bias current from causing the
output voltage to rise above the designed level. A 16k
preload resistor will prevent this from happening for all
programmed output voltages down to the minimum 0.925V
level.

The power dissipation on the topside MOSFET can be
easily estimated. Choosing a International Rectifier IRF7811
results in; R
input voltage with T(estimated) = 50°C:

DS(ON)

= 0.011Ω, C

= 240pF. At maximum

RSS

∆I

=

L

The ripple current is 35% of maximum output current.
Increasing the ripple current will also help ensure that the

minimum on-time of 200ns is not violated. The minimum
on-time occurs at maximum VIN:

t

ON MIN

()

Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins current.

Rk

124

MAX

()

Choosing 1% resistors; R1 = R2 = 20k yields an output
voltage of 1.600V. If the VID section of the LTC1708-PG is
used, R1 will range from a value of 6.6k to 64k. If the forced

26

.

kHz H

300 1

()

V

OUT

== =

VfVV kHz

IN MAX

()



=







=

K

24





1

–



µ



22 300

.

V

08

.–

VV

24

.

V

08

.–.

VV

24 16



V

16



V

16

.

=

495

.



V

22



.

16
()






OUT



=

k

24





A

242

ns

A short-circuit to ground will result in a folded back current
of:

mV ns V

=

SC

SYNC

ORIPPLE

25

0 003

.

22 1 6

VV

=

.

=

123

= R

I

with a typical value of R

0.1. The resulting power dissipated in the bottom MOSFET
is:

P

which is similar to full-load conditions.
CIN is chosen for an RMS current rating of at least 5A at

temperature assuming only this channel is on. C
chosen with an ESR of 0.01Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:

V

12200 22

+

Ω

–.

22

V

W

ESR(∆IL)






µ

1

DS(ON)

...

12 7 1 1 0 0075

()()

= 0.01Ω(4.95A) = 50mV



()

H

A

=





and δ = (0.005/°C)(20) =

2

A

12 7

.

()

Ω

OUT

P–P

is

LTC1708-PG

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PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1708. These items are also illustrated graphically in
the layout diagram of Figure 10. The Figure 11 illustrates
the current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:

1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection

INTV

INTV

1

RUN/SS1

2

3

4

5

CC

6

7

CC

8

9

10

11

12

13

14

15

16

17

18

SENSE1

SENSE1

EAIN1

FREQSET

STBYMD

FCB

I

TH1

SGND

LTC1708-PG

3.3V

OUT

I

TH2

EAIN2

SENSE2

SENSE2

ATTNOUT

ATTNIN

VID0

VID1

+

–

–

+

RUN/SS2

PGOOD

TG1

SW1

BOOST1

V

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

VIDV

VID4

VID3

VID2

36

35

34

33

32

IN

31

30

CC

29

CC

28

27

26

25

24

23

22

CC

21

20

VID CONTROL

19

INPUTS

at CIN? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.

2. Are the signal and power grounds kept separate? The
combined LTC1708 signal ground pin and the ground
return of C

INTVCC

must return to the combined C

OUT

(–)
terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to the
(–) terminals of the input capacitor by placing the

POWER GOOD
INTV

CC

V

OUT1

+ +

+

V

IN

V

OUT2

Figure 10. LTC1708 Recommended Printed Circuit Layout Diagram

1708 F10

27

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APPLICATIO S I FOR ATIO

capacitors next to each other and away from the Schottky
loop described above.

3. Do the LTC1708 feedback resistive dividers connect to
the (+) terminals of C
connected between the (+) terminal of C
ground. The R2 (Figure 8) connection should not be along
the high current input feeds from the input capacitor(s).

4. Are the SENSE– and SENSE+ leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections.

? The resistive divider must be

OUT

and signal

OUT

5. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve noise
performance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC1708 and occupy minimum PC trace area.

SW1

D1

V

IN

R

IN

+

C

IN

BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.

SW2

D2

L1

L2

R

SENSE1

R

SENSE2

C

C

OUT1

OUT2

V

V

OUT1

+

OUT2

+

1628 F11

R

L1

R

L2

28

Figure 11. Branch Current Waveforms

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APPLICATIO S I FOR ATIO

7. Use a modified “star ground” technique: a low imped­ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the appli­cation. The frequency of operation should be maintained
over the input voltage range down to dropout and until the
output load drops below the low current operation thresh­old—typically 10% to 20% of the maximum designed
current level in Burst Mode operation.

The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple­mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Over­compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for their individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current com­parator trip point when the other channel is turning on its
top MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.

CC

Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5µA can be provided to the RUN/
SS pin(s) by resistors from VIN to prevent the short-circuit
latchoff from occurring.

Reduce VIN from its nominal level to verify operation of the
regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If prob­lems coincide with high input voltages and low output
currents, look for capacitive coupling between the BOOST,
SW, TG, and possibly BG connections and the sensitive
voltage and current pins. The capacitor placed across the
current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due to
high frequency capacitive coupling. If problems are en­countered with high current output loading at lower input
voltages, look for inductive coupling between CIN, Schottky
and the top MOSFET components to the sensitive current
and voltage sensing traces. In addition, investigate com­mon ground path voltage pickup between these compo­nents and the SGND pin of the IC.

An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still be
maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.

29

LTC1708-PG

TYPICAL APPLICATIO

20k
1%

15k

33k

68k

INTV

0.1µF

180pF

4.3k

0.01µF

100pF

160k

CC

INTV

CC

330pF

10k

17.5k
1%

33pF

V

IN

1000pF

1000pF

1000pF

1M

1000pF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

RUN/SS1

SENSE1

SENSE1

EAIN1

FREQSET

STBYMD

FCB

I

TH1

SGND

3.3V

I

TH2

EAIN2

SENSE2

SENSE2

ATTNOUT

ATTNIN

VID0

VID1

U

+

–

LTC1708-PG

OUT

–

+

PGOOD

TG1

SW1

BOOST1

V

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

VIDV

VID4

VID3

VID2

CC

CC

CC

IN

36

35

34

33

32

31

30

5V
(OPTIONAL)

29

28

27

26

25

24

23

22

21

20

19

1µF
10V

INTV

CC

VID CONTROL
INPUTS

100k

0.1µF

CMDSH-3TR

+

4.7µF

CMDSH-3TR

0.47µF

0.1µF

POWER GOOD
INTV

CC

M1a M1b

10Ω

10µF

35V

×3

M2

L1

2.2µH

M3

L2

1µH

TIGHTLY COUPLE
THESE CURRENT
SENSING FEEDBACK
PATHS

0.015Ω

D1
MBRM140T3

D2
MBRM340T3

0.003Ω

TIGHTLY COUPLE
THESE CURRENT
SENSING FEEDBACK
PATHS

+

+

+

180µF 4V
PANASONIC SP

+ +

270µF 2V
PANASONIC SP
×4

10µF

6.3V
CER

V

OUT1

1.5V/2.5A
PEAK

V

IN

7.5V TO 24V

V

OUT2

0.925V TO 2V
14A

0.1µF

: 12V TO 22V

V

IN

: 1.5V/2.5A

V

OUT1

: 0.925V TO 2V/14A

V

OUT2

SWITCHING FREQUENCY: 250kHz

Figure 12. LTC1708 High Efficiency, Constant Frequency CPU Core/IO Power Supply with Active Voltage Positioning

30

M1a, M1b: FDS6982
M2: IRF7811
M3: IRF7809

L1: 2.2µH
L2: 1µH

1708 F12

NOTE: ELECTRICAL PATHS DRAWN WITH THICK LINES
SHOULD BE KEPT AS SHORT AND WIDE AS POSSIBLE.
THESE PATHS WILL RADIATE EMI AT THE SWITCHING
FREQUENCY. KEEP THE PATHS’ ENCLOSED AREA SMALL.

PACKAGE DESCRIPTIO

5.20 – 5.38**
(0.205 – 0.212)

LTC1708-PG

U

Dimensions in inches (millimeters) unless otherwise noted.

G Package

36-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

12.67 – 12.93*
(0.499 – 0.509)

2526 22 21 20 19232427282930313233343536

7.65 – 7.90

(0.301 – 0.311)

12345678 9 10 11 12 14 15 16 17 1813

1.73 – 1.99

(0.068 – 0.078)

° – 8°

0

0.13 – 0.22

(0.005 – 0.009)

NOTE: DIMENSIONS ARE IN MILLIMETERS

*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

0.55 – 0.95

(0.022 – 0.037)

0.65

(0.0256)

BSC

0.25 – 0.38

(0.010 – 0.015)

0.05 – 0.21

(0.002 – 0.008)

G36 SSOP 1098

31

LTC1708-PG

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32

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

1708i LT/TP 0200 4k • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2000