Datasheet LTC1668 Datasheet (Linear Technology)

Final Electrical Specifications

FREQUENCY (1.25MHz/DIV)

0.05

SIGNAL AMPLITUDE (dBm)

–45

–25

–5

1668 G01

–65

–85

–55

–35

–15

–75

–95

–105

6.3

12.55

f

CLOCK

= 25Msps

f

OUT

= 1.007MHz
AMPLITUDE = 0dBFS
= –8.5dBm
SFDR = 86dBc

FEATURES

LTC1668

16-Bit, 50Msps DAC

February 2000

U

DESCRIPTIO

■

50Msps Update Rate

■

16-Bit Resolution

■

High Spectral Purity: 87dB SFDR at 1MHz f

■

Differential Current Outputs

■

30ns Settling Time

■

5pV-s Glitch Impulse

■

Low Power: 180mW from ±5V Supplies

■

TTL/CMOS (3.3V or 5V) Inputs

■

Small Package: 28-Pin SSOP

U

APPLICATIO S

■

Cellular Base Stations

■

Multicarrier Base Stations

■

Wireless Communication

■

Direct Digital Synthesis (DDS)

■

xDSL Modems

■

Arbitrary Waveform Generation

■

Automated Test Equipment

■

Instrumentation

OUT

The LTC®1668 is a 16-bit, 50Msps differential current
output DAC implemented on a high performance BiCMOS
process with laser trimmed, thin-film resistors. The com­bination of a novel current-steering architecture and a
high performance process produces a DAC with excep­tional AC and DC performance. This is the first 16-bit DAC
in the marketplace to exhibit an SFDR (spurious free
dynamic range) of 87dB for an output signal frequency of
1MHz.

Operating from ±5V supplies, the LTC1668 can be con­figured to provide full-scale output currents up to 10mA.
The differential current outputs of the DAC allow single­ended or true differential operation. The –1V to 1V output
compliance of the LTC1668 allows the outputs to be con­nected directly to external resistors to produce a differ­ential output voltage without degrading the converter’s
linearity. Alternatively, the outputs can be connected to the
summing junction of a high speed operational amplifier,
or to a transformer.

The LTC1668 is available in a 28-pin SSOP and is fully
specified over the industrial temperature range.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

REFOUT

R

0.1µF

0.1µF

SET

C1

C2

0.1µF

2k

I

REFIN

COMP1

COMP2

V

SS

–5V

U

16-Bit, 50Msps DAC

5V

0.1µF

V

2.5V

REFERENCE

+

–

AGND DGND CLK DB15 DB0

0.1µF

DD

HIGH SPEED

CLOCK

INPUT

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

16-BIT

DAC

16-BIT DATA

INPUT

LTC1668

I

OUT A

I

OUT B

LADCOM

1668 TA01

52.3Ω

52.3Ω V

+

OUT

–

1V

P-P

DIFFERENTIAL

Single Tone SFDR

1

LTC1668

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Supply Voltage (VDD)................................................ 6V

Negative Supply Voltage (VSS) ............................... – 6V

Total Supply Voltage (VDD to VSS) .......................... 12V

Digital Input Voltage ....................–0.3V to (VDD + 0.3V)

Analog Output Voltage

(I

and I

OUT A

Power Dissipation............................................. 500mW

Operating Temperature Range

LTC1668C .............................................. 0°C to 70°C

LTC1668I........................................... –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

) ........ (VSS – 0.3V) to (VDD + 0.3V)

OUT B

UU

W

PACKAGE/ORDER I FOR ATIO

TOP VIEW

DB13
DB12
DB11
DB10

DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1

DB0 (LSB)

1
2
3
4
5
6
7
8

9
10
11
12
13
14

G PACKAGE

28-LEAD PLASTIC SSOP

T

= 110°C, θJA = 100°C/W

JMAX

DB14

28

DB15 (MSB)

27

CLK

26

V

25

DGND

24

V

23

COMP2

22

COMP1

21

I

20

I

19

LADCOM

18

AGND

17

I

16

REFOUT

15

DD

SS

OUT A

OUT B

REFIN

Consult factory for Military grade parts.

ORDER PART

NUMBER

LTC1668CG
LTC1668IG

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, LADCOM = AGND = DGND = 0V, I

The ● denotes specifications which apply over the full operating

= 10mA.

OUTFS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Accuracy (Measured at I

, Driving a Virtual Ground)

OUTA

Resolution 16 Bits
Monotonicity 14 Bits

INL Integral Nonlinearity ±8 LSB
DNL Differential Nonlinearity ±1 ±4 LSB

Offset Error 0.1 ±0.2 % FSR
Offset Error Drift 5 ppm/°C

GE Gain Error Internal Reference, R

External Reference, V

= 2k 2 % FSR

IREFIN

= 2.5V, R

REF

= 2k 1 % FSR

IREFIN

Gain Error Drift Internal Reference 75 ppm/°C

External Reference 50 ppm/°C

PSRR Power Supply Rejection Ratio VDD = 5V ±5% ±0.1 % FSR/V

= –5V ±5% ±0.1 % FSR/V

V

SS

Analog Output

I

OUTFS

Full-Scale Output Current ● 110mA
Output Compliance Range IFS = 10mA ● –1 1 V
Output Resistance; R

IOUTA

, R

IOUTB

I

to LADCOM ● 0.7 1.1 1.5 kΩ

OUTA, B

Output Capacitance 5pF

Reference Output

Reference Voltage REFOUT Tied to I

Through 2kΩ 2.475 2.5 2.525 V

REFIN

Reference Output Drift 25 ppm/°C
Reference Output Load Regulation I

= 0mA to 5mA 6 mV/mA

LOAD

2

LTC1668

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, LADCOM = AGND = DGND = 0V, I

The ● denotes specifications which apply over the full operating

= 10mA.

OUTFS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Input

Reference Small-Signal Bandwidth IFS = 10mA, C

= 0.1µF20kHz

COMP1

Power Supply

V

DD

V

SS

I

DD

I

SS

P

DIS

Positive Supply Voltage ● 4.75 5 5.25 V
Negative Supply Voltage ● –4.75 –5 –5.25 V
Positive Supply Current IFS = 10mA, f
Negative Supply Current IFS = 10mA, f
Power Dissipation IFS = 10mA, f

IFS = 1mA, f

= 25Msps, f

CLK

= 25Msps, f

CLK

= 25Msps, f

CLK

= 25Msps, f

CLK

= 1MHz ● 35 mA

OUT

= 1MHz ● 33 40 mA

OUT

= 1MHz ● 180 mW

OUT

= 1MHz ● 85 mW

OUT

Dynamic Performance (Differential Transformer Coupled Output, 50Ω Double Terminated, Unless Otherwise Noted)

f

CLOCK

t

S

t

PD

Maximum Update Rate ● 50 75 Msps
Output Settling Time To 0.1% FSR 30 ns
Output Propagation Delay 8ns
Glitch Impulse Single Ended 15 pV-s

Differential 5 pV-s

t

r

t

f

i

NO

Output Rise Time 4ns
Output Fall Time 4ns
Output Noise IFS = 10mA 50 pA/√Hz

IFS = 1mA 30 pA/√Hz

AC Linearity

SFDR Spurious Free Dynamic Range f

= 25Msps, f

CLK

OUT

= 1MHz

to Nyquist 0dB FS Output 78 87 dB

–6dB FS Output 87 dB
–12dB FS Output 86 dB
–18dB FS Output 80 dB

f

Spurious Free Dynamic Range f
Within a Window f

THD Total Harmonic Distortion f

= 50Msps, f

CLK

f

= 50Msps, f

CLK

f

= 50Msps, f

CLK

f

= 50Msps, f

CLK

= 25Msps, f

CLK

= 50Msps, f

CLK

= 25Msps, f

CLK

f

= 50Msps, f

CLK

= 1MHz 84 dB

OUT

= 2.5MHz 80 dB

OUT

= 5MHz 77 dB

OUT

= 20MHz 65 dB

OUT

= 1MHz, 2MHz Span 86 96 dB

OUT

= 5MHz, 4MHz Span 88 dB

OUT

= 1MHz –84 –77 dB

OUT

= 5MHz –76 dB

OUT

Digital Inputs

V

IH

V

IL

I

IN

C

IN

t

DS

t

DH

t

CLKH

t

CLKL

Digital High Input Voltage ● 2.4 V
Digital Low Input Voltage ● 0.8 V
Digital Input Current ● ±10 µA
Digital Input Capacitance 5pF
Input Setup Time ● 8ns
Input Hold Time ● 4ns
Clock High Time ● 5ns
Clock Low Time ● 8ns

Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.

3

LTC1668

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Single Tone SFDR 2-Tone SFDR

–5
–15
–25
–35
–45
–55
–65
–75

SIGNAL AMPLITUDE (dBm)

–85
–95

–105

0.05
FREQUENCY (1.25MHz/DIV)

f

= 25Msps

CLOCK

f

= 1.007MHz

OUT

AMPLITUDE = 0dBFS
= –8.5dBm
SFDR = 86dBc

6.3

1668 G01

12.55

Integral Nonlinearity Differential Nonlinearity

5
4
3
2

1

0
–1
–2
–3

INTEGRAL NONLINEARITY (LSB)

–4
–5

16384

32768

DIGITAL INPUT CODE

49152

65535

1668 G03

–10
–20
–30
–40
–50
–60
–70
–80

SIGNAL AMPLITUDE (dBm)

–90
–100
–110

2.0

1.5

1.0

0.5

–0.5

–1.0

DIFFERENTIAL NONLINEARITY (LSB)

–1.5

–2.0

f

= 50Msps

CLOCK

=

f

OUT1

4.028MHz
=

f

OUT2

4.419MHz

AMPLITUDE 1, 2
= –6dBFS
= –14.5dBm
SFDR > 77dBc

3.2

0

0

4.2

FREQUENCY (0.2MHz/DIV)

16384

32768

DIGITAL INPUT CODE

49152

5.2

1668 G02

65535

1668 G04

U

UU

PI FU CTIO S

REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1µF bypass capacitor
to AGND.

I

(Pin 16): Reference Input Current. Nominal value is

REFIN

1.25mA for IFS = 10mA. IFS = I

REFIN

• 8.

AGND (Pin 17): Analog Ground.
LADCOM (Pin 18): Attenuator Ladder Common. Normally

tied to GND.

I

(Pin 19): Complementary DAC Output Current. Full-

OUT B

scale output current occurs when all data bits are 0s.

I

(Pin 20): DAC Output Current. Full-scale output

OUT A

current occurs when all data bits are 1s.

4

COMP1 (Pin 21): Current Source Control Amplifier Com­pensation. Bypass to VSS with 0.1µF.

COMP2 (Pin 22): Internal Bypass Point. Bypass to V

SS

with 0.1µF.
VSS (Pin 23): Negative Supply Voltage. Nominal value is

–5V.

DGND (Pin 24): Digital Ground.
VDD (Pin 25): Positive Supply Voltage. Nominal value is 5V.
CLK (Pin 26): Clock Input. Data is latched and the output

is updated on positive edge of clock.
DB15 to DB0 (Pins 27, 28, 1 to 14): Digital Input Data Bits.

BLOCK DIAGRA

LTC1668

0.1µF

V

REF

REFOUT

15

R

SET

2k

IREFIN

16

W

2.5V

REFERENCE

IFS/8

5V

25

ATTENUATOR

LADDER

LSB SWITCHES

0.1µF

SEGMENTED SWITCHES

FOR DB15–DB12

LADCOM

I

OUT A

I

OUT B

18

20

19

52.3Ω 52.3Ω

+
–

LTC1668

V

OUT

1V

P-P

DIFFERENTIAL

COMP121

22

0.1µF

COMP2

0.1µF

–5V

UWW

TI I G DIAGRA

+

–

23

V

SS

0.1µF

AGND17DGND

DB0

TO DB15

CLK

I

INT

24

N – 1

CLK DB0DB15 • • •

26 27 14

CLOCK

INPUT

CURRENT SOURCE ARRAY

• • • • • •

INPUT LATCHES

16-BIT

DATA INPUT

N N + 1

t

DS

t

DH

1668 BD

I

OUT A/IOUT B

t

CLKL

N – 1 N

t

CLKH

t

PD

t

ST

0.1%

1668 TD

5

LTC1668

WUUU

APPLICATIO S I FOR ATIO

Theory of Operation

The LTC1668 is a high speed current steering 16-Bit DAC
made on an advanced BiCMOS process. Precision thin
film resistors and well matched bipolar transistors result
in excellent DC linearity and stability. A low glitch current
switching design gives excellent AC performance at sample
rates up to 50Msps. The device is complete with a 2.5V
internal bandgap reference and edge triggered latches,
and sets a new standard for DAC applications requiring
very high dynamic range at output frequencies up to
several megahertz.

Referring to the Block Diagram, the DAC contains an array
of current sources that are steered to I

OUTA

or I

OUTB

with
NMOS differential current switches. The four most signifi­cant bits, DB15 to DB12 are made up of 15 current
segments of equal weight. The lower bits, DB11 to DB0 are
binary weighted, using a combination of current scaling
and a differential resistive attenuator ladder. All bits and
segments are precisely matched, both in current weight
for DC linearity, and in switch timing for low glitch impulse
and low spurious tone AC performance.

Setting the Full-Scale Current, I

The full-scale DAC output current, I

OUTFS

OUTFS

, is nominally
10mA, and can be adjusted down to 1mA. Placing a
resistor, R
sets I

OUTFS

, between the REFOUT pin, and the I

SET

as follows.

REFIN

pin

The internal reference control loop amplifier maintains a
virtual ground at I
source, I
I

is a scaled replica of the DAC current sources and

INT

I

OUTFS

I

OUTFS

, to sink the exact current flowing into I

INT

= 8 • (I

= 8 • (I

), therefore:

INT

REFIN

For example, if R

2.5V, I

= 2.5/2k = 1.25mA and I

REFIN

by servoing the internal current

REFIN

) = 8 • (V

= 2k and is tied to V

SET

REF/RSET

) (1)

REF

= 8 • (1.25mA)

OUTFS

REFIN

= REFOUT =

.

= 10mA.
The reference control loop requires a capacitor on the

COMP1 pin for compensation. For optimal AC perfor­mance, C

should be connected to VSS and be placed

COMP1

very close to the package (less than 0.1").

For fixed reference voltage applications, C

COMP1

should

be 0.1µF or more. The reference control loop small-signal
bandwidth is approximately 1/(2π) • C
for C

COMP1

= 0.1µF.

COMP1

• 80 or 20kHz

Internal Reference Output—REFOUT

The onboard 2.5V bandgap voltage reference drives the
REFOUT pin. It is trimmed and specified to drive a 2k
resistor tied from REFOUT to I

1.25mA load (I

= 10mA). REFOUT has nominal

OUTFS

, corresponding to a

REFIN

output impedance of 6Ω, or 0.24% per mA, so it must be
buffered to drive any additional external load. A 0.1µF
capacitor is required on the REFOUT pin for compensa­tion. Note that this capacitor is required for stability, even
if the internal reference is not being used.

DAC Transfer Function

The LTC1668 uses straight binary digital coding. The
complementary current outputs, I
current from 0 to I
I

swings from 0mA when all bits are low (i.e., Code =

OUT A

OUTFS

. For I

OUTFS

OUT A

and I

OUT B

, sink

= 10mA (nominal),

0) to 10mA when all bits are high (i.e., Code = 65535) (deci­mal representation). I
I

OUT A

I

OUT A

I

OUT B

and I

= I
= I

are given by the following formulas:

OUT B

• (DAC Code/65536) (2)

OUTFS

• (65535-DAC Code)/65536 (3)

OUTFS

is complementary to I

OUT B

OUT A

.

In typical applications, the LTC1668 differential output
currents either drive a resistive load directly or drive an
equivalent resistive load through a transformer, or as the
feedback resistor of an I-to-V converter. The voltage
outputs generated by the I

OUT A

and I

output currents

OUT B

are then:

V

OUT A

V

OUT B

= I
= I

OUT A

OUT B

• R

• R

LOAD

LOAD

(4)
(5)

The differential voltage is:

V

DIFF

= V

= (I

OUT A
OUT A

– V

– I

OUT B

OUT B

) • (R

LOAD

(6)

)

6

WUUU

APPLICATIO S I FOR ATIO

LTC1668

Substituting the values found earlier for I
I

:

OUTFS

V

= {2 • DAC Code – 65535)/65536} • 8 •

DIFF

(R

LOAD/RSET

) • (V

) (7)

REF

OUT A

, I

OUT B

and

From these equations some of the advantages of differen­tial mode operation can be seen. First, any common mode
noise or error on I

OUT A

and I

is cancelled. Second, the

OUT B

signal power is twice as large as in the single-ended case.
Third, any errors and noise that multiply times I
I

, such as reference or I

OUT B

noise, cancel near

OUTFS

OUT A

and

midscale, where AC signal waveforms tend to spend the
most time. Fourth, this transfer function is bipolar; e.g. the
output swings positive and negative around a zero output
at mid-scale input, which is more convenient for AC
applications.

Note that the term (R

LOAD/RSET

) appears in both the
differential and single-ended transfer functions. This means
that the Gain Error of the DAC depends on the ratio of
R

to R

LOAD

temperature tracking of R
the absolute tempco of R

, and the Gain Error tempco is affected by the

SET

with R

LOAD

is very critical for DC

LOAD

. Note also that

SET

nonlinearity. As the DAC output changes from 0mA to
10mA the R

resistor will heat up slightly, and even a

LOAD

very low tempco can produce enough INL bowing to be
significant at the 16-bit level. This effect disappears with
medium to high frequency AC signals due to the slow
thermal time constant of the load resistor.

Analog Outputs

The LTC1668 has two complementary current outputs,
I

and I

OUT A

impedance of I

(see DAC Transfer Function). The output

OUT B

OUT A

and I

OUT B

(R

IOUT A

and R

IOUT B

) is

typically 1.1kΩ to LADCOM. (See the Equivalent Analog
Output Circuit, Figure 1.) The LADCOM pin is the com­mon connection for the internal DAC attenuator ladder. It
usually is tied to analog ground, but more generally it
should connect to the same potential as the lead resistors
on I
current to VSS of approximately 0.32 • (I
current that flows from I
R

IOUT A

OUT A

and I

and R

. The LADCOM pin carries a constant

OUT B

OUTFS

IOUT B

OUT A

resistors.

and I

through the

OUT B

), plus any

R

IOUT A

1.1k

LADCOM

I

OUT A

I

OUT B

5pF

V

18

20

52.3Ω

19

52.3Ω

SS

–5V

23

1668 F01

LTC1668

R

IOUT B

1.1k

5pF

Figure 1. Equivalent Analog Output Circuit

The specified output compliance voltage range is ±1V. The
DC linearity specifications, INL and DNL, are trimmed and
guaranteed on I

into the virtual ground of an

OUT A

I-to-V converter, but are typically very good over the full
output compliance range. Above 1V the output current will
start to increase as the DAC current steering switch
impedance decreases, degrading both DC and AC linear­ity. Below – 1V, the DAC switches will start to approach the
transition from saturation to linear region. This will de­grade AC performance first, due to nonlinear capacitance
and increased glitch impulse. AC distortion performance
is optimal at amplitudes less than ±0.5V
I

due to nonlinear capacitance and other large-signal

OUT B

P-P

on I

OUT A

and

effects. At first glance, it may seem counter-intuitive to
decrease the signal amplitude when trying to optimize
SFDR. However, the error sources that affect AC perfor­mance generally behave as additive currents, so decreas­ing the load impedance to reduce signal voltage amplitude
will reduce most spurious signals by the same amount.

The LTC1668 is specified to operate with full-scale output
current, I

, from the nominal 10mA down to 1mA.

OUTFS

This can be useful to reduce power dissipation or to adjust
full-scale value. However, that the LTC1668 DC and AC
accuracy is specified only at I
AC accuracy will fall off significantly at lower I
At I

= 1mA, INL and DNL typically degrade to the 14-

OUTFS

= 10mA, and DC and

OUTFS

OUTFS

values.

bit to 13-bit level, compared to 16-bit to 15-bit typical
accuracy at 10mA I

. Increasing I

OUTFS

from 1mA, the

OUTFS

7

LTC1668

WUUU

APPLICATIO S I FOR ATIO

accuracy improves rapidly, roughly in proportion to
1/I
reducing I

. The AC performance tends to be less affected by

OUTFS

, except for the unavoidable affects on

OUTFS

SFDR and THD due to increased INL and DNL.

Output Configurations

Based on the specific application requirements, the
LTC1668 allows a choice of the best of several output
configurations. Voltage outputs can be generated by ex­ternal load resistors, transformer coupling or with an op
amp I-to-V converter. Single-ended DAC output configu­rations use only one of the outputs, preferably I

OUT A

, to
produce a single-ended voltage output. Differential mode
configurations use the difference between I
I

to generate an output voltage, V

OUT B

, as shown in

DIFF

OUT A

and

equation 7. Differential mode gives much better accuracy
in most AC applications. Because the DAC chip is the point
of interface between the digital input signals and the
analog output, some small amount of noise coupling to
I

OUT A

and I

is unavoidable. Most of that digital noise

OUT B

is common mode and is canceled by the differential mode
circuit. Other significant digital noise components can be
modeled as V

REF

or I

noise. In single-ended mode,

OUTFS

I

noise is gone at zero scale and is fully present at full

OUTFS

scale. In differential mode, I

noise is cancelled at

OUTFS

midscale input, corresponding to zero analog output.
Many AC signals, including broadband and multitone
communications signals with high peak to average ratios,
stay mostly near midscale.

Differential transformer-coupled output configurations
usually give the best AC performance. An example is the
AC Characterization Setup circuit, Figure 2. The advan­tages of transformer coupling include excellent rejection
of common mode distortion and noise over a broad
frequency range and convenient differential-to-single­ended conversion with isolation or level shifting. Also, as
much as twice the power can be delivered to the load, and
impedance matching can be accomplished by selecting
the appropriate transformer turns ratio. The center tap on
the primary side of the transformer is tied to ground to
provide the DC current path for I
distortion, the DC average of the I

OUT A

OUT A

and I

and I

OUT B

OUT B

. For low

currents
must be exactly equal to avoid biasing the core. This is
especially important for compact RF transformers with
small cores. The circuit in Figure 2 uses a Mini-Circuits
T1-1T RF transformer with a 1:1 turns ratio. The load

0.1µF

0.1µF

5V

0.1µF

V

REFOUT

R

SET

2k

I

REFIN

2.5V

REFERENCE

+

–

COMP1

C1

C2

0.1µF

COMP2

V

SS

–5V

LOW JITTER

CLOCK SOURCE

AGND DGND CLK DB15 DB0

0.1µF

CLK
IN

PULSE GENERATOR

OUT 1 OUT 2

HP8110A DUAL

DD

16-BIT

HIGH SPEED

DAC

CLK
IN

LTC1668

I

OUT A

I

OUT B

LADCOM

16

DIGITAL
DATA

HP1663EA

LOGIC ANALYZER WITH

PATTERN GENERATOR

1668 F02

50Ω

50Ω

110Ω

MINI-CIRCUITS

T1–1T

TO HP3589A
SPECTRUM
ANALYZER
50Ω INPUT

Figure 2. AC Characterization Setup

8

WUUU

APPLICATIO S I FOR ATIO

resistance on I
differential resistor of 50Ω, and the 1:1 turns ratio means
the output impedance from the transformer is 50Ω. Note
that the load resistors are optional, and they dissipate half
of the output power. However, in lab environments or
when driving long transmission lines it is very desirable to
have a 50Ω output impedance. This could also be done
with a 50Ω resistor at the transformer secondary, but
putting the load resistors on I
since it reduces the current through the transformer. At
signal frequencies lower than about 1MHz, the trans­former core size required to maintain low distortion gets
larger, and at some lower frequencies this becomes
impractical.

A differential resistor loaded output configuration is shown
in the Block Diagram. It is simple and economical, but it
can drive only differential loads with impedance levels and
amplitudes appropriate for the DAC outputs.

The recommended single-ended resistor loaded configu­ration is essentially the same circuit as the differential
resistor loaded, case—simply use the I
referred to ground. Rather than tying the unused I
output to ground, it is preferred to load it with the equiva­lent R

LOAD

of I

waveform complementary to I
Adding an op amp differential to single-ended converter

circuit to the differential resistor loaded output gives the
circuit of Figure 10.

This circuit complements the capabilities of the trans­former-coupled application at lower frequencies, since
available op amps can deliver good AC distortion perfor­mance at signal frequencies of a few MHz down to DC. The
optional capacitor adds a single real pole of filtering, and
helps reduce distortion by limiting the high frequency
signal amplitude at the op amp inputs. The circuit swings
±1V around ground.

Figure 3 shows a simplified circuit for a single-ended
output using I-to-V converter to produce a unipolar
buffered voltage output. This configuration typically has
the best DC linearity performance, but its AC distortion at
higher frequencies is limited by U1’s slewing capabilities.

OUT A

OUT A

and I

OUT B

. Then I

is equivalent to a single

and I

OUT A

will still swing with a

OUT B

.

OUT A

is preferred

OUT B

OUT A

output,

OUT B

LTC1668

C

OUT

R

FB

I

OUTFS

10mA

I

OUT A

LTC1668

I

OUT B

LADCOM

Figure 3. Unipolar Buffered Voltage Output

200Ω

Digital Interface

The LTC1668 has 16 parallel inputs that are latched on the
rising edge of the clock input. They accept CMOS levels
from either 5V or 3.3V logic and can accept clock rates of
up to 50MHz.

Referring to the Timing Diagram and Block Diagram, the
data inputs go to master-slave latches that update on the
rising edge of the clock. The input logic thresholds, VIH =

2.4V min, VIL = 0.8V max, work with 3.3V or 5V CMOS
levels over temperature. The guaranteed setup time, tDS,
is 8ns minimum and the hold time, tDH, is 4ns minimum.
The minimum clock high and low times are guaranteed at
6ns and 8ns, respectively. These specifications allow the
LTC1668 to be clocked at up to 50Msps minimum.

For best AC performance, the data and clock waveforms
need to be clean and free of undershoot and overshoot.
Clock and data interconnect lines should be twisted pair,
coax or microstrip, and proper line termination is impor­tant. If the digital input signals to the DAC are considered
as analog AC voltage signals, they are rich in spectral
components over a broad frequency range, usually in­cluding the output signal band of interest. Therefore, any
direct coupling of the digital signals to the analog output
will produce spurious tones that vary with the exact digital
input pattern.

Clock jitter should be minimized to avoid degrading the
noise floor of the device in AC applications, especially
where high output frequencies are being generated. Any
noise coupling from the digital inputs to the clock input will

200Ω

–

U1

®

LT

1812

+

V

OUT

0V TO 2V

1668 F03

9

LTC1668

WUUU

APPLICATIO S I FOR ATIO

cause phase modulation of the clock signal and the DAC
waveform, and can produce spurious tones. It is normally
best to place the digital data transitions near the falling
clock edge, well away from the active rising clock edge.
Because the clock signal contains spectral components
only at the sampling frequency and its multiples, it is
usually not a source of in band spurious tones. Overall, it
is better to treat the clock as you would an analog signal
and route it separately from the digital data input signals.
The clock trace should be routed either over the analog
ground plane or over its own section of the ground plane.
The clock line needs to have accurately controlled imped­ance and should be well terminated near the LTC1668.

Printed Circuit Board Layout Considerations—
Grounding, Bypassing and Output Signal Routing

The close proximity of high frequency digital data lines and
high dynamic range, wide-band analog signals makes
clean printed circuit board design and layout an absolute
necessity. Figures 5 to 9 are the printed circuit board layers
for an AC evaluation circuit for the LTC1668. Ground
planes should be split between digital and analog sections
as shown. All bypass capacitors should have minimum
trace length and be ceramic 0.1µF or larger with low ESR.

Bypass capacitors are required on VSS, VDD and REFOUT,
and all connected to the AGND plane. The COMP2 pin ties
to a node in the output current switching circuitry, and it
requires a 0.1µF bypass capacitor. It should be bypassed
to VSS along with COMP1. The AGND and DGND pins
should both tie directly to the AGND plane, and the tie point
between the AGND and DGND planes should nominally be
near the DGND pin. LADCOM should either be tied directly
to the AGND plane or be bypassed to AGND. The I
I

traces should be close together, short, and well

OUT B

matched for good AC CMRR. The transformer output
ground should be capable of optionally being isolated or
being tied to the AGND plane, depending on which gives
better performance in the system.

Suggested Evaluation Circuit

Figure 4 is the schematic and Figures 5 to 9 are the circuit
board layouts for a suggested evaluation circuit, DC245A.
The circuit can be programmed with component selection
and jumpers for a variety of differentially coupled trans­former output and differential and single-ended resistor
loaded output configurations.

OUT A

and

10

WUUU

APPLICATIO S I FOR ATIO

OUT

J4

V

4
T1
3

2

TP4

OUT A

J2

I

C18

0.1µF

JP2

TP3

R3

1.91k

R4

WHT

TESTPOINT

C3

0.1µF

0.1%

JP4

R5 R6

JP3

C17

0.1µF

1516

REFOUTREFIN

LTC1668-28

5V

TESTPOINT WHT
C4

R7

110Ω

TP5

20

19

OUT AIOUT B

I

DB15 (MSB)

DB14

DB13

DB12

123456789

27

28

C5

R8

6

MINI-

1

J5

JP5

C8

21

22

18

TESTPOINT WHT

COMP1

LADCOM

DB11

DB10

DB9

T1–1T

CIRCUITS

JP8

C9

OUT B

I

0.1µF

C8

0.1µF

C7

0.1µF

COMP2

DB8

DB7

JP7

JP6

0.1µF

–5V

5V

23

25

SS

V

V

DB6

DB5

C12

22pF

R10

50Ω

0.1%

R9

50Ω

0.1%

C12

22pF

C11

0.1µF

C10

0.1µF

17

24

DD

AGND

DGND

DB4

DB3

DB2

1011121314

1668 F04

DB1

DB0

26

CLK

TIE POINT

AGND DGND

GROUND PLANE

J6

EXTCLK

1%

R12

49.9Ω

123

JP9

TP8

TESTPOINT RED

–5V

J9

C16

C20

C22

LTC1668

10µF

25V

+

0.1µF

0.1µF

Figure 4. Suggested Evaluation Circuit

TP10

TESTPOINT BLK

TP1

R1

10Ω

J1

EXTREF

C1

0.1µF

R2

200Ω

REF

TP2

2.5V

TESTPOINT WHT

246

JP1

135

6

2

LT1460DCS8-2.5

5V

C15

10µF

+5VD

16151413121110

RN5

1234567

+5VD

4

OUT

V

GND

IN

V

C2

0.1µF

13579

AMP

2468101214161820222426283032343638

102159-9

SIP

(NOT

PULL-UP/

OPTIONAL

RESISTORS

INSTALLED)

PULL-DOWN

16151413121110

9

RN6

22Ω

1234567

8

SIP

(NOT

PULL-UP/

OPTIONAL

RESISTORS

INSTALLED)

PULL-DOWN

111315171921232527293133353739

9

22Ω

8

TP7

TESTPOINT RED

+5VA

TP6

TESTPOINT RED

40

+5VD

25V

+

C23

C21

J8

C14

TP9

0.1µF

0.1µF

J11

10µF

TESTPOINT BLK

25V

+

C19

0.1µF

J7

J10

11

LTC1668

WUUU

APPLICATIO S I FOR ATIO

Figure 5. Suggested Evaluation Circuit Board—Silkscreen

12

Figure 6. Suggested Evaluation Circuit Board—Component Side

WUUU

APPLICATIO S I FOR ATIO

LTC1668

Figure 7. Suggested Evaluation Circuit Board—GND Plane

Figure 8. Suggested Evaluation Circuit Board—Power Plane

13

LTC1668

WUUU

APPLICATIO S I FOR ATIO

Figure 9. Suggested Evaluation Circuit Board—Solder Side

14

PACKAGE DESCRIPTIO

U

Dimensions in millimeters (inches) unless otherwise noted.

G Package

28-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

10.07 – 10.33*

(0.397 – 0.407)

2526 22 21 20 19 181716 1523242728

LTC1668

7.65 – 7.90

(0.301 – 0.311)

5.20 – 5.38**
(0.205 – 0.212)

° – 8°

0

0.13 – 0.22

(0.005 – 0.009)

NOTE: DIMENSIONS ARE IN MILLIMETERS

*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

0.55 – 0.95

(0.022 – 0.037)

12345678 9 10 11 12 1413

0.65

(0.0256)

BSC

0.25 – 0.38

(0.010 – 0.015)

1.73 – 1.99

(0.068 – 0.078)

0.05 – 0.21

(0.002 – 0.008)

G28 SSOP 1098

15

LTC1668

TYPICAL APPLICATIO

U

5V

0.1µF

0.1µF

0.1µF

R

0.1µF

SET

V

REFOUT

2k

I

REFIN

2.5V

REFERENCE

+

–

COMP1

COMP2

V

–5V

SS

AGND DGND CLK DB15 DB0

0.1µF

DD

CLOCK
INPUT

16-BIT

HIGH SPEED

DAC

16-BIT DATA

INPUT

Figure 10. High Speed Buffered V

LTC1668

I

OUT A

I

OUT B

LADCOM

1668 F10

OUT

DAC

C

OPT

52.3Ω

200Ω

200Ω

52.3Ω

500Ω

–

+

500Ω

LT

®

1812

V

OUT

±1V
10dBm

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1406 8-Bit, 20Msps ADC Undersampling Capability Up to 70MHz Input
LTC1414 14-Bit, 2.2Msps ADC 84dB SFDR at 1.1MHz f
LTC1420 12-Bit, 10Msps ADC 72dB SINAD at 5MHz f
LTC1604 16-Bit, 333ksps ADC 16-Bit, No Missing Codes, 90dB SINAD, –100dB THD

Linear Technology Corporation

16

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

IN

IN

1668i LT/TP 0200 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2000