Page 1
FEATURES
■
Tiny: 8 DACs in the Board Space of an SO-8
■
Micropower: 56µA per DAC Plus
1µA Sleep Mode for Extended Battery Life
■
Pin Compatible 8-Bit LTC1665 and 10-Bit LTC1660
■
Wide 2.7V to 5.5V Supply Range
■
Rail-to-Rail Voltage Outputs Drive 1000pF
■
Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
■
Reference Input Impedance is Constant—
Eliminates External Buffer
U
APPLICATIO S
■
Mobile Communications
■
Remote Industrial Devices
■
Automatic Calibration for Manufacturing
■
Portable Battery-Powered Instruments
■
Trim/Adjust Applications
LTC1665/LTC1660
Micropower Octal
8-Bit and 10-Bit DACs
U
DESCRIPTIO
The 8-bit LTC®1665 and 10-bit LTC1660 integrate eight
accurate, serially addressable digital-to-analog converters (DACs) in tiny 16-pin narrow SSOP packages. Each
buffered DAC draws just 56µA total supply current, yet is
capable of supplying DC output currents in excess of
5mA and reliably driving capacitive loads to 1000pF.
Sleep mode further reduces total supply current to 1µA.
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external
form factor.
Ultralow supply current, power-saving Sleep mode and
extremely compact size make the LTC1665 and LTC1660
ideal for battery-powered applications, while their ease of
use, high performance and wide supply range make them
excellent choices as general purpose converters.
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
1GND
2
V
OUT A
V
3 14
OUT B
V
4 13
OUT C
V
5
OUT D
REF
6
7
CS/LD
SCK
8
DAC A DAC H
DAC B DAC G
DAC C DAC F
DAC D DAC E
CONTROL
LOGIC
W
SHIFT REGISTER
ADDRESS
DECODER
16
15
12
11
10
9
1665/60 BD
V
V
V
V
V
CLR
D
D
CC
OUT H
OUT G
OUT F
OUT E
OUT
IN
LTC1665 Differential Nonlinearity (DNL)
0.5
VCC = 5V
0.4
V
= 4.096V
REF
0.3
0.2
0.1
0
LSB
–0.1
–0.2
–0.3
–0.4
–0.5
0 64 128 192 255
CODE
1665/60 G09
LTC1660 Differential Nonlinearity (DNL)
1
VCC = 5V
0.8
V
= 4.096V
REF
0.6
0.4
0.2
0
LSB
–0.2
–0.4
–0.6
–0.8
–1
0 256 512 768 1023
CODE
1665/60 G13
1
Page 2
LTC1665/LTC1660
WU
A
W
O
LUTEXI TIS
S
A
WUW
ARB
U
G
PACKAGE
/
O
RDER I FOR ATIO
(Note 1)
VCC to GND .............................................. –0.2V to 7.5V
Logic Inputs to GND ................................ –0.2V to 7.5V
V
OUT A
, V
OUT B…VOUT H
,
REF to GND ................................. –0.2V to (VCC + 0.2V)
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LTC1665C/LTC1660C ............................ 0°C to 70°C
LTC1665I/LTC1660I .......................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
LECTRICAL C CHARA TERIST
E
ICS
TOP VIEW
1
GND
2
V
OUT A
3
V
OUT B
4
V
OUT C
5
V
OUT D
6
REF
7
CS/LD
8
SCK
GN PACKAGE
16-LEAD PLASTIC SSOP
T
= 125°C, θJA = 150°C/W (GN)
JMAX
T
= 125°C, θJA = 100°C/W (N)
JMAX
Consult factory for Military grade parts.
V
16
CC
V
15
OUT H
V
14
OUT G
V
13
OUT F
V
12
OUT E
CLR
11
D
10
OUT
D
9
IN
N PACKAGE
16-LEAD PDIP
ORDER PART
NUMBER
LTC1665CGN
LTC1665CN
LTC1665IGN
LTC1665IN
LTC1660CGN
LTC1660CN
LTC1660IGN
LTC1660IN
GN PART MARKING
1665
1665I
1660
1660I
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VCC = 2.7V to 5.5V, V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Accuracy
Resolution ● 8 10 Bits
Monotonicity V
DNL Differential Nonlinearity V
INL Integral Nonlinearity V
V
OS
FSE Full-Scale Error VCC = 5V, V
PSR Power Supply Rejection V
Offset Error (Note 7) ● ±10 ±30 ±10 ±30 mV
VOS Temperature Coefficient ● ±15 ±15 µV/°C
Full-Scale Error Temperature Coefficient ● ±30 ±30 µV/°C
≤ VCC, V
REF
unloaded, unless otherwise noted.
OUT
LTC1665 LTC1660
≤ VCC – 0.1V (Note 2) ● 8 10 Bits
REF
≤ VCC – 0.1V (Note 2) ● ±0.1 ±0.5 ±0.2 ±0.75 LSB
REF
≤ VCC – 0.1V (Note 2) ● ±0.2 ±1.0 ±0.6 ±2.5 LSB
REF
= 4.096V ● ±1 ±4 ±3 ±15 LSB
REF
= 2.5V 0.045 0.18 LSB/V
REF
U
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VCC = 2.7V to 5.5V, V
SYMBOL PARAMETER CONDITONS MIN TYP MAX UNITS
Reference Input
Input Voltage Range ● 0V
Resistance Not in Sleep Mode ● 35 65 kΩ
Capacitance (Note 6) 15 pF
I
REF
Power Supply
V
CC
I
CC
Reference Current Sleep Mode ● 0.001 1 µA
Positive Supply Voltage For Specified Performance ● 2.7 5.5 V
Supply Current VCC = 5V (Note 3) ● 450 730 µA
≤ VCC, V
REF
unloaded, unless otherwise noted.
OUT
= 3V (Note 3) ● 340 550 µA
V
CC
Sleep Mode (Note 3)
● 13µA
CC
2
V
Page 3
LTC1665/LTC1660
LECTRICAL C CHARA TERIST
E
ICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VCC = 2.7V to 5.5V, V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Performance
Short-Circuit Current Low V
Short-Circuit Current High V
AC Performance
Voltage Output Slew Rate Rising (Notes 4, 5) 0.60 V/µs
Voltage Output Settling Time To ±0.5LSB (Notes 4, 5) 30 µs
Capacitive Load Driving 1000 pF
Digital I/O
V
IH
V
IL
V
OH
V
OL
I
LK
C
IN
Digital Input High Voltage VCC = 2.7V to 5.5V ● 2.4 V
Digital Input Low Voltage VCC = 4.5V to 5.5V ● 0.8 V
Digital Output High Voltage I
Digital Output Low Voltage I
Digital Input Leakage VIN = GND to V
Digital Input Capacitance (Note 6) ● 10 pF
≤ VCC, V
REF
= 0V, VCC = 5.5V, V
OUT
= VCC = 5.5V, V
OUT
Falling (Notes 4, 5) 0.25 V/µs
= 2.7V to 3.6V ● 2.0 V
V
CC
VCC = 2.7V to 5.5V ● 0.6 V
= –1mA, D
OUT
= 1mA, D
OUT
unloaded, unless otherwise noted.
OUT
= 5.1V, Code = Full Scale ● 10 30 100 mA
REF
= 5.1V, Code = 0 ● 10 27 120 mA
REF
Only ● VCC – 1 V
OUT
Only ● 0.4 V
OUT
CC
● ±10 µA
UW
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 4.5V to 5.5V
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
VCC = 2.7V to 5.5V
t
1
t
2
t
3
t
4
t
5
DIN Valid to SCK Setup ● 40 15 ns
DIN Valid to SCK Hold ● 0 –11 ns
SCK High Time (Note 6) ● 30 5 ns
SCK Low Time (Note 6) ● 30 7 ns
CS/LD Pulse Width (Note 6) ● 80 30 ns
LSB SCK High to CS/LD High (Note 6) ● 30 4 ns
CS/LD Low to SCK High (Note 6) ● 80 26 ns
D
Propagation Delay C
OUT
SCK Low to CS/LD Low (Note 6) ● 20 0 ns
CLR Pulse Width (Note 6) ● 100 37 ns
CS/LD High to SCK Positive Edge (Note 6) ● 30 0 ns
SCK Frequency Continuous Square Wave (Note 6) ● 5.00 MHz
DIN Valid to SCK Setup (Note 6) ● 60 20 ns
DIN Valid to SCK Hold (Note 6) ● 0 –14 ns
SCK High Time (Note 6) ● 50 8 ns
SCK Low Time (Note 6) ● 50 12 ns
CS/LD Pulse Width (Note 6) ● 100 30 ns
The ● denotes specifications which apply over the full operating temperature
= 15pF (Note 6) ● 52680ns
LOAD
Continuous 23% Duty Cycle Pulse (Note 6)
Gated Square Wave (Note 6) ● 16.7 MHz
● 7.69 MHz
3
Page 4
LTC1665/LTC1660
UW
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
6
t
7
t
8
t
9
t
10
t
11
LSB SCK High to CS/LD High (Note 6) ● 50 5 ns
CS/LD Low to SCK High (Note 6) ● 100 27 ns
D
Propagation Delay C
OUT
SCK Low to CS/LD Low (Note 6) ● 30 0 ns
CLR Pulse Width (Note 6) ● 120 41 ns
CS/LD High to SCK Positive Edge (Note 6) ● 30 0 ns
SCK Frequency Continuous Square Wave (Note 6) ● 3.85 MHz
The ● denotes specifications which apply over the full operating temperature
= 15pF (Note 6) ● 5 47 150 ns
LOAD
Continuous 28% Duty Cycle Pulse ● 5.55 MHz
Gated Square Wave
● 10 MHz
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined from code 4 to code
255 for the LTC1665 and from code 20 to code 1023 for the LTC1660.
See Applications Information.
Note 3: Digital inputs at 0V or VCC.
Note 5: VCC = V
i.e., codes 26 and 230 for the LTC1665 or codes 102 and 922 for the
LTC1660.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured at code 4 for the LTC1665 and code 20 for the
LTC1660.
Note 4: Load is 10kΩ in parallel with 100pF.
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Midscale Output Voltage
vs Load Current
3
V
= V
REF
CC
CODE = 128 (LTC1665)
2.9
CODE = 512 (LTC1660)
2.8
2.7
2.6
(V)
2.5
OUT
V
2.4
2.3
2.2
2.1
2
–30 –20 –10 0 10 20 30
VCC = 5.5V
VCC = 5V
VCC = 4.5V
I
(mA)
OUT
SINKSOURCE
1665/60 G01
2
1.9
1.8
1.7
1.6
(V)
1.5
OUT
V
1.4
1.3
1.2
1.1
1
–15 – 4–8–12 0 4 8 12 15
= 5V. DAC switched between 0.1VFS and 0.9VFS,
REF
(LTC1665/LTC1660)
Midscale Output Voltage
vs Load Current
V
= V
REF
CC
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
VCC = 3.6V
VCC = 3V
VCC = 2.7V
SINKSOURCE
I
(mA)
OUT
1665/60 G02
4
Page 5
UW
LOGIC INPUT VOLTAGE (V)
012345
SUPPLY CURRENT (mA)
1665/60 G07
2
1.6
1.2
0.8
0.4
0
ALL DIGITAL INPUTS
SHORTED TOGETHER
TYPICAL PERFOR A CE CHARACTERISTICS
LTC1665/LTC1660
(LTC1665/LTC1660)
Minimum Supply Headroom vs
Load Current (Output Sourcing)
1400
V
= 4.096V
REF
< 1LSB
∆V
OUT
1200
CODE = 255 (LTC1665)
CODE = 1023 (LTC1660)
1000
(mV)
800
OUT
600
– V
CC
V
400
200
0
0246810
|
I
|
(mA) (Sourcing)
OUT
Large-Signal Step Response Supply Current vs Logic Input Voltage
5
4
3
(V)
OUT
V
2
1
0
0 20406080100
TIME (µs)
VCC= V
10% TO
90% STEP
REF
1665/60 G05
= 5V
125°C
25°C
–55°C
1665/60 G03
Supply Current vs Temperature
500
480
460
440
420
400
380
360
SUPPLY CURRENT (µA)
340
320
300
–55 –35 –15 5 25 45 65 85 105 125
VCC = 5.5V
VCC = 4.5V
VCC = 3.6V
VCC = 2.7V
TEMPERATURE (°C)
Minimum V
Load Current (Output Sinking)
1400
VCC = 5V
CODE = 0
1200
1000
800
(mV)
OUT
600
V
400
200
0
0246810
1665/60 G06
OUT
|
I
|
(mA) (Sinking)
OUT
vs
125°C
25°C
–55°C
1665/60 G04
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
1
0.8
0.6
0.4
0.2
0
LSB
–0.2
–0.4
–0.6
–0.8
–1
0 64 128 192 255
VCC = 5V
= 4.096V
V
REF
UW
CODE
1665/60 G08
(LTC1665)
Differential Nonlinearity (DNL)
0.5
VCC = 5V
0.4
0.3
0.2
0.1
LSB
–0.1
–0.2
–0.3
–0.4
–0.5
= 4.096V
V
REF
0
0 64 128 192 255
CODE
1665/60 G09
5
Page 6
LTC1665/LTC1660
UW
TYPICAL PERFOR A CE CHARACTERISTICS
(LTC1665)
Load Regulation vs Output Current
VCC = V
0.5
CODE = 128
0.25
(LSB)
0
OUT
∆V
–0.25
–0.5
–2 –1 0 1 2
REF
= 5V
I
OUT
SINKSOURCE
(mA)
1665/60 G10
Load Regulation vs Output Current
0.5
0.25
(LSB)
0
OUT
∆V
–0.25
–0.5
–500 0 500
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
2.5
VCC = 5V
2.0
1.5
1.0
0.5
LSB
–0.5
–1.0
–1.5
–2.0
–2.5
= 4.096V
V
REF
0
0 256 512 768 1023
CODE
1665/60 G12
Differential Nonlinearity (DNL)
1
0.8
0.6
0.4
0.2
0
LSB
–0.2
–0.4
–0.6
–0.8
–1
0 256 512 768 1023
VCC = V
= 3V
REF
CODE = 128
(LTC1660)
VCC = 5V
= 4.096V
V
REF
I
OUT
(µA)
CODE
SINKSOURCE
1665/60 G11
1665/60 G13
6
Load Regulation vs Output Current
VCC = V
2
CODE = 512
1.5
1
0.5
(LSB)
0
OUT
–0.5
∆V
–1
–1.5
–2
–2 –1 0 1 2
REF
= 5V
I
OUT
SINKSOURCE
(mA)
1665/60 G14
Load Regulation vs Output Current
VCC = V
2
CODE = 512
1.5
1
0.5
(LSB)
0
OUT
–0.5
∆V
–1
–1.5
–2
–500 0 500
REF
= 3V
I
OUT
SINKSOURCE
(µA)
1665/60 G15
Page 7
UUU
PIN FUNCTIONS
LTC1665/LTC1660
(LTC1665/LTC1660)
GND (Pin 1): System Ground.
V
OUT A
to V
(Pins 2-5 and 12-15): DAC Analog
OUT H
Voltage Outputs. The output range is
255
256
1023
1024
REF
REF
1665
1660
REF
≤ VCC.
0
to V for the LTC
0
to V for the LTC
REF (Pin 6): Reference Voltage Input. 0V ≤ V
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on D
IN
into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.
W
BLOCK DIAGRA
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
DIN (Pin 9): Serial Interface Data Input. Data on the DIN pin
is shifted into the 16-bit register on the rising edge of SCK.
CMOS and TTL compatible.
D
(Pin 10): Serial Interface Data Output. Data appears
OUT
on D
16 positive SCK edges after being applied to DIN.
OUT
May be tied to DIN of another LTC1665/LTC1660 for daisychain operaton. CMOS and TTL compatible.
CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero scale.
CMOS and TTL compatible.
VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
1GND
2
V
OUT A
V
3 14
OUT B
V
4 13
OUT C
V
5
OUT D
REF
6
7
CS/LD
SCK
8
DAC A DAC H
DAC B DAC G
DAC C DAC F
DAC D DAC E
CONTROL
LOGIC
SHIFT REGISTER
ADDRESS
DECODER
16
15
12
11
10
9
1665/60 BD
V
V
V
V
V
CLR
D
D
CC
OUT H
OUT G
OUT F
OUT E
OUT
IN
7
Page 8
LTC1665/LTC1660
UWW
TI I G DIAGRA
SCK
t
1
t
2
t
t
3
4
t
6
t
9
D
CS/LD
D
OUT
IN
t
5
A3
A3 A2
t
7
t
8
A2 X1A1 X0
Figure 1
U
OPERATIO
Transfer Function
The transfer function is
k
V
OUT IDEAL REF
()
V
OUT IDEAL REF
()
=
=
where k is the decimal equivalent of the binary DAC input
code and V
is the voltage at REF (Pin 6).
REF
Power-On Reset
256
1024
V for theLTC
k
V for theLTC
1665
1660
t
11
A1 X1
X0
A3
1665/60 F01
Serial Interface
Referring to Figure 2a (2b): With CS/LD held low, data on
the DIN input is shifted into the 16-bit shift register on the
positive edge of
SCK
. The 4-bit DAC address, A3-A0, is
loaded first (see Table 2), then the 8-bit (10-bit) input
code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.
Four (two) don’t-care bits, X3-X0 (X1-X0), are loaded last.
When the full 16-bit input word has been shifted in, CS/LD
is pulled high, loading the DAC register with the word and
causing the addressed DAC output(s) to update. The
clock is disabled internally when CS/LD is high. Note:
SCK
must be low before CS/LD is pulled low.
The LTC1665 clears the outputs to zero scale when power
is first applied, making system initialization consistent and
repeatable.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.2V ≤ V
≤ VCC + 0.2V (see Absolute Maximum
REF
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition.
8
The buffered serial output of the shift register is available
on the D
appears on D
pin, which swings from GND to VCC. Data
OUT
16 positive SCK edges after being applied
OUT
to DIN.
Multiple LTC1665/LTC1660’s can be controlled from a
single 3-wire serial port (i.e., SCK, DIN and CS/LD) by
using the included “daisy-chain” facility. A series of
chips is configured by connecting each D
(except the
OUT
m
last) to DIN of the next chip, forming a single 16m-bit shift
register. The SCK and CS/LD signals are common to all
Page 9
OPERATIO
LTC1665/LTC1660
U
SCK
D
CS/LD
D
OUT
SCK
D
16151413121110987654321
IN
(ENABLE CLK) (UPDATE OUTPUT)
A3 A2
ADDRESS/CONTROL DON’T CARE
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2 X1 X0 A3
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2
INPUT CODE
INPUT WORD W
INPUT WORD W
0
–1
X1 X0
INPUT WORD W
Figure 2a. LTC1665 Register Loading Sequence
16151413121110987654321
IN
A3 A2
ADDRESS/CONTROL
A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
INPUT CODE DON’T CARE
X1 X0
0
1665/60 F02a
CS/LD
D
OUT
(ENABLE CLK) (UPDATE OUTPUT)
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 A3
Table 1a. LTC1665 Input Word
A3 A2 A1
Address/Control
A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X1 X0X2
Table 1b. LTC1660 Input Word
A3 A2 A1
Address/Control
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 X1 X0D0
INPUT WORD W
Figure 2b. LTC1660 Register Loading Sequence
Don’t CareInput Code
Input Code Don’t
Care
INPUT WORD W
0
–1
INPUT WORD W
chips in the chain. In use, CS/LD is held low while
16-bit words are clocked to DIN of the first chip; CS/LD is
then pulled high, updating all of them simultaneously.
Sleep Mode
DAC address 1110b is reserved for the special Sleep
instruction (see Table 2). In this mode, the digital interface
stays active while the analog circuits are disabled; static
power consumption is thus virtually eliminated. The reference input and analog outputs are set in a high impedance
0
1665/60 F02b
m
9
Page 10
LTC1665/LTC1660
U
OPERATIO
Table 2. DAC Address/Control Functions
ADDRESS/CONTROL
A3 A2 A1 A0 DAC STATUS SLEEP STATUS
0000 No Change Wake
0001 Load DAC A Wake
0010 Load DAC B Wake
0011 Load DAC C Wake
0100 Load DAC D Wake
0101 Load DAC E Wake
0110 Load DAC F Wake
0111 Load DAC G Wake
1000 Load DAC H Wake
1001 No Change Wake
1010 No Change Wake
1011 No Change Wake
1100 No Change Wake
1101 No Change Wake
1110 No Change Sleep
1111Load ALL DACs Wake
with Same
8/10-Bit Code
state and all DAC settings are retained in memory so that
when Sleep mode is exited, the outputs of DACs not
updated by the Wake command are restored to their last
active state.
Voltage Outputs
Each of the eight rail-to-rail output amplifiers contained in
these parts can source or sink up to 5mA. The outputs
swing to within a few millivolts of either supply rail when
unloaded and have an equivalent output resistance of 85Ω
when driving a load to the rails. The output amplifiers are
stable driving capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1µF
load can be successfully driven by inserting a 20Ω resistor; a 2.2µF load needs only a 10Ω resistor. In either case,
larger values of resistance, capacitance or both may be
safely substituted for the values given.
Rail-to-Rail Output Considerations
In any rail-to-rail output voltage DAC, the output is limited
to voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 3b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If V
= VCC and the DAC full-scale error
REF
(FSE) is positive, the output for the highest codes limits at
VCC as shown in Figure 3c. No full-scale limiting can occur
if V
is less than VCC – FSE.
REF
Sleep mode is initiated by performing a load sequence to
address 1110b (the DAC input word D7-D0 [D9-D0] is
ignored). Once in Sleep mode, a load sequence to any
other address (including “No Change” addresses 0000
b
and 1001-1101b) causes the LTC1665/LTC1660 to Wake.
It is possible to keep one or more chips of a daisy chain in
continuous Sleep mode by giving the Sleep instruction to
these chips each time the active chips in the chain are
updated.
10
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Page 11
OPERATIO
LTC1665/LTC1660
U
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
V
= V
REF
CC
1280 255
INPUT CODE
(a)
V
= V
REF
INPUT CODE
(c)
POSITIVE
CC
FSE
OUTPUT
VOLTAGE
OFFSET
0V
INPUT CODE
(b)
NEGATIVE
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
REF
= V
1665/60 F03
CC
11
Page 12
LTC1665/LTC1660
U
TYPICAL APPLICATIONS
A Low Power Quad Trim Circuit with Coarse/Fine Adjustment
3.3V 3.3V
V
V
1
OUT1
7
OUT2
R1
0.1µF
U2A
®
1491
LT
11
R1 R2
U2B
LT1491
R2
4
–
2
3
+
0.1µF
–
6
5
+
R1
COARSE
R2
FINE
R1
COARSE
GND
1
V
OUT A
2
V
OUT B
3 14
V
OUT C
4 13
U1
LTC1665
DAC A DAC H
DAC B DAC G
DAC C DAC F
0.1µF
V
CC
16
V
OUT H
15
V
OUT G
V
OUT F
COARSE
FINE
COARSE
R2
13
R1
12
R2
R2
R1
10
0.1µF
9
–
LT1491
+
–
LT1491
+
U2D
U2C
R1
14
V
OUT4
R1
8
V
OUT3
3.3V
2
LTC1258-2.5
4
0.1µF
1
INTERFACE
0.1µF
3-WIRE
SERIAL
R2
FINE
V
OUT D
CS/LD
REF
SCK
0.1µF
R2
V
5
6
7
8
DAC D DAC E
CONTROL
LOGIC
SHIFT REGISTER
ADDRESS
DECODER
OUT E
12
CLR
11
D
OUT
10
D
IN
9
1665/60 TA01
R2 >> R1
V
OUT 1
Similarly V
FINE
TO OTHER
LTC1665s
= V
OUT A
OUT 2
+
, V
R1
)
R2
OUT 3
)
V
OUT B
, V
OUT 4
Example: For R1 = 110Ω and R2 = 11k,
V
OUT 1
= V
OUT A
+ 0.01 V
OUT B
12
Page 13
U
TYPICAL APPLICATIONS
An 8-Channel Bipolar Output Voltage Circuit Configuration
LTC1665/LTC1660
V
OUT A
±5V
V
V
V
V
V
CLR
D
D
0.1µF
CC
OUT H
OUT G
OUT F
OUT E
OUT
IN
5V
R
R
0.1µF
+
V
S
4
–
2
V
S
0
512
–
11
RR
RR
RR
1
0.1µF
7
8
14
V
+4.99V
OUT X
–5V
0V
U3A
LT1491
3
+
–
6
U3B
LT1491
5
+
–
9
U3C
LT1491
10
+
–
13
U3D
LT1491
12
+
CODE
1023
V
±5V
V
±5V
V
±5V
OUT G
OUT F
OUT E
V
′
OUT H
±5V
′
′
′
R
0.1µF
+
V
S
4
±5V
±5V
±5V
1
U2A
LT1491
0.1µF
11
–
V
S
R R
7
′
′
′
8
14
U2B
LT1491
R R
U2C
LT1491
R
U2D
LT1491
INTERFACE
′
V
OUT B
V
OUT C
V
OUT D
3-WIRE
SERIAL
R
–
2
3
+
–
6
5
+
–
9
10
+
–
13
12
+
GND
1
V
OUT A
2
V
OUT B
3 14
V
OUT C
4 13
R
V
OUT D
5
REF
6
CS/LD
7
CLK
8
DAC A DAC H
DAC B DAC G
DAC C DAC F
DAC D DAC E
CONTROL
LOGIC
U1
LTC1660
SHIFT REGISTER
ADDRESS
DECODER
16
15
12
11
10
9
1665/60 TA01
13
Page 14
LTC1665/LTC1660
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
16
15
14
12 11 10
13
0.009
9
(0.229)
REF
0.015
± 0.004
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0.016 – 0.050
(0.406 – 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0° – 8° TYP
× 45°
0.229 – 0.244
(5.817 – 6.198)
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
12
0.150 – 0.157**
(3.810 – 3.988)
5
4
3
678
0.0250
(0.635)
BSC
0.004 – 0.0098
(0.102 – 0.249)
GN16 (SSOP) 1098
14
Page 15
PACKAGE DESCRIPTION
LTC1665/LTC1660
U
Dimensions in inches (millimeters) unless otherwise noted.
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
12
13
4
11
6
5
7
0.255 ± 0.015*
(6.477 ± 0.381)
14
15
16
2
1
3
910
8
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
–0.015
+0.889
8.255
()
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.125
(3.175)
MIN
0.100
(2.54)
BSC
0.045 – 0.065
(1.143 – 1.651)
0.065
(1.651)
TYP
0.018 ± 0.003
(0.457 ± 0.076)
N16 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
Page 16
LTC1665/LTC1660
TYPICAL APPLICATION
A Pin Driver VH and VL Adjustment Circuit for ATE Applications
U
5V
0.1µF
GND
REF
CC
1
CS/LD
SCK
CLR V
U1 LTC1660
DAC H
DAC G
DAC F
DAC E
7
D
9
IN
8
Note: DACs E Through H Can Be
Configured for a Second Pin Driver
With U2C and U2D of the LT1369
61611
DAC A
DAC B
DAC C
DAC D
2
3
4
5
CODE A
512
512
512
V
(FROM MAIN DAC)
R
G
50k
V
A
R
G
50k
V
B
V
(FROM MAIN DAC)
R
G
50k
V
C
R
G
50k
V
D
CODE B
1023
512
0
H
R
5k
L
R
5k
F
3
+
2
–
F
5
+
6
–
10V
U2A
LT1369
QUAD
–5V
U2B
LT1369
QUAD
, ∆V
∆V
H
–250mV
0
+250mV
0.1µF
0.1µF
R
5k
R
5k
′
V
′
= V
+ ∆V
V
H
H
L
0.1µF
+ ∆V
0.1µF
H
′
V
L
V
H
V
L
PIN DRIVER
LOGIC
DRIVE
(1 OF 2)
L
1
F
′
V
= V
L
7
F
1665/60 TA03
H
V
OUT
VA = VC = 2.5V
′
= V
V
H
′
= V
V
L
L
R
F
+
H
+
L
R
– VB)
(V
A
R
G
R
F
– VD)
(V
C
G
For Resistor Values Shown:
Adjustment Range = ±250mV
Adjustment Step Size = 500µV
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1661 Dual 10-Bit V
LTC1663 Single 10-Bit V
LTC1446/LTC1446L Dual 12-Bit V
LTC1448 Dual 12-Bit V
LTC1454/LTC1454L Dual 12-Bit V
LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, V
LTC1590 Dual 12-Bit I
LTC1659 Single Rail-to-Rail 12-Bit V
VCC: 2.7V to 5.5V GND to REF. REF Input Can Be Tied to V
LT1460 Micropower Precision Series Reference, 2.5V, 5V, 10V Versions 0.075% Max, 10ppm/°C Max, Only 130µA Supply Current
Linear Technology Corporation
16
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
DAC in 8-Lead MSOP Package VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output
OUT
DAC in SOT-23 Package VCC = 2.7V to 5.5V, Internal Reference, 60µA
OUT
DACs in SO-8 Package with Internal Reference LTC1446: VCC = 4.5V to 5.5V, V
OUT
LTC1446L: VCC = 2.7V to 5.5V, V
DAC in SO-8 Package VCC = 2.7V to 5.5V, External Reference Can Be Tied to V
OUT
DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, V
OUT
LTC1454L: V
LTC1458L: V
DAC in SO-16 Package VCC = 4.5V to 5.5V, 4-Quadrant Multiplication
OUT
DAC in 8-Lead MSOP Package Low Power Multiplying V
OUT
●
www.linear-tech.com
= 2.7V to 5.5V, V
CC
= 2.7V to 5.5V, V
CC
OUT
166560f LT/TP 0999 4K • PRINTED IN THE USA
LINEAR TECHNOLOGY CORPORATION 1999
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
DAC. Output Swings from
CC
CC
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