Datasheet LTC1664 Datasheet (Linear Technology)

Final Electrical Specifications

FEATURES

■

Tiny: 4 DACs in the Board Space of an SO-8

■

Micropower: 59µA per DAC Plus 1µA Sleep Mode for Extended Battery Life

■

Wide 2.7V to 5.5V Supply Range

■

Rail-to-Rail Voltage Outputs Drive 1000pF

■

Reference Range Includes Supply for Ratiometric 0V-to-VCC Output

■

Reference Input Has Constant Impedance over All Codes—Eliminates External Reference Buffer

■

Individually Addressable DACs

■

Differential Nonlinearity: ≤ ±0.75LSB Max

■

Pin-Compatible Octal Version Available (LTC1660)

U

APPLICATIO S

■

Mobile Communications

■

Remote Industrial Devices

■

Automatic Calibration for Manufacturing

■

Portable Battery-Powered Instruments

■

Trim/Adjust Applications

LTC1664

Micropower Quad

10-Bit DAC

January 2000

U

DESCRIPTIO

The LTC®1664 integrates four accurate, serially addressable 10-bit digital-to-analog converters (DACs) in a tiny 16-pin Narrow SSOP package. Each buffered DAC draws just 59µA total supply current, yet is capable of supplying DC output currents in excess of 5mA and reliably driving capacitive loads of up to 1000pF. Sleep mode further reduces total supply current to 1µA.

Linear Technology’s proprietary, inherently monotonic voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external form factor.

Ultralow supply current, power-saving Sleep mode and extremely compact size make the LTC1664 ideal for battery-powered applications, while its ease of use, high performance and wide supply range make it an excellent choice as a general purpose converter.

, LTC and LT are registered trademarks of Linear Technology Corporation.

BLOCK DIAGRA

1GND

2

V

OUT A

V

3 4

OUT B

REF

6

7

CS/LD

SCK

8

10-BIT DAC A

10-BIT DAC B

CONTROL

W

V

16

CC

10-BIT DAC D

10-BIT DAC C

ADDRESS

LOGIC

SHIFT REGISTER

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

DECODER

V

5

OUT D

V

OUT C

CLR

11

10

D

OUT

D

9

IN

1664 BD

LTC1664 Differential Nonlinearity (DNL)

1

0.8

0.6

0.4

0.2 0

LSB

–0.2 –0.4 –0.6 –0.8

–1

VCC = 5V

= 4.096V

V

REF

0 256 512 768 1023

CODE

1664 G08

1

LTC1664

WU

A

W

O

LUTEXI TIS

S

A

WUW

ARB

U G

PACKAGE

/

O

RDER I FOR ATIO

(Note 1)

VCC to GND.............................................. –0.2V to 7.5V

Logic Inputs to GND ................................ –0.2V to 7.5V

V

OUT A

, V

OUT B…VOUT D

,

REF to GND ................................. –0.2V to (VCC + 0.2V)

Maximum Junction Temperature......................... 125°C

Operating Temperature Range

LTC1664C ............................................. 0°C to 70°C

LTC1664I........................................... –40°C to 85°C

Storage Temperature Range................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................ 300°C

LECTRICAL C CHARA TERIST

E

ICS

GND

V

OUT A

V

OUT B

V

OUT C

V

OUT D

REF

CS/LD

SCK

GN PACKAGE

16-LEAD PLASTIC SSOP

T

JMAX

T

JMAX

Consult factory for Military grade parts.

TOP VIEW

1 2 3 4 5 6 7 8

= 125°C, θJA = 150°C/W (GN) = 125°C, θJA = 100°C/W (N)

V

16

NC

15

NC

14

NC

13

NC

12

CLR

11

D

10

D

9

N PACKAGE

16-LEAD PDIP

CC

OUT IN

ORDER PART

NUMBER

LTC1664CGN LTC1664CN LTC1664IGN LTC1664IN

GN PART MARKING

1664 1664I

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, V

SYMBOL PARAMETER CONDITONS MIN TYP MAX UNITS Accuracy

Resolution ● 10 Bits

Monotonicity 1V ≤ V DNL Differential Nonlinearity 1V ≤ V INL Integral Nonlinearity 1V ≤ V V

OS

FSE Full-Scale Error VCC = 5V, V

PSR Power Supply Rejection V

Reference Input

I

REF

Power Supply

V

CC

I

CC

Offset Error (Note 7) ● ±10 ±30 mV

VOS Temperature Coefficient ● ±15 µV/°C

Full-Scale Error Temperature Coefficient ● ±30 µV/°C

Input Voltage Range ● 0V

Resistance Not in Sleep Mode ● 70 130 kΩ

Capacitance (Note 6) 15 pF

Reference Current Sleep Mode ● 0.001 1 µA

Positive Supply Voltage For Specified Performance ● 2.7 5.5 V

Supply Current VCC = 5V (Note 3) ● 236 380 µA

≤ VCC, V

REF

unloaded, unless otherwise noted.

OUT

≤ VCC – 0.1V (Note 2, 4) ● 10 Bits

REF

≤ VCC – 0.1V (Note 2, 4) ● ±0.2 ±0.75 LSB

REF

≤ VCC – 0.1V (Note 2, 4) ● ±0.6 ±2.5 LSB

REF

= 4.096V (Note 4) ● ±3 ±15 LSB

REF

= 2.5V 0.18 LSB/V

REF

CC

VCC = 3V (Note 3) ● 186 290 µA Sleep Mode (Note 3)

● 13µA

U

V

2

LTC1664

LECTRICAL C CHARA TERIST

E

ICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Performance

Short-Circuit Current Low V

Short-Circuit Current High V

AC Performance

Voltage Output Slew Rate Rising (Notes 4, 5) 0.60 V/µs

Voltage Output Settling Time To ±0.5LSB (Notes 4, 5) 30 µs

Capacitive Load Driving 1000 pF

Digital I/O

V

IH

V

IL

V

OH

V

OL

I

LK

C

IN

Digital Input High Voltage VCC = 2.7V to 5.5V ● 2.4 V

Digital Input Low Voltage VCC = 4.5V to 5.5V ● 0.8 V

Digital Output High Voltage I

Digital Output Low Voltage I

Digital Input Leakage VIN = GND to V

Digital Input Capacitance (Note 6) ● 10 pF

≤ VCC, V

REF

= 0V, VCC = 5.5V, V

OUT

Code = Full Scale (Note 4)

= VCC = 5.5V, V

OUT

Falling (Notes 4, 5) 0.25 V/µs

= 2.7V to 3.6V ● 2.0 V

V

CC

= 2.7V to 5.5V ● 0.6 V

V

CC

= –1mA, D

OUT

= 1mA, D

OUT

unloaded, unless otherwise noted.

OUT

= 5.1V, ● 10 30 100 mA

REF

= 5.1V, Code = 0 (Note 4) ● 10 27 120 mA

REF

Only ● VCC – 1 V

OUT

Only ● 0.4 V

OUT

CC

● ±10 µA

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (See Figure 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC = 4.5V to 5.5V

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

VCC = 2.7V to 5.5V

t

1

t

2

t

3

t

4

t

5

DIN Valid to SCK Setup ● 40 15 ns

DIN Valid to SCK Hold ● 0 –11 ns

SCK High Time (Note 6) ● 30 5 ns

SCK Low Time (Note 6) ● 30 7 ns

CS/LD Pulse Width (Note 6) ● 80 30 ns

LSB SCK High to CS/LD High (Note 6) ● 30 4 ns

CS/LD Low to SCK High (Note 6) ● 80 26 ns

D

Propagation Delay C

OUT

SCK Low to CS/LD Low (Note 6) ● 20 0 ns

CLR Pulse Width (Note 6) ● 100 37 ns

CS/LD High to SCK Positive Edge (Note 6) ● 30 0 ns

SCK Frequency Continuous Square Wave (Note 6) ● 5.00 MHz

DIN Valid to SCK Setup (Note 6) ● 60 20 ns

DIN Valid to SCK Hold (Note 6) ● 0 –14 ns

SCK High Time (Note 6) ● 50 8 ns

SCK Low Time (Note 6) ● 50 12 ns

CS/LD Pulse Width (Note 6) ● 100 30 ns

The ● denotes specifications which apply over the full operating temperature

= 15pF (Note 6) ● 52680ns

LOAD

Continuous 23% Duty Cycle Pulse (Note 6) Gated Square Wave (Note 6) ● 16.7 MHz

● 7.69 MHz

3

LTC1664

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (See Figure 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t

6

t

7

t

8

t

9

t

10

t

11

LSB SCK High to CS/LD High (Note 6) ● 50 5 ns

CS/LD Low to SCK High (Note 6) ● 100 27 ns

D

Propagation Delay C

OUT

SCK Low to CS/LD Low (Note 6) ● 30 0 ns

CLR Pulse Width (Note 6) ● 120 41 ns

CS/LD High to SCK Positive Edge (Note 6) ● 30 0 ns

SCK Frequency Continuous Square Wave (Note 6) ● 3.85 MHz

The ● denotes specifications which apply over the full operating temperature

= 15pF (Note 6) ● 5 47 150 ns

LOAD

Continuous 28% Duty Cycle Pulse ● 5.55 MHz Gated Square Wave

● 10 MHz

Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired.

Note 2: Nonlinearity and monotonicity are defined from code 20 to code

1023. See Applications Information. Note 3: Digital inputs at 0V or V

CC

.

Note 5: V i.e., codes 102 and 922.

Note 6: Guaranteed by design and not subject to test. Note 7: Measured at code 20.

CC

= V

Note 4: Load is 10kΩ in parallel with 100pF.

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Differential Nonlinearity (DNL)Integral Nonlinearity (INL)

2.5 VCC = 5V

2.0

1.5

1.0

0.5

LSB

–0.5 –1.0 –1.5 –2.0 –2.5

= 4.096V

V

REF

0

0 256 512 768 1023

CODE

1664 G07

1

VCC = 5V

0.8

0.6

0.4

0.2

LSB

–0.2 –0.4 –0.6 –0.8

= 4.096V

V

REF

0

–1

0 256 512 768 1023

CODE

= 5V. DAC switched between 0.1VFS and 0.9VFS,

REF

Supply Current vs Temperature

250

1664 G08

240 230 220 210 200 190 180

SUPPLY CURRENT (µA)

170 160 150

–55 –35 –15 5 25 45 65 85 105 125

VCC = 5.5V VCC = 4.5V

VCC = 3.6V

VCC = 2.7V

TEMPERATURE (°C)

1664 G06

4

UW

I

OUT

(mA)

–2 –1 0 1 2

∆V

OUT

(LSB)

2

1.5 1

0.5 0

–0.5

–1

–1.5

–2

1664 G09

VCC = V

REF

= 5V

CODE = 512

SINKSOURCE

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1664

Midscale Output Voltage vs Load Current

3

V

= V

REF

CC

CODE = 512

2.9

2.8

2.7

2.6

(V)

2.5

OUT

V

2.4

2.3

2.2

2.1 2

–30 –20 –10 0 10 20 30

Minimum V

VCC = 5.5V

VCC = 5V

VCC = 4.5V

I

OUT

vs

OUT

SINKSOURCE

(mA)

Load Current (Output Sinking)

1400

VCC = 5V CODE = 0

1200

1000

800

(mV)

OUT

600

V

400

200

1664 G01

125°C

25°C

–55°C

Midscale Output Voltage vs Load Current

2

V

= V

REF

CC

CODE = 512

1.9

1.8

1.7

1.6

(V)

1.5

OUT

V

1.4

1.3

1.2

1.1 1

–15 –4–8–12 0 4 8 12 15

VCC = 3.6V

VCC = 3V

VCC = 2.7V

I

OUT

SINKSOURCE

(mA)

Large-Signal Step Response

(V)

OUT

V

5

4

3

2

1

VCC= V

= 5V

REF

10% TO 90% STEP

1664 G02

Minimum Supply Headroom vs Load Current (Output Sourcing)

1400

V

= 4.096V

REF

< 1LSB

∆V

OUT

1200

CODE = 1023

1000

(mV)

800

OUT

600

– V

CC

V

400

200

0

0246810

|

I

|

(mA) (Sourcing)

OUT

Load Regulation vs Output Current

125°C

25°C

–55°C

1664 G03

0

0246810

|

I

OUT

|

(mA) (Sinking)

1664 G04

0

0 20406080100

TIME (µs)

Load Regulation vs Output Current

VCC = V

2

CODE = 512

1.5 1

0.5

(LSB)

0

OUT

–0.5

∆V

–1

–1.5

–2

–500 0 500

REF

= 3V

SINKSOURCE

I

(µA)

OUT

1664 G05

1664 G10

5

LTC1664

UUU

PIN FUNCTIONS

GND (Pin 1): System Ground. V

to V

OUT A

The output range is

1023



0

to V





1024

REF (Pin 6): Reference Voltage Input. 0V ≤ V CS/LD (Pin 7): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on D into the register. When CS/LD is pulled high, SCK is disabled and data is loaded from the shift register into the specified DAC register(s), updating the analog output(s). CMOS and TTL compatible.

SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL compatible.

(Pins 2–5): DAC Analog Voltage Outputs.

OUT D

 

REF



REF

≤ VCC.

IN

DIN (Pin 9): Serial Interface Data Input. Data on the DIN pin is shifted into the 16-bit register on the rising edge of SCK. CMOS and TTL compatible.

D

(Pin 10): Serial Interface Data Output. Data appears

OUT

on D May be tied to DIN of another serial device for daisy-chain operaton. CMOS and TTL compatible.

CLR (Pin 11): Asynchronous Clear Input. All internal shift and DAC registers are cleared to zero at the falling edge of the CLR signal, forcing the analog outputs to zero scale. CMOS and TTL compatible.

NC (Pins 12–15): Make no electrical connection to these pins.

VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.

16 positive SCK edges after being applied to DIN.

OUT

6

BLOCK DIAGRA

LTC1664

W

UWW

TI I G DIAGRA

1GND

2

V

OUT A

V

3 4

OUT B

REF

6

7

CS/LD

SCK

8

10-BIT DAC A

10-BIT DAC B

CONTROL

LOGIC

SHIFT REGISTER

10-BIT DAC D

10-BIT DAC C

ADDRESS DECODER

V

16

CC

V

5

OUT D

V

OUT C

CLR

11

10

D

OUT

D

9

IN

1664 BD

SCK

D

CS/LD

D

OUT

t

1

t

2

t

9

IN

t

5

A3

A3 A2

t

7

A2 X1A1 X0

t

3

4

A1 X1

t

8

t

6

t

11

X0

A3

1664 F01

Figure 1

7

LTC1664

OPERATIO

U

Transfer Function

The transfer function is

V

OUT IDEAL REF()



=





1024



V





k

where k is the decimal equivalent of the binary DAC input code and V

is the voltage at REF (Pin 6).

REF

Power-On Reset

The LTC1664 clears the outputs to zero scale when power is first applied, making system initialization consistent and repeatable.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range –0.2V ≤ V

≤ VCC + 0.2V (see Absolute Maximum

REF

Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition.

Serial Interface

Referring to Figure 2: With CS/LD held low, data on the D

IN

input is shifted into the 16-bit shift register on the positive edge of

SCK

. The 4-bit DAC address, A3-A0, is loaded first (see Table 2), then the 10-bit input code, D9-D0, ordered MSB-to-LSB in each case. Two don’t-care bits, X1-X0, are loaded last. When the full 16-bit input word has been shifted in, CS/LD is pulled high, loading the DAC register with the word and causing the addressed DAC output(s) to update. The clock is disabled internally when CS/LD is high. Note:

SCK

must be low before CS/LD is pulled low.

The buffered serial output of the shift register is available on the D appears on D

pin, which swings from GND to VCC. Data

OUT

16 positive SCK edges after being applied

OUT

to DIN. Multiple LTC1664’s can be controlled from a single 3-wire

serial port (i.e., SCK, DIN and CS/LD) by using the included “daisy-chain” facility. A series of m chips is configured by connecting each D

(except the last) to DIN of the next

OUT

chip, forming a single 16m-bit shift register. The SCK and CS/LD signals are common to all chips in the chain. In use, CS/LD is held low while m 16-bit words are clocked to D

IN

of the first chip; CS/LD is then pulled high, updating all of them simultaneously.

Sleep Mode

DAC address 1110b is reserved for the special Sleep instruction (see Table 2). In this mode, the digital interface stays active while the analog circuits are disabled; static power consumption is thus virtually eliminated. The reference input and analog outputs are set in a high impedance state and all DAC settings are retained in memory so that when Sleep mode is exited, the outputs of DACs not updated by the Wake command are restored to their last active state.

Sleep mode is initiated by performing a load sequence to address 1110b (the DAC input word D9-D0 is ignored). Once in Sleep mode, a load sequence to any other address (including “No Change” addresses 0000b and 1001-1101b) causes the LTC1664 to Wake. It is possible to keep one or more chips of a daisy chain in continuous Sleep mode by giving the Sleep instruction to these chips each time the active chips in the chain are updated.

8

Table 1. LTC1664 Input Word

A3 A2 A1

Address/Control

A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 X1 X0D0

Input Code Don’t

Care

OPERATIO

LTC1664

U

SCK

D

CS/LD

D

OUT

16151413121110987654321

IN

(ENABLE SCK) (UPDATE OUTPUT)

A3 A2

ADDRESS/CONTROL

A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 A3

A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

INPUT CODE DON’T CARE

INPUT WORD W

0

–1

X1 X0

INPUT WORD W

Figure 2. LTC1664 Register Loading Sequence

Table 2. DAC Address/Control Functions

ADDRESS/CONTROL

A3 A2 A1 A0 DAC STATUS SLEEP STATUS

0000 No Change Wake 0001 Load DAC A Wake 0010 Load DAC B Wake 0011 Load DAC C Wake 0100Load DAC D Wake 0101 Reserved 0110 Reserved 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved

1110 No Change Sleep

1111Load ALL DACs Wake

with Same

10-Bit Code

0

1664 F02

9

LTC1664

OPERATIO

U

Voltage Outputs

Each of the four rail-to-rail output amplifiers contained in these parts can source or sink up to 5mA. The outputs swing to within a few millivolts of either supply rail when unloaded and have an equivalent output resistance of 85Ω when driving a load to the rails. The output amplifiers are stable driving capacitive loads up to 1000pF.

A small resistor placed in series with the output can be used to achieve stability for any load capacitance. A 1µF load can be successfully driven by inserting a 20Ω resistor; a 2.2µF load needs only a 10Ω resistor. In either case, larger values of resistance, capacitance or both may be safely substituted for the values given.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output DAC, the output is limited to voltages within the supply range.

If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 3b.

Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If V (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if V

is less than VCC – FSE.

REF

Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.

= VCC and the DAC full-scale error

REF

10

OPERATIO

LTC1664

U

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

V

= V

REF

CC

5120 1023

INPUT CODE

(a)

V

= V

REF

INPUT CODE

(c)

POSITIVE

CC

FSE

OUTPUT VOLTAGE

OFFSET

0V

INPUT CODE

(b)

NEGATIVE

Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V

REF

= V

1665/60 F03

CC

11

LTC1664

U

TYPICAL APPLICATIONS

A Low Power Dual Trim Circuit with Coarse/Fine Adjustment

3.3V 3.3V

V

OUT1

0.1µF

1

LTC1258-2.5

R1

U2A

®

LT

1490

4

3.3V

2

4

8

–

2

3

+

0.1µF

1

INTERFACE

R2

0.1µF

3-WIRE SERIAL

R1

COARSE

R2

FINE

GND

1

V

OUT A

2

V

OUT B

3 4

REF

6

CS/LD

7

SCK

8

U1

LTC1664

DAC A DAC D

DAC B DAC C

CONTROL

LOGIC

SHIFT REGISTER

ADDRESS DECODER

0.1µF

V

CC

16

V

OUT D

5

V

OUT C

CLR

11

D

OUT

10

D

IN

9

COARSE

FINE

TO OTHER LTC1664s

R2

R1

R2

6

5

0.1µF

–

LT1490

+

U2B

R1

7

V

OUT2

R2 >> R1 V

= V

OUT 1

Similarly V

OUT A

OUT 2

+

R1

)

R2

)

V

OUT B

Example: For R1 = 110Ω and R2 = 11k, V

OUT 1

= V

OUT A

+ 0.01 V

OUT B

1664 TA01

12

U

TYPICAL APPLICATIONS

A 4-Channel Bipolar Output Voltage Circuit Configuration

V

OUT A

±5V

R

0.1µF

+

V

S

4

′

1

LT1491

0.1µF

11

V

R R

S

U2A

–

R

V

GND

OUT A

1

2

–

2

3

+

U1

LTC1664

DAC A DAC D

LTC1664

5V

–

U2D

LT1491

+

RR

14

V

′

OUT D

±5V

RR

0.1µF

V

CC

16

V

OUT D

5

13

12

V

OUT B

±5V

–

6

7

′

U2B

LT1491

3-WIRE

SERIAL

INTERFACE

V

5

+

OUT B

3 4

REF

6

CS/LD

7

CLK

8

DAC B DAC C

CONTROL

LOGIC

SHIFT REGISTER

ADDRESS DECODER

V

OUT C

CLR

11

D

10

OUT

D

IN

9

1664 TA02

10

9

–

U2C

LT1491

+

CODE

512

1023

8

V

′

OUT C

±5V

V

OUT X

0

–5V

0V

+4.99V

13

LTC1664

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

GN Package

16-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.189 – 0.196* (4.801 – 4.978)

16

15

14

12 11 10

13

0.009

9

(0.229)

REF

0.015

± 0.004

(0.38 ± 0.10)

0.007 – 0.0098

(0.178 – 0.249)

0.016 – 0.050

(0.406 – 1.270)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0° – 8° TYP

× 45°

0.229 – 0.244

(5.817 – 6.198)

0.053 – 0.068

(1.351 – 1.727)

0.008 – 0.012

(0.203 – 0.305)

12

0.150 – 0.157** (3.810 – 3.988)

5

4

3

678

0.0250

(0.635)

BSC

0.004 – 0.0098 (0.102 – 0.249)

GN16 (SSOP) 1098

14

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

N Package

16-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

0.770*

(19.558)

MAX

12

13

4

11

6

5

7

0.255 ± 0.015* (6.477 ± 0.381)

14

15

16

2

1

3

LTC1664

910

8

0.300 – 0.325

(7.620 – 8.255)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015 +0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.130 ± 0.005

(3.302 ± 0.127)

0.020

(0.508)

MIN

0.125

(3.175)

MIN

0.100

(2.54)

BSC

0.045 – 0.065

(1.143 – 1.651)

0.065

(1.651)

TYP

0.018 ± 0.003

(0.457 ± 0.076)

N16 1098

15

LTC1664

TYPICAL APPLICATION

A Pin Driver VH and VL Adjustment Circuit for ATE Applications

U

5V

0.1µF

CS/LD

D

SCK

61611

CLR V

7 9

IN

8

CC

U1 LTC1664

DAC A

DAC B

DAC C

DAC D

GND

1

REF

2

3

4

5

CODE A

512 512 512

V

(FROM MAIN DAC)

R

G

50k

V

A

R

G

50k

V

B

V

(FROM MAIN DAC)

R

G

50k

V

C

R

G

50k

V

D

CODE B

1023

512

0

H

R 5k

L

R 5k

F

3

2

F

5

6

10V

8

+

U2A

LT1368

–

4 –5V

+

U2B

LT1368

–

, ∆V

∆V

H

–250mV

0

+250mV

0.1µF

R 5k

R

5k

′

V

′

+ ∆V

V

= V

H

+ ∆V

L

0.1µF

H

′

V

L

V

H

V

L

LOGIC DRIVE

DRIVER

L

1

F

′

= V

V

L

7

F

H

V

OUT

1664 TA03

VA = VC = 2.5V

′

V

= V

H

′

= V

V

L

R

F

+

H

R

+

L

R

– VB)

(V

A

R

G

F

– VD)

(V

C

G

For Resistor Values Shown: Adjustment Range = ±250mV Adjustment Step Size = 500µV

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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LTC1448 Dual 12-Bit V LTC1454/LTC1454L Dual 12-Bit V

LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, V

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LT1460 Micropower Precision Series Reference, 2.5V, 5V, 10V Versions 0.075% Max, 10ppm/°C Max, Only 130µA Supply Current

Linear Technology Corporation

16

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

DAC in 8-Lead MSOP Package VCC = 2.7V to 5.5V Micropower, Rail-to-Rail Output

OUT

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OUT

DACs in SO-8 Package with Internal Reference LTC1446: VCC = 4.5V to 5.5V, V

OUT

LTC1446L: V

DAC in SO-8 Package VCC = 2.7V to 5.5V, External Reference Can Be Tied to V

OUT

DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, V

OUT

LTC1454L: V

= 2.7V to 5.5V, V

CC

= 2.7V to 5.5V, V

CC

LTC1458L: VCC = 2.7V to 5.5V, V

DAC in SO-16 Package VCC = 4.5V to 5.5V, 4-Quadrant Multiplication

OUT

DAC in 8-Lead MSOP Package Low Power Multiplying V

OUT

●

www.linear-tech.com

OUT

1664i LT/TP 0100 4K • PRINTED IN THE USA

 LINEAR TECHNOLOGY CORPORATION 2000

= 0V to 4.095V

OUT

= 0V to 2.5V

OUT

= 0V to 4.095V

OUT

= 0V to 2.5V

OUT

= 0V to 4.095V

OUT

= 0V to 2.5V

OUT

DAC. Output Swings from

CC