Page 1
LTC1662
Final Electrical Specifications
Ultralow Power, Dual
10-Bit DAC in MSOP
FEATURES
■
Ultralow Power: 1.5µA (Typ) I
per DAC Plus
CC
0.05µA Sleep Mode for Extended Battery Life
■
Tiny: Two 10-Bit DACs in an 8-Lead MSOP—
Half the Size of an SO-8
■
Wide 2.7V to 5.5V Supply Range
■
Double Buffered for Simultaneous DAC Updates
■
Rail-to-Rail Voltage Outputs Drive 1000pF
■
Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
■
Reference Input Impedance Is Code-Independent
(7.1MΩ Typ)—Eliminates External Buffers
■
3-Wire Serial Interface with
Schmitt Trigger Inputs
■
Differential Nonlinearity: ±0.75LSB Max
U
APPLICATIO S
■
Mobile Communications
■
Portable Battery-Powered Instruments
■
Remote Industrial Devices
■
Digitally Controlled Amplifiers and Attenuators
■
Automatic Calibration for Manufacturing
U
March 2000
DESCRIPTIO
The LTC®1662 is an ultralow power, fully buffered voltage output, dual 10-bit digital-to-analog converter (DAC).
Each DAC draws just 1.7µA (typ) total supply-plus-
reference operating current, yet is capable of supplying
DC output currents in excess of 1mA and reliably driving
capacitive loads of up to 1000pF. A programmable Sleep
mode further reduces total operating current to a negligible 0.05µA.
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external
form factor. The double-buffered input logic provides
simultaneous update capability and can be used to write to
either DAC without interrupting Sleep mode.
With its ultralow operating current and exceptionally
small size, the LTC1662 is ideal for use in batterypowered products.
The LTC1662 is pin- and software-compatible with the
LTC1661 micropower dual 10-bit DAC. It is available in
8-pin MSOP and PDIP packages and is specified over the
industrial temperature range.
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
V
OUT A
8 5
10-BIT
DAC A
1
CS/LD
W
GND
7
LATCH
LATCH
CONTROL
LOGIC
SHIFT REGISTER
2
SCK
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
V
LATCH
ADDRESS
DECODER
D
CC
6
10-BIT
LATCH
3
IN
DAC B
V
OUT B
TOTAL OPERATING CURRENT (µA)
4
REF
1662 BD
Total Supply-Plus-Reference
Operating Current
5.5
V
= V
REF
CC
TA = 25°C
5.0
4.5
4.0
3.5
3.0
2.5
2.5 3.5 4.53.0 4.0 5.0 5.5
CODE = 1023
CODE = 512
CODE = 0
VCC (V)
1662 G01
1
Page 2
LTC1662
1
2
3
4
8
7
6
5
TOP VIEW
CS/LD
SCK
D
IN
REF
V
OUT A
GND
V
CC
V
OUT B
N8 PACKAGE
8-LEAD PLASTIC DIP
A
S
(Note 1)
W
O
LUTEXI TIS
A
WUW
U
ARB
G
VCC to GND .............................................. –0.3V to 7.5V
Logic Inputs to GND ................................ –0.3V to 7.5V
V
OUT A
, V
, REF to GND ......... –0.3V to (VCC + 0.3V)
OUT B
Maximum Junction Temperature ......................... 125°C
Storage Temperature Range ................ –65°C to 150°C
WU
/
PACKAGE
CS/LD
SCK
D
IN
REF
8-LEAD PLASTIC MSOP
T
JMAX
O
RDER I FOR ATIO
TOP VIEW
1
2
3
4
MS8 PACKAGE
= 125°C, θJA = 150°C/W
8
7
6
5
V
OUT A
GND
V
CC
V
OUT B
ORDER PART
NUMBER
LTC1662CMS8
LTC1662IMS8
MS8 PART MARKING
LTKB
LTKC
Operating Temperature Range
LTC1662C ............................................. 0°C to 70°C
LTC1662I........................................... –40°C to 85°C
Lead Temperature (Soldering, 10 sec)................ 300°C
U
ORDER PART
NUMBER
LTC1662CN8
LTC1662IN8
T
= 125°C, θJA = 100°C/W
JMAX
Consult factory for Military grade parts.
LECTRICAL C CHARA TERIST
E
temperature range (TA = T
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Accuracy
Resolution ● 10 Bits
Monotonicity (Note 2) ● 10 Bits
DNL Differential Nonlinearity (Note 2) ● ±0.12 ±0.75 LSB
INL Integral Nonlinearity (Note 2) ● ±0.8 ±4 LSB
V
OS
VOS TC VOS Temperature Coefficient ±15 µV/°C
GE Gain Error VCC = 5V, V
GE TC Gain Error Temperature ±12 µV/°C
PSR Power Supply Rejection V
Reference Input
2
Offset Error VCC = 5V, V
Coefficient
Input Voltage Range ● 0V
Input Resistance Active Mode ● 3.9 7.1 MΩ
Input Capacitance 10 pF
MIN
to T
), otherwise specifications are at T
MAX
= 2.5V 0.18 LSB/V
REF
Sleep Mode 2.5 GΩ
ICS
= 4.096V, Measured at Code 20 ● ±5 ±25 mV
REF
= 4.096V ● ±1 ±8 LSB
REF
The ● denotes the specifications which apply over the full operating
= 25°C. V
A
= 2.7V to 5.5V, V
CC
REF
≤ V
CC
, V
Unloaded
OUT
CC
V
Page 3
LTC1662
The ● denotes the specifications which apply over the full operating
LECTRICAL C CHARA TERIST
E
temperature range (TA = T
MIN
to T
), otherwise specifications are at T
MAX
ICS
The ● denotes the specifications which apply over the full operating
= 25°C. V
A
= 2.7V to 5.5V, V
CC
REF
≤ V
CC
, V
Unloaded
OUT
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
V
CC
I
CC
DC Performance
AC Performance
Digital I/O
V
IH
V
IL
I
LK
C
IN
Positive Supply Voltage For Specified Performance ● 2.7 5.5 V
Supply Current VCC = 3V (Note 3) 3.0 4.0 µA
= 5V (Note 3) 3.5 4.5 µA
V
CC
V
= 3V (Note 3) ● 5.0 µA
CC
= 5V (Note 3) ● 5.5 µA
V
CC
Sleep Mode Operating Current Supply Plus Reference Current, VCC = V
Short-Circuit Current Low V
Short-Circuit Current High V
Voltage Output Slew Rate Rising (Notes 4, 5) 20 V/ms
Voltage Output Settling Time 0.1VFS to 0.9VFS ±0.5LSB (Notes 4, 5) 0.40 ms
Capacitive Load Driving 1000 pF
Digital Input High Voltage VCC = 2.7V to 5.5V ● 2.4 V
Digital Input Low Voltage VCC = 4.5V to 5.5V ● 0.8 V
Digital Input Leakage VIN = GND to V
Digital Input Capacitance (Note 6) 1.5 pF
= 0V, VCC = V
OUT
= VCC = V
OUT
Falling (Notes 4, 5) 7 V/ms
to 0.1VFS ±0.5LSB (Notes 4, 5) 0.75 ms
0.9V
FS
= 2.7V to 3.6V ● 2.0 V
V
CC
VCC = 2.7V to 5.5V ● 0.6 V
= 5V, Code = 1023 (Note 7) ● 51270mA
REF
= 5V, Code = 0 (Note 7) ● 31080mA
REF
CC
= 5V, (Note 3) 0.05 0.10 µA
REF
● 0.18 µA
● ±0.05 ±1.0 µA
UW
TI I G CHARACTERISTICS
range, otherwise specifications are at T
= 25°C.
A
The ● denotes the specifications which apply over the full operating temperature
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 4.5V to 5.5V
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
9
t
11
VCC = 2.7V to 5.5V
t
1
t
2
t
3
t
4
DIN Valid to SCK Setup ● 55 15 ns
DIN Valid to SCK Hold ● 0–10 ns
SCK High Time (Note 6) ● 30 14 ns
SCK Low Time (Note 6) ● 30 14 ns
CS/LD Pulse Width (Note 6) ● 100 27 ns
LSB SCK High to CS/LD High (Note 6) ● 30 2 ns
CS/LD Low to SCK High (Note 6) ● 20 – 21 ns
SCK Low to CS/LD Low (Note 6) ● 0–5 ns
CS/LD High to SCK Positive Edge (Note 6) ● 20 0 ns
SCK Frequency Square Wave (Note 6) ● 16.7 MHz
DIN Valid to SCK Setup (Note 6) ● 75 20 ns
DIN Valid to SCK Hold (Note 6) ● 0–10 ns
SCK High Time (Note 6) ● 50 15 ns
SCK Low Time (Note 6) ● 50 15 ns
3
Page 4
LTC1662
UW
TI I G CHARACTERISTICS
range, otherwise specifications are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
5
t
6
t
7
t
9
t
11
CS/LD Pulse Width (Note 6) ● 150 30 ns
LSB SCK High to CS/LD High (Note 6) ● 50 3 ns
CS/LD Low to SCK High (Note 6) ● 30 – 14 ns
SCK Low to CS/LD Low (Note 6) ● 0–5 ns
CS/LD High to SCK Positive Edge (Note 6) ● 30 0 ns
SCK Frequency Square Wave (Note 6) ● 10 MHz
= 25°C.
A
The ● denotes the specifications which apply over the full operating temperature
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined and tested at V
V
= 4.096V, from code 20 to code 1023. See Figure 2.
REF
Note 3: Digital inputs at 0V or V
CC
.
CC
= 5V,
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: V
CC
codes k = 102 and k = 922.
Note 6: Guaranteed by design, not subject to test.
Note 7: One DAC output loaded.
UWW
TI I G DIAGRA
t
1
SCK
D
CS/LD
t
2
t
9
IN
t
5
A3 A2
t
7
t
t
3
4
A1 X1
UW
TYPICAL PERFOR A CE CHARACTERISTICS
= V
= 5V. DAC switched between 0.1VFS and 0.9VFS; i.e.,
REF
t
6
t
11
X0
1662 TD
4
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
4
3
2
1
0
–1
–2
INTEGRAL NONLINEARITY (LSB)
–3
–4
0 256 512 768 1023
CODE
1662 G02
0.75
0.60
0.40
0.20
0
–0.20
–0.40
–0.60
DIFFERENTIAL NONLINEARITY (LSB)
–0.80
0 256 512 768 1023
CODE
1662 G03
Page 5
OPERATIO
LTC1662
U
SCK
D
CS/LD
IN
A3 A2
(SCK ENABLED)
A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONTROL CODE
INPUT CODE DON’T CARE
INPUT WORD W
0
16151413121110987654321
X1 X0
(INSTRUCTION
EXECUTED)
Figure 1. Register Loading Sequence
Table 1. DAC Control Functions
CONTROL
A3 A2 A1 A0 STATUS STATUS (SLEEP/WAKE) COMMENTS
0000 No Change No Update No Change No Operation. Power-Down Status Unchanged
0001 Load DAC A No Update No Change Load Input Register A with Data. DAC Outputs
0010 Load DAC B No Update No Change Load Input Register B with Data. DAC Outputs
0011 Reserved
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 No Change Update Outputs Wake Load Both DAC Regs with Existing Contents of Input
1001 Load DAC A Update Outputs Wake Load Input Reg A. Load DAC Regs with New Contents
1010 Load DAC B Update Outputs Wake Load Input Reg B. Load DAC Regs with Existing Contents
1011 Reserved
1100 Reserved
1101 No Change No Update Wake Part Wakes Up. Input and DAC Regs Unchanged. DAC
1110 No Change No Update Sleep Part Goes to Sleep. Input and DAC Regs Unchanged. DAC
1111 Load DACs A, B Update Outputs Wake Load Both Input Regs. Load Both DAC Regs with New
INPUT REGISTER DAC REGISTER POWER-DOWN STATUS
(Part Stays In Wake or Sleep Mode)
Unchanged. Power-Down Status Unchanged
Unchanged. Power-Down Status Unchanged
Regs. Outputs Update. Part Wakes Up
of Input Reg A and Existing Contents of Reg B. Outputs
Update. Part Wakes Up
of Input Reg A and New Contents of Reg B. Outputs
Update. Part Wakes Up
Outputs Reflect Existing Contents of DAC Regs
Outputs Set to High Impedance State
with Same Contents of Input Regs. Outputs Update. Part Wakes Up
10-Bit Code
1662 F01
5
Page 6
LTC1662
UUU
PI FU CTIO S
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on D
into the register. When CS/LD is pulled high, SCK is
disabled and the operation(s) specified in the Control
code, A3-A0, is (are) performed. CMOS and TTL compatible.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
DIN (Pin 3): Serial Interface Data Input. Input word data on
the DIN pin is shifted into the 16-bit register on the rising
edge of SCK. CMOS and TTL compatible.
IN
UU
DEFI ITIO S
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆V
where ∆V
two adjacent codes.
Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Gain Error (GE): The deviation from the slope of the ideal
DAC transfer function, expressed in LSBs at full scale.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
than zero. The INL error at a given input code is
as follows:
OUT
– LSB)/LSB
OUT
is the measured voltage difference between
calculated
REF (Pin 4): Reference Voltage Input. 0V ≤ V
V
, V
OUT A
The output range is
0
≤≤
VV V
V
(Pin 6): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
CC
GND (Pin 7): System Ground.
INL = [V
where V
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = V
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
(Pins 8,5): DAC Analog Voltage Outputs.
OUT B
1023
,
OUTA OUTB REF
– VOS – (VFS – VOS)(code/1023)]/LSB
OUT
is the output voltage of the DAC measured at
OUT
/1024
REF
1024
REF
≤ VCC.
6
Page 7
OPERATIO
LTC1662
U
Transfer Function
The transfer function for the LTC1662 is:
V
OUT IDEAL REF()
where k is the decimal equivalent of the binary DAC input
code D9-D0 and V
Power-On Reset
The LTC1662 positively clears the outputs to zero scale
when power is first applied, making system initialization
consistent and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 4) should be kept within the range
–0.3V ≤ V
Ratings). Particular care should be taken during power
supply turn-on and turn-off sequences, when the voltage
at VCC (Pin 6) is in transition.
Serial Interface
See Table 1. The 16-bit Input word consists of the 4-bit
Control code, the 10-bit Input code and two don’t-care bits.
Table 1. LTC1662 Input Word
A3 A2 A1
Control Code
After the Input word is loaded into the register (see Figure␣ 1),
it is internally converted from serial to parallel format. The
parallel 10-bit-wide Input code data path is then buffered
by two latch registers.
The first of these, the Input Register, is used for loading new
input codes. The second buffer, the DAC Register, is used
for updating the DAC outputs. Each DAC has its own 10-bit
Input Register and 10-bit DAC Register.
By selecting the appropriate 4-bit Control code (see Table␣ 2)
it is possible to perform single operations, such as loading
one DAC or changing Power-Down status (Sleep/Wake).
=
≤ VCC + 0.3V (see Absolute Maximum
REF
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 X1 X0D0
k
V
1024
is the voltage at REF (Pin 6).
REF
Input Word
Input Code
Don’t
Care
In addition, some Control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part up.
The DACs can be loaded separately or together, but the
outputs are always updated together.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the DIN input
is shifted into the 16-bit Shift Register on the positive edge
of SCK. The 4-bit Control code, A3-A0, is loaded first, then
the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each
case. Two don’t-care bits, X1 and X0, are loaded last.
When the full 16-bit Input word has been shifted in, CS/LD
is pulled high, causing the system to respond according to
Table␣ 2. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Sleep Mode
DAC control code 1110b is reserved for the special Sleep
instruction (see Table 2). In this mode, the digital circuits
remain active while the analog sections are disabled; static
power consumption is greatly reduced. The reference
input and analog outputs are set in a high impedance state
and all DAC settings are retained in memory so that when
Sleep mode is exited, the outputs of DACs not updated by
the Wake command are restored to their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110b (the DAC input code D9-D0 is
ignored).
To save instruction cycles, the DACs may be prepared with
new input codes during Sleep (control codes 0001b and
0010b); then, a single command (1000b) can be used both
to wake the part and to update the output values.
Alternatively, one DAC may be loaded with a new input
code during Sleep; then with just one command, the other
DAC is loaded, the part is awakened and both outputs are
updated.
For example, control code 0001b is used to load DAC A
during Sleep. Then Control code 0101b loads DAC B,
wakes the part and simultaneously updates both DAC
outputs.
7
Page 8
LTC1662
OPERATIO
U
Voltage Outputs
Each of the rail-to-rail output amplifiers contained in the
LTC1662 can typically source or sink up to 1mA
(VCC␣ =␣ 5V). The outputs swing to within a few millivolts
of either supply when unloaded and have an equivalent
output resistance of 85Ω (typical) when driving a load to
the rails. The output amplifiers are stable driving capacitive loads up to 1000pF.
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If V
= VCC and the DAC full-scale error
REF
(FSE = VOS + GE) is positive, the output for the highest
codes limits at VCC as shown in Figure 2c. No full-scale
limiting can occur if V
is less than VCC – FSE.
REF
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
V
= V
REF
CC
POSITIVE
FSE
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
OUTPUT
VOLTAGE
INPUT CODE
(c)
V
= V
REF
CC
OUTPUT
VOLTAGE
5120 1023
INPUT CODE
(a)
0V
INPUT CODE
(b)
1662 F02
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
8
REF
= V
CC
Page 9
TYPICAL APPLICATIO
Using the LTC1258 and the LTC1662 In a Portable Application
Powered by a Single Li-Ion Battery. Total Supply Current Is 8.2µA
Li-ION BATTERY INPUT
U
V
≥ 4.3V
IN
2
LTC1258-4.1
4
0.1µF
1
4.096V
4
3
2
1
REF
D
IN
SCK
CS/LD
6
V
CC
LTC1662
GND
7
V
V
OUT A
OUT B
0.1µF
8
5
LTC1662
0V TO 4.096V
(4mV/BIT)
0V TO 4.096V
(4mV/BIT)
1662 F03
9
Page 10
LTC1662
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7
6
5
0.193 ± 0.006
(4.90 ± 0.15)
12
0.040
± 0.006
PLANE
(1.02 ± 0.15)
0.012
(0.30)
0.0256
REF
(0.65)
BSC
0.007
(0.18)
0.021
± 0.006
(0.53 ± 0.015)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
° – 6° TYP
0
SEATING
0.118 ± 0.004**
4
3
0.034 ± 0.004
(0.86 ± 0.102)
(3.00 ± 0.102)
0.006 ± 0.004
(0.15 ± 0.102)
MSOP (MS8) 1098
10
Page 11
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
876
0.255 ± 0.015*
(6.477 ± 0.381)
5
LTC1662
12
0.300 – 0.325
(7.620 – 8.255)
0.065
(1.651)
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
–0.015
+0.889
8.255
()
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.100
(2.54)
BSC
3
4
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.020
(0.508)
MIN
N8 1098
11
Page 12
LTC1662
TYPICAL APPLICATIO
Micropower Trim Circuit with Coarse/Fine Adjustment. Total Supply Current Is 9.5µA
3.3V
2
LTC1258-2.5
4
CS/LD
D
SCK
0.1µF
3.3V
1
2.5V
IN
REF
46V
DAC A
1
3
2
LTC1662
DAC B
U1
U
R2
1.1M
0.1µF
CC
R1
COARSE
11k
8
V
OUT A
5
V
OUT B
GND7
0.1µF
R2
FINE
1.1M
2
–
3
+
3.3V
8
LT1495
4
V
0.1µF
OUT
R1
11k
1
=
=
V
OUT
V
REF
()
2.5V +
()
CODE A
1024
CODE A
1024
+
R1
R2
1
100
CODE B
•
1024
CODE B
•
1024
1662 F04
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1661 Dual 10-Bit V
LTC1663 Single 10-Bit V
LTC1664 Quad 10-Bit V
LTC1665/LTC1660 Octal 8/10-Bit V
LTC1446/LTC1446L Dual 12-Bit V
LTC1448 Dual 12-Bit V
LTC1454/LTC1454L Dual 12-Bit V
LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, V
LTC1659 Single Rail-to-Rail 12-Bit V
V
: 2.7V to 5.5V GND to REF. REF Input Can Be Tied to V
CC
DAC in 8-Lead MSOP Package VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
OUT
DAC with 2-Wire Interface in SOT-23 Package VCC = 2.7V to 5.5V, Internal Reference, 60µA
OUT
DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
OUT
DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
OUT
DACs in SO-8 Package with Internal Reference LTC1446: VCC = 4.5V to 5.5V, V
OUT
DAC in SO-8 Package VCC = 2.7V to 5.5V, External Reference Can Be Tied to V
OUT
DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, V
OUT
DAC in 8-Lead MSOP Package Low Power Multiplying V
OUT
LTC1446L: V
LTC1454L: V
LTC1458L: V
= 2.7V to 5.5V, V
CC
= 2.7V to 5.5V, V
CC
= 2.7V to 5.5V, V
CC
OUT
DAC. Output Swings from
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
CC
CC
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
1662i LT/TP 0300 4K • PRINTED IN THE USA
LINEAR TECHNOLOGY CORPORATION 2000
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