Datasheet LTC1657L Datasheet (Linear Technology)

LTC1657L

CODE

0

–1.0

–0.2
–0.4
–0.6
–0.8

0

0.2

0.4

0.6

0.8

1.0

DNL ERROR (LSB)

16484 32768

1657 TA02

49152

65535

Final Electrical Specifications

Parallel 16-Bit Rail-to-Rail

Micropower DAC

FEATURES

■

16-Bit Monotonic Over Temperature

■

3V Single Supply Operation

■

Deglitched Rail-to-Rail Voltage Output: 8nV • s

■

ICC: 650µA Typ

■

Maximum DNL Error: ±1LSB

■

Settling Time: 20µs to ±1LSB

■

Internal or External Reference

■

Internal Power-On Reset to 0V

■

Asynchronous CLR Pin

■

Output Buffer Configurable for Gain of 1 or 2

■

Parallel 16-Bit or 2-Byte Double Buffered Interface

■

Narrow 28-Lead SSOP Package

■

5V Version Available (LTC1657)

U

APPLICATIONS

■

Instrumentation

■

Industrial Process Control

■

Automatic Test Equipment

■

Communication Test Equipment

U

April 2000

DESCRIPTION

The LTC®1657L is a complete single supply, rail-to-rail
voltage output, 16-bit digital-to-analog converter (DAC) in
a 28-pin SSOP or PDIP package. It includes a rail-to-rail
output buffer amplifier, an internal 1.25V reference and a
double buffered parallel digital interface.

The LTC1657L operates from a 2.7V to 5.5V supply. It has
a separate reference input pin that can be driven by an
external reference. The full-scale output can be 1 or 2
times the reference voltage depending on how the X1/X2
pin is connected.

The LTC1657L is similar to Linear Technology Corporation’s
LTC1450 12-bit V
grade path. It is the only buffered 16-bit parallel DAC in a
28-lead SSOP package and includes an onboard reference
for stand alone performance.

, LTC and LT are registered trademarks of Linear Technology Corporation.

DAC family allowing an easy up-

OUT

BLOCK DIAGRA

D15 (MSB)

19
18
17
16
15
14
13

FROM

12

11
10

28

27

9
8
7
6
5
4

3

1

2

D8
D7

D0 (LSB)
CSMSB

WR

CSLSB

LDAC

CLR

DATA IN FROM

MICROPROCESSOR

DATA BUS

MICROPROCESSOR

DECODE LOGIC

SYSTEM RESET

FROM

W

22 2423
REFHIREFOUT

REFERENCE

MSB

8-BIT

INPUT

REGISTER

16-BIT

DAC

REGISTER

LSB

8-BIT

INPUT

REGISTER

POWER-ON

RESET

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

1.25V

16-BIT

DAC

REFLOGND
2120 26

2.7V TO 5.5V

+

–

R

X1/X2

V

CC

V

OUT

25

0V TO

2.5V

R

1657 TA01

Differential Nonlinearity

vs Input Code

1

LTC1657L

WW

W

U

ABSOLUTE MAXIMUM RATINGS

(Note 1)

VCC to GND .............................................. –0.5V to 7.5V

TTL Input Voltage,

REFHI, REFLO, X1/X2 .......................... –0.5V to 7.5V

V

, REFOUT ............................ –0.5V to (VCC + 0.5V)

OUT

Operating Temperature Range

LTC1657LC ............................................. 0°C to 70°C

LTC1657LI......................................... – 40°C to 85°C

Maximum Junction Temperature ..........................125°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

U

W

PACKAGE/ORDER INFORMATION

TOP VIEW

1

WR

2

CSLSB

3

CSMSB

(LSB) D0

Consult factory for Military grade parts.

4
5

D1

6

D2

7

D3

8

D4

9

D5

10

D6

11

D7

12

D8

13

D9

14

D10

N PACKAGE

28-LEAD PDIP

T

= 125°C, θJA = 95°C/ W (G)

JMAX

T

= 125°C, θJA = 58°C/ W (N)

JMAX

28-LEAD PLASTIC SSOP

LDAC

28

CLR

27

X1/X2

26

V

25

OUT

V

24

CC

REFOUT

23

REFHI

22

REFLO

21

GND

20

D15 (MSB)

19

D14

18

D13

17

D12

16

D11

15

GN PACKAGE

ORDER PART

NUMBER

LTC1657LCGN
LTC1657LCN
LTC1657LIGN
LTC1657LIN

U

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, V

The ● denotes specifications which apply over the full operating

unloaded, REFOUT tied to REFHI,

OUT

REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DAC (Note 2)

Resolution ● 16 Bits
Monotonicity ● 16 Bits

DNL Differential Nonlinearity Guaranteed Monotonic (Note 3) ● ±0.5 ±1.0 LSB
INL Integral Nonlinearity (Note 3) ● ±4 ±12 LSB
ZSE Zero Scale Error ● 02mV
V

OS

VOSTC Offset Error Tempco ±5 µV/°C

Power Supply

V

CC

I

CC

Op Amp DC Performance

Offset Error Measured at Code 200 ● ±0.3 ±4mV

Gain Error ● ±2 ±16 LSB
Gain Error Drift 1 ppm/°C

Positive Supply Voltage For Specified Performance ● 2.7 5.5 V
Supply Current 2.7V ≤ VCC ≤ 5.5V (Note 4) ● 650 1200 µA

Short-Circuit Current Low V
Short-Circuit Current High V
Output Impedance to GND Input Code = 0 ● 120 275 Ω
Output Line Regulation Input Code = 65535, VCC = 2.7V to 5.5V ● 3 mV/V

Shorted to GND ● 60 120 mA

OUT

Shorted to V

OUT

CC

● 70 140 mA

2

LTC1657L

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, V

The ● denotes specifications which apply over the full operating

unloaded, REFOUT tied to REFHI,

OUT

REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AC Performance

Voltage Output Slew Rate (Note 5) ● ±0.3 ±0.7 V/µs
Voltage Output Settling Time (Note 5) to 0.0015% (16-Bit Settling Time) 20 µs

(Note 5) to 0.012% (13-Bit Settling Time) 10 µs

Digital Feedthrough 0.3 nV•s
Midscale Glitch Impulse DAC Switch Between 8000H and 7FFF
Output Voltage Noise At 1kHz 200 nV/√Hz

Spectral Density

Digital I/O (VCC = 3V)

V

IH

V

IL

I

LEAK

C

IN

Switching Characteristics (VCC = 3V)

t

CS

t

WR

t

CWS

t

CWH

t

DWS

t

DWH

t

LDAC

t

CLR

Reference Output (REFOUT)

Reference Input

Digital Input High Voltage ● 2.0 V
Digital Input Low Voltage ● 0.6 V
Digital Input Leakage VIN = GND to V
Digital Input Capacitance (Note 6) 10 pF

CS (MSB or LSB) Pulse Width ● 60 ns
WR Pulse Width ● 60 ns
CS to WR Setup ● 0ns
CS to WR Hold ● 0ns
Data Valid to WR Setup ● 60 ns
Data Valid to WR Hold ● 0ns
LDAC Pulse Width ● 60 ns
CLR Pulse Width ● 60 ns

Reference Output Voltage ● 1.24 1.25 1.26 V
Reference Output 15 ppm/°C

Temperature Coefficient
Reference Line Regulation VCC = 2.7V to 5.5V ● ±1 mV/V
Reference Load Regulation Measured at I
Short-Circuit Current REFOUT Shorted to GND ● 50 100 mA

REFHI, REFLO Input Range (Note 6) See Applications Information

REFHI Input Resistance ● 16 23 kΩ

CC

= 100µA ● 3 mV/A

OUT

X1/X2 Tied to V

X1/X2 Tied to GND

OUT

H

● ±10 µA

● 0V

● 0V

8 nV•s

– 1.5 V

CC

/2

CC

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: External reference REFHI = 1.3V, V
Note 3: Nonlinearity is defined from code 128 to code 65535 (full scale).

See Applications Information.

CC

= 3V

Note 4: Digital inputs at 0V or V
Note 5: DAC switched between all 1s all 0s, slew rate is measured from

0.8V to 2V. V
Note 6: Guaranteed by design. Not subject to test.

CC

=3V.

CC

.

3

LTC1657L

UUU

PIN FUNCTIONS

WR (Pin 1): Write Input (Active Low). Used with CSMSB
and/or CSLSB to control the input registers. While WR and
CSMSB and/or CSLSB are held low, data writes into the
input register.

CSLSB (Pin 2): Chip Select Least Significant Byte (Active
Low). Used with WR to control the LSB 8-bit input regis­ters. While WR and CSLSB are held low, the LSB byte
writes into the LSB input register. Can be connected to
CSMSB for simultaneous loading of both sets of input
latches on a 16-bit bus.

CSMSB (Pin 3): Chip Select Most Significant Byte (Active
Low). Used with WR to control the MSB 8-bit input
registers. While WR and CSMSB are held low, the MSB
byte writes into the MSB input register. Can be connected
to CSLSB for simultaneous loading of both sets of input
latches on a 16-bit bus.

D0 to D7 (Pins 4 to 11): Input data for the Least Significant
Byte. Written into LSB input register when WR = 0 and
CSLSB = 0.

D8 to D15 (Pins 12 to 19): Input data for the Most Signifi­cant Byte. Written into MSB input register when WR = 0
and CSMSB = 0.

GND (Pin 20): Ground.
REFLO (Pin 21): Lower input terminal of the DAC’s inter-

nal resistor ladder. Typically connected to Analog Ground.
An input code of (0000)H will connect the positive input of

the output buffer to this end of the ladder. Can be used to
offset the zero scale above ground.

REFHI (Pin 22): Upper input terminal of the DAC’s internal
resistor ladder. Typically connected to REFOUT. An input
code of (FFFF)H will connect the positive input of the
output buffer to 1LSB below this voltage.

REFOUT (Pin 23): Output of the internal 1.25V reference.
Typically connected to REFHI to drive internal DAC resistor
ladder.

VCC (Pin 24): Positive Power Supply Input. 2.7V ≤ VCC ≤

5.5V. Requires a 0.1µF bypass capacitor to ground.

V

(Pin 25): Buffered DAC Output.

OUT

X1/X2 (Pin 26): Gain Setting Resistor Pin. Connect to GND

for G = 2 or to V
tied to a low impedance source, such as ground or V
to ensure stability of the output buffer when driving
capacitive loads.

CLR (Pin 27): Clear Input (Asynchronous Active Low). A
low on this pin asynchronously resets all input and DAC
registers to 0s.

LDAC (Pin 28): Load DAC (Asynchronous Active Low).
Used to asynchronously transfer the contents of the input
registers to the DAC register which updates the output
voltage. If held low, the DAC register loads data from the
input registers which will immediately update V

for G = 1. This pin should always be

OUT

OUT

.

OUT

,

4

U

DIGITAL INTERFACE TRUTH TABLE

CLR CSMSB CSLSB WR LDAC FUNCTION

L X X X X Clears input and DAC registers to zero
H X X X L Loads DAC register with contents of input registers
H X X X H Freezes contents of DAC register
H L H L X Writes MSB byte into MSB input register
H H L L X Writes LSB byte into LSB input register
H L L L X Writes MSB and LSB bytes into MSB and LSB input registers
H X X H X Inhibits write to MSB and LSB input registers
H H X X X Inhibits write to MSB input register
H X H X X Inhibits write to LSB input register
H L L L L Data bus flows directly through input and DAC registers

WUW

TIMING DIAGRAM

t

CS

CSLSB

LTC1657L

t

CS

CSMSB

WR

LDAC

DATA

t

CWS

t

t

WR

t

CWH

t

DWH

DWS

DATA VALID DATA VALID

t

WR

t

LDAC

DAC UPDATE

1657 TD

5

LTC1657L

UU

DEFI ITIO S

Resolution (n): Resolution is defined as the number of
digital input bits (n). It defines the number of DAC output
states (2n) that divide the full-scale range. Resolution does
not imply linearity.

Full-Scale Voltage (VFS): This is the output of the DAC
when all bits are set to 1.

Voltage Offset Error (VOS): Normally, the DAC offset is the
voltage at the output when the DAC is loaded with all zeros.
The DAC can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below zero. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.

OUTPUT

VOLTAGE

NEGATIVE

0V

OFFSET

Figure 1. Effect of Negative Offset

DAC CODE

1657 F01

G = 1 for X1/X2 connected to V

OUT

G = 2 for X1/X2 connected to GND
CODE = Decimal equivalent of digital input

(0 ≤ CODE ≤ 65535)
Zero-Scale Error (ZSE): The output voltage when the

DAC is loaded with all zeros. Since this is a single supply
part, this value cannot be less than 0V.

Integral Nonlinearity (INL): End-point INL is the maxi­mum deviation from a straight line passing through the
end points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset
specification. The INL error at a given input code is
calculated as follows:

INL (In LSBs) = [V

– VOS – (VFS – VOS)

OUT

(code/65535)]
V

= The output voltage of the DAC measured at

OUT

the given input code

The offset of the part is measured at the code that corre­sponds to the maximum offset specification:

VOS = V

– [(Code)(VFS)/(2n – 1)]

OUT

Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.

LSB = (VFS – VOS)/(2n – 1) = (VFS – VOS)/65535

Nominal LSBs:

LTC1657L LSB = 2.5V/65535 = 38.1µV

DAC Transfer Characteristic:



VG

=

OUT

REFHI REFLO





–

65536



CODE REFLO

()





+•

Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal one LSB
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:

DNL = (∆V

∆V

= The measured voltage difference between

OUT

– LSB)/LSB

OUT

two adjacent codes

Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
nV • s.

6

U

OPERATION

LTC1657L

Parallel Interface

The data on the input of the DAC is written into the DAC’s
input registers when Chip Select (CSLSB and/or CSMSB)
and WR are at a logic low. The data that is written into the
input registers will depend on which of the Chip Selects
are at a logic low (see Digital Interface Truth Table). If WR
and CSLSB are both low and CSMSB is high, then only
data on the eight LSBs (D0 to D7) is written into the input
registers. Similarly, if WR and CSMSB are both low and
CSLSB is high, then only data on the eight MSBs (D8 to
D15) is written into the input registers. Data is written into
both the Least Significant Data Bits (D0 to D7) and the Most
Significant Bits (D8 to D15) at the same time if WR, CSLSB
and CSMSB are low. If WR is high or both CSMSB and
CSLSB are high, then no data is written into the input
registers.

Once data is written into the input registers, it can be
written into the DAC register. This will update the analog
voltage output of the DAC. The DAC register is written by
a logic low on LDAC. The data in the DAC register will be
held when LDAC is high.

used or the resistor ladder can be driven by an external
source in multiplying applications. The external reference
or source must be capable of driving the 16k (minimum)
DAC ladder resistance.

Internal reference output voltage noise spectral density
can be reduced with a bypass capacitor to ground. (Note:
The reference does not require a bypass capacitor to
ground for nominal operation.) When bypassing the refer­ence, a small value resistor in series with the capacitor is
recommended to help reduce peaking on the output. A
10Ω resistor in series with a 4.7µF capacitor is optimum
for reducing reference generated noise. Internal reference
output noise at 1kHz is typically 80nV/√Hz.

DAC Resistor Ladder

The high and low end of the DAC ladder resistor string
(REFHI and REFLO, respectively) are not connected inter­nally on this part. Typically, REFHI will be connected to
REFOUT and REFLO will be connected to GND. X1/X2
connected to GND will give the LTC1657L a full-scale
output swing of 2.5V.

When WR, CSLSB, CSMSB and LDAC are all low, the
registers are transparent and data on pins D0 to D15 flows
directly into the DAC register.

For an 8-bit data bus connection, tie the MSB byte data
pins to their corresponding LSB byte pins (D15 to D7, D14
to D6, etc).

Power-On Reset

The LTC1657L has an internal power-on reset that resets
all internal registers to 0’s on power-up (equivalent to the
CLR pin function).

Reference

The LTC1657L includes an internal 1.25V reference, giv­ing the LTC1657L a full-scale range of 2.5V in the gain-of­2 configuration. The onboard reference in the LTC1657L is
not internally connected to the DAC’s reference resistor
string but is provided on an adjacent pin for flexibility.
Because the internal reference is not internally connected
to the DAC resistor ladder, an external reference can be

Either of these pins can be driven up to VCC – 1.5V when
using the buffer in the gain-of-1 configuration. The resis­tor string pins can be driven to VCC/2 when the buffer is in
the gain of 2 configuration. The resistance between these
two pins is typically 30k (16k min).

Voltage Output

The output buffer for the LTC1657L can be configured for
two different gain settings. By tying the X1/X2 pin to GND,
the gain is set to 2. By tying the X1/X2 pin to V
is set to unity.

The LTC1657L rail-to-rail buffered output can source or
sink 5mA to within 500mV of the positive supply voltage
or ground at room temperature. The output stage is
equipped with a deglitcher that results in a midscale glitch
impulse of 8nV • s. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 40Ω when driving a load to
the rails.

, the gain

OUT

7

LTC1657L

U

WUU

APPLICATIONS INFORMATION

Rail-to-Rail Output Considerations

In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.

If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.

Similarly, limiting can occur near full scale when the REF
pin is tied to VCC/2. If V

= VCC/2 and the DAC full-scale

REF

error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 1c. No full-scale limiting
can occur if V

is less than (VCC – FSE)/2.

REF

Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.

POSITIVE
FSE

V

CC

V

INPUT CODE

(c)

REF

= VCC/2

OUTPUT
VOLTAGE

V

CC

= VCC/2

V

REF

327680 65535

INPUT CODE

(a)

1657 F02

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

OUTPUT

VOLTAGE

0V

INPUT CODE

(b)

Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V

= VCC/2

REF

8

TYPICAL APPLICATION

LTC1657L

U

This circuit shows how to measure negative offset. Since
LTC1657L operates on a single supply, if its offset is
negative, the output for code 0 limits at 0V. To measure

22 23

REFHI

X1/X2

REFOUT V

LTC1657L

REFLO

26

5:19

DATA 10:15

2

CSLSB

3

µP

CSMSB

1

WR

28

LDAC

27

CLR

this negative offset, a negative supply is needed. Connect
resister R1 as shown in the figure, the output voltage is the
offset when code 0 is loaded in.

3V

24

CC

V

OUT

GND

21

20

0.1µF

25

R1
100k

–3V

1657 TA03

9

LTC1657L

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

GN Package

28-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.015

± 0.004

(0.38 ± 0.10)

0.0075 – 0.0098
(0.191 – 0.249)

0.016 – 0.050

(0.406 – 1.270)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0° – 8° TYP

× 45°

0.229 – 0.244

(5.817 – 6.198)

0.053 – 0.069

(1.351 – 1.748)

0.008 – 0.012

(0.203 – 0.305)

12

3

0.386 – 0.393*
(9.804 – 9.982)

5

4

678 9 10 11 12

0.0250

(0.635)

BSC

0.033

202122232425262728

19

16

18

17

13 14

(0.838)

15

(0.102 – 0.249)

REF

0.150 – 0.157**
(3.810 – 3.988)

0.004 – 0.009

GN28 (SSOP) 1098

10

PACKAGE DESCRIPTION

0.255 ± 0.015*
(6.477 ± 0.381)

U

Dimensions in inches (millimeters) unless otherwise noted.

N Package

28-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

1.370*
(34.789)

MAX

26

27

28

23

2425

22

LTC1657L

171920

151618

2

1

0.300 – 0.325

(7.620 – 8.255)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015

+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.020

(0.508)

MIN

0.125

(3.175)

MIN

0.130 ± 0.005

(3.302 ± 0.127)

0.005

(0.127)

MIN

3456

0.045 – 0.065

(1.143 – 1.651)

0.100

(2.54)

BSC

7

9

8

10 11 122113 14

0.065

(1.651)

TYP

0.018 ± 0.003

(0.457 ± 0.076)

N28 1098

11

LTC1657L

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OUT

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with Internal Reference

= 0V to 4.095V (0V to 2.5V)

OUT

= 0V to 4.095V (0V to 2.5V)

OUT

= 0V to 4.095V (0V to 2.5V)

OUT

= 0V to 4.096V

OUT

OUT

= 0V to 4.096V (0V to 2.5V)

OUT

12

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

1657Li LT/TP 0400 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2000