Datasheet LTC1655L Datasheet (Linear Technology)

1

LTC1655L

16-Bit Rail-to-Rail

Micropower DAC in

SO-8 Package

August 1999

FEATURES

■

16-Bit Monotonicity Over Temperature

■

3V Single Supply Operation

■

Deglitched Rail-to-Rail Voltage Output

■

SO-8 Package

■

I

CC(TYP)

: 600µA

■

Internal 1.25V Reference or External
Reference Override

■

Maximum DNL Error: 1LSB

■

Power-On Reset

■

3-Wire Cascadable Serial Interface

■

Low Cost

■

Pin Compatible Upgrade to 12-Bit LTC1453

■

5V Version Available (LTC1655)

The LTC®1655L is a rail-to-rail voltage output, 16-bit
digital-to-analog converter (DAC) in an SO-8 package. It
includes an output buffer and a reference. The 3-wire serial
interface is compatible with SPI/QSPI and MICROWIRE

TM

protocols. The SCK input has a Schmitt trigger that allows
direct optocoupler interface.

The LTC1655L has an onboard 1.25V reference that can be
overdriven to a higher voltage. The output swings from 0V
to 2.5V when using the internal reference. The typical
power dissipation is 1.6mW on a single 3V supply.

The LTC1655L is pin compatible with Linear Technology’s
12-bit V

OUT

DAC family, allowing an easy upgrade path.
It is the only buffered 16-bit DAC in an SO-8 package and
it includes an onboard reference for stand alone
performance.

DESCRIPTION

U

■

Digital Calibration

■

Industrial Process Control

■

Automatic Test Equipment

■

Smart Remote Transmitters

APPLICATIONS

U

, LTC and LT are registered trademarks of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

–

+

16-BIT

DAC

2.7V TO 5.5V 1.25V

GND

R

R

POWER-ON

RESET

TO

OTHER

DACS

16-BIT

SHIFT

REG
AND
DAC

LATCH

µP

D

IN

V

CC

16

REF

2

86

D

OUT

4

5

1655 TA01

SCK1

CS/LD3

7

RAIL-TO-RAIL
VOLTAGE
OUTPUT
(0V TO 2.5V)

V

OUT

REF

A 16-Bit Rail-to-Rail V

OUT

DAC Differential Nonlinearity

vs Input Code

CODE

0

–1.0

–0.2
–0.4
–0.6
–0.8

0

0.2

0.4

0.6

0.8

1.0

DNL ERROR (LSB)

16384 32768

1655 TA02

49152

65535

Final Electrical Specifications

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

BLOCK DIAGRA

W

2

LTC1655L

ABSOLUTE MAXIMUM RATINGS

W

WW

U

ORDER PART

NUMBER

WU

U

PACKAGE

/

O

RDER I FOR ATIO

LTC1655LCN8
LTC1655LIN8
LTC1655LCS8
LTC1655LIS8

S8 PART MARKING

1655L
1655LI

Consult factory for Military grade parts.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DAC

Resolution ● 16 Bits
Monotonicity ● 16 Bits

DNL Differential Nonlinearity Guaranteed Monotonic (Note 2) ● ±0.3 ±1.0 LSB
INL Integral Nonlinearity REF = 1.3V (External) (Note 2) ● ±8 ±20 LSB
ZSE Zero-Scale Error ● 0 3.5 mV
V

OS

Offset Error Measured at Code 200 ● ±0.5 ±3.5 mV

VOSTC Offset Error Tempco ±5 µV/°C

Gain Error REF = 2.2V (External) ● ±5 ±16 LSB
Gain Error Drift 0.5 ppm/°C

Power Supply

V

CC

Positive Supply Voltage For Specified Performance ● 2.7 5.5 V

I

CC

Supply Current 2.7V ≤ VCC ≤ 5.5V (Note 4) ● 600 1200 µA

Op Amp DC Performance

Short-Circuit Current Low V

OUT

Shorted to GND ● 70 140 mA

Short-Circuit Current High V

OUT

Shorted to V

CC

● 80 150 mA

Output Impedance to GND Input Code = 0 ● 80 160 Ω
Output Line Regulation Input Code = 65535, VCC = 2.7V to 5.5V, ● ±3 mV/V

with Internal Reference

AC Performance

Voltage Output Slew Rate (Note 3) ● ±0.3 ±0.7 V/µs
Voltage Output Settling Time (Note 3) to 0.0015% (16-Bit Settling Time) 20 µs

(Note 3) to 0.012% (13-Bit Settling Time) 10 µs

Digital Feedthrough 0.3 nV •s
Midscale Glitch Impulse DAC Switched Between 8000 and 7FFF 12 nV•s

(Note 1)

VCC to GND .............................................. –0.5V to 7.5V

TTL Input Voltage .................................... –0.5V to 7.5V

V

OUT

, REF ....................................... –0.5V to V

CC

+ 0.5V

Maximum Junction Temperature ......................... 125°C

Operating Temperature Range

LTC1655LC ............................................ 0°C to 70°C

LTC1655LI......................................... –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

1

2

3

4

8

7

6

5

TOP VIEW

V

CC

V

OUT

REF
GND

SCK

D

IN

CS/LD

D

OUT

S8 PACKAGE

8-LEAD PLASTIC SO

N8 PACKAGE
8-LEAD PDIP

T

JMAX

= 125°C, θJA = 100°C/W (N8)

T

JMAX

= 125°C, θJA = 150°C/W (S8)

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.7V to 5.5V, V

OUT

unloaded, REF unloaded.

ELECTRICAL CHARACTERISTICS

3

LTC1655L

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital I/O

V

IH

Digital Input High Voltage VCC = 3V ● 2V

V

IL

Digital Input Low Voltage VCC = 3V ● 0.6 V

V

OH

Digital Output High Voltage I

OUT

= –1mA, D

OUT

Only, VCC = 3V ● VCC – 0.7 V

V

OL

Digital Output Low Voltage I

OUT

= 1mA, D

OUT

Only, VCC = 3V ● 0.4 V

I

LEAK

Digital Input Leakage VIN = GND to VCC, VCC = 3V ● ±10 µA

C

IN

Digital Input Capacitance (Note 6) 10 pF

Timing Characteristics

t

1

DIN Valid to SCK Setup VCC = 3V ● 60 ns

t

2

DIN Valid to SCK Hold VCC = 3V ● 0ns

t

3

SCK High Time VCC = 3V (Note 6) ● 60 ns

t

4

SCK Low Time VCC = 3V (Note 6) ● 60 ns

t

5

CS/LD Pulse Width VCC = 3V (Note 6) ● 80 ns

t

6

LSB SCK to CS/LD VCC = 3V (Note 6) ● 60 ns

t

7

CS/LD Low to SCK VCC = 3V (Note 6) ● 30 ns

t

8

D

OUT

Output Delay VCC = 3V, C

LOAD

= 100pF ● 20 300 ns

t

9

SCK Low to CS/LD Low VCC = 3V (Note 6) ● 30 ns

Reference Output

Reference Output Voltage ● 1.24 1.25 1.26 V
Reference Input Range (Notes 5, 6) 1.3 VCC/2 V
Reference Output Tempco 5 ppm/°C
Reference Input Resistance REF Overdriven to 1.3V ● 713 kΩ
Reference Short-Circuit Current ● 40 100 mA
Reference Output Line Regulation VCC = 2.7V to 5.5V ● ±1.5 mV/V
Reference Load Regulation I

OUT

= 100µA ● 0.5 mV

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: Nonlinearity is defined from code 128 to code 65535 (full scale).
See Applications Information.

Note 3: DAC switched between all 1s and code 400, slew rate is measured
from 0.75V to 1.75V.

Note 4: Digital inputs at 0V or V

CC

.

Note 5: Reference can be overdriven (see Applications Information).
Note 6: Guaranteed by design. Not subject to test.

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.7V to 5.5V, V

OUT

unloaded, REF unloaded.

4

LTC1655L

PIN FUNCTIONS

UUU

SCK (Pin 1): The TTL Level Input for the Serial Interface
Clock.

D

IN

(Pin 2): The TTL Level Input for the Serial Interface

Data. Data on the DIN pin is latched into the shift register
on the rising edge of the serial clock and is loaded MSB
first. The LTC1655L requires a 16-bit word.

CS/LD (Pin 3): The TTL Level Input for the Serial Inter­face Enable and Load Control. When CS/LD is low the
SCK signal is enabled, so the data can be clocked in.
When CS/LD is pulled high, data is loaded from the shift
register into the DAC register, updating the DAC output.

D

OUT

(Pin 4): Output of the Shift Register. Becomes valid

on the rising edge of the serial clock and swings from GND
to VCC.

GND (Pin 5): Ground.
REF (Pin 6): Reference. Output of the internal reference is

1.25V. There is a gain of two from this pin to the output.
The reference can be overdriven from 1.3V to VCC/2. When
tied to VCC/2, the output will swing from GND to VCC. The
output can only swing to within its offset specification of
VCC (see Applications Information).

V

OUT

(Pin 7): Deglitched Rail-to-Rail Voltage Output. V

OUT

clears to 0V on power-up.

V

CC

(Pin 8): Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V.

Requires a bypass capacitor to ground.

TI I G DIAGRA

WU W

D15

MSB

D14 D13 D1

t

1

t

6

D0

LSB

t

2

t

4

t

3

t

8

SCK

D

IN

D

OUT

CS/LD

t

5

1655 TD

D15

PREVIOUS WORD

D14

PREVIOUS WORD

D0

PREVIOUS WORD

D15

CURRENT WORD

D13

PREVIOUS WORD

t

9

t

7

12 3

15 16

5

LTC1655L

DEFI ITIO S

UU

Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:

DNL = (∆V

OUT

– LSB)/LSB

Where ∆V

OUT

is the measured voltage difference between

two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog

output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).

Full-Scale Error (FSE): The deviation of the actual full­scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).

Gain Error (GE): The difference between the full-scale
output of a DAC from its ideal full-scale value after offset
error has been adjusted.

Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the

lowest code that guarantees the output will be greater than
zero. The INL error at a given input code is

calculated as

follows:

INL = [V

OUT

– VOS – (VFS – VOS)(code/65535)]/LSB

Where V

OUT

is the output voltage of the DAC measured at

the given input code.
Least Significant Bit (LSB): The ideal voltage difference

between two successive codes.

LSB = 2V

REF

/65536

Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.

Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).

For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.

OPERATIO

U

Serial Interface

The data on the DIN input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first. The
DAC register loads the data from the shift register when
CS/LD is pulled high. The clock is disabled internally when
CS/LD is high. Note: SCK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse. The input
word must be 16 bits wide.

The buffered output of the 16-bit shift register is available
on the D

OUT

pin which swings from GND to VCC.

Multiple LTC1655Ls may be daisy-chained together by
connecting the D

OUT

pin to the DIN pin of the next chip
while the clock and CS/LD signals remain common to all
chips in the daisy chain. The serial data is clocked to all of

the chips, then the CS/LD signal is pulled high to update all
of them simultaneously. The shift register and DAC regis­ter are cleared to all 0s on power-up.

Voltage Output

The LTC1655L rail-to-rail buffered output can source or sink
5mA over the entire operating temperature range while
pulling to within 400mV of the positive supply voltage or
ground. The output stage is equipped with a deglitcher that
gives a midscale glitch impulse of 12nV•s. At power-up, the
output clears to 0V.

The output swings to within a few millivolts of either sup­ply rail when unloaded and has an equivalent output resis­tance of 40Ω when driving a load to the rails. The output
can drive 1000pF without going into oscillation.

6

LTC1655L

APPLICATIONS INFORMATION

WUU

U

Rail-to-Rail Output Considerations

In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.

If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.

Similarly, limiting can occur near full-scale when the REF
pin is tied to VCC/2. If V

REF

= VCC/2 and the DAC full-scale

error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 1c. No full-scale limiting
can occur if V

REF

is less than (VCC – FSE)/2.

Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.

Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full-Scale When V

REF

= VCC/2

1655 F01

INPUT CODE

(b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

0V

327680 65535

INPUT CODE

OUTPUT

VOLTAGE

(a)

V

REF

= VCC/2

V

CC

V

CC

V

REF

= VCC/2

(c)

INPUT CODE

OUTPUT
VOLTAGE

POSITIVE
FSE

7

LTC1655L

Dimensions in inches (millimeters) unless otherwise noted.

PACKAGE DESCRIPTION

U

N8 Package

8-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

N8 1098

0.100
(2.54)

BSC

0.065

(1.651)

TYP

0.045 – 0.065

(1.143 – 1.651)

0.130 ± 0.005

(3.302 ± 0.127)

0.020

(0.508)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

0.125

(3.175)

MIN

12

3

4

876

5

0.255 ± 0.015*
(6.477 ± 0.381)

0.400*
(10.160)

MAX

0.009 – 0.015

(0.229 – 0.381)

0.300 – 0.325

(7.620 – 8.255)

0.325

+0.035
–0.015

+0.889
–0.381

8.255

()

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.016 – 0.050

(0.406 – 1.270)

0.010 – 0.020

(0.254 – 0.508)

× 45°

0°– 8° TYP

0.008 – 0.010

(0.203 – 0.254)

SO8 1298

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

TYP

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

1

2

3

4

0.150 – 0.157**
(3.810 – 3.988)

8

7

6

5

0.189 – 0.197*
(4.801 – 5.004)

0.228 – 0.244

(5.791 – 6.197)

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

*

**

8

LTC1655L

 LINEAR TECHNOLOGY CORPORATION 1999

1655li LT/TP 0899 4K • PRINTED IN USA

Linear T echnolog y Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

PART NUMBER DESCRIPTION COMMENTS

LTC1257 Single 12-Bit V

OUT

DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, 5V to 15V Single Supply, Complete V

OUT

DAC in

Reference Can Be Overdriven Up to 12V, i.e., FS

MAX

= 12V SO-8 Package

LTC1446/ Dual 12-Bit V

OUT

DACs in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, V

OUT

= 0V to 4.095V

LTC1446L LTC1446L: V

CC

= 2.7V to 5.5V, V

OUT

= 0V to 2.5V

LTC1448 Dual 12-Bit V

OUT

DAC, VCC: 2.7V to 5.5V Output Swings from GND to REF. REF Input Can Be Tied to V

CC

LTC1450/ Single 12-Bit V

OUT

DACs with Parallel Interface LTC1450: VCC = 4.5V to 5.5V, V

OUT

= 0V to 4.095V

LTC1450L LTC1450L: V

CC

= 2.7V to 5.5V, V

OUT

= 0V to 2.5V

LTC1451 Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, 5V, Low Power Complete V

OUT

DAC in SO-8 Package

Internal 2.048V Reference Brought Out to Pin

LTC1452 Single Rail-to-Rail 12-Bit V

OUT

Multiplying DAC, VCC: 2.7V to 5.5V Low Power, Multiplying V

OUT

DAC with Rail-to-Rail

Buffer Amplifier in SO-8 Package

LTC1453 Single Rail-to-Rail 12-Bit V

OUT

DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V 3V, Low Power, Complete V

OUT

DAC in SO-8 Package

LTC1454/ Dual 12-Bit V

OUT

DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, V

OUT

= 0V to 4.095V

LTC1454L LTC1454L: V

CC

= 2.7V to 5.5V, V

OUT

= 0V to 2.5V

LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Low Power, Complete V

OUT

DAC in SO-8

Full Scale: 4.095V, V

CC

: 4.5V to 5.5V Package with Clear Pin

LTC1458/ Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, V

OUT

= 0V to 4.095V

LTC1458L LTC1458L: V

CC

= 2.7V to 5.5V, V

OUT

= 0V to 2.5V

LTC1650 Single 16-Bit V

OUT

Industrial DAC in 16-Pin SO, VCC = ±5V Low Power, Deglitched, 4-Quadrant Mulitplying V

OUT

DAC, Output Swing ±4.5V

LTC1655 Single Rail-to-Rail 16-Bit V

OUT

DAC in SO-8 Package VCC = 4.5V to 5.5V, V

OUT

= 0V to 4.096V, Internal 2048V

Reference, Deglitched V

OUT

LTC1658 Single Rail-to-Rail 14-Bit V

OUT

DAC in 8-Pin MSOP, Low Power, Multiplying V

OUT

DAC in MS8 Package. Output

V

CC

= 2.7V to 5.5V Swings from GND to REF. REF Input Can Be Tied to V

CC

LTC1659 Single Rail-to-Rail 12-Bit V

OUT

DAC in 8-Pin MSOP, Low Power, Multiplying V

OUT

DAC in MS8 Package. Output

V

CC

= 2.7V to 5.5V Swings from GND to REF. REF Input Can Be Tied to V

CC

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