Page 1
CODE
0
–1.0
–0.2
–0.4
–0.6
–0.8
0
0.2
0.4
0.6
0.8
1.0
DNL ERROR (LSB)
16384 32768
1655 TA02
49152
65535
FEATURES
■
16-Bit Monotonicity Over Temperature
■
Deglitched Rail-to-Rail Voltage Output
■
SO-8 Package
■
5V Single Supply Operation
■
I
CC(TYP)
■
Internal Reference
■
Maximum DNL Error: 1LSB
■
Power-On Reset
■
3-Wire Cascadable Serial Interface
■
Low Cost
: 600µA
LTC1655
16-Bit Rail-to-Rail
Micropower DAC in
SO-8 Package
U
DESCRIPTIO
The LTC®1655 is a rail-to-rail voltage output, 16-bit digital-to-analog converter (DAC) in an SO-8 package. It
includes an output buffer and a reference. The 3-wire serial
interface is compatible with SPI/QSPI and MICROWIRE
protocols. The CLK input has a Schmitt trigger that allows
direct optocoupler interface.
The LTC1655 has an onboard 2.048V reference that can be
overdriven to a higher voltage. The output swings from 0V
to 4.096V when using the internal reference. The typical
power dissipation is 3.0mW on a single 5V supply.
TM
APPLICATIO S
■
■
■
■
TYPICAL APPLICATIO
µP
TO
OTHER
DACS
U
Digital Calibration
Industrial Process Control
Automatic Test Equipment
Cellular Telephones
Functional Block Diagram: 16-Bit Rail-to-Rail DAC
4.5V TO 5.5V 2.048V
86
V
CC
2
D
IN
CLK1
16-BIT
SHIFT
OUT
REG
AND
DAC
LATCH
POWER-ON
RESET
CS/LD3
D
4
REF
16
16-BIT
DAC
GND
U
REF
5
The LTC1655 is pin compatible with Linear Technology’s
12-bit V
DAC family, allowing an easy upgrade path.
OUT
It is the only buffered 16-bit DAC in an SO-8 package and
it includes an onboard reference for stand alone
performance.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
Differential Nonlinearity
vs Input Code
+
V
OUT
–
RAIL-TO-RAIL
7
VOLTAGE
OUTPUT
(0V TO 4.096V)
1655 TA01
1
Page 2
LTC1655
1
2
3
4
8
7
6
5
TOP VIEW
V
CC
V
OUT
REF
GND
CLK
D
IN
CS/LD
D
OUT
S8 PACKAGE
8-LEAD PLASTIC SO
N8 PACKAGE
8-LEAD PDIP
WW
W
U
ABSOLUTE MAXIMUM RATINGS
PACKAGE
/
O
RDER I FOR ATIO
WU
U
(Note 1)
VCC to GND.............................................. –0.5V to 7.5V
TTL Input Voltage .................................... –0.5V to 7.5V
V
, REF ....................................... –0.5V to V
OUT
+ 0.5V
CC
Maximum Junction Temperature......................... 125°C
Operating Temperature Range
LTC1655C .............................................. 0°C to 70°C
ORDER PART
NUMBER
LTC1655CN8
LTC1655IN8
LTC1655CS8
LTC1655IS8
LTC1655I........................................... –40°C to 85°C
Storage Temperature Range................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
T
= 125°C, θJA = 100°C/W (N8)
JMAX
T
= 125°C, θJA = 150°C/W (S8)
JMAX
S8 PART MARKING
1655
1655I
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VCC = 4.5V to 5.5V, V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DAC
Resolution ● 16 Bits
Monotonicity ● 16 Bits
DNL Differential Nonlinearity Guaranteed Monotonic (Note 2) ● ±0.3 ±1.0 LSB
INL Integral Nonlinearity REF = 2.2V (External) (Note 2) ● ±8 ±20 LSB
ZSE Zero Scale Error ● 03mV
V
OS
V
OS
Power Supply
V
CC
I
CC
Op Amp DC Performance
AC Performance
Offset Error Measured at Code 200, REF = 2.2V (External) ● ±0.5 ±3mV
TC Offset Error Tempco ±5 µV/°C
Gain Error REF = 2.2V (External) ● ±5 ±16 LSB
Gain Error Drift 0.5 ppm/°C
Positive Supply Voltage For Specified Performance ● 4.5 5.5 V
Supply Current 4.5V ≤ VCC ≤ 5.5V (Note 4) ● 600 1200 µA
Short-Circuit Current Low V
Short-Circuit Current High V
Output Impedance to GND Input Code = 0 ● 40 120 Ω
Output Line Regulation Input Code = 65535, VCC = 4.5V to 5.5V, ● ±3 mV/V
Voltage Output Slew Rate (Note 3) ● ±0.3 ±0.7 V/µs
Voltage Output Settling Time (Note 3) to 0.0015% (16-Bit Settling Time) 20 µs
Digital Feedthrough 0.3 nV-s
Midscale Glitch Impulse DAC Switch Between 8000 and 7FFF 12 nV-s
unloaded, REF unloaded, TA = T
OUT
Shorted to GND ● 70 120 mA
OUT
Shorted to V
OUT
with Internal Reference
(Note 3) to 0.012% (13-Bit Settling Time) 10 µs
CC
MIN
to T
, unless otherwise noted.
MAX
● 80 140 mA
2
Page 3
LTC1655
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VCC = 4.5V to 5.5V, V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital I/O
V
IH
V
IL
V
OH
V
OL
I
LEAK
C
IN
Switching
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Reference Output
Digital Input High Voltage ● 2.4 V
Digital Input Low Voltage ● 0.8 V
Digital Output High Voltage I
Digital Output Low Voltage I
Digital Input Leakage VIN = GND to V
Digital Input Capacitance (Note 6) 10 pF
DIN Valid to CLK Setup VCC = 5V ● 40 ns
DIN Valid to CLK Hold VCC = 5V ● 0ns
CLK High Time VCC = 5V (Note 6) ● 40 ns
CLK Low Time VCC = 5V (Note 6) ● 40 ns
CS/LD Pulse Width VCC = 5V (Note 6) ● 50 ns
LSB CLK to CS/LD VCC = 5V (Note 6) ● 40 ns
CS/LD Low to CLK VCC = 5V (Note 6) ● 20 ns
D
Output Delay VCC = 5V, C
OUT
CLK Low to CS/LD Low VCC = 5V (Note 6) ● 20 ns
Reference Output Voltage ● 2.036 2.048 2.060 V
Reference Input Range (Notes 5, 6) 2.2 VCC/2 V
Reference Output Tempco 5 ppm/°C
Reference Input Resistance REF Overdriven to 2.2V ● 8.5 13 kΩ
Reference Short-Circuit Current ● 40 100 mA
Reference Output Line Regulation VCC = 4.5V to 5.5V ● ±1.5 mV/V
Reference Load Regulation I
unloaded, REF unloaded, TA = T
OUT
= –1mA, D
OUT
= 1mA, D
OUT
= 100µA ● 0.5 mV
OUT
to T
MIN
Only ● VCC – 1 V
OUT
Only ● 0.4 V
OUT
CC
= 15pF ● 0 120 ns
LOAD
, unless otherwise noted.
MAX
● ±10 µA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity is defined from code 128 to code 65535 (full scale).
See Applications Information.
Note 3: DAC switched between all 1s and code 400.
Note 4: Digital inputs at 0V or V
CC
.
Note 5: Reference can be overdriven (see Applications Information).
Note 6: Guaranteed by design. Not subject to test.
3
Page 4
LTC1655
LOAD CURRENT (mA)
0
V
CC
– V
OUT
(V)
1.2
1.0
0.8
0.6
0.4
0.2
0
1655 F03
5
10
15
125°C
25°C
–55°C
∆V
OUT
< 1LSB
V
OUT
= 4.096V
CODE: ALL 1’s
UW
TYPICAL PERFORMAN CE CHAR ACTERISTICS
Differential Nonlinearity
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
DIFFERENTIAL NONLINEARITY (LSB)
–0.8
–1.0
16,384
0
32,768
DIGITAL INPUT CODE
49,152
65,535
1655 G01
Integral Nonlinearity
5
4
3
2
1
0
–1
–2
–3
INTEGRAL NONLINEARITY (LSB)
–4
–5
16,384
0
32,768
DIGITAL INPUT CODE
49,152
Minimum Supply Headroom for
Full Output Swing vs Load Current
65,535
1655 G02
Minimum Output Voltage vs
Output Sink Current
1.0
CODE: ALL 0’s
0.8
0.6
0.4
0.2
OUTPUT PULL-DOWN VOLTAGE (V)
0
0
OUTPUT SINK CURRENT (mA)
125°C
25°C
5
–55°C
10
Supply Current vs
Logic Input Voltage
3.4
3.0
2.6
2.2
1.8
1.4
SUPPLY CURRENT (mA)
1.0
0.6
0.2
0
1
LOGIC INPUT VOLTAGE (V)
2
1655 F04
Full-Scale Voltage vs
Temperature
4.10
4.09
4.08
FULL-SCALE VOLTAGE (V)
4.07
15
–55
53565
–25
TEMPERATURE (°C)
95 125
1655 G05
Offset vs Temperature
1.0
0.8
0.6
0.4
0.2
0
–0.2
OFFSET (mV)
–0.4
–0.6
–0.8
–1.0
–55
–10
TEMPERATURE (°C)
35
80
125
1655 G06
Supply Current vs Temperature
700
680
660
640
620
SUPPLY CURRENT (µA)
600
3
4
5
1655 G07
580
–35 5
–55
–15
VCC = 5.5V
VCC = 5V
VCC = 4.5V
45 125
65
25
TEMPERATURE (°C)
85
105
1655 G08
4
Page 5
UUU
PIN FUNCTIONS
LTC1655
CLK (Pin 1): The TTL Level Input for the Serial Interface
Clock.
D
(Pin 2): The TTL Level Input for the Serial Interface
IN
Data. Data on the DIN pin is latched into the shift register
on the rising edge of the serial clock and is loaded MSB
first. The LTC1655 requires a 16-bit word.
CS/LD (Pin 3): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low the
CLK signal is enabled, so the data can be clocked in.
When CS/LD is pulled high, data is loaded from the shift
register into the DAC register, updating the DAC output.
D
(Pin 4): Output of the Shift Register. Becomes valid
OUT
on the rising edge of the serial clock and swings from GND
to VCC.
WU W
TI I G DIAGRA
GND (Pin 5): Ground.
REF (Pin 6): Reference. Output of the internal reference is
2.048V. There is a gain of two from this pin to the output.
The reference can be overdriven from 2.2V to VCC/2. When
tied to VCC/2, the output will swing from GND to VCC. The
output can only swing to within its offset specification of
VCC (see Applications Information).
V
(Pin 7): Deglitched Rail-to-Rail Voltage Output. V
OUT
OUT
clears to 0V on power-up.
V
(Pin 8): Positive Supply Input. 4.5V ≤ VCC ≤ 5.5V.
CC
Requires a bypass capacitor to ground.
CLK
D
CS/LD
D
OUT
t
9
t
7
12 3
D15
D15
MSB
t
8
PREVIOUS WORD
IN
PREVIOUS WORD
t
1
t
2
D14 D13 D1
D14
D13
PREVIOUS WORD
t
t
3
4
15 16
D0
LSB
D0
PREVIOUS WORD
t
6
CURRENT WORD
D15
t
5
1655 TD
5
Page 6
LTC1655
UU
DEFI ITIO S
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆V
Where ∆V
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Gain Error (GE): The difference between the full-scale
output of a DAC from its ideal full-scale value after offset
error has been adjusted.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
OUT
– LSB)/LSB
OUT
is the measured voltage difference between
lowest code that guarantees the output will be greater than
zero. The INL error at a given input code is
follows:
INL = [V
Where V
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = 2V
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
– VOS – (VFS – VOS)(code/65535)]/LSB
OUT
is the output voltage of the DAC measured at
OUT
/65536
REF
calculated as
U
OPERATIO
Serial Interface
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first. The
DAC register loads the data from the shift register when
CS/LD is pulled high. The clock is disabled internally when
CS/LD is high. Note: CLK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse. The input
word must be 16 bits wide.
The buffered output of the 16-bit shift register is available
on the D
Multiple LTC1655s may be daisy-chained together by
connecting the D
while the clock and CS/LD signals remain common to all
chips in the daisy chain. The serial data is clocked to all of
pin which swings from GND to VCC.
OUT
pin to the DIN pin of the next chip
OUT
the chips, then the CS/LD signal is pulled high to update all
of them simultaneously. The shift register and DAC register are cleared to all 0s on power-up.
Voltage Output
The LTC1655 rail-to-rail buffered output can source or sink
5mA over the entire operating temperature range while
pulling to within 400mV of the positive supply voltage or
ground. The output stage is equipped with a deglitcher that
gives a midscale glitch of 12nV-s. At power-up, output stage
clears to 0V.
The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 40Ω when driving a load to the rails. The output
can drive 1000pF without going into oscillation.
6
Page 7
LTC1655
U
WUU
APPLICATIONS IN FORMA TION
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC/2. If V
= VCC/2 and the DAC full-scale
REF
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 1c. No full-scale limiting
can occur if V
is less than (VCC – FSE)/2.
REF
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
POSITIVE
FSE
V
CC
V
REF
= VCC/2
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
INPUT CODE
(c)
V
CC
V
OUTPUT
VOLTAGE
0V
INPUT CODE
(b)
REF
= VCC/2
327680 65535
INPUT CODE
(a)
1655 F01
Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
= VCC/2
REF
7
Page 8
LTC1655
U
TYPICAL APPLICATIONS
This circuit shows how to use an LTC1655 to make an
optoisolated digitally controlled 4mA to 20mA process
controller. The controller circuitry, including the
optoisolation, is powered by the loop voltage that can have
a wide range of 6V to 30V. The 2.048V reference output of
the LTC1655 is used for the 4mA offset current and V
An Isolated 4mA to 20mA Process Controller
®
1121-5
LT
OUTIN
1µF
FROM
OPTOISOLATED
INPUTS
CLK
D
IN
CS/LD
V
CC
LTC1655
OUT
V
REF
V
OUT
is used for the digitally controlled 0mA to 16mA current.
RS is a sense resistor and the op amp modulates the
transistor Q1 to provide the 4mA to 20mA current through
this resistor. The potentiometers allow for offset and fullscale adjustment. The control circuitry dissipates well
under the 4mA budget at zero scale.
V
LOOP
6V TO 30V
150k
1%
20k
75k
1%
5k
+
3k
LT®1077
–
1k
Q1
2N3440
CLK
D
CS/LD
IN
OPTOISOLATORS
500Ω
4N28
R
5V
10k
CLK
D
IN
CS/LD
S
10Ω
1655 TA03
I
OUT
8
Page 9
U
TYPICAL APPLICATIONS
LTC1655
This circuit shows how to make a bipolar output 16-bit
DAC with a wide output swing using an LTC1655 and an
LT1077. R1 and R2 resistively divide down the LTC1655
output and an offset is summed in using the LTC1655
onboard 2.048V reference and R3 and R4. R5 ensures that
A Wide Swing, Bipolar Output 16-Bit DAC
5V
0.1µF
V
IN
LTC1655
GND V
D
IN
CC
V
OUT
REF
R3
100k
1%
R5
100k
1%
4.096
V
OUT
–4.096
0
µP
TRANSFER CURVE
32768
CLK
D
CS/LD
65535
the onboard reference is always sourcing current and
never has to sink any current even when V
is at full
OUT
scale. The LT1077 output will have a wide bipolar output
swing of –4.096V to 4.096V as shown in the figure below.
With this output swing 1LSB = 125µV.
R1
100k
1%
R2
200k
1%
+
LT1077
–
5V
–5V
R4
200k
1%
V
OUT
1655 TA05
(2)(DIN)(4.096)
:
65536
– 4.096V
9
Page 10
LTC1655
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
876
0.255 ± 0.015*
(6.477 ± 0.381)
5
12
0.300 – 0.325
(7.620 – 8.255)
0.065
(1.651)
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
–0.015
+0.889
8.255
()
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
TYP
(2.540 ± 0.254)
0.045 – 0.065
(1.143 – 1.651)
0.100 ± 0.010
3
4
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.020
(0.508)
MIN
N8 1197
10
Page 11
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
8
5
6
LTC1655
0.228 – 0.244
(5.791 – 6.197)
0.010 – 0.020
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
× 45°
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
0.150 – 0.157**
(3.810 – 3.988)
1
3
2
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
TYP
SO8 0996
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
Page 12
LTC1655
TYPICAL APPLICATION
U
This circuit shows a digitally programmable current source
from an external voltage source using an external op amp,
an LT1077 and an NPN transistor (2N3440). Any digital
word from 0 to 65535 is loaded into the LTC1655 and its
output correspondingly swings from 0V to 4.096V. In the
configuration shown, R1, R2 resistively divide down the
LTC1655 output voltage. This divided voltage will be
Digitally Programmable Current Source
5V
V
CLK
µP
D
CS/LD
CC
LTC1655
IN
GND
V
OUT
RELATED PARTS
forced across the resistor RA. If RA is chosen to be 205Ω,
the output current will range from 0mA at zero scale to
10mA at full scale. The minimum voltage for VS is determined by the load resistor RL and Q1’s V
CESAT
voltage.
With a load resistor of 50Ω, the voltage source can be as
low as 3.3V.
V
+ 3.3V TO 100V
S
≤ 50Ω
FOR R
0.1µF
R1
100k
1%
R2
100k
1%
+
LT1077
–
L
R
Q1
2N3440
R
205Ω
1%
)(4.096)
(D
IN
I
L
A
= •
OUT
(65536)(R
≈ 0mA TO 10mA
1655 TA04
1
)
2
A
PART NUMBER DESCRIPTION COMMENTS
LTC1257 Single 12-Bit V
Reference Can Be Overdriven Up to 12V, i.e., FS
LTC1446/ Dual 12-Bit V
LTC1446L LTC1446L: V
LTC1448 Dual 12-Bit V
LTC1450/ Single 12-Bit V
LTC1450L LTC1450L: V
LTC1451 Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, 5V, Low Power Complete V
DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, 5V to 15V Single Supply, Complete V
OUT
DACs in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, V
OUT
DAC, VCC: 2.7V to 5.5V Output Swings from GND to REF. REF Input Can Be Tied to V
OUT
DACs with Parallel Interface LTC1450: VCC = 4.5V to 5.5V, V
OUT
= 12V SO-8 Package
MAX
= 2.7V to 5.5V, V
CC
= 2.7V to 5.5V, V
CC
DAC in SO-8 Package
OUT
Internal 2.048V Reference Brought Out to Pin
LTC1452 Single Rail-to-Rail 12-Bit V
Multiplying DAC, VCC: 2.7V to 5.5V Low Power, Multiplying V
OUT
DAC with Rail-to-Rail
OUT
Buffer Amplifier in SO-8 Package
LTC1453 Single Rail-to-Rail 12-Bit V
LTC1454/ Dual 12-Bit V
DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, V
OUT
DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V 3V, Low Power, Complete V
OUT
DAC in SO-8 Package
OUT
LTC1454L LTC1454L: VCC = 2.7V to 5.5V, V
LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Low Power, Complete V
Full Scale: 4.095V, V
: 4.5V to 5.5V Package with Clear Pin
CC
DAC in SO-8
OUT
LTC1458/ Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, V
LTC1458L LTC1458L: V
LTC1650 Single 16-Bit V
Industrial DAC in 16-Pin SO, VCC = ±5V Low Power, Deglitched, 4-Quadrant Mulitplying V
OUT
= 2.7V to 5.5V, V
CC
DAC, Output Swing ±4.5V
LTC1658 Single Rail-to-Rail 14-Bit V
= 2.7V to 5.5V Swings from GND to REF. REF Input Can Be Tied to V
V
CC
LTC1659 Single Rail-to-Rail 12-Bit V
= 2.7V to 5.5V Swings from GND to REF. REF Input Can Be Tied to V
V
CC
DAC in 8-Pin MSOP, Low Power, Multiplying V
OUT
DAC in 8-Pin MSOP, Low Power, Multiplying V
OUT
DAC in MS8 Package. Output
OUT
DAC in MS8 Package. Output
OUT
DAC in
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
CC
OUT
CC
CC
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
1655f LT/TP 0399 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1998
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