Page 1
LTC1654
Final Electrical Specifications
Dual 14-Bit Rail-to-Rail DAC
in 16-Lead SSOP Package
FEATURES
■
14-Bit Monotonic Over Temperature
■
Individually Programmable Speed/Power:
3.5µs Settling Time at 750µA
8µs Settling Time at 450µA
■
Maximum Update Rate: 0.9MHz
■
Smallest Dual 14-Bit DAC: 16-Lead Narrow
SSOP Package
■
Buffered True Rail-to-Rail Voltage Outputs
■
3V to 5V Single Supply Operation
■
User Selectable Gain
■
Power-On Reset and Clear Function
■
Schmitt Trigger On Clock Input Allows Direct
Optocoupler Interface
U
APPLICATIO S
■
Digital Calibration
■
Industrial Process Control
■
Automatic Test Equipment
■
Offset/Gain Adjustment
U
April 2000
DESCRIPTIO
The LTC®1654 is a dual, rail-to-rail voltage output, 14-bit
digital-to-analog converter (DAC). It is available in a
16-lead narrow SSOP package, making it the smallest dual
14-bit DAC available. It includes output buffer amplifiers
and a flexible serial interface.
The LTC1654 has REFHI pins for each DAC that can be
driven up to VCC. The output will swing from 0V to VCC in
gain of 1 configuration or VCC/2 in gain of 1/2 configuration. It operates from a single 2.7V to 5.5V supply.
The LTC1654 has two programmable speeds: a FAST and
SLOW mode with ±1LSB settling times of 3.5µs or 8µs
respectively and supply currents of 750µA and 450µA in
the two modes. The LTC1654 also has shutdown capability, power-on reset and clear function to 0V.
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
CS/LD
SCK
SDI
SDO
CLR
CONTROL
LOGIC
32-BIT
SHIFT
REGISTER
W
INPUT
LATCH
INPUT
LATCH
POWER-ON
RESET
DAC
REGISTER
DAC
REGISTER
DAC B
DAC A
REFHI B
+
V
OUT B
–
X1/X
B
1/2
REFHI A
+
V
OUT A
–
A
X
1/X1/2
REFLO AREFLO B
1654 BD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1
Page 2
LTC1654
WWWU
ABSOLUTE AXI U RATI GS
(Note 1)
VCC to GND .............................................. –0.5V to 7.5V
TTL Input Voltage, REFHI,
REFLO, X1/X
V
, SDO .................................. –0.5V to (VCC + 0.5V)
OUT
Operating Temperature Range
LTC1654C ............................................. 0°C to 70°C
LTC1654I ........................................ –40°C to 85°C
Maximum Junction Temperature ..........................125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ELECTRICAL CHARACTERISTICS
ture range, otherwise specifications are at TA = 25°C, VCC = 2.7V to 5.5V, V
(VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X
........................................ –0.5V to 7.5V
1/2
The ● denotes specifications which apply over the full operating tempera-
PACKAGE/ORDER I FOR ATIO
X
1/X1/2
X
1/X1/2
Consult factory for Military grade parts.
= 0V.
1/2
TOP VIEW
1
B
2
CLR
3
SCK
4
SDI
5
CS/LD
6
DGND
7
SDO
8
A
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
T
= 125°C, θJA = 95°C/W
JMAX
OUT A
, V
unloaded, REFHI A, REFHI B = 4.096V
OUT B
16
15
14
13
12
11
10
9
UU
W
ORDER PART
NUMBER
V
CC
V
OUT B
REFHI B
REFLO B
AGND
REFLO A
REFHI A
V
OUT A
LTC1654CGN
LTC1654IGN
GN PART MARKING
1654
1654I
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DAC
Resolution ● 14 Bits
Monotonicity ● 14 Bits
DNL Differential Nonlinearity Guaranteed Monotonic (Note 2) ● ±1 LSB
INL Integral Nonlinearity Integral Nonlinearity (Note 2) ● ±4 LSB
ZSE Zero Scale Error C Grade ● 0 6.5 mV
V
OS
VOSTC Offset Error Tempco ±15 µV/°C
Power Supply
V
CC
I
CC
Op Amp DC Performance
Offset Error Measured at Code 50, C Grade ● ±6.5 mV
Gain Error ● ±15 LSB
Gain Error Drift 5 ppm/°C
Positive Supply Voltage For Specified Performance ● 2.7 5.5 V
Supply Current (SLOW/FAST) 2.7V ≤ VCC ≤ 5.5V (Note 5) SLOW ● 450 800 µA
Short-Circuit Current Low V
Short-Circuit Current High V
Output Impedance to GND Input Code = 0 ● 40 200 Ω
Output Line Regulation Input Code = 16383, VCC = 2.7V to 5.5V, ● 2.25 mV/V
I Grade
Measured at Code 50, I Grade ● ±9.0 mV
2.7V ≤ VCC ≤ 5.5V (Note 5) FAST ● 750 1300 µA
2.7V ≤ V
2.7V ≤ V
In Shutdown (Note 5) ● 730 µA
OUT
OUT
V
REF
≤ 3.3V (Note 5) SLOW ● 250 500 µA
CC
≤ 3.3V (Note 5) FAST ● 450 900 µA
CC
Shorted to GND ● 70 120 mA
Shorted to V
= 2.048V
CC
● 9.0 mV
● 80 120 mA
2
Page 3
LTC1654
ELECTRICAL CHARACTERISTICS
ture range, otherwise specifications are at TA = 25°C, VCC = 2.7V to 5.5V, V
(VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X
The ● denotes specifications which apply over the full operating tempera-
1/2
OUT A
= 0V.
, V
unloaded, REFHI A, REFHI B = 4.096V
OUT B
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AC Performance
Voltage Output Slew Rate (Note 3) SLOW ● 0.20 V/µs
(Note 3) FAST
● 1.25 V/µs
Voltage Output Settling Time (Note 4) to ±1LSB, SLOW 8.0 µs
(Note 4) to ±1LSB, FAST 3.5 µs
Digital Feedthrough (Note 8) 1 nV•s
Midscale Glitch Impulse DAC Switch Between 8000 and 7FFF 20 nV•s
Output Noise Voltage Density at 1kHz, SLOW 540 nV/√Hz
at 1kHz, FAST 320 nV/√Hz
Digital I/O
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
OH
V
OL
I
LEAK
C
IN
Digital Input High Voltage VCC = 5V ● 2.4 V
Digital Input Low Voltage VCC = 5V ● 0.8 V
Digital Output High Voltage VCC = 5V, I
Digital Output Low Voltage VCC = 5V, I
= –1mA, D
OUT
= 1mA, D
OUT
Only ● VCC – 0.75 V
OUT
Only ● 0.4 V
OUT
Digital Input High Voltage VCC = 3V ● 2.4 V
Digital Input Low Voltage VCC = 3V ● 0.8 V
Digital Output High Voltage VCC = 3V, I
Digital Output Low Voltage VCC = 3V, I
Digital Input Leakage VIN = GND to V
= –1mA, D
OUT
= 1mA, D
OUT
CC
Only ● VCC – 0.75 V
OUT
Only ● 0.4 V
OUT
● ±10 µA
Digital Input Capacitance (Note 6) 10 pF
Reference Input
Reference Input Resistance REFHI to REFLO ● 30 60 kΩ
Reference Input Range (Notes 6, 7) ● 0VCCV
Reference Input Current In Shutdown ● 1 µA
Switching Characteristics (VCC = 4.5V to 5.5V)
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
SDI Valid to SCK Setup ● 30 ns
SDI Valid to SCK Hold (Note 6) ● 0ns
SCK High Time (Note 6) ● 15 ns
SCK Low Time (Note 6) ● 15 ns
CS/LD Pulse Width (Note 6) ● 15 ns
LSB SCK to CS/LD (Note 6) ● 10 ns
CS/LD Low to SCK (Note 6) ● 10 ns
SD0 Output Delay C
= 100pF ● 5 100 ns
LOAD
SCK Low to CS/LD Low (Note 6) ● 10 ns
Switching Characteristics (VCC = 2.7V to 5.5V)
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
SDI Valid to SCK Setup ● 45 ns
SDI Valid to SCK Hold (Note 6) ● 0ns
SCK High Time (Note 6) ● 20 ns
SCK Low Time (Note 6) ● 20 ns
CS/LD Pulse Width (Note 6) ● 20 ns
LSB SCK to CS/LD (Note 6) ● 15 ns
CS/LD Low to SCK (Note 6) ● 15 ns
SDO Output Delay C
= 100pF ● 5 150 ns
LOAD
SCK Low to CS/LD Low (Note 6) ● 15 ns
3
Page 4
LTC1654
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity is defined from code 50 to code 16383 (full scale).
See Applications Information.
Note 3: 100pF Load Capacitor
Note 4: DAC switched between code 200 and code 16383.
U
UU
PI FU CTIO S
X1/X
1/2 Pin. When this pin is tied to V
up to REFHI/2 and when this pin is tied to REFLO, the
output will swing up to REFHI. These pins should not be
left floating.
CLR (Pin 2): The Asynchronous Clear Input.
SCK (Pin 3): The TTL Level Input for the Serial Interface
Clock.
SDI (Pin 4): The TTL Level Input for the Serial Interface
Data. Data on the SDI pin is latched into the shift register
on the rising edge of the serial clock. The LTC1654 requires a 24-bit word. The first 8 bits are control/address
followed by 16 data bits. The last two of the 16 data bits are
don’t cares. If daisy-chaining is desired, then a 32-bit data
word can be used with the first 8 being don’t cares and the
following 24 bits as above.
CS/LD (Pin 5): The TTL Level Input for the Serial Interface
Enable and Load Control. When CS/LD is low, the SCK
B, X1/X
1/2
A (Pins 1, 8): The Gain of 1 or Gain of
1/2
, the output will swing
OUT
Note 5: Digital inputs at 0V or VCC.
Note 6: Guaranteed by design.
Note 7: V
when output is unloaded. See Applications Information.
Note 8: CS/LD = 0, V
can only swing from (GND +VOS) to (VCC –VOS)
OUT
= 4.096 and data is being clocked in.
OUT
signal is enabled, so the data can be clocked in. When
CS/LD is pulled high, the control/address bits are
decoded.
DGND/AGND (Pins 6, 12): Digital and Analog Grounds.
SDO (Pin 7): The output of the shift register that becomes
valid on the rising edge of the serial clock.
V
OUT A/B
(Pins 9, 15): The Buffered DAC Outputs.
REFHI A/B (Pins 10, 14): The Reference High Inputs of the
LTC1654. There is a gain of 1 from this pin to the output
in a gain of 1 configuration. In a gain of 1/2 configuration,
there is a gain of 1/2 from this pin to V
OUT
.
REFLO A/B (Pins 11, 13): The Reference Low Inputs of the
LTC1654.
VCC (Pin 16): The Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V.
Requires a 0.1µF bypass capacitor to ground.
UW
W
TI I G DIAGRA S
SCK
SDI
CS/LD
SDO
4
t
2
t
1
XX
(PREVIOUS
WORD)
t
4
XXXX
t
8
B0C3
C3 X X
t
t
3
6
t
7
t
9
t
5
CURRENT WORD
X
1654 TD01
Page 5
LTC1654
UW
W
TI I G DIAGRA S
1654 TD02
WORD
CURRENT
X
X
30 31 322322
B0
B1
B2
B3
26 27 28 29
242322212019181716151413121110987654
X
X
B0
B2 B1
B4
B5
24 25
B6
B7
B8
2120191817
B10 B9
30 31 322322
26 27 28 29
24 25
2120191817
X
X
B0
B1
B2
B3
B4
B5
B6
B7
B8
B10 B9
XX
B0 X
B1
B2
B3
B4
B5
B6
B7
B8
B10 B9
321
B5 B4 B3
B7 B6
B12 B11 B10 B9 B8
B13
A0
A1
A3 A2
C0
C3 C2 C1
B11
B12
B13
1615
A1 A0
141312
C0 A3 A2
1110
C1
C2
9
C3
8
X
7654
X
X
X
X
32
X
X
1
X
B12 B11
B12 B11
B13
B13
1615
A1 A0
141312
C0 A3 A2
1110
C1
9
C3 C2
8
X
7654
X
X
X
X
32
X
X
1
X
PREVIOUS WORD
A1 A0
C0 A3 A2
C1
C2
C3
X
X
X
X
X
X
XX
CS/LD
24-Bit Update (Without Daisy-Chain)
CS/LD
32-Bit Update (Without Daisy-Chain)
SDI
SCK
SCK
SDI
SDI
SCK
CS/LD
32-Bit Update (Can Daisy-Chain)
SDO
5
Page 6
LTC1654
OPERATIO
U
Serial Interface
The data on the SDI input is loaded into the shift register
on the rising edge of SCK. The MSB is loaded first. The
Clock is disabled internally when CS/LD is high. Note:
SCK must be low before CS/LD is pulled low to avoid an
extra internal clock pulse.
If no daisy-chaining is required, the input word can be
24-bit wide, as shown in the timing diagrams. The 8 MSBs,
which are loaded first, are the control and address bits
followed by a 16-bit data word. The last two LSBs in the
data word are don’t cares. The input word can be a stream
of three 8-bit wide segments as shown in the “24-Bit
Update” timing diagram.
If daisy-chaining is required or if the input needs to be
written in two 16-bit wide segments, then the input word
can be 32 bits wide and the top 8 bits (MSBs) are don’t
cares. The remaining 24 bits are control/address and
data. This is also shown in the timing diagrams. The
buffered output of the internal 32-bit shift register is
available on the SDO pin, which swings from GND to VCC.
2. Load and update DAC A in SLOW mode. Power down
DAC B. Perform the following sequence for the control,
address and DATA bits:
Step 1: Set DAC A in SLOW mode
CS/LD clock in 0110 0000 XXXXXXXX XXXXXXXX;
CS/LD
Step 2: Load and update DAC A with DATA
CS/LD clock in 0011 0000 + DATA; CS/LD
Step 3: Power down DAC B
CS/LD clock in 0100 0001 XXXXXXXX XXXXXXXX;
CS/LD
3. Power down both DACs at the same time. Perform the
following sequence for the control, address and DATA
bits:
Step 1: Power down both DACs simultaneously
CS/LD clock in 0100 1111 XXXXXXXX XXXXXXXX;
CS/LD
Multiple LTC1654s may be daisy-chained together by
connecting the SDO pin to the SDI pin of the next IC. The
SCK and CS/LD signals remain common to all ICs in the
daisy-chain. The serial data is clocked to all of the chips,
then the CS/LD signal is pulled high to update all DACs
simultaneously.
Table 1 shows the truth table for the control/address bits.
When the supplies are first applied, the LTC1654 uses
SLOW mode, the outputs are set at 0V, and zeros are
loaded into the 32-bit input shift register. Three examples
are given to illustrate the DAC’s operation:
1. Load and update DAC A in FAST mode. Leave DAC B
unchanged. Perform the following sequence for the
control, address and DATA bits:
Step 1: Set DAC A in FAST mode
CS/LD
CS/LD
Step 2: Load and update DAC A with DATA
clock in 0101 0000 XXXXXXXX XXXXXXXX;
Voltage Output
The LTC1654 comes complete with rail-to-rail voltage
output buffer amplifiers. These amplifiers will swing to
within a few millivolts of either supply rail when unloaded
and to within a 300mV of either supply rail when sinking
or sourcing 5mA.
There are two GAIN configuration modes for the LTC1654:
a) GAIN of 1: (X1/X
V
= (V
OUT
b) GAIN of 1/2: (X1/X
V
OUT
The LTC 1654 has two SPEED modes: A FAST mode and
a SLOW mode. When operating in the FAST mode, the
output amplifiers will settle in 3.5µs (typ) to 14 bits on a
4V output swing. In the SLOW mode, they will settle in
8µs. The total supply current is 750µA in the FAST mode
and 450µA in the SLOW mode.
REFHI
= (1/2)(V
tied to REFLO)
1/2
– V
REFLO
tied to V
1/2
– V
REFHI
REFLO
)(SDI/16384) + V
)
OUT
)(SDI/16384) + V
REFLO
REFLO
CS/LD clock in 0011 0000 + DATA; CS/LD
6
Page 7
U
OPERATION
LTC1654
Power Down
Each DAC can also be independently powered down to less
than 5µA/DAC of supply current. The reference pin also
goes into a high impedance state when the DAC is powered
down and the reference current will drop to below 0.1µA.
The amplifiers’ output stage is also three-stated but the
Table 1.
CONTROL
C3 C2 C1 C0
0000 Load Input Register n
0001 Update (Power-Up) DAC Register n
0010 Load Input Register n, Update (Power-Up) All
0011 Load and Update n
0100 Power Down n
0101 Fast n (Speed States are Maintained Even If DAC is
Put in Power-Down Mode)
0110 Slow n (Default State is Slow When Supplies are
Powered Up)
0111 Reserved (Do Not Use)
1000 Reserved (Do Not Use)
1001 Reserved (Do Not Use)
1010 Reserved (Do Not Use)
1011 Reserved (Do Not Use)
1100 Reserved (Do Not Use)
1101 Reserved (Do Not Use)
1110 Reserved (Do Not Use)
1111 No Operation
V
pins still have the internal gain-setting resistors
OUT
connected to them resulting in an effective resistance from
V
to REFLO. This resistance is typically 90k when the
OUT
X1/X
REFLO. Because of this resistance, V
when the DAC is powered down and V
ADDRESS (n)
A3 A2 A1 A0
pin is tied to V
1/2
0000 DAC A
0001 DAC B
0010 Reserved (Do Not Use)
0011 Reserved (Do Not Use)
0100 Reserved (Do Not Use)
0101 Reserved (Do Not Use)
0110 Reserved (Do Not Use)
0111 Reserved (Do Not Use)
1000 Reserved (Do Not Use)
1001 Reserved (Do Not Use)
1010 Reserved (Do Not Use)
1011 Reserved (Do Not Use)
1100 Reserved (Do Not Use)
1101 Reserved (Do Not Use)
1110 Reserved (Do Not Use)
1111 Both DACs
and 36k when X1/X
OUT
will go to V
OUT
is unloaded.
OUT
is tied to
1/2
REFLO
INPUT WORD
CONTROL ADDRESS DATA (14 + 2 DUMMY LSBs)
C3
C2
C1
C0
A3
A2
A1
A0
D13
D12
D11 D10 D9 D8
D7
D6
D5 D4 D3 D2 D1
D0
X
X
1654 TABLE
7
Page 8
LTC1654
U
WUU
APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If V
= VCC and the DAC full-scale error
REF
V
REF
= V
CC
(FSE) is positive, the output for the highest codes limits at
VCC as shown in Figure 2c. No full-scale limiting can occur
if V
is less than (VCC – FSE).
REF
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
V
= V
REF
INPUT CODE
CC
(c)
POSITIVE
FSE
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
81920 16383
INPUT CODE
(a)
OUTPUT
VOLTAGE
OFFSET
0V
INPUT CODE
(b)
1654 F02
NEGATIVE
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
REF
= V
CC
8
Page 9
UU
DEFI ITIO S
LTC1654
Resolution (n): Resolution is defined as the number of
digital input bits (n). It is also the number of DAC output
states (2n) that divide the full-scale range. Resolution does
not imply linearity.
Full-Scale Voltage (VFS): This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (VOS): Normally, DAC offset is the
voltage at the output when the DAC is loaded with all zeros.
The DAC can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below 0V. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
OUTPUT
VOLTAGE
NEGATIVE
0V
OFFSET
Figure 1. Effect of Negative Offset
DAC CODE
1654 F01
The offset of the part is measured at the code that corresponds to the maximum offset specification:
VOS = V
– [(Code)(VFS)/(2n – 1)]
OUT
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
Zero-Scale Error (ZSE): The output voltage when the
DAC is loaded with all zeros. Since this is a single supply
part, this value cannot be less than 0V.
Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the
end points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset
specification. The INL error at a given input code is
calculated as follows:
INL = [V
V
= The output voltage of the DAC measured at the
OUT
– VOS – (VFS – VOS)(code/16383)]/LSB
OUT
given input code
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal one LSB
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:
DNL = (∆V
∆V
= The measured voltage difference between
OUT
– LSB)/LSB
OUT
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
nV • s.
LSB = (VFS – VOS)/(2n – 1) = (VFS – VOS)/16383
Nominal LSBs:
LTC1654 LSB = 4.09575V/16383 = 250µV
9
Page 10
LTC1654
TYPICAL APPLICATION
U
Dual 14-Bit Voltage Output DAC
2.7V TO 5.5V
LTC1654
1
X
B
1/X1/2
2
CLR
3
SCK
µP
4
SDI
CS/LD
DGND
SDO
X
1/X1/2
REFLO B
REFLO A
A
5
6
7
8
V
V
OUT B
REFHI B
AGND
REFHI A
V
OUT A
16
CC
15
14
13
12
11
10
9
1654 TA01
0.1µF
OUTPUT B: 0V TO V
OUTPUT A: 0V TO V
CC
CC
10
Page 11
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
16
15
14
12 11 10
13
LTC1654
0.009
(0.229)
9
REF
0.015
± 0.004
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0.016 – 0.050
(0.406 – 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0° – 8° TYP
× 45°
0.229 – 0.244
(5.817 – 6.198)
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
12
0.150 – 0.157**
(3.810 – 3.988)
5
4
3
678
0.0250
(0.635)
BSC
0.004 – 0.0098
(0.102 – 0.249)
GN16 (SSOP) 1098
11
Page 12
LTC1654
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1257 Single 12-Bit V
Reference Can Be Overdriven Up to 12V, i.e., FS
LTC1446/LTC1446L Dual 12-Bit V
LTC1448 Dual 12-Bit V
LTC1450/LTC1450L Single 12-Bit V
LTC1451 Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, 5V, Low Power Complete V
Internal 2.048V Reference Brought Out to Pin
LTC1452 Single Rail-to-Rail 12-Bit V
LTC1453 Single Rail-to-Rail 12-Bit V
LTC1454/LTC1454L Dual 12-Bit V
LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Low Power, Complete V
Full Scale: 4.095V, V
LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, V
LTC1658 14-Bit Rail-to-Rail Micropower DAC in MSOP, VCC: 2.7V to 5.5V Output Swings from GND to REF. REF Input
LTC1659 Single Rail-to-Rail 12-Bit V
References
LT1460 Micropower Precision Reference Low Cost, 10ppm Drift
LT1461 Precision Voltage Reference Ultralow Drift 3ppm/°C, Initial Accuracy: 0.04%
LT1634 Micropower Precision Reference Low Drift 10ppm/°C, Initial Accuracy: 0.05%
DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, 5V to 15V Single Supply, Complete V
OUT
DACs in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, V
OUT
DAC, VCC: 2.7V to 5.5V Output Swings from GND to REF. REF Input
OUT
DACs with Parallel Interface LTC1450: VCC = 4.5V to 5.5V, V
OUT
Multiplying DAC, VCC: 2.7V to 5.5V Low Power, Multiplying V
OUT
= 12V SO-8 Package
MAX
LTC1446L: V
Can Be Tied to V
LTC1450L: V
= 2.7V to 5.5V, V
CC
CC
= 2.7V to 5.5V, V
CC
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
DAC in SO-8 Package
OUT
DAC with Rail-to-Rail
Buffer Amplifier in SO-8 Package
DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V 3V, Low Power, Complete V
OUT
DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, V
OUT
LTC1454L: V
: 4.5V to 5.5V Package with Clear Pin
CC
LTC1458L: V
Can Be Tied to V
DAC in 8-Pin MSOP, VCC: 2.7V to 5.5V Low Power, Multiplying V
OUT
= 2.7V to 5.5V, V
CC
= 2.7V to 5.5V, V
CC
CC
DAC in SO-8 Package
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
DAC in SO-8
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
DAC in MS8 Package.
OUT
Output Swings from GND to REF. REF Input Can Be
Tied to VCC.
OUT
DAC in
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
1654i LT/TP 0400 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2000
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