Datasheet LTC1645 Datasheet (Linear Technology)

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FEATURES

LTC1645

Dual-Channel Hot Swap

Controller/Power Sequencer

DESCRIPTIO

■

Allows Safe Board Insertion and Removal from a Live Backplane

■

Programmable Power Supply Sequencing

■

Programmable Electronic Circuit Breaker

■

User-Programmable Supply Voltage Power-Up and Power-Down Rate

■

High Side Drivers for External N-Channel FETs

■

Controls Supply Voltages from 1.2V to 12V

■

Ensures Proper Power-Up Behavior

■

Undervoltage Lockout

■

Glitch Filter Protects Against Spurious RESET Signals

APPLICATIO S

■

Hot Board Insertion

■

Power Supply Sequencing

■

Electronic Circuit Breaker

TYPICAL APPLICATIO

The LTC®1645 is a 2-channel Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. Using external N-channel pass transistors, the supply voltages can be ramped at a programmable rate. Two high side switch drivers control the N-channel gates for supply voltages ranging from 1.2V to 12V. The two channels can be set to ramp up and down separately, or they can be programmed to rise and fall simultaneously, ensuring power supply tracking at the two outputs.

Programmable electronic circuit breakers protect against shorts at either output. The RESET output can be used to generate a system reset when a supply voltage falls below a user-programmed voltage. An additional spare comparator is available for monitoring a second supply voltage.

The LTC1645 is available in the 8- and 14-pin SO packages.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Hot Swap is a trademark of Linear Technology Corporation.

IN2

IN1

GND

CONNECTOR 1

CONNECTOR 2

PLUG-IN CARDBACKPLANE

5V and 3.3V Hot Swap

0.005Ω*

10k

IRF7413

10Ω

GATE1 SENSE2

SENSE1 V

CC1

0.01µF 25V

LTC1645 (8-LEAD)

GND

0.005Ω*

CC2

IRF7413

10Ω

GATE2

*LRF1206-01-R005-J (IRC)

1645 TA01

LOAD2

LOAD1

0.01µF 25V

OUT2

3.3V 5A

OUT1

5V 5A

5V/DIV

GATE

10V/DIV

OUT2

5V/DIV

OUT1

5V/DIV

5V and 3.3V Hot Swap Waveforms

LTC1645

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Supply Voltage (V

CC1

, V

) ................................. 13.2V

CC2

Input Voltage

FB, ON, COMP+..................... –0.3V to (V

+ 0.3V)

CC1

TIMER ................................................. – 0.3V to 2.5V

SENSE1 ..................... (V

SENSE2 ...................... (V

– 0.7V) to (V

CC1

– 0.7V) to (V

CC1

+ 0.3V)

CC1

+ 0.3V)

CC2

Output Voltage

RESET, COMPOUT, FAULT .....................–0.3V to 16V

GATE1, GATE2................. Internally Limited (Note 3)

PACKAGE/ORDER I FOR ATIO

ORDER PART

NUMBER

LTC1645CS8 LTC1645IS8

S8 PART MARKING

1645 1645I

CC2

SENSE2

GATE2

GND

TOP VIEW

S8 PACKAGE

8-LEAD PLASTIC SO

= 125°C, θJA = 150°C/W

JMAX

CC1

SENSE1 GATE1 ON

Output Current

GATE1, GATE2............................................... ±20mA

Operating Temperature Range

LTC1645C ............................................... 0°C to 70°C

LTC1645I............................................ –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ORDER PART

NUMBER

LTC1645CS LTC1645IS

CC2

SENSE2

GATE2 FAULT RESET

GND

TOP VIEW

1 2 3 4 5 6

S PACKAGE

14-LEAD PLASTIC SO

= 125°C, θJA = 110°C/W

JMAX

14 13 12 11 10

9 8

CC1

SENSE1 GATE1 TIMER ON COMPOUT

COMP

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.

2.375V ≤ V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Characteristics

CC1

CC2

LKO1

LKO2

LKH

∆V

FBHST

COMP

∆V

COMP

COMPHST

≤ 12V, 1.2V ≤ V

CC1

Supply Current ON = V

CC1

Supply Current ON = V

CC2

Undervoltage Lockout High to Low ● 2.16 2.23 2.3 V

CC1

Undervoltage Lockout High to Low ● 1.06 1.12 1.18 V

CC2

Undervoltage Lockout Hysteresis 25 mV

CCn

FB Pin Voltage Threshold High to Low ● 1.226 1.238 1.250 V FB Pin Threshold Line Regulation High to Low, V FB Pin Voltage Threshold Hysteresis 5 mV COMP+ Pin Voltage Threshold High to Low ● 1.226 1.238 1.250 V COMP+ Pin Threshold Line Regulation High to Low, V COMP+ Pin Voltage Threshold Hysteresis 5 mV

≤ 12V unless otherwise noted (Note 2).

CC2

= 5V, V

CC1

= 5V, V

CC1

= 3.3V ● 1.1 2.0 mA

CC2

= 3.3V ● 0.28 0.4 mA

CC2

= 2.375V to 12V ● 14 mV

CC1

= 2.375V to 12V ● 14 mV

CC1

LTC1645

TEMPERATURE (°C)

–40

0.8

1.0

1.4

20 60

1645 G03

0.6

0.4

–20 0

40 80 100

0.2

1.2

(mA)

CC1

= 5V

CC2

= 3.3V

CC1

CC2

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.

2.375V ≤ V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

∆V

CB1

CB2

CBD

∆V

GATE

ONFPD

ON1

ON2

ONHYST

≤ 12V, 1.2V ≤ V

CC1

≤ 12V unless otherwise noted (Note 2).

CC2

TIMER Pin Voltage Threshold ● 1.212 1.230 1.248 V TIMER Pin Threshold Line Regulation V TIMER Pin Current Timer On, V

Circuit Breaker Trip Voltage 1 V Circuit Breaker Trip Voltage 2 V Circuit Breaker Trip Delay V GATEn Pin Output Current ON = 2.2V, V

External N-Channel Gate Drive ∆V

= 2.375V to 12V ● 19 mV

CC1

Timer Off, V

= (V

CB1

CC1

= (V

CB2

CC2

= (V

ON = 0.7V, V ON = 0.3V, V

= (V

GATE

= 0.6V, V

TIMER

= 1.5V 12 mA

TIMER

– V

SENSE1

– V

SENSE2

– V

SENSE

= V

GATE

= V

GATE

= V

GATE

– V

GATE

= 5V ● –2.3 –2 –1.7 µA

CC1

) ● 46 50 56 mV ) ● 46 50 56 mV ) > 60mV 1.5 µs

, V

CC CC CC

= 5V, V

CC1

, V

= 5V, V

CC1

, V

= 5V, V

CC1

) ● 4.5 16 V

= 3.3V ● –12.5 –10 –7.5 µA

CC2

= 3.3V ● 30 40 50 µA

CC2

= 3.3V 12 mA

CC2

ON Pin Fast Pull-Down Threshold Low to High ● 0.375 0.4 0.425 V

High to Low, Fast Pull-Down Engaged

● 0.35 0.375 0.4 V

ON Pin Threshold #1 Low to High, GATE1 Turns On ● 0.8 0.825 0.85 V

High to Low, GATE1 Turns Off

● 0.775 0.8 0.825 V

ON Pin Threshold #2 Low to High, GATE2 Turns On ● 2 2.025 2.050 V

High to Low, GATE2 Turns Off

● 1.975 2 2.025 V

ON Pin Hysteresis 25 mV ON Pin Input Current V Output Low Voltage RESET, FAULT, COMPOUT, I

CC1

= 5V, V

= 3.3V ● ±0.01 ±2 µA

CC2

= 1.6mA, V

OUT

= 5V ● 0.16 0.4 V

CC1

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.

Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.

Note 3: An internal zener on the GATEn pins clamps the charge pump voltage to a typical maximum operating voltage of 22V. External overdrive of a GATE pin (for example, from capacitive coupling of V beyond the internal zener voltage may damage the device. If a lower GATEn pin clamp voltage is desired, use an external zener diode.

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Voltage V

CC1

3.0 TA = 25°C

2.5

2.0

(mA)

1.5

CC1

1.0

0.5

= 1.5V

CC2

= 12V

CC2

46810

(V)

CC1

123257911

1645 G01

3.5

3.0

2.5

2.0

(mA)

CC2

1.5

1.0

0.5

Supply Current vs Voltage

CC2

TA = 25°C

= 2.375V

CC1

CC2

(V)

CC1

= 12V

10 11 12

1645 G02

glitches)

Supply Current vs Temperature

LTC1645

FEEDBACK TRANSIENT (mV)

GLITCH FILTER TIME (µs)

100

160

200

1645 G06

120

240

280

TA = 25°C

TYPICAL PERFOR A CE CHARACTERISTICS

GATE Voltage vs Supply Voltage

TA = 25°C

(V)

GATE

311

HIGHEST VCC (V)

1645 G04

GATE Voltage vs Temperature

16.0 V

= 5V

CC1

15.8

15.6

15.4

15.2

(V)

15.0

GATE

14.8

14.6

14.4

14.2

14.0

–40

= 3.3V

CC2

–20

TEMPERATURE (°C)

Glitch Filter Time vs Feedback Transient

100

1645 G05

RESET, FAULT, COMPOUT Output Voltage vs Temperature

450

= 5V

CC1

400

350

300

250

200

150

OUTPUT VOLTAGE (mV)

100

SINK CURRENT = 3mA

SINK CURRENT = 1.6mA

–20 0 20 100

–40

TEMPERATURE (°C)

40 60 80

1645 G07

RESET, FAULT, COMPOUT Output Voltage vs V

800

700

600

500

400

300

OUTPUT VOLTAGE (mV)

200

100

SINK CURRENT = 1.6mA

CC1

SINK CURRENT = 3mA

468 129357 11

(V)

CC1

TA = 25°C

1645 G08

Fast Pull-Down Current vs V

TA = 25°C

= 1.5V

CC2

16 15 14 13 12 11 10

FAST PULL-DOWN CURRENT (mA)

9 8

23 5 9 11

687

CC1

(V)

CC1

1645 G09

LTC1645

PI FU CTIO S

(Pin 1/Pin 1): Positive Supply Input. V

CC2

from 1.2V to 12V for normal operation. I

0.2mA. An undervoltage lockout circuit disables the LTC1645 whenever the voltage at V

SENSE2 (Pin 2/Pin 2): V a sense resistor placed in the supply path between V and SENSE2, the circuit breaker trips when the voltage across the resistor exceeds 50mV for more than 1.5µs. If the circuit breaker trip current is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the circuit breaker, short V

GATE2 (Pin 3/Pin 3): Channel 2 High Side Gate Drive. Connect to the gate of an external N-channel MOSFET. An internal charge pump guarantees at least 4.5V of gate drive. The charge pump is powered by the higher of V and V on by connecting a 10µA current source from the charge pump output to the GATE2 pin and the voltage starts to ramp up with a slope dv/dt = 10µA/C pin is below 2V but above 0.4V, a 40µA current source pulls GATE2 toward ground. If the ON pin is below 0.4V, the circuit breaker trips or the undervoltage lockout circuit trips, the GATE2 pin is immediately pulled to ground with a 12mA (typ) current source.

FAULT (Pin 4/NA): Circuit Breaker Fault. FAULT is an open-drain output that pulls low when the circuit breaker function trips. The circuit breaker is reset by pulling the ON pin below 0.4V. An external pull-up is required to generate a logic high at the FAULT pin. When the ON pin is low, FAULT will release.

The circuit breaker can be programmed to automatically reset by connecting the FAULT pin to the ON pin. In this circuit configuration, if a logic device is driving the ON pin, use a series resistor between the logic output and the ON pin to prevent large currents from flowing.

RESET (Pin 5/NA): Open-Drain RESET Output. The RESET pin is pulled low when the voltage at the FB pin goes below

1.238V or V old. The RESET pin goes high one timing cycle after the voltage at the FB pin goes above the FB pin threshold. The ON pin must remain above 0.8V during this timing cycle.

. When the ON pin exceeds 2V, GATE2 is turned

CC2

is below the undervoltage lockout thresh-

CC1

(14-Lead Package/8-Lead Package)

CC2

Circuit Breaker Set Pin. With

CC2

and SENSE2 together.

CC2

can range

CC2

is typically

CC2

is less than 1.12V.

. While the ON

GATE2

CC2

CC1

An external pull-up is required to generate a logic high at the RESET pin.

FB (Pin 6/NA): RESET Comparator Input. The FB pin is used to monitor the output supply voltage with an external resistive divider. When the voltage on the FB pin is lower than 1.238V, the RESET pin is pulled low. A glitch filter on the FB pin prevents fast transients from forcing RESET low. When the voltage on the FB pin rises above the trip point, the RESET pin goes high after one timing cycle.

GND (Pin 7/Pin 4): Ground. Connect to a ground plane for optimum performance.

COMP+ (Pin 8/NA): Spare Comparator Noninverting Input. When the voltage on COMP+ is lower than 1.238V, COMPOUT pulls low.

COMPOUT (Pin 9/NA): Open-Drain Spare Comparator Output. COMPOUT pulls low when the voltage on COMP is below 1.238V or V threshold. An external pull-up is required to generate a logic high at the COMPOUT pin.

ON (Pin 10/Pin 5): Analog Control Input. If the ON pin voltage is below 0.4V, both GATE1 and GATE2 are immediately pulled to ground. While the voltage is between 0.4V and 0.8V, both GATE1 and GATE2 are each pulled to ground with a 40µA current source. While the voltage is between 0.8V and 2V, the GATE1 pull-up is turned on after one timing cycle, but GATE2 continues to be pulled to ground with a 40µA current source. When the voltage exceeds 2V, both the GATE1 and GATE2 pull-ups are turned on one timing cycle after the voltage exceeds 0.8V.

The ON pin is also used to reset the electronic circuit breaker. If the ON pin is brought below and then above

0.4V following the trip of the circuit breaker, the circuit breaker resets, and a normal power-up sequence occurs.

TIMER: (Pin 11/NA): System Timing Pin. The TIMER pin requires an external capacitor to ground to generate a timing delay. The pin is used to set the delay before the RESET pin goes high after the output supply voltage is good as sensed by the FB pin. It is also used to set the delay between the ON pin exceeding 0.8V and the GATE1 and GATE2 pins turning on (GATE2 turns on only if the ON pin exceeds 2V).

is below the undervoltage lockout

CC1

LTC1645

PI FU CTIO S

(14-Lead Package/8-Lead Package)

Whenever the timer is inactive, an internal N-channel FET shorts the TIMER pin to ground. Activating the timer connects a 2µA current source from V

to the TIMER pin

CC1

and the voltage starts to ramp up with a slope dv/dt = 2µA/ C

. When the voltage reaches the trip point (1.23V),

TIMER

the timer is reset by pulling the TIMER pin back to ground. The timer period is (1.23V • C

TIMER

)/2µA.

GATE1 (Pin 12/Pin 6): Channel 1 High Side Gate Drive. Connect to the gate of an external N-channel MOSFET. An internal charge pump guarantees at least 4.5V of gate drive. The charge pump is powered by the higher of V and V

. When the ON pin exceeds 0.8V, GATE1 is turned

CC2

CC1

on by connecting a 10µA current source from the charge pump output to the GATE1 pin and the voltage starts to ramp up with a slope dv/dt = 10µA/C

. While the ON

GATE1

pin is below 0.8V but above 0.4V, a 40µA current source pulls GATE1 toward ground. If the ON pin is below 0.4V,

the circuit breaker trips or the undervoltage lockout circuit trips, the GATE1 pin is immediately pulled to ground with a 12mA (typ) current source.

SENSE1 (Pin 13/Pin 7): V a sense resistor placed in the supply path between V

Circuit Breaker Set Pin. With

CC1

and SENSE1, the circuit breaker trips when the voltage across the resistor exceeds 50mV for more than 1.5µs. If the circuit breaker trip current is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the circuit breaker, short V

(Pin 14/Pin 8): Positive Supply Input. V

CC1

from 2.375V to 12V for normal operation. I

and SENSE1 together.

CC1

can range

CC1

is typically

CC1

1mA. An undervoltage lockout circuit disables the chip whenever the voltage at V logic is powered by V

is less than 2.23V. All internal

CC1

BLOCK DIAGRA

0.8V

0.4V

2µA

REF

–

TIMER

FAULT

CC1

2.23V UVL

SENSE113V

1.5µs

FILTER

CC2

–

50mV 50mV

–

1.12V UVL

LOGIC

SENSE2

1.5µs

FILTER

GATE112GATE2

– +

–

GLITCH

FILTER

4× CHARGE

PUMP

1.238V

REFERENCE

REF

–

REF

6 5

FB RESET

GND

COMP

COMPOUT

1645 BD

WUUU

APPLICATIO S I FOR ATIO

LTC1645

Hot Circuit Insertion

When a circuit board is inserted into a live backplane, the supply bypass capacitors on the board can draw huge transient currents from the backplane power bus as they charge. These transient currents can cause permanent damage to the connector pins and produce glitches on the system supply, resetting other boards in the system.

The LTC1645 is designed to turn a board’s supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip provides a system reset signal and a spare comparator to indicate when board supply voltages drop below userprogrammable voltages, and a fault signal to indicate if an overcurrent condition has occurred.

The LTC1645 can be located before or after the connector as shown in Figure 1. A staggered PCB connector can sequence pin connections when plugging and unplugging circuit boards. Alternatively, the control signal can be generated by processor control.

Power Supply Tracking and Sequencing

Some applications require that the potential difference between two power supplies not exceed a certain voltage. This requirement applies during power-up and powerdown as well as during steady state operation, often to prevent latch-up in a dual supply ASIC. Other systems require one supply to come up after another, for example, if a system clock needs to start before a block of logic. Typical dual supplies or backplane connections may come up at arbitrary rates depending on load current, capacitor size, soft-start rates, etc. Traditional solutions are cumbersome and require complex circuitry to meet the power supply requirements.

The LTC1645 provides a simple solution to power supply tracking and sequencing needs. The LTC1645 guarantees supply tracking by ramping the supplies up and down together (see Figure 15). The sequencing capabilities of the LTC1645 allow nearly any combination of supply ramping (e.g., see Figure 17) to satisfy various sequencing specifications. See the Power Supply Tracking and Sequencing Applications section for more information.

FAULT

SENSE

BACKPLANE

CONNECTOR

LTC1645

FAULT GND

(a) Hot Swap Controller on Motherboard

STAGGERED PCB EDGE CONNECTOR

(b) Hot Swap Controller on Daughterboard

GATE

ON FAULT GND

BACKPLANE

CONNECTOR

SENSE

LTC1645

STAGGERED PCB EDGE CONNECTOR

GATE

1645 F01

OUT

LOAD

OUT

Figure 1. Staggered Pins Connection

LTC1645

WUUU

APPLICATIO S I FOR ATIO

Power Supply Ramping

The power supplies on a board are controlled by placing external N-channel pass transistors in the power paths as shown in Figure 2. Consult Table 1 for a selection of N-channel FETs suitable for use with the LTC1645. R and R

SENSE2

provide current fault detection and R1 and R2

SENSE1

prevent high frequency oscillation. By ramping the gates of the pass transistors up and down at a controlled rate, the transient surge current (I = C • dv/dt) drawn from the main backplane supply is limited to a safe value when the board makes connection.

When power is first applied to the chip, the gates of the N-channels (GATE1 and GATE2 pins) are pulled low. After the ON pin is held above 0.8V for at least one timing cycle, the voltage at GATE1 begins to rise with a slope equal to dv/dt = 10µA/C1 (Figure 3), where C1 is the external capacitor connected between the GATE1 pin and GND. If the ON pin is brought above 2V (and the ON pin has been held above 0.8V for at least one timing cycle), the voltage at GATE2 begins to rise with a slope equal to dv/dt = 10µA/C2.

The ramp time for each supply is t = (V

• Cn)/10µA. If

the ON pin is pulled below 2V for GATE2 or 0.8V for GATE1 (but above 0.4V), a 40µA current source is connected from GATEn to GND, and the voltage at the GATEn pin will ramp down, as shown in Figure 4.

Ringing

Good engineering practice calls for bypassing the supply rail of any circuit. Bypass capacitors are often placed at the supply connection of every active device, in addition to one or more large value bulk bypass capacitors per supply rail. If power is connected abruptly, the bypass capacitors slow the rate of rise of voltage and heavily damp any parasitic resonance of lead or trace inductance working against the supply bypass capacitors.

The opposite is true for LTC1645 Hot Swap circuits on a daughterboard. In most cases, on the powered side of the N-channel FET switches (V

) there is no supply bypass

capacitor present. An abrupt connection, produced by plugging a board into a backplane connector, results in a fast rising edge applied to the V

line of the LTC1645.

CC1

CC2

SENSE1

SENSE1 GATE2

CC1

FAULT

TIMER GND

R1 10Ω

SENSE2

1314

(14-LEAD)

11 7

TIMER

LTC1645

SENSE2GATE1

CC2

COMPOUT

COMP

RESET

R2 10Ω

+ ∆V

CCn

GATE

SLOPE = 10µA/C

Figure 3. Supply Turning On

+ ∆V

GATE

OUT

SLOPE = 40µA/C

OUT1

LOAD1

OUT2

LOAD2

1645 F02

GATE

OUT

1645 F03

1645 F04

Figure 2. Typical Hot Swap Connection

Figure 4. Supply Turning Off

WUUU

1µs/DIV

4V/DIV

1645 F05b

24V

APPLICATIO S I FOR ATIO

LTC1645

No bulk capacitance is present to slow the rate of rise and heavily damp the parasitic resonance. Instead, the fast edge shock excites a resonant circuit formed by a combination of wiring harness, backplane and circuit board parasitic inductances and FET capacitance. In theory, the peak voltage should rise to 2X the input supply, but in practice the peak can reach 2.5X, owing to the effects of voltage dependent FET capacitance.

The absolute maximum V

potential for the LTC1645 is

13.2V; any circuit with an input of 5V or greater should be scrutinized for ringing. A well-bypassed backplane should not escape suspicion: circuit board trace inductances of as little as 10nH can produce sufficient ringing to overvoltage VCC.

Check ringing with a fast storage oscilloscope (such as a LECROY 9314AL DSO) by attaching coax or a probe to V

POWER

LEADS

12V

–

SCOPE PROBE

and GND, then repeatedly inserting the circuit board into the backplane. Figures 5a and 5b show typical results in a 12V application with different VCC lead lengths. The peak amplitude reaches 22V, breaking down the ESD protection diode in the process.

There are two methods for eliminating ringing: clipping and snubbing. A transient voltage suppressor is an effective means of limiting peak voltage to a safe level. Figure␣ 6 shows the effect of adding an ON Semiconductor, 1SMA12CAT3, on the waveform of Figure 5.

Figures 7a and 7b show the effects of snubbing with different RC networks. The capacitor value is chosen as 10X to 100X the FET C

under bias and R is selected for

OSS

best damping—1Ω to 50Ω depending on the value of parasitic inductance.

0.01Ω

IRF7413

10Ω

OUT

LOAD

0.1µF

LTC1645

1645 F05

24V

4V/DIV

µs/DIV

(a) Undamped VCC Waveform (48" Leads) (b) Undamped VCC Waveform (8" Leads)

1645 F05a

Figure 5. Ring Experiment

LTC1645

1µs/DIV

1645 F06a

2V/DIV

12V

1µs/DIV

1645 F07b

2V/DIV

12V

WUUU

APPLICATIO S I FOR ATIO

12V

+ –

POWER

LEADS

0.01Ω

D1*

IRF7413

10Ω

OUT

LOAD

0.1µF

ON SEMICONDUCTOR * 1SMA12CAT3

PCB EDGE CONNECTOR

BACKPLANE CONNECTOR

12V

+ –

LTC1645

1645 F06

Figure 6. Transient Suppressor Clamp

10Ω

POWER

LEADS

BACKPLANE CONNECTOR

0.1µF

PCB EDGE CONNECTOR

VCC Waveform Clamped by a Transient Suppressor

0.01Ω

IRF7413

10Ω

LTC1645

OUT

LOAD

0.1µF

1645 F07

12V

2V/DIV

1µs/DIV

1645 F07a

(a) VCC Waveform Damped by a Snubber (15Ω, 6.8nF) (b) VCC Waveform Damped by a Snubber (10Ω, 0.1µF)

Figure 7. Snubber “Fixes”

WUUU

APPLICATIO S I FOR ATIO

LTC1645

Supply Glitching

LTC1645 Hot Swap circuits on the backplane are generally used to provide power-up/down sequence at insertion/ removal as well as overload/short-circuit protection. If a short-circuit occurs at supply ramp-up, the circuit breaker

SUPPLY

12V

GLITCH

+ –

100µF

0.01Ω

LTC1645

trips. The partially enhanced FET is easily disconnected without any supply glitch.

If a dead short occurs after a supply connection is made (Figure 8), the sense resistor R1 and the R

DS(ON)

of the

fully enhanced FET provide a low impedance path for

10Ω

2µH

0.1µF

BACKPLANE CONNECTOR

1645 F08

GATE

SHORT-CIRCUIT FAULT

BOARD WITH POSSIBLE

IRF7413

25A/DIV

1µs/DIV

1645 F08a

4V/DIV

1µs/DIV

1645 F08b

(a) VCC Short-Circuit Supply Current Glitch Without Any Limiting (b) VCC Supply Glitch Without Any Limiting

GATE

5A/DIV

1µs/DIV

1645 F08c

4V/DIV

1µs/DIV

1645 F08d

(d) VCC Supply Glitch with 2µH Series Inductor

with 2µH Series Inductor

Figure 8. Supply Glitch

LTC1645

–

COMP

TIMER

2µA

TIMER

1.23V

SUPPLY

MONITOR

1645 F11

LOGIC

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APPLICATIO S I FOR ATIO

nearly unlimited current flow. The LTC1645 discharges the GATE pin in a few microseconds, but during this discharge time current on the order of 150 amperes flows from the VCC power supply. This current spike glitches the power supply, causing VCC to dip (Figure 8a and 8b).

On recovery from overload, some supplies may overshoot. Other devices attached to this supply may reset or malfunction and the overshoot may also damage some components. An inductor (1µH to 10µH) in series with the FET’s source limits the short-circuit di/dt, thereby limiting the peak current and the supply glitch (Figure 8c and 8d). Additional power supply bypass capacitance also reduces the magnitude of the VCC glitch.

Reset

The LTC1645 uses an internal 1.238V bandgap reference, a precision voltage comparator, and a resistive divider to monitor the output supply voltage (Figure 9).

Whenever the voltage at the FB pin rises above its reset threshold (1.238V), the comparator output goes high, and a timing cycle starts (see Figure 10, time points 1 and 4). After a complete timing cycle, RESET is released. An external pull-up is required for the RESET pin to rise to a logic high.

When the voltage at the FB pin drops below its reset threshold, the comparator output goes low. After passing through a glitch filter, RESET is pulled low (time point 2). If the FB pin rises above the reset threshold for less than a timing cycle, the RESET output remains low (time point 3).

OUT

Glitch Filter

The LTC1645 has a glitch filter to prevent RESET from generating a spurious system reset in the presence of transients on the FB pin. The filter is 20µs for large transients (greater than 150mV) and up to 80µs for smaller transients. The relationship between glitch filter time and the transient voltage is shown in Typical Performance Characteristics: Glitch Filter Time vs Feedback Transient.

Timer

The system timing for the LTC1645 is generated by the circuitry shown in Figure 11. The timer is used to set the turn-on delay after the ON pin goes high. It also sets the delay before the RESET pin goes high after the FB pin exceeds 1.238V.

Whenever the timer is off, the internal N-channel shorts the TIMER pin to ground (Figure 11). Activating the timer connects a 2µA current from V

OUT

TIMER

RESET

1.23V

Figure 10. Supply Monitor Waveforms

23 4

to the TIMER pin and the

CC1

V2 V1 V2

1.23V

1645 F10

LOGIC

TIMER

Figure 9. Supply Monitor Block Diagram

TIMER

COMP

1.238V

REFERENCE

–

RESET

10k

µP

RESET

1645 F09

Figure 11. System Timing Block Diagram

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APPLICATIO S I FOR ATIO

LTC1645

voltage on the external capacitor C with a slope dv/dt = 2µA/C

. When the voltage reaches

TIMER

starts to ramp up

TIMER

the trip point (1.23V), the timer is reset by pulling the TIMER pin back to ground. The timer period is t = (1.23V • C

)/2µA. For a 200ms delay, use a 0.33µF

TIMER

capacitor.

Electronic Circuit Breaker

The LTC1645 features an electronic circuit breaker function that protects against short circuits or excessive output currents. By placing sense resistors between the supply inputs and sense pins of the supplies, the circuit breaker trips whenever the voltage across either sense resistor is greater than 50mV for more than 1.5µs. If the circuit breaker trips, both GATE pins are immediately pulled to ground and the external N-channels FETs are quickly turned off (time point 6 in Figure 12). The circuit breaker resets and another timing cycle starts by taking

RAMPING UP

12 3 4

– V

SENSE

TIMER

GATE

CURRENT

FAULT

56 7 89 10

RESET FAULT

AND RAMP UP

the ON pin below 0.4V and then high as shown at time point 7.

At the end of the timer cycle (time point 8), the charge pump turns on again. If the circuit breaker feature is not required, short the SENSEn pin to V

If the 1.5µs response time is too fast to reject supply noise, add external resistors and capacitors RF and CF to the sense circuit as shown in Figure 13.

The ON Pin

The ON pin is used to control system operation as shown in Figure 14. At time point 1, the board makes connection and the supplies power up the chip. At time point 2, the ON pin goes high and a timer cycle starts as long as both V

pins are higher than the undervoltage lockout trip point (2.23V for V

and 1.12V for V

CC1

) and an overcurrent

CC2

fault is not detected. At the end of the timer cycle (time point 3), the charge pump is turned on and the GATEn pin voltages start to ramp up with the output supply voltages, V

, following one gate-to-source voltage drop lower.

OUT

At time point 4, V

reaches its power-good trip level

OUT2

(this example assumes the FB pin resistive divider is connected to V

) and a timing cycle starts. At the end

OUT2

of the timing cycle (time point 5), RESET goes high and the power-up process is complete.

RAMPING UP AND DOWN TOGETHER

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

RAMPING UP AND

DOWN SEPARATELY

RAMPING UP AND

TURNING OFF FAST

OUT

RESET

1645 F12

Figure 12. Current Fault Timing

SENSE

GATE

LTC1645

1645 G13

Figure 13. Extending the Short-Circuit Protection Delay

TIMER

GATE1

OUT1

GATE2

OUT2

RESET

0.8V

0.4V

1645 F14

Figure 14. ON Pin Waveforms

LTC1645

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APPLICATIO S I FOR ATIO

An external hard reset is initiated at time point 6. The ON pin is forced below 0.8V but above 0.4V, and the GATE pin voltages start to ramp down. V down, and RESET goes low when V

also starts to ramp

OUT

drops below the

OUT2

power-good trip level at time point 7. Time points 8 to 15 are similar to time points 1 to 7, except

the ON pin’s different voltage thresholds are used to ramp V

OUT1

and V

separately. At time point 8, the ON pin

OUT2

goes above 0.8V but below 2V, and one timing cycle later (time point 9) GATE1 begins to ramp up with V

OUT1

following one gate-to-source voltage drop lower. At time point 10, the ON pin goes above 2V and GATE2 immediately begins ramping up with V source voltage drop lower. As soon as V

following one gate-to-

OUT2

reaches its

OUT2

power-good trip level at time point 11, a timing cycle starts. At the end of the timing cycle (time point 12), RESET goes high and the power-up process is complete.

The ON pin is forced below 2V but above 0.8V at time point 13 and the GATE2 pin voltage starts to ramp down. V also starts to ramp down and RESET goes low when V

OUT2 OUT2

drops below the power-good trip level at time point 14. When the ON pin goes below 0.8V but above 0.4V at time point 15, GATE1 and V

ramp down.

OUT1

Time points 16 to 19 show the same power-up sequence as time points 2 to 5, while time point 20 demonstrates the GATEn pins being pulled immediately to ground (instead of ramping down) by the ON pin going below 0.4V.

Power Supply Tracking and Sequencing Applications

The LTC1645 is able to sequence V ways, including ramping V ramping V first and V V

and V

OUT1

up first and down first; ramping V

OUT1

and V

OUT1

OUT2

up and down together.

up first and down last;

OUT1

down together; and ramping

Figure 15 shows an application ramping V

in a number of

OUT

and V

OUT1

OUT2

up and down together. The ON pin must reach 0.8V to ramp up V ON pin low until V reach 0.8V before V

OUT1

and V

CC2

. The spare comparator pulls the

OUT2

is above 2.3V, and the ON pin cannot

is above 3V. Thus, both input

CC1

supplies must be within regulation before a timing cycle can start. At the end of the timing cycle, the output voltages ramp up together. If either input supply falls out of regulation, the gates of Q1 and Q2 are pulled low together. Figure 16 shows an oscilloscope photo of the circuit in Figure 15.

BOTH CURRENT LIMITS: 5A

IN1

3.3V

IN2

2.5V

TRIP

POINT:

1.18k 1%

1.37k 1%

10k

4.99k 1%

1.82k 1%

*WSL1206-01-1% (VISHAY DALE)

0.01Ω*

13 1214

SENSE1 GATE2GATE1

CC1

FAULT

TIMER GND

0.33µF

LTC1645

(14-LEAD)

CC2

0.01Ω*

SENSE2

1/2 Si4920DY

COMP

COMPOUT

1/2 Si4920DY

10Ω

RESET

D1 1N4002

0.1µF 25V

1645 F15

D2 1N4002

1.18k 1%

1.37k 1%

10Ω

Figure 15. Ramping 3.3V and 2.5V Up and Down Together

D3 MBR0530T1

10k

LOAD1

LOAD2

µP RESET

OUT1

3.3V

2.5A

OUT2

2.5V

2.5A

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APPLICATIO S I FOR ATIO

IN2

5V/DIV

IN1

5V/DIV

OUT2

5V/DIV

OUT1

5V/DIV

TIMER

2V/DIV

RESET

5V/DIV

Figure 16. Ramping 3.3V and 2.5V Up and Down Together

LTC1645

This circuit guarantees that: (1) V V

by more than 1.2V, and (2) V

OUT2

than V V

OUT2

by more than 0.4V. On power-up, V

OUT1

ramp up together. On power-down, the LTC1645

never exceeds

OUT1

is never greater

OUT2

OUT1

and

turns off Q1 and Q2 simultaneously. Charge remains stored on C

LOAD1

and C

and the output voltages will

LOAD2

vary depending on the loads. D1 and D2 turn on at ≈1V (≈0.5V each), ensuring condition 1 is satisfied, while D3 prevents violations of condition 2. Different diodes may be necessary for different output voltage configurations. Barring an overvoltage condition at the input(s), the only time these diodes might conduct current is during a power-down event, and then only to discharge C C

. In the case of an input overvoltage condition that

LOAD2

LOAD1

causes excess current to flow, the circuit breaker will trip if the current limit level is set appropriately.

Figure 17 shows an application circuit where V ramps up before V

OUT2

. V

is initially discharged and

OUT1

D1 is reverse-biased, thus the voltage at the ON pin is determined only by V and R2. The voltage at the ON pin exceeds 0.8V if V above 4.6V and V cycle. As V

OUT1

ramps up, D1 becomes forward-biased and pulls the ON pin above 2V when V turns on GATE2 and V monitors V V

with R

OUT1

, and the spare comparator monitors

OUT2

creating ≈50mV of hysteresis.

HYST

through the resistor divider R1

CC1

begins to ramp up after a timing

≈ 4.5V. This

OUT1

ramps up. The FB comparator

OUT2

Power Supply Multiplexer

Using back-to-back FETs, the LTC1645 can Hot Swap two supplies to the same output, automatically selecting the primary supply if present or the secondary supply if the primary supply is not available. Referring to Figure 18, a diode-or circuit provides power to the LTC1645 if either supply is up. Schottky diodes are used to prevent the voltage at V

from approaching the undervoltage lock-

CC1

out threshold. This application assumes that if a supply is not present, the supply input is floating.

If only the 3.3V supply is present, the voltage at the COMP

pin is below the trip point and COMPOUT pulls the base of Q3 low, allowing the GATE1 pin to ramp up normally. The voltage at the ON pin exceeds 0.8V if the 3.3V supply is greater than 3V, ramping up GATE1 and turning on Q1A and Q1B. The ON pin does not exceed 2V (unless the 3.3V supply exceeds 7.5V!), keeping GATE2 low and Q2A and Q2B off.

If only the 5V supply is present or if both supplies are present, the COMP+ pin is above 1.238V and COMPOUT allows the base of Q3 to be pulled high by R2. This turns Q3 on, keeping GATE1 low and Q1A and Q1B off. The voltage at the ON pin is pulled above 2V by R1 and GATE2 turns Q2A and Q2B on.

LTC1645

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APPLICATIO S I FOR ATIO

IN2

3.3V

IN1

10k

FAULT

*LRF1206-01-R005-J (IRC)

BOTH CURRENT LIMITS: 10A

D1 1N4148

13k 1%

47.5k 1%

R2 10k 1%

FAULT

0.005Ω*

SENSE1

CC1

IRF7413

1314

GATE1

TIMER GND

10Ω

LTC1645

(14-LEAD)

0.33µF

0.01µF 25V

0.005Ω*

112

CC2

SENSE2

IRF7413

GATE2

COMP

COMPOUT

RESET

10Ω

R 681k

9 6

Figure 17. Ramping Up 5V Followed by 3.3V

0.01µF 25V

HYST

28k 1%

10k 1%

10k 10k

14.7k 1%

10k 1%

1645 F17

LOAD2

LOAD1

µP RESET2

µP RESET

OUT2

3.3V 5A

OUT1

5V 5A

IN1

3.3V

IN2

Q1A Q1B

IRF7313

D1 1/2 BAT54C

D2 1/2 BAT54C

SENSE1

CC1

TIMER GND

0.33µF

10k

22.6k 1%

11.3k 1%

FAULT

1314

10Ω

GATE1

LTC1645

(14-LEAD)

CC2

0.1µF 25V

112

Q2A Q2B

SENSE2

COMPOUT

IRF7313

GATE2

COMP

RESET

10Ω

OUT

5V OR

3.3V 5A

R2 10k

0.1µF 25V

1645 F18

Q3 PN2222

Figure 18. Power Supply Multiplexer

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APPLICATIO S I FOR ATIO

LTC1645

Using the LTC1645 as a Linear Regulator

This application uses the LTC1645 to Hot Swap one primary supply and generate a secondary low dropout regulated supply. Figure 19 shows how to switch a 5V supply and create a 3.3V supply using the spare comparator and one additional transistor. The COMP+ pin is used to monitor the 3.3V output. As the voltage on the gate of Q2 increases, the 3.3V output increases. At the 3.3V threshold the spare comparator trips. The COMPOUT pin

1314

IRF7413

0.33µF

10Ω

LTC1645

(14-LEAD)

0.1µF 25V

0.01Ω*

CC2

BOTH CURRENT LIMITS: 5A

IRFZ24

10Ω

COMPOUT

GATE2 COMP

RESET

SENSE2GATE1

0.01Ω*

10k

SENSE1

CC1

FAULT

TIMER GND

goes high which turns on Q3. This lowers the voltage on the gate of Q2. This feedback loop is compensated by capacitors C1 and C2 and resistor R1. When power is first applied, the FB pin is low and RESET holds one side of C2 low, slowing the ramp-up of V

OUT2

. As V

OUT2

exceeds

2.75V, RESET releases to allow improved loop transient response. Figure 20 shows the load transient response and voltage ripple of the generated supply.

OUT1

12.1k 1%

10k 1%

1645 F19

2.5A

3.3V

2.5A

OUT2

R1 200k

Q3 PN2222

0.1µF 25V

LRF1206-01-R010-J (IRC)

T510X477K006AS (KEMET)

2.49k 1%

0.033µF

1.5k 1%

LOAD1

470µF** 6V ×2

Figure 19. Switching 5V and Generating 3.3V

OUT2

0.1V/DIV

2.5A

OUT2

1A/DIV

0.5A

Figure 20. Load Transient Response and Voltage Ripple

LTC1645

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APPLICATIO S I FOR ATIO

Switching Regulator Supply Sequencing

Figure 21 shows the LTC1645 sequencing two power supplies, the lower of which is generated by the LTC1430A switching regulator. Connecting the regulator’s FB pin resistor divider (R1 and R2) to the other side of the pass FET (Q1) allows the LTC1430A to compensate for the voltage drop across R

SENSE1

and Q1, assuring an accurate voltage output. The spare comparator holds the LTC1645’s ON pin low until the LTC1430A’s output is at least 3V, and shuts both channels off if it drops below 3V. When the ON/OFF signal is taken high to 5V (turn-on), the voltage at the ON pin rises with an RC exponential characteristic, reaching 0.8V first. This starts a timing cycle, and GATE1 begins to rise. GATE2 starts to ramp up after the ON pin reaches 2V. As long as the timing cycle is shorter than the time for the ON pin to rise from 0.8V to 2V, V up after V V

exceeds 3V. When the ON/OFF signal is brought

OUT1

. RESET goes high one timing cycle after

OUT1

OUT2

ramps

low, the voltage at the ON pin exponentially decays and GATE2 ramps down before GATE1. RESET goes low as soon as V

falls below 3V. Figure 22 shows the power-

OUT1

up and power-down sequences of the circuit in Figure 21.

Switching Regulator Hot Swapping

High current switching regulators usually require large bypass capacitors on both input and output for proper operation. The application in Figure 23 controls the inrush current to the LTC1649’s input bypass capacitors and ramps the two output voltages up and down together. As with the previous application, connecting the regulator’s FB pin resistor divider to the other side of the output pass FET (Q2) allows the LTC1649 to compensate for the voltage drop across Q2, assuring an accurate voltage output. The voltage at the LTC1645’s ON pin reaches 0.8V when VIN exceeds 3V, and GATE1 begins to ramp up one timing cycle later. As the regulator’s output rises, D2 pulls the ON pin above 2V and GATE2 begins to rise, ramping V

and V

OUT1

cycle after V

up together. RESET goes high one timing

OUT2

exceeds 3V and V

OUT1

exceeds 2.35V.

OUT2

Figure 24 shows the circuit in Figure 23 powering up. Care should be taken connecting a switching regulator’s

FB or SENSE pins to a node other than its output. Depending on the regulator’s internal architecture, unusual behavior may occur as it tries in vain to raise the voltage at

2V/DIV

REGOUT

2V/DIV

OUT1

2V/DIV

OUT2

2V/DIV

RESET

5V/DIV

Figure 22. Switching Regulator Supply Sequencing

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APPLICATIO S I FOR ATIO

LTC1645

OUT2

1/2 Si4920DY

SENSE2

0.01Ω

2.5A

LOAD2

OUT1

3.3V

2.5A

LOAD1

0.047µF

25V

10Ω

0.047µF

SENSE1

16.5k

16.9k

10Ω

1/2 Si4920DY

0.01Ω

1µF

25V

1314

2.67k

10k

GATE2

COMP

SENSE2

CC2

GATE1

SENSE1

CC1

3.16k

1.87k

COMPOUT

LTC1645

(14-LEAD)

1µF

RESET

1645 F21

1.15k

RESET

0.33µF

TIMER GND

FAULT

1500µF

6.3V

1µF

MBR0530T1

51Ω

× 3

680pF

143

CC1

CC2

LTC1430ACS8

856

2.4µH

CDRH1272R4

0.1µF

Si4410DY

SHDN

22k

REGOUT

GND

COMP

1500µF

6.3V

1Ω

Si4410DY

4700pF

× 2

4700pF

MBRS130T3

0.1µF

10V

15µF

270pF

162k

130k

*LRF1206-01-R010-J (IRC)

Figure 21. Switching Regulator Supply Sequencing

10k

ON/OFF

FAULT

LTC1645

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APPLICATIO S I FOR ATIO

REGIN

FDB8030L

†

1µF

IRF7801

1500µF

6.3V

OUT2

FDB8030L

REGOUT

1.2µH

× 6

10Ω

2.5V

15A

GND

LOAD2

10Ω

1µF

1500µF

6.3V

× 4

2200pF

5.1Ω

IRF7801

16151413121110

1234567

0.1µF

MBR0530LT1

3.09k

3.01k

0.01µF

1N4148

1.8k

18k

CC2

MAX

CC1

LTC1649

GNDFBSHDNSSVINC

100k

10µF

COMP

0.33µF

0.1µF

CPOUT

0.33µF

OUT1

3.3V

10A

LOAD1

220pF

33k

0.015µF

100µF

1.02k

1.13k

2.67k

10k

0.047µF

25V

1.87k

RESET

1645 F23

GATE2

SENSE2

CC2

GATE1

SENSE1

CC1

4.99k

MBR0530T1

RESET

1.82k

1µF

220Ω

–

0.1µF

MBR0530LT1

0.33µF

0.003Ω*

FDS6680

10Ω

112

25V

0.01µF

1314

COMP

LTC1645

(14-LEAD)

COMPOUT

FAULT

TIMER GND

0.01µF

Figure 23. Switching Regulator Hot Swap

0.003Ω*

10k

3.3V

GND

ETQP6F1R2HFA (PANASONIC)

†

*LRF2010-01-R003-J (IRC)

**MBRS340T (ON SEMICONDUCTOR)

FAULT

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APPLICATIO S I FOR ATIO

2V/DIV

REGIN

2V/DIV

REGOUT

2V/DIV

OUT2

2V/DIV

OUT1

2V/DIV

RESET

5V/DIV

Figure 24. Switching Regulator Hot Swap

its FB or SENSE pin. In the case of the LTC1649, large peak currents result if the FB pin is at ground and not connected directly to the output inductor and capacitors. To keep the peak currents under control, R1, R2 and D1 hold the FB pin above ground but below its normal regulated value until V

ramps up and D1 reverse-biases.

OUT2

Power N-Channel Selection

The R enough so that the voltage drop across them is 100mV or less at full current. If the R drop across the transistor can cause the output voltage to trip the reset circuit. The transistors listed in Table 1 or other similar transistors are recommended for use with the LTC1645.

Low voltage applications may require the use of logic-level FETs; ensure their maximum VGS rating is sufficient for the application. GATE voltage as a function of VCC is illustrated in the Typical Performance curves. If lower GATE drive is desired, connect a diode in series with a zener between GATE and VCC or between GATE and V Figure 25.

of the external pass transistors must be low

DS(ON)

is too high, the voltage

DS(ON)

as shown in

OUT

LTC1645

Table 1. N-Channel Selection Guide

CURRENT PART

LEVEL NUMBER MANUFACTURER DESCRIPTION

1A to 2A NDH8503N Fairchild Dual N-Channel

= 0.033

DS(ON)

SuperSOT-8

1A to 2A Si6928DQ Siliconix Dual N-Channel

= 0.035

DS(ON)

TSSOP-8

2A to 5A Si4920DY Siliconix Dual N-Channel

= 0.025

DS(ON)

SO-8

2A to 5A IRF7313 International Dual N-Channel

Rectifier R

5A to 10A Si4420 Siliconix Single N-Channel

5A to 10A FDS6680 Fairchild Single N-Channel

5A to 10A IRF7413 International Single N-Channel

Rectifier R

5A to 10A MMSF3300 ON Semiconductor Single N-Channel

10A to 20A FDB8030L Fairchild Single N-Channel

10A to 20A SUD75N03-04 Siliconix Single N-Channel

D1*D21N4148 D4*

*USER SELECTED VOLTAGE CLAMP 1N4688 (5V) 1N4692 (7V): LOGIC-LEVEL MOSFET 1N4695 (9V) 1N4702 (15V): STANDARD-LEVEL MOSFET

1N4148

Figure 25. Optional Gate Clamp

= 0.029

DS(ON)

SuperSOT-8

= 0.009

DS(ON)

SO-8

= 0.01

DS(ON)

SO-8

= 0.011

DS(ON)

SO-8

= 0.0125

DS(ON)

SO-8

= 0.0035

DS(ON)

TO-263AB

= 0.004

DS(ON) 2

PAK

OUT

1645 F25

LTC1645

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.189 – 0.197* (4.801 – 5.004)

0.228 – 0.244

(5.791 – 6.197)

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

× 45°

(1.346 – 1.752)

0°– 8° TYP

0.016 – 0.050

(0.406 – 1.270)

0.053 – 0.069

0.014 – 0.019

(0.355 – 0.483)

TYP

0.150 – 0.157** (3.810 – 3.988)

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

SO8 1298

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

S Package

14-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.337 – 0.344* (8.560 – 8.738)

LTC1645

0.228 – 0.244

(5.791 – 6.197)

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

× 45°

0° – 8° TYP

0.016 – 0.050

(0.406 – 1.270)

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

TYP

0.150 – 0.157** (3.810 – 3.988)

0.050

(1.270)

BSC

0.004 – 0.010

(0.101 – 0.254)

S14 1298

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1645

TYPICAL APPLICATIO

Dual Supply Hot Swap with Tracking Outputs

BOTH CURRENT LIMITS: 5A

IN1

3.3V

IN2

2.5V

TRIP

POINT:

1.18k 1%

1.37k 1%

10k

4.99k 1%

1.82k 1%

*WSL1206-01-1% (VISHAY DALE)

0.01Ω*

13 1214

SENSE1 GATE2GATE1

CC1

FAULT

TIMER GND

0.33µF

LTC1645

(14-LEAD)

CC2

0.01Ω*

SENSE2

1/2 Si4920DY

COMP

COMPOUT

RESET

1/2 Si4920DY

10Ω

0.1µF 25V

1645 F15

D1 1N4002

D2 1N4002

1.18k 1%

1.37k 1%

D3 MBR0530T1

10k

LOAD1

LOAD2

µP RESET

3.3V

2.5A

2.5V

2.5A

OUT1

OUT2

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1421 Hot Swap Controller Dual Supplies from 3V to 12V, Additionally –12V LTC1422 Hot Swap Controller Single Supply Hot Swap in SO-8 from 3V to 12V LT1640L/LT1640H Negative Voltage Hot Swap Controllers Negative High Voltage Supplies from –10V to –80V LT1641 Positive Voltage Hot Swap Controller Positive High Voltage Supplies From 9V to 80V LTC1642 Fault Protected Hot Swap Controller 3V to 15V, Overvoltage Protection Up to 33V LTC1643L/LTC1643L-1/ PCI-Bus Hot Swap Controllers 3.3V, 5V, 12V, –12V Supplies for PCI Bus

LTC1643H LTC1647 Dual Hot Swap Controller Dual ON Pins for Supplies from 3V to 15V

1645f LT/TP 0400 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1999

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear-tech.com

Datasheet LTC1645 Datasheet (Linear Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual