Datasheet LTC1642 Datasheet (Linear Technology)

Final Electrical Specifications

FEATURES

■

Single Channel Positive NFET Driver

■

Programmable Undervoltage and Overvoltage
Protection

■

Foldback Current Limit

■

Adjustable Current Limit Time-Out

■

Latch Off or Automatic Retry on Current Fault

■

Driver for SCR Crowbar on Overvoltage

■

Programmable Reset Timer

■

Reference Output with Uncommitted Comparator

■

VCC: 2.97V to 16.5V Normal Operation, Protected
Against Surges to 33V.

■

16-Pin SSOP Package

U

APPLICATIO S

■

Hot Board Insertion

■

Electronic Circuit Breaker

LTC1642

Hot Swap Controller

May 1999

U

DESCRIPTIO

TM

The LTC®1642 is a 16-pin Hot Swap
allows a board to be safely inserted and removed from a
live backplane. Using an external N-channel pass transis­tor, the board supply voltage can be ramped up at a
programmable rate. A high side switch driver controls the
N-channel gate for supply voltages ranging from 2.97V to

16.5V.
The SENSE pin allows foldback limiting of the load current,

with circuit breaker action after a programmable delay
time. The delay allows the part to power-up in current
limit. The CRWBR output can be used to trigger an SCR
for crowbar load protection after a programmable delay if
the input supply exceeds a programmable voltage. The
RESET output can be used to generate a system reset with
programmable delay when the supply voltage falls below
a programmable voltage. The ON pin can be used to cycle
the board power. The LTC1642 is available in the 16-pin
SSOP package.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Hot Swap is a trademark of Linear Technology Corporation.

controller that

TYPICAL APPLICATIO

12V

R5

110k

1%

LATCH OFF: FLOAT FAULT
AUTOMATIC RETRY: TIE FAULT TO ON

UNDERVOLTAGE = 10.8V

R6

2.87k
1%

OVERVOLTAGE = 13.2V

R7

11.3k

RESET TIME = 200ms
CURRENT LIMIT TIME = 20ms
CROWBAR TIME = 90µs

1%

U

R1

0.010Ω
5%

C7

0.1µF

16 15 14

V

CC

10

COMPOUT

4

6

9

ON

FAULT

OV

GND BRK TMR

D1

1N4148

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

SENSE GATE

LTC1642

823

C3

0.33µF

Q1

FDR9410A

R2

100Ω

5%

RST TMR

RESET

CRWBR

COMP
COMP

REF

C2

0.33µF

FB

–

+

0.1µF

R8

330Ω

5%

5
7
1
12
11
13

C5

C1

0.047µF

Q2

2N2222

220Ω

C6

0.01µF

R9 REQUIRED ONLY WITH SENSITIVE GATE SCRs,

NOT NEEDED WITH MCR12

5%

12V
AT 2.5A

+

C

LOAD

R3
107k
1%

POWER-GOOD = 11.4V

Q3
MCR
12DC

R4
13k

R9

1%

1642 TA01

1

LTC1642

WW

W

ABSOLUTE AXI U RATI GS

U

UUW

PACKAGE/ORDER I FOR A TIO

(Note 1)

Supply Voltage (VCC) .................................–0.3V to 33V

SENSE Pin ................................... –0.3V to (VCC + 0.3V)

GATE Pin ...................................................–0.3V to 27V

All Other Pins..........................................–0.3V to 16.5V

Operating Temperature Range

LTC1642C ...............................................0°C to 70°C

LTC1642I............................................ –40°C to 85°C

Storage Temperature Range................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

TOP VIEW

1

CRWBR
BRK TMR
RST TMR

ON
RESET
FAULT

GND

2
3
4
5
6
7

FB

8

GN PACKAGE

16-LEAD PLASTIC SSOP

T

= 150°C, θJA = 130°C/W

JMAX

16
15
14
13
12
11
10

9

V

CC

SENSE
GATE
REF
COMP
COMP
COMPOUT
OV

Consult factory for Military grade parts.

–
+

ORDER PART

NUMBER

LTC1642CGN
LTC1642IGN

DC ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

CC

V

LKHI

V

LKLO

V

LKHYST

V

CC

V

FB

∆V

FB

V

FBHST

V

OV

∆V

OV

V

OVHYST

V

RST

∆V

RST

I

RST

V

BRK

∆V

BRK

I

BRK

V

CR

∆V

CR

I

CR

VCC Supply Current ON = V
V

Undervoltage Lockout (Low to High) ● 2.55 2.73 2.95 V

CC

V

Undervoltage Lockout (High to Low) ● 2.35 2.50 2.80 V

CC

V

Undervoltage Lockout Hysteresis 230 mV

CC

CC

● 1.25 3.0 mA

Operating Voltage Range 2.97 16.5 V
FB Pin Voltage Threshold (FB Falling) ● 1.208 1.220 1.232 V
FB Pin Threshold Line Regulation 2.97V ≤ VCC ≤ 16.5V ● 515 mV
FB Pin Voltage Threshold Hysteresis 3 mV
OV Pin Voltage Threshold (OV Rising) ● 1.208 1.220 1.232 V
OV Pin Threshold Line Regulation 2.97V ≤ VCC ≤ 16.5V ● 515 mV
OV Pin Voltage Theshold Hysteresis 3 mV
RST TMR Pin Voltage Threshold (RST TMR Rising) ● 1.200 1.220 1.250 V
RST TMR Pin Threshold Line Regulation 2.97V ≤ VCC ≤ 16.5V ● 515 mV
RST TMR Pin Current Timer On ● –2.5 –2.0 –1.5 µA

Timer Off, V

= 1.5V 10 mA

RSTTMR

BRK TMR Pin Voltage Threshold (BRK TMR Rising) ● 1.200 1.220 1.250 V
BRK TMR Pin Threshold Line Regulation 2.97V ≤ VCC ≤ 16.5V ● 515 mV
BRK TMR Pin Current Timer On ● –30 –20 –15 µA

Timer Off, V

= 1.5V 10 mA

BRKTMR

CRWBR Pin Voltage Theshold ● 375 410 425 mV
CRWBR Pin Threshold Line Regulation 2.97V ≤ VCC ≤ 16.5V ● 415 mV
CRWBR Pin Current CRWBR On, V

CRWBR On, V
CRWBR Off, V

= 0V ● –60 –45 –30 µA

CRWBR

= 2.1V ● –1500 –1000 µA

CRWBR

= 1.5V 2.3 mA

CRWBR

2

LTC1642

DC ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

CB

I

CP

∆V

GATE

V

ONHI

V

ONLO

V

ONHYST

V

OL

I

PU

V

REF

∆V

LNR

∆V

LDR

I

RSC

V

COS

V

CHYST

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Circuit Breaker Trip Voltage VCB = (VCC – V

= (VCC – V

V

CB

GATE Pin Output Current Charge Pump On, V

Charge Pump Off, V

External N-Channel Gate Drive V

ON Pin Threshold (Low to High) 1.30 1.34 1.38 V
ON Pin Threshold (High to Low) ● 1.20 1.22 1.26 V
ON Pin Hysteresis 110 mV
Output Low Voltage RESET, FAULT, COMPOUT IO = 1.5mA ● 0.4 V
Logic Output Pull-Up Current RESET, FAULT = GND –15 µA
Reference Output Voltage No Load ● 1.208 1.220 1.232 V
Reference Line Regulation 2.97V ≤ VCC ≤ 16.5V, No Load ● 515 mV
Reference Load Regulation IO = 0mA to –1mA, Sourcing Only ● 2.5 7.5 mV
Reference Short-Circuit Current V
Comparator Offset Voltage VCM = V
Comparator Hysteresis VCM = V

– V

GATE

CC, VCC

– V

V

GATE

CC, VCC

– V

V

GATE

CC, VCC

= 0V 4.5 mA

REF

REF

REF

), VFB = GND ● 15 25 36 mV

SENSE

), VFB = 1V ● 45 52.5 60 mV

SENSE

= GND ● –30 –25 –20 µA

GATE

= 5V 10 mA

GATE

= 3V ● 4.5 5.9 8.0 V
= 5V ● 10 11.5 14 V
= 15V ● 4.5 8.5 18 V

● ±10 mV

3mV

UUU

PI FU CTIO S

CRWBR (Pin 1): Combination Overvoltage Timer and
Crowbar Circuit Trigger. The timer sets the overvoltage
time needed to trigger the crowbar circuit. To use the timer
connect a capacitor C to ground; the trigger time is
9ms•C(µF). When the timer is off an internal N-channel
pulls the pin to ground. The timer is started when the OV
comparator trips. A 45µA current source is connected
from VCC to the CRWBR pin, and the voltage increases at
a rate of 45/C(µF) Volts/second. When the voltage reaches
410mV the current sourced by the pin increases to 1.5mA.
Boost this current with an NPN emitter follower to trigger
a crowbar SCR.

BRK TMR (Pin 2): Analog Timer which Limits the Time the
Part Remains In Current Limit. To use the timer connect a
capacitor from BRK TMR to ground. BRK TMR is pulled to
ground until the sense resistor current reaches its limit,

when the pin begins sourcing 20µA and the pin voltage
increases at a rate of 20/C(µF) Volts/second. When the pin
reaches 1.23V the GATE pin is pulled to ground and the
FAULT output is asserted until the chip is reset. To allow
the part to remain in current limit indefinitely ground BRK
TMR.

RST TMR (Pin 3): Analog System Timer. To use the timer
connect a capacitor from RST TMR to ground. This timer
sets the delay from the ON pin going high to the start of the
GATE pin’s ramp; it also sets the delay from output voltage
good, as sensed by the FB pin, to RESET going high. When
the timer is off, an internal N-channel shorts RST TMR to
ground. When the timer is turned on a 2µA current from
VCC is connected and the RST TMR pin voltage starts to
ramp up at a rate of 2/C(µF) Volts/second. The timer trips
when the voltage reaches 1.23V.

3

LTC1642

UUU

PI FU CTIO S

ON (Pin 4): Control. When ON is low the GATE pin is
grounded and FAULT goes high. The GATE pin voltage
starts ramping up one RST TMR timing cycle after ON
goes high. Pulsing the ON pin low for at least 2µs also
resets the chip when it latches off after a sustained
overvoltage or current limit. The threshold on a low to high
transition is 1.34V with 110mV of hysteresis.

RESET (Pin 5): Open Drain Output. RESET is pulled low if
the voltage at the FB pin is below its trip point and goes
high one timing cycle after the FB voltage exceeds its trip
point plus 3mV of hysteresis. RESET has a weak pull-up to
one diode drop below VCC; an external resistor can pull the
pin above VCC.

FAULT (Pin 6): Open Drain Output. FAULT is pulled low
when the part latches itself off following a sustained
overvoltage or current limit. It goes high 2µs after the ON
pin goes low. FAULT has a weak pull-up to one diode drop
below VCC; an external resistor can pull the pin above VCC.

FB (Pin 7): Noninverting Input to An Analog Comparator;
the inverting input is tied to the 1.23V internal reference.
The FB comparator can be used with an external resistive
divider to monitor the output supply voltage. When the FB
voltage is lower than 1.23V the RESET pin is pulled low.
RESET goes high one system timing cycle after the voltage
at FB exceeds its threshold by 3mV of hysteresis. A low
pass filter at the comparator’s output prevents negative
voltage glitches from triggering a false reset.

GND (Pin 8): Chip Ground.
OV (Pin 9): Analog Input Used to Monitor Overvoltages.

When the voltage on OV exceeds its trip point the GATE pin
is pulled low immediately and the CRWBR timer starts. If
OV remains above its trip point (minus 3mV of hysteresis)
long enough for CRWBR to reach its trip point the part
latches off until reset by pulsing the ON pin low; otherwise,
the GATE pin begins ramping up one RST TMR timing
cycle after OV goes below its trip point.

COMPOUT (Pin 10): Uncommitted Comparator’s Open
Drain Output.

COMP– (Pin 12): Uncommitted Comparator’s Inverting
Input.

REF (Pin 13): The Reference Voltage Output, 1.232V
±2%. To ensure stability the pin should be bypassed with
a 0.1µF compensation capacitor. For VCC = 5V it can
source 1mA.

GATE (Pin 14): High Side Gate Drive for the External
N-Channel. An internal charge pump provides at least 4.5V
of gate drive, but can only source 25µA. The pin requires
an external series RC network to ground to compensate
the current limit loop, and to limit the maximum voltage
ramp which is dV/dt (V/s) = 25/C(µF). GATE is immediately
pulled to ground when the overvoltage comparator trips or
the input supply is below the undervoltage lockout trip
point. During current limit the GATE voltage is adjusted to
maintain constant load current until the BRK TMR pin
trips, when the pin is pulled to ground until the chip is
reset.

SENSE (Pin 15): Current Limit Set. To use the current limit
place a sense resistor in the supply path between VCC and
SENSE. Should the drop across the resistor exceed a
threshold voltage the GATE pin is adjusted to maintain a
constant load current and the timer at the BRK TMR pin is
started. To protect the external FET from thermal damage
the circuit breaker trips after the BRK TMR timing cycle. A
foldback feature makes the current limit decrease as the
voltage at FB approaches ground. Figure 3 quantifies the
relationship. To disable the current limit short SENSE to
VCC.

VCC (Pin 16): Positive Supply Voltage; between 2.97V and

16.5V in normal operation. An internal undervoltage lock­out circuit holds the GATE pin at ground until VCC exceeds

2.73V. If VCC exceeds 16.5V an internal shunt regulator
protects the chip from VCC and SENSE pin voltages up to
33V. When the internal shunt regulator is active and the
charge pump is on the GATE pin voltage will usually be low
but this is not guaranteed; use the OV pin to ensure that the
pass device is off. The VCC pin also provides a Kelvin
connection to the high side of the SENSE resistor.

COMP+ (Pin 11): Uncommitted Comparator’s Noninvert­ing Input.

4

LTC1642

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APPLICATIO S I FOR ATIO

Hot Circuit Insertion

When a circuit board is inserted into a live backplane its
supply bypass capacitors can draw large currents from the
backplane power bus as they charge. These currents can
permanently damage connector pins and can glitch the
backplane supply, resetting other boards in the system.
The LTC1642 limits the charging currents drawn by a
board’s capacitors, allowing safe insertion in a live
backplane.

Power Supply Ramping

In the circuit shown in Figure 1 the LTC1642 and the
external N-channel pass transistor Q1 work together to
limit charging currents. When power is first applied to V
the chip holds Q1’s gate at ground. After a programmable
delay a 25µA current source begins to charge the external
capacitor C2, generating a voltage ramp of 25µA/C2 V/s at
the GATE pin. Because Q1 acts as a source follower while
its gate ramps, the current charging the board’s bypass
capacitance C

is limited to 25µA•C

LOAD

LOAD

/C2.

An internal charge pump supplies the 25µA gate current,
ensuring sufficient gate drive to Q1. At 3V VCC the mini­mum gate drive is 4.5V; at 5V VCC the minimum is 10V; at
15V VCC the minimum is again 4.5V, due to a Zener clamp
from the GATE pin to ground. Resistor R3 limits this
Zener’s transient current during board insertion and re­moval and protects against high frequency FET oscilla­tions.

V

IN

12V

2.5A
C7

0.1µF

0.33µF

ALL RESISTORS ±5% UNLESS NOTED
RESET DELAY = 200ms
SHORT-CIRCUIT DURATION = 20ms

R1
10k

4

2

C4

0.33µF

Figure 1. Supply Control Circuitry

V

CC

BRK TMR

RST TMR

C1

R2

0.010Ω

16

LTC1642

3

SENSE

GATEON

RESET

GND

15

Q1

FDR9410A

+

R3
100Ω

14

R4
330Ω

C2

0.047µF

5

8

C

LOAD

1642 F01

CC

V

OUT

The delay before the GATE pin voltage begins ramping is
determined by the system timer. It comprises an external
capacitor C1 from the RST TMR pin to ground; an internal
2µA current source feeding RST TMR from VCC; an internal
comparator, with the positive input tied to RST TMR and
the negative input tied to the 1.23V reference; and an
NMOS pull-down. In standby, the NMOS holds RST TMR
at ground; when the timer starts the NMOS turns off and
the RST TMR voltage ramps up as the current source
charges the capacitor. When RST TMR reaches 1.23V the
timer comparator trips; the GATE voltage begins ramping
and RST TMR returns to ground. The ramp time ∆t needed
to trip the comparator is : ∆t(ms) = 615•C1(µF).

V

IN

RST TMR

VOLTS

GATE
SLOPE = 25µA/C(V/s)

V

OUT

TIME

1642 F02

Figure 2. Supply Control Timing

Powering-Up In Current Limit

Ramping the GATE pin voltage
ing current to I = 25µA•C
capacitor connected to the GATE and C
capacitance. If the value of C

indirectly

/C2, where C2 is the external

LOAD

LOAD

limits the charg-

is the load

LOAD

is uncertain, then a
worst-case design can often result in needlessly long
ramp times, and it may be better to limit the charging
current directly.

Current Limiting and Solid-State Circuit Breaker

The board current can be limited by connecting a sense
resistor between the LTC1642’s VCC and SENSE pins. An
internal servo loop adjusts the GATE pin voltage such that
Q1 acts as a constant current source if the voltage drop
across the sense resistor reaches a limit. The voltage limit
across the sense resistor increases as the output charges

5

LTC1642

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APPLICATIO S I FOR ATIO

up; this “foldback” limiting tends to keep the power
dissipation in the N-channel pass transistor constant. The
output voltage is sensed at the FB pin. The limiting sense
resistor voltage is 23mV when FB is grounded, but in­creases gradually to 53mV when FB exceeds 1V; Figure 3
shows the full dependence.

When the sense resistor voltage reaches its limit, a circuit
breaker timer starts. This timer uses the BRK TMR pin and
has a 1.23V threshold. If BRK TMR reaches 1.23V the
timer comparator trips, tripping the circuit breaker; if the
sense resistor voltage falls below its limit before the
comparator trips the GATE voltage begins ramping back
up immediately. The ramp time ∆t needed to trip the
comparator is ∆t(ms) = 62•C(µF), where C is the external
capacitance.

Once the circuit breaker trips, GATE and FAULT remain at
ground until the chip is restarted. To restart, hold the ON
pin low for at least 2µs and FAULT will go high. Then take
ON high again and the GATE will ramp up after a system
timing cycle. Or, configure the LTC1642 to restart itself
after the circuit breaker trips by connecting FAULT to the
ON pin.

The servo loop controlling Q1 during current limit has a
unity-gain frequency of about 125kHz; in Figure 1 R4,
together with C2, provide compensation. To ensure stabil­ity the product 1/(2•π•R4•C2) should be kept below the
unity-gain frequency, and C2 should be more than Q1’s
gate-source capacitance. The values shown in Figure 1,

0.047µF and 330Ω, are a starting point.
Typical waveforms during a load short to ground are

shown in Figure 4. The load is shorted to ground at time 1.
The GATE voltage drops until the load current equals its
maximum limit, and the circuit breaker timer starts. The
short is cleared at time 2, before the timer trips. The BRK
TMR pin returns to ground, and the GATE voltage begins
ramping up. At time 3 the load is shorted again and at time
4 the timer trips, pulling the GATE to ground and asserting
FAULT. Although the short is cleared at time 5, FAULT
doesn’t go high until the ON pin is pulled low at time 6. At
time 7 ON goes high and the system timer starts. When it
trips at time 8 the GATE voltage begins ramping.

70

60

50

40

30

20

10

MAXIMUM SENSE RESISTOR VOLTAGE (mV)

0

0 100 200 300 400 500 600 700 800 9001000

Figure 3. Maximum Sense Resistor Voltage vs FB Voltage

FB PIN VOLTAGE (mV)

1642 F03

6

I

LOAD

GATE

V

OUT

BRK TMR

FAULT

ON

RST TMR

Figure 4. Current Limit and Circuit Breaker Timing

754321 8

GATE

I

LIMIT

0A

1.23V

1.23V

1642 F04

6

LTC1642

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APPLICATIO S I FOR ATIO

Automatic Restart After a Current Fault

The LTC1642 will automatically attempt to restart itself
after the circuit breaker opens if the FAULT output is tied
to the ON pin. The circuit is shown in Figure 5, and the
waveforms during a load short in Figure 6.

During a continuous current limit such as a load short, the
N-channel pass transistor’s duty cycle is equal to the
circuit breaker timer period, divided by the sum of the
circuit breaker and system timer periods. If FAULT is tied
to ON then open drain logic should be used to drive the

15

8

Q1

FDR9410A

14

1

R3
100Ω

R4
330Ω

C2

0.047µF

C5

+

2N2222

V

OUT

C

LOAD

Q3
MCR

Q2

12DC

1642 F05

R2

4
6

FAULT

9

OV

2

BRK TMR

0.010Ω

16

V

CC

LTC1642

RST TMR

3

SENSE

GATEON

CRWBR

GND

C1

0.33µF

C4

C4 + 10 • C1

V

IN

12V

2.5A
C7

0.1µF

ALL RESISTORS ±5% UNLESS NOTED

SHORT-CIRCUIT DUTY CYCLE = = 9%

R5

0.33µF

R1

C4

node. The external pull-up resistor at the ON pin may be
omitted because FAULT provides a weak pull-up.

Undervoltage Lockout

An internal undervoltage lockout circuit holds the charge
pump off until VCC exceeds 2.73V. If VCC falls below 2.5V,
it turns off the charge pump and clears overvoltage and
current limit faults.

For higher lockout thresholds tie the ON pin to a resistor
divider driven from VCC, as shown in Figure 7. This
circuit keeps the charge pump off until VCC exceeds
(1+R1/R5)•1.34V, and also turns it off if VCC falls below
(1+R1/R5)•1.23V.

654321

GATE

V

OUT

BRK TMR

ON/FAULT

RST TMR

1.23V

1.23V

1642 F06

Figure 5. Automatic Restart Circuit

V

IN

12V

2.5A

UNDERVOLTAGE

THRESHOLD = 10.7V

ALL RESISTORS ±5% UNLESS NOTED

C7

0.1µF

LOCKOUT

Figure 7. Setting a Higher Undervoltage Lockout

R1
464k
1%

R5

60.4k
1%

4

ON

0.010Ω

16

V

CC

LTC1642

RST TMR

3

R2

C1

0.33µF

Figure 6. Automatic Retry Following a Load Short

Q1

SENSE

GATE

GND

15

8

FDR9410A

R3
100Ω

14

C2

0.047µF

R4
330Ω

V

C

1642 F07

OUT

LOAD

+

7

LTC1642

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APPLICATIO S I FOR ATIO

Overvoltage Protection

The LTC1642 can protect a load from overvoltages by
turning off the pass transistor if the supply voltage ex­ceeds a programmable limit, and by triggering a crowbar
SCR if the overvoltage lasts longer than a programmable
time. The part can also be configured to automatically
restart when the overvoltage clears.

The overvoltage protection circuitry is shown in Figure 8.
The external components comprise a resistor divider
driving the OV pin, timing capacitor C5, NPN emitter
follower Q2, and crowbar SCR Q3. Because the MCR12DC
is not a sensitive-gate device, the optional resistor shunt­ing the SCR gate to ground is omitted. The internal
components comprise a comparator, 1.23V bandgap ref­erence, two current sources, and a timer at the CRWBR
pin. When VCC exceeds (1+R1/R5)•1.23V the comparator’s
output is high and internal logic pulls the GATE down and
starts the timer. This timer has a 0.410V threshold and
uses the CRWBR pin; when CRWBR reaches 0.410V the
timer comparator trips, and the current sourced from V
increases to 1.5mA. Emitter follower Q2 boosts this cur­rent to trigger crowbar SCR Q3. The ramp time ∆t needed
to trip the comparator is : ∆t(ms) = 9.1•C5(µF).

Once the CRWBR timer trips the LTC1642 latches off: after
the overvoltage clears GATE and FAULT remain at ground
and CRWBR continues sourcing 1.5mA. To restart the part
after the overvoltage clears, hold the ON pin low for at least
2µs and then bring it high. The GATE voltage will begin
ramping up one system timing cycle later. The part will
restart itself if FAULT and ON are connected: GATE begins
ramping up one system timing cycle after the overvoltage
clears.

CC

V

IN

12V

2.5A
C7

0.1µF

ALL RESISTORS ±5% UNLESS NOTED
OV COMPARATOR TRIPS AT V
RESET TIME = 200ms
CROWBAR DELAY TIME = 90µs

R1
127k
1%

R5

12.4k
1%

9

4
6

OV

ON
FAULT

16

V

CC

RST TMR

= 13.85V

IN

Figure 8. Overvoltage Protection Circuitry

V

CC

OV

GATE

V

OUT

R2

0.010Ω

LTC1642

3

C1

0.33µF

15

SENSE

GATE

CRWBR

GND

0V

14

1

8

Q1

FDR9410A

R3
100Ω

R4
330Ω

2N2222

C2

0.047µF
Q2

C5

0.01µF

6 7 854321

+

C

Q3
MCR12DC

1642 F08

0V

1.23V

0V

V

V

LOAD

CC

OUT

Figure 9 shows typical waveforms when the divider is
driven from VCC. The OV comparator goes high at time 1,
causing the chip to pull the GATE pin to ground and start
the CRWBR timer. At time 2, before the timer’s compara­tor trips, OV falls below its threshold; the timer resets and
GATE begins charging one system timing cycle later at
time 3. Another overvoltage begins at time 4, and at time
5 the CRWBR timer trips; FAULT goes low and the CRWBR
pin begins sourcing 1.5mA. Even after OV falls below

1.23V at time 6, GATE and FAULT stay low, and CRWBR
continues to source 1.5mA. FAULT goes high when ON

8

CRWBR

RST TMR

ON

FAULT

0.41V

1.23V

1642 F09

Figure 9. Overvoltage Timing (High Side)

LTC1642

U

WUU

APPLICATIO S I FOR ATIO

goes low at time 7, and GATE begins charging at time 8,
one RST TMR cycle after FAULT goes high.

Figure 10 shows typical waveforms when the OV divider is
driven from the N-channel’s low side. Because the voltage
driving the divider collapses after the OV comparator trips,
FAULT stays high and CRWBR stays near ground, which
prevents the pin from triggering an SCR. The GATE voltage
begins ramping up after a RST TMR timing cycle.

Automatic Restart

If there is an overvoltage, and the resistor divider feeding
OV is connected to the output of the N-channel pass
transistor, the LTC1642 will automatically restart even if
FAULT is not tied to ON. If the divider is connected to the
input side, the LTC1642 will restart itself only if FAULT is
tied to ON, and only after the overvoltage clears.

The OV and FB Comparators

The propagation delay through the OV and FB compara­tors on low to high transitions depends strongly on the
differential input voltage. The relationship is shown in
Figure 11. The minimum propagation delay for large
overdrives is about 20µs. In addition the comparators
have 3mV of hysteresis.

Internal Voltage Clamp Protection

The LTC1642 includes a shunt regulator to protect itself
from VCC and SENSE pin voltages up to 33V. The regulator
turns on when VCC exceeds 16.5V and limits most of the
chip’s circuitry to 15V. When it is on the chip functions
normally with one exception: if the charge pump is on, the
GATE voltage is usually near ground but this is not
guaranteed. Use the OV pin to ensure that GATE is grounded.
The pull-up voltage on the RESET and FAULT pins follows
VCC until the shunt regulator turns on. When the regulator
is on the pull-up voltage is 14.4V.

6 754321

V

CC

0V

1642 F10

1.23V
0V

0.41V

1.23V

0V

OV

GATE

V

OUT

CRWBR

RST TMR

FAULT

Figure 10. Overvoltage Timing (Low Side)

70

60

50

40

30

20

10

OV COMPARATOR PROPAGATION DELAY (µs)

0

0 40 80 120 160 200 240

Figure 11. OV Comparator Propagation Delay vs
Overdrive Voltage

OV OVERDRIVE (mV)

1642 F11

9

LTC1642

U

WUU

APPLICATIO S I FOR ATIO

Undervoltage Monitor

The LTC1642 will assert RESET if a monitored voltage falls
below a programmable minimum. When the monitored
voltage has exceeded its minimum for at least one system
timing cycle, RESET goes high. The monitoring circuitry
comprises an internal 1.23V bandgap reference, an inter­nal precision voltage comparator and an external resistive
divider to monitor the output supply voltage. The circuit is
shown in Figure 12, and typical waveforms in Figure 13.
When the voltage at the FB pin rises above its reset
threshold (1.23V), the comparator output goes low and a
timing cycle starts (times 1 and 5). Following the cycle
RESET is pulled high.

At time 2 the voltage at FB drops below the comparator’s
threshold and RESET is pulled low. If the FB pin rises
above the reset threshold for less than a timing cycle the
RESET output will remain low (time 3 to time 4). The 15µA
pull-up current source to VCC on RESET has a series diode
so the pin can be pulled above VCC by an external pull-up
resistor without forcing current back into the supply.

V

CC

RST TMR

C1

R2

0.010Ω

16

SENSE

GATEON

LTC1642

RESET
GND

3

V

IN

12V

2.5A

4

0.33µF

ALL RESISTORS ±5% UNLESS NOTED.
FB COMPARATOR TRIPS AT V

15

FB

8

Q1

FDR9410A

14

7

5

= 10.7V

OUT

R3
100Ω

R4
330Ω

C2

0.047µF

R7

95.3k
1%

R6

12.4k
1%

Figure 12. Undervoltage Monitoring Circuitry

54321

V

OUT

+

C

LOAD

1642 F12

Reference

The LTC1642’s internal voltage reference is buffered and
brought out to the REF pin. The buffer amplifier should be
compensated with a capacitor connected between REF
and ground. If no DC current is drawn from REF, 0.1µF
ensures an adequate phase margin, but the minimum
compensation increases if REF sources a substantial DC
current, as shown in Figure 14.

Uncommitted Comparator

The uncommitted comparator has an open drain output.
The comparator has 3mV of hysteresis: the output goes
high when the differential input voltage exceeds 1.5mV
and goes low when the differential input is less than
–1.5mV.

V1 V2 V2V1

V

OUT

RST TMR

RESET

V1

Figure 13. Supply Monitor Waveforms

10.0

4.0

2.0

1.0

0.4

0.2

0.1

MINIMUM REF COMPENSATION (µF)

100µA 1mA 10mA

REFERENCE CURRENT

1642 F13

1642 F14

10

Figure 14. Minimum REF Compensation vs REF Current

PACKAGE DESCRIPTIO

U

Dimensions in inches (millimeters) unless otherwise noted.

GN Package

16-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.189 – 0.196*
(4.801 – 4.978)

16

15

14

13

12 11 10

9

LTC1642

0.009

(0.229)

REF

0.015

0.004

±

(0.38 ± 0.10)

0.007 – 0.0098
(0.178 – 0.249)

0.016 – 0.050

(0.406 – 1.270)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0° – 8° TYP

× 45°

0.229 – 0.244

(5.817 – 6.198)

0.053 – 0.068

(1.351 – 1.727)

0.008 – 0.012

(0.203 – 0.305)

12

0.150 – 0.157**
(3.810 – 3.988)

5

4

678

3

0.004 – 0.0098
(0.102 – 0.249)

0.025

(0.635)

BSC

GN16 (SSOP) 0398

11

LTC1642

TYPICAL APPLICATIO

U

5V To 3.3V Hot Swap Supply Using the LTC1430

C9

270pF

5V

36.5k

LATCH OFF: FLOAT FAULT
AUTOMATIC RETRY: TIE FAULT TO ON

3.3V POWER-GOOD = 3.00V
UNDERVOLTAGE = 4.49V

2.55k

OVERVOLTAGE = 5.47V

11.3k

R10

1%

1%

1%

12k

R5

R6

R7

15µF

10V

KEMET

TANT

C14
2200pF

C6

0.1µF

1N4148

C16

330µF

6.3V

KEMET

TANT

R11

16.5k
1%

C10

330µF

6.3V

KEMET

TANT

R12

10.2k
1%

R3

32.4k
1%

R4
13k
1%

C15

0.1µF

Q1

R2

RST TMR

5 6 78

4

1 2 3

5

6 78

4

1 2 3

RESET

FB

CRWBR

COMP
COMP

REF

0.1µF

C2

0.33µF

330Ω

–

+

R8

5
7
1
12
11
13

C4

Q4
Si4412DY

Q5
Si4412DY

CDRH1273R5

C1
47nF

Q2

2N2222

C5

0.01µF

L1

3.5µH

D1
MBRS130T3

C18

680pF

Q3
MCR
12DC

D2

R9

51Ω

7
8
5
6

C8

+

C7

0.1µF

V

10

COMPOUT

4

ON

D3

6

FAULT

9

OV

MBR0530T1

U2

LTC1430CS

PV

CC2

G2
SHDN
COMP

R1, 0.005Ω

16 15 14

CC

GND BRK TMR

823

PV

CC1

G1
FB

GND

SENSE GATE

U1

LTC1642

C3

0.33µF

2
1
4
3

MTB50N06V

100Ω

C17

+

+

+

330µF

6.3V

KEMET

TANT

C11

+

330µF

6.3V

KEMET

TANT

5V POWER-GOOD = 4.75V

C13
1µF

C12

330µF

6.3V

KEMET

TANT

+

1642 TA02

R13

17.4k
1%

R14

12.1k
1%

3.3V
OUT
AT 5A

ALL RESISTORS 5% UNLESS OTHERWISE NOTED
RESET TIME = 200ms
CURRENT LIMIT TIME =20ms
CROWBAR TIME = 90µs

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1421 Hot Swap Controller Multiple Supplies
LTC1422 Hot Swap Controller Single Supply in SO-8
LT1640 Negative Voltage Hot Swap Controller Negative High Voltage Supplies
LTC1643 PCI-Bus Hot Swap Controller 3.3V, 5V, 12V, –12V Supplies for PCI Bus

1642is, sn1642 LT/TP 0599 4K • PRINTED IN USA

 LINEAR TE CHNOLOGY CORPORATION 1999

12

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com