Simultaneously Monitors 5V, 3.3V and
Adjustable Inputs
■
Guaranteed Threshold Accuracy: ±0.75%
■
Low Supply Current: 100µA
■
Internal Reset Time Delay: 200ms
■
Manual Pushbutton Reset Input
■
Active Low and Active High Reset Outputs
■
Active Low “Soft” Reset Output
■
Power Supply Glitch Immunity
■
Guaranteed Reset for Either V
■
Meets PCI t
■
8-Pin SO and MSOP Packages
Timing Specifications Rev 2.1
FAIL
≥ 1V or V
CC3
U
APPLICATIO S
■
PCI-Based Systems
■
Desktop Computers
■
Notebook Computers
■
Intelligent Instruments
■
Portable Battery-Powered Equipment
■
Network Servers
CC5
≥ 1V
LTC1536
Precision Triple Supply Monitor
for PCI Applications
U
DESCRIPTIO
The LTC®1536 is designed for PCI local bus applications
with multiple supply voltages that require low power,
small size, high speed and high accuracy supply
monitoring.
For 3.3V and 5V supplies that are >500mV below spec or
for the condition when the 5V supply falls below the 3.3V
supply, the LTC1536 has a very fast response time capable
of meeting the PCI t
threshold accuracy and glitch immunity ensure reliable
reset operation without false triggering.
The RST output is guaranteed to be in the correct state for
V
CC5
or V
down to 1V. The 100µA typical supply current
CC3
makes the LTC1536 ideal for power-conscious systems.
A manual pushbutton reset input provides the ability to
generate a very narrow “soft” reset pulse (100µs typ) or a
200ms reset pulse equivalent to a power-on reset. Both
SRST and RST outputs are open-drain and can be OR-tied
with other reset sources.
, LTC and LT are registered trademarks of Linear Technology Corporation.
timing specification. Tight 0.75%
FAIL
TYPICAL APPLICATIO
Motherboard PCI RST Generation
3.3V ±0.3V
5V ±5%
PWR GOOD
0.1µF
0.1µF
LTC1536
1
V
CC3
2
V
CC5
3
V
CCA
4
GND
SELECTED TO MEET RISE TIME
R
PU
SLEW RATE REQUIREMENTS (1k MIN)
U
PBR
SRST
RST
RST
PUSHBUTTON
RESET
8
7
6
5
R
RST
Power Fail Waveform
5V Dropping Below 3.3V by 300mV
V
= 5V TO 3V STEP
CC5
= V
RST
CCA
= 3.3V
CC3
1536 TA02
V
CC3
PU
PCI
LOCAL
BUS
1536 TA01
5
4
3
2
VOLTAGE (1V/DIV)
1
0
4.7k PULL-UP FROM
RST TO V
V
CC5
TIME (20ns/DIV)
1
Page 2
LTC1536
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
V
CC3
V
CC5
V
CCA
GND
PBR
SRST
RST
RST
1
2
3
4
V
CC3
V
CC5
V
CCA
GND
8
7
6
5
PBR
SRST
RST
RST
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
A
W
O
LUTEXI TIS
S
A
WUW
U
ARB
G
(Notes 1, 2)
Terminal Voltage
V
, V
, V
CC3
CC5
.................................... –0.3V to 7V
CCA
RST, SRST ............................................ –0.3V to 7V
RST ......................................... –0.3V to V
CC3
+ 0.3V
PBR .......................................................... –7V to 7V
WU
/
= 125°C, θ
O
RDER IFORATIO
ORDER
PART NUMBER
LTC1536CMS8
MS8 PART MARKING
= 160°C/W
JA
LTBV
PACKAGE
T
JMAX
Operating Temperature Range
LTC1536C .............................................. 0°C to 70°C
LTC1536I............................................ –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
U
ORDER
PART NUMBER
LTC1536CS8
LTC1536IS8
S8 PART MARKING
T
JMAX
= 125°C, θ
= 150°C/W
JA
1536
1536I
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
V
= 3.3V, V
CC3
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
V
RT3
V
RT5
V
RTA
V
CC
I
VCC3
I
VCC5
I
VCCA
t
RST
t
SRST
t
UV
2
= 5V, V
CC5
Reset Threshold V
Reset Threshold V
Reset Threshold V
V
or V
CC3
V
Supply CurrentPBR = V
CC3
V
Input CurrentV
CC5
V
Input CurrentV
CCA
Reset Pulse WidthRST Low with 10kΩ Pull-Up to V
Soft Reset Pulse WidthSRST Low with 10kΩ Pull-Up to V
VCC Undervoltage Detect to RSTV
PBR, RST Input Low Voltage●0.8V
PBR, RST Input High Voltage●2V
PBR Min Pulse Width●40ns
PBR DebounceDeassertion of PBR Input to SRST●2035ms
Output (PBR Pulse Width = 1µs)
PBR Assertion Time for TransitionPBR Held Less Than VIL, 0°C to 70°C●1.42.02.8s
from Soft to Hard Reset ModePBR Held Less Than V
RST Output Voltage LowI
SRST Output Voltage LowI
RST Output Voltage LowI
RST Output Voltage High (Note 3)I
SRST Output Voltage High (Note 3)I
RST Output Voltage HighI
Propagation Delay RST to RSTC
= 5mA●0.150.4V
SINK
I
= 100µAV
SINK
≤ 70°CV
0°C ≤ T
A
I
= 100µAV
SINK
–40°C ≤ T
SINK
SINK
SOURCE
SOURCE
SOURCE
RST
≤ 85°CV
A
= 2.5mA●0.150.4V
= 2.5mA●0.150.4V
= 1µA●V
= 1µA●V
= 600µA●V
= 20pF25ns
, –40°C to 85°C●1.42.03.0s
IL
CC3
CC3
V
CC3
CC3
CC3
V
CC3
= 1V, V
= 0V, V
= 1V, V
= 1.1V, V
= 0V, V
= 1.1V, V
= 0V●0.050.4V
CC5
= 1V●0.050.4V
CC5
= 1V●0.050.4V
CC5
= 0V●0.050.4V
CC5
= 1.1V●0.050.4V
CC5
= 1.1V●0.050.4V
CC5
– 1V
CC3
– 1V
CC3
– 1V
CC3
High Input to Low Output
Propagation Delay RST to RSTC
= 20pF45ns
RST
Low Input to High Output
V
or V
CC5
0.5V UndervoltageV
CC3
Drops Below 4.25V or V
CC5
Drops●150450ns
CC3
to RST (Note 4)Below 2.5V (Note 5)
V
< (V
CC5
– 300mV) RST (Note 4)V
CC3
Drops Below V
CC5
By 300mV●5090ns
CC3
(Note 6)
● denotes specifications which apply over the full operating
The
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: The output pins SRST and RST have weak internal pull-ups to
V
of 6µA. However, external pull-up resistors may be used when faster
CC3
rise times are required.
Note 4: Conforms to PCI Local Bus Specification Rev 2.1,
Sect. 4.3.2 for t
Note 5: V
V
Note 6: V
V
CC3
– 500mV to RST at 1.5V.
RTX
CC5
= (V
CC5
CC3
.
FAIL
or V
falling at –0.1V/µs, time measured from
CC5
falling from 5V to 3V in ≤10ns, time measured from
– 300mV) to RST at 1.5V.
3
Page 4
LTC1536
INPUT VOLTAGE (V)
0.8
–3
INPUT CURRENT (nA)
–2
–1
0
1
0.91.0
1.1
1.2
1536 G03
2
3
0.850.95
1.05
1.15
TA = 25°C
UW
TYPICAL PERFORMANCE CHARACTERISTICS
I
vs Temperature
VCC3
140
120
100
80
(µA)
60
VCC3
I
40
20
0
–45
V
–5
–25
TEMPERATURE (°C)
Threshold Voltage
CC5
vs Temperature
4.750
4.745
(V)
4.740
RT5
4.735
4.730
4.725
4.720
4.715
THRESHOLD VOLTAGE, V
4.710
CC5
V
4.705
4.700
–60
–400
–20
TEMPERATURE (°C)
35
15
20
55
75
1536 G01
80
60
40
100
1536 G04
I
vs Temperature
VCC5
20.0
17.5
15.0
12.5
(µA)
10.0
VCC5
I
7.5
5.0
2.5
0
–45
V
CC3
–5
–25
TEMPERATURE (°C)
Threshold Voltage
vs Temperature
3.010
3.005
(V)
3.000
RT3
2.995
2.990
2.985
2.980
2.975
THRESHOLD VOLTAGE, V
2.970
CC3
V
2.965
2.960
–60
–2020
–4080
TEMPERATURE (°C)
35
15
040100
55
60
75
1536 G02
1536 G05
V
Input Current
CCA
vs Input Voltage
V
Threshold Voltage
CCA
vs Temperature
1.005
1.004
(V)
1.003
RTA
1.002
1.001
1.000
0.999
0.998
THRESHOLD VOLTAGE, V
0.997
CCA
V
0.996
0.995
–60
–400
–20
TEMPERATURE (°C)
80
20
60
40
100
1536 G06
225
220
(ms)
215
RST
210
205
200
RESET PULSE WIDTH, t
195
190
4
Reset Pulse Width
vs Temperature
–50
–250
TEMPERATURE (°C)
50100
2575
1536 G07
“Soft” Reset Pulse Width
vs Temperature
112.5
110.0
(µs)
SRST
107.5
105.0
102.5
100.0
97.5
SOFT RESET PULSE WIDTH, t
95.0
–50
–250
TEMPERATURE (°C)
50100
2575
1536 G08
PBR Assertion Time to Reset
vs Temperature
2.25
(SEC)
2.20
PB
2.15
2.10
2.05
2.00
1.95
PBR ASSERTION TIME TO RESET, t
1.90
–50
–250
2575
TEMPERATURE (°C)
50100
1536 G09
Page 5
UW
TYPICAL PERFORMANCE CHARACTERISTICS
V
Typical Transient Duration
CC3
vs Reset Comparator Overdrive
50
45
40
35
30
25
20
15
10
TYPICAL TRANSIENT DURATION (µs)
5
0
0.001
V
RESET COMPARATOR OVERDRIVE, V
CC3
0.010.11
RESET OCCURS
ABOVE CURVE
– V
RT3
1536 G10
CC3
(V)
V
Typical Transient Duration
CC5
vs Reset Comparator Overdrive
45
40
35
30
25
20
15
10
TYPICAL TRANSIENT DURATION (µs)
5
0
0.001
V
RESET COMPARATOR OVERDRIVE, V
CC5
0.010.11
RESET OCCURS
ABOVE CURVE
RT5
– V
1536 G11
CC5
(V)
LTC1536
V
Typical Transient Duration
CCA
vs Reset Comparator Overdrive
40
35
30
25
20
15
10
5
TYPICAL TRANSIENT DURATION (µs)
0
0.001
RESET COMPARATOR OVERDRIVE, V
V
CCA
0.010.11
RESET OCCURS
ABOVE CURVE
– V
RTA
1536 G12
CCA
(V)
RST Output Voltage
vs Supply Voltage
5.0
V
= V
= V
CC5
CC3
4.5
4.7k PULL-UP FROM RST TO V
TA = 25°C
4.0
3.5
3.0
2.5
2.0
1.5
RST OUTPUT VOLTAGE (V)
1.0
0.5
0
0
0.54.5
CCA
1.0
1.5
SUPPLY VOLTAGE, VCC (V)
2.0
2.5
3.0
Undervoltage Response Time
vs Temperature
DEVICE THRESHOLD
PCI SPEC
85° –40°
25°
3.5
CC5
4.0
1536 G13
V
CC3
5.0
RST Output Voltage
vs Supply Voltage
5.0
V
= V
CC5
4.5
RST PIN LOADED WITH
10MΩ TO GND
4.0
T
A
3.5
3.0
2.5
2.0
1.5
RST OUTPUT VOLTAGE (V)
1.0
0.5
0
0
0.54.5
= V
CC3
CCA
= 25°C
1.0
1.5
2.0
2.5
SUPPLY VOLTAGE, VCC (V)
Power-Fail Response Time
vs Temperature
V
CC5
3.0
3.5
4.0
5.0
1536 G16
VOLTAGE (500mV/DIV)
V
FALLING
CC3
FROM 3.3V TO
2.3V AT (–0.1V/µs)
TIME (1µs/DIV)
t
FAIL
MARGIN
SPEC
RST
1536 G15
VOLTAGE (1V/DIV)
–40°
85°
25°
RST
TIME (20ns/DIV)
1536 G14
5
Page 6
LTC1536
UUU
PIN FUNCTIONS
V
(Pin 1): 3.3V Sense Input and Power Supply Pin for
CC3
the IC. Bypass to ground with ≥0.1µF ceramic capacitor.
V
(Pin 2): 5V Sense Input. Used as gate drive for RST
CC5
output FET when the voltage on V
voltage on V
V
(Pin 3): 1V Sense, High Impedance Input. Can be
CCA
CC3
.
is greater than the
CC5
used as a logic input with a 1V threshold. If unused it can
be tied to either V
CC3
or V
CC5
.
GND (Pin 4): Ground.
RST (Pin 5): Reset Logic Output. Active high CMOS logic
output, drives high to V
, buffered compliment of RST.
CC3
An external pull-down on the RST pin will drive this pin high.
RST (Pin 6):
logic output with weak pull-up to V
greater than V
Reset Logic Output. Active low, open-drain
. Can be pulled up
CC3
when interfacing to 5V logic.
CC3
W
BLOCK DIAGRAM
Asserted when one or more of the supplies are below trip
thresholds and held for 200ms after all supplies become
valid. Also asserted after PBR is held low for more than two
seconds and for an additional 200ms after PBR is released.
SRST (Pin 7): “Soft” Reset. Active low, open-drain logic
output with weak pull-up to V
than V
when interfacing to 5V logic. Asserted for 100µs
CC3
. Can be pulled up greater
CC3
after PBR is held low for less than two seconds and released.
PBR (Pin 8): Pushbutton Reset. Active low logic input with
weak pull-up to V
. Can be pulled up greater than V
CC3
CC3
when interfacing to 5V logic. When asserted for less than
two seconds, outputs a soft reset 100µs pulse on the SRST
pin. When PBR is asserted for greater than two seconds,
the RST output is forced low and remains low until 200ms
after PBR is released.
CC3
CC5
CCA
8PBR
1V
2V
3V
4GND
TO
POWER
DETECT
V
CC3
7µA
TO POWER DETECT
INTERNAL
AND V
CC
REF
–
FAST
+
–
SLOW
+
+
FAST
–
–
FAST
+
–
SLOW
+
–
SLOW
+
PBR
TIMER
SOFT RESET
RESET
200ms
RESET
GENERATOR
V
CC3
POWER
DETECT/
GATE DRIVE
V
CC5
6µA
6µA
V
CC3
7 SRST
V
CC3
6 RST
V
CC3
5
RST
6
1326 BD
Page 7
WWU
TI I G DIAGRA S
VCC Monitor TimingPushbutton Reset Function Timing
LTC1536
V
V
CCX
RST
RTX
V
CC3 OR
V
RST
CC5
t
Fast Undervoltage Detect
FAIL
SLEW RATE ≤0.1V/µs
V
RTX
t
FAIL
U
t
RST
500mV
WUU
1536 TD03
APPLICATIONS INFORMATION
1536 TD01
PBR
RST
SRST
t < t
V
CC5
RST
PB
t
DB
t
SRST
t
PB
t
RST
1536 TD02
Power-Fail Detect
3.3V
FALL TIME ≤ 10ns, V
t
PF
CC3
300mV
= 3.3V
1536 TD04
Operation
The LTC1536 is a low power, high accuracy triple supply
monitoring circuit. This reset generator has two basic
functions: generation of a reset when power supplies are
out of range, and generation of a reset or “soft” reset when
the reset button is pushed. The LTC1536 has the added
feature that when the reset supplies are grossly undervoltage there is a very short delay from undervoltage detect to
assertion of RST.
Supply Monitoring
All three VCC inputs must be above predetermined thresholds for 200ms before the reset output is released. The
LTC1536 will assert reset during power-up, power-down
and brownout conditions on any one or more of the V
CC
inputs.
On power-up, either the V
CC5
or V
pin can power the
CC3
drive circuits for the RST pin. This ensures that RST will
be low when either V
CC5
or V
reaches 1V. As long as
CC3
any one of the VCC inputs is below its predetermined
threshold, RST will stay a logic low. Once all of the V
CC
inputs rise above their thresholds, an internal timer is
started and RST is released after 200ms. RST outputs the
inverted state of what is seen on RST.
RST is reasserted whenever any one of the VCC inputs
drops below its predetermined threshold and remains
asserted until 200ms after all of the VCC inputs are above
their thresholds.
On power-down, once any of the VCC inputs drops below
its threshold, RST is held at a logic low. A logic low of 0.4V
is guaranteed until V
CC3
and V
drops below 1V.
CC5
Pushbutton Reset
The LTC1536 provides a pushbutton reset input pin. The
PBR input has an internal pull-up current source to V
CC3
.
If the PBR pin is not used it can be left floating.
7
Page 8
LTC1536
U
WUU
APPLICATIONS INFORMATION
When the PBR is pulled low for less than tPB (≈2 sec), a
narrow (100µs typ) soft reset pulse is generated on the
SRST output pin after the button is released. The pushbutton circuitry contains an internal debounce counter
which delays the output of the soft reset pulse by typically
20ms. This pin can be OR-tied to the RST pin and issue
what is called a “soft” reset. The SRST thereby resets the
microprocessor without interrupting the DRAM refresh
cycle. In this manner DRAM information remains undisturbed. Alternatively, SRST may be monitored by the
processor to initiate a software-controlled reset.
When the PBR pin is held low for longer than tPB ( ≈2 sec),
a standard reset is generated. Once the 2-second period
has elapsed, a reset signal is produced by the pushbutton
logic, thereby clearing the reset counter. Once the PBR
pin is released, the reset counter begins counting the
reset period (200ms nominal). Consequently, the reset
outputs remain asserted for approximately 200ms after
the button is released.
Fast Undervoltage for PCI Applications
The LTC1536 is designed for PCI Local Bus applications
that require reset to be asserted quickly in response to one
or both of the power supply rails (5V and 3.3V) going out
of spec. The spec for t
margin to give the designer the ability to add follow-on
logic as needed by system requirements. The V
be used to monitor the “power good” signal and keep reset
applied until both supplies are in spec and the power good
signal is high.
and tPF are met with enough
FAIL
CCA
pin can
Glitch Immunity and Fast Undervoltage Detection
The LTC1536 achieves its high speed characteristics while
maintaining glitch immunity by using two sets of comparators. The V
CC5
and V
sense inputs each have two
CC3
comparators set at different thresholds. A slow, very
accurate comparator monitors the supply for precision
undervoltage detection. In parallel, but with a threshold
250mV lower than the precision threshold, is a very fast
comparator that detects when the supply is quickly going
out of specification. Because the fast comparator threshold is set 250mV above the PCI specification, typical
values for t
can be negative.
FAIL
3V or 5V Power Detect/Gate Drive
The LTC1536 for the most part is powered internally from
the V
pin. The exception is at the gate drive of the output
CC3
FET on the RST pin. On the gate to this FET is power detect
circuitry used to detect and drive the gate from either the
3.3V pin or the 5V pin, whichever pin has the highest
potential. This ensures the part pulls the RST pin low as
soon as either input pin is ≥1V.
Extended ESD Tolerance of the PBR Input Pin
The PBR pin is susceptible to ESD since it can be brought
out to a front panel in normal applications. The ESD
tolerance of this pin can be increased by adding a resistor
in series with the PBR pin. A 10k resistor can increase the
ESD tolerance of the PBR pin to approximately 10kV. The
PBR’s internal pull-up current of 7µA typical means there
is only 70mV (150mV max) dropped across the resistor.
U
TYPICAL APPLICATIONS N
PCI Expansion Board RST Generation
3.3V SUPPLY
PCI
LOCAL
BUS
0.1µF
5V SUPPLY
0.1µF
RESET
LTC1536
1
V
CC3
2
V
CC5
3
V
CCA
4
GND
PBR
SRST
RST
RST
8
7
6
5
8
ONBOARD
DEVICE
1536 TA08
Dual Supply Monitor (3.3V and 5V, V
Monitoring “Power Good”)
LTC1536
3.3V
PWR GOOD
1
V
CC3
5V
2
V
CC5
3
V
CCA
4
GND
PBR
SRST
RST
RST
8
7
6
SYSTEM RESET
5
CCA
Input
1536 TA04
Page 9
U
TYPICAL APPLICATIONS N
LTC1536
Triple Supply Monitor (3.3V, 5V and Adjustable)
ADJUSTABLE SUPPLY
OR DC/DC FEEDBACK
DIVIDER
LTC1536
3.3V
R1
1
2
5V
3
4
R2
PBR
V
CC3
SRST
V
CC5
RST
V
CCA
GND
RST
*OPTIONAL RESISTOR EXTENDS
ESD TOLERANCE OF PBR INPUT
8kV TO 10kV
10k*
8
7
6
5
SRST Tied to RST and OR-Tying Other Sources to RST to
Generate Reset and Reset
PUSHBUTTON
8
6µA
V
CC3
PBR
SRST
RST
RST
3.3V
4.7k
7
6
5
RESET
RESET
OTHER OPEN DRAIN
RESET SOURCES
OR-TIED TO RESET
LTC1536
6µA
PUSHBUTTON
RESET
SYSTEM RESET
1536 TA03
3.3V
5V
Using V
LTC1435
V
OSENSE
ADJUSTABLE
RESET TRIP
THRESHOLD 2.74V
RESET Valid for V
Down to 0V
CC3
in a Dual Supply Application
LTC1536
1
V
CC3
2
V
CC5
3
V
CCA
4
GND
Tied to DC/DC Feedback Divider
CCA
2.9V
35.7k
1%
6
2.8k
1%
22.1k
1%
3.3V
SRST
5V
PBR
RST
RST
8
7
6
5
1
V
CC3
2
V
CC5
3
V
CCA
4
GND
100k
SYSTEM RESET
LTC1536
SRST
PBR
RST
RST
1536 TA09
8
7
6
5
SYSTEM RESET
1536 TA07
1536 TA05
9
Page 10
LTC1536
(
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7
6
5
0.192 ± 0.004
(4.88 ± 0.10)
12
0.040
± 0.006
SEATING
PLANE
(1.02 ± 0.15)
0.012
(0.30)
0.0256
REF
(0.65)
0.152mm) PER SIDE
TYP
0.007
(0.18)
0.021
± 0.006
(0.53 ± 0.015)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006"
° – 6° TYP
0
0.118 ± 0.004**
4
3
0.034 ± 0.004
(0.86 ± 0.102)
(3.00 ± 0.102)
0.006 ± 0.004
(0.15 ± 0.102)
MSOP (MS8) 1197
10
Page 11
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
8
5
6
LTC1536
0.228 – 0.244
(5.791 – 6.197)
0.010 – 0.020
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
×
°
45
0.016 – 0.050
0.406 – 1.270
0°– 8° TYP
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
0.150 – 0.157**
(3.810 – 3.988)
1
3
2
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
TYP
SO8 0996
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.