Datasheet LTC1430 Datasheet (Linear Technology)

FEATURES

LTC1430

High Power Step-Down

Switching Regulator Controller

U

DESCRIPTIO

■

High Power 5V to 3.xV Switching Controller:
Can Exceed 10A Output

■

All N-Channel External MOSFETs

■

Constant Frequency Operation—Small Inductor

■

Excellent Output Regulation: ±1% Over Line, Load
and Temperature Variations

■

High Efficiency: Over 95% Possible

■

Fixed Frequency Operation

■

No Low Value Sense Resistor Needed

■

Outputs Can Drive External FETs with Up to
10,000pF Gate Capacitance

■

Quiescent Current: 350µA Typ, 1µA in Shutdown

■

Fast Transient Response

■

Adjustable or Fixed 3.3V Output

■

Available in 8- and 16-Lead PDIP and SO Packages

U

APPLICATIO S

■

Power Supply for P6 and Pentium
Microprocessors

■

High Power 5V to 3.xV Regulators

■

Local Regulation for Dual Voltage Logic Boards

■

Low Voltage, High Current Battery Regulation

®

The LTC®1430 is a high power, high efficiency switching
regulator controller optimized for 5V to 3.xV applications.
It includes a precision internal reference and an internal
feedback system that can provide output regulation of ±1%
over temperature, load current and line voltage shifts. The
LTC1430 uses a synchronous switching architecture with
two N-channel output devices, eliminating the need for a
high power, high cost P-channel device. Additionally, it
senses output current across the drain-source resistance
of the upper N-channel FET, providing an adjustable
current limit without an external low value sense resistor.

The LTC1430 includes a fixed frequency PWM oscillator for
low output ripple under virtually all operating conditions.
The 200kHz free-running clock frequency can be externally
adjusted from 100kHz to above 500kHz. The LTC1430
features low 350µA quiescent current, allowing greater
than 90% efficiency operation in converter designs from
1A to greater than 50A output current. Shutdown mode
drops the LTC1430 supply current to 1µA.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Pentium is a registered trademark of Intel Corporation.

TYPICAL APPLICATIO

Typical 5V to 3.3V, 10A Application

VIN 5V

+

R

C

7.5k
C

4700pF

1µF

0.01µF

C

PV

CC2

V

CC

SS

LTC1430

FREQSET
SHDN
COMP

SENSE

PV

CC1

I

MAX

PGND

GND

SENSE

–

4.7µF

100Ω

+

0.1µF

SHUTDOWN

C1
220pF

U

1N4148

G1

I

FB

G2NC

+

FB NC

16k

0.1µF

0.1µF

1k

: AVX-TPSE227M010R0100

C

IN

C

: AVX-TPSE337M006R0100

OUT

L1: ETQP6F1R6SFA
M1A, M1B, M2: MOTOROLA MTD20N03HL

+

C

IN

220µF
×4

M1A, M1B
2 IN PARALLEL

L1, 2.8µH

+

M2

C

OUT

330µF
×6

LTC1430 • TA01

3.3V
10A

100

TA = 25°C
V

= 5V

IN

90

= 3.3V

V

OUT

80

70

EFFICIENCY (%)

60

50

40

0.1 1

Efficiency

10

LOAD CURRENT (A)

LTC1430 • TA02

1

LTC1430

WW

W

U

ABSOLUTE AXI U RATI GS

Supply Voltage

VCC....................................................................... 9V

PV

.............................................................. 13V

CC1, 2

Input Voltage

IFB......................................................... –0.3V to 18V

All Other Inputs ...................... –0.3V to (VCC + 0.3V)

UUW

PACKAGE/ORDER I FOR ATIO

ORDER

TOP VIEW

G1

1

PV

2

CC1

GND

3

FB

4

N8 PACKAGE
8-LEAD PDIP

T

= 150°C, θJA = 100°C/W (N8)

JMAX

= 150°C, θJA = 150°C/W (S8)

T

JMAX

G2

8

V

/PV

7

CC

COMP

6

SHDN

5

S8 PACKAGE

8-LEAD PLASTIC SO

CC2

PART NUMBER

LTC1430CN8
LTC1430CS8

S8 PART MARKING

1430

(Note 1)

Operating Temperature Range

LTC1430C .............................................. 0°C to 70°C

LTC1430I........................................... –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

TOP VIEW

G1

PV

CC1

PGND

GND

–

SENSE

FB

+

SENSE

SHDN

N PACKAGE

16-LEAD PDIP

T

JMAX

T

JMAX

1
2
3
4
5
6
7
8

16-LEAD PLASTIC SO

= 150°C, θJA = 70°C/W (N)

= 150°C, θJA = 110°C/W (S)

G2

16

PV

15

V

14

CC

I

13

FB

I

12

MAX

FREQSET

11

COMP

10

SS

9

S PACKAGE

PART NUMBER

CC2

LTC1430CN
LTC1430CS

LTC1430IS

ORDER

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise noted. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V
PV
V
V

∆V

IV

IPV

f

OSC

CC

CC

OUT

FB

OUT

CC

CC

Supply Voltage ● 48V
PV

CC1

, PV

CC2

● 13 V

Output Voltage Figure 1 ● 3.30 V
Feedback Voltage Figure 1, SENSE+ and SENSE– Floating (LTC1430C) ● 1.25 1.265 1.28 V

Figure 1, SENSE

Output Load Regulation Figure 1, I

Figure 1, I

+

and SENSE– Floating (LTC1430I) ● 1.23 1.265 1.29 V

= 0A to 10A (Note 3) (LTC1430C) ● 520 mV

OUT

= 0A to 10A (Note 3) (LTC1430I) 5 mV

OUT

Output Line Regulation Figure 1, VCC = 4.75V to 5.25V (Note 3) (LTC1430C) ● 15 mV

Figure 1, V

Supply Current (VCC Only) Figure 2, V

V

SHDN

Supply Current (PVCC) Figure 2, PVCC = 5V, V

V

SHDN

= 4.75V to 5.25V (Note 3) (LTC1430I) 1 mV

CC

SHDN

= V

CC

● 350 700 µA

= 0V 1 10 µA

= VCC (Note 4) 1.5 mA

SHDN

= 0V 0.1 µA

Internal Oscillator Frequency FREQSET Floating (LTC1430C) ● 140 200 260 kHz

FREQSET Floating (LTC1430I)

● 130 200 300 kHz

2

LTC1430

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise noted. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IN

A

V

gm

V

gm

I

I

MAX

I

SS

tr, t

s

t

NOV

DC

MAX

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.

Note 3: This parameter is guaranteed by correlation and is not tested
directly.

SHDN Input High Voltage ● 2.4 V
SHDN Input Low Voltage ● 0.8 V
SHDN Input Current ● ±0.1 ±1 µA
Error Amplifier Open-Loop DC Gain (LTC1430I) ● 40 48 dB
Error Amplifier Transconductance (LTC1430C) 650 µMho

(LTC1430I)

I

Amplifier Transconductance (Note 5) 1300 µMho

LIM

I

Sink Current V

MAX

= VCC (LTC1430C) ● 81216 µA

I(MAX)

= VCC (LTC1430I) ● 81217 µA

V

I(MAX)

● 300 650 1200 µMho

Soft-Start Source Current VSS = 0 (LTC1430C) ● –8 –12 –16 µA

V

= 0 (LTC1430I) ● –8 –12 –17 µA

SS

Driver Rise/Fall Time Figure 3, PV
Driver Non-Overlap Time Figure 3, PV
Maximum Duty Cycle V

= VCC (LTC1430C) ● 90 96 %

COMP

V

= VCC, VFB = 0 (LTC1430I) ● 90 96 %

COMP

V

= VCC, VFB = 1.265V (LTC1430I) ● 83 88 %

COMP

CC1

CC1

= PV

= 5V 80 250 ns

CC2

= PV

= 5V 25 130 250 ns

CC2

Note 4: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC1430 operating frequency, operating voltage and the external FETs
used.

Note 5: The I
normal (not current limited) operation, the I

amplifier can sink but cannot source current. Under

LIM

output current will be zero.

LIM

3

LTC1430

UUU

PI FU CTIO S

(16-Lead Package/8-Lead Package)

G1 (Pin 1/Pin 1): Driver Output 1. Connect this pin to the

gate of the upper N-channel MOSFET, M1. This output will
swing from PV

to PGND. It will always be low when G2

CC1

is high.

PV

(Pin 2/Pin 2): Power VCC for Driver 1. This is the

CC1

power supply input for G1. G1 will swing from PGND to
PV

. PV

CC1

PVCC + V

must be connected to a potential of at least

CC1

(M1). This potential can be generated

GS(ON)

using an external supply or a simple charge pump con­nected to the switching node between the upper MOSFET
and the lower MOSFET; see Applications Information for
details.

PGND (Pin 3/Pin 3): Power Ground. Both drivers return to
this pin. It should be connected to a low impedance ground
in close proximity to the source of M2. 8-lead parts have
PGND and GND tied together at pin 3.

GND (Pin 4/Pin 3): Signal Ground. All low power internal
circuitry returns to this pin. To minimize regulation errors
due to ground currents, GND should be connected to
PGND right at the LTC1430. 8-lead parts have PGND and
GND tied together internally at pin 3.

SENSE–, FB, SENSE+ (Pins 5, 6, 7/Pin 4): These three
pins connect to the internal resistor divider and to the
internal feedback node. To use the internal divider to set
the output voltage to 3.3V, connect SENSE+ to the positive
terminal of the output capacitor and SENSE– to the nega­tive terminal. FB should be left floating in applications that
use the internal divider. To use an external resistor divider
to set the output voltage, float SENSE+ and SENSE– and
connect the external resistor divider to FB.

SHDN (Pin 8/Pin 5): Shutdown. A TTL compatible low
level at SHDN for longer than 50µs puts the LTC1430 into
shutdown mode. In shutdown, G1 and G2 go low, all
internal circuits are disabled and the quiescent current
drops to 10µA max. A TTL compatible high level at SHDN
allows the part to operate normally.

SS (Pin 9/NA): Soft-Start. The SS pin allows an external
capacitor to be connected to implement a soft-start func­tion. An external capacitor from SS to ground controls the
start-up time and also compensates the current limit loop,
allowing the LTC1430 to enter and exit current limit
cleanly. See Applications Information for more details.

COMP (Pin 10/Pin 6): External Compensation. The COMP
pin is connected directly to the output of the error amplifier
and the input of the PWM. An RC network is used at this
node to compensate the feedback loop to provide opti­mum transient response. See Applications Information for
compensation details.

FREQSET (Pin 11/NA): Frequency Set. This pin is used to
set the free running frequency of the internal oscillator.
With the pin floating, the oscillator runs at about 200kHz.
A resistor from FREQSET to ground will speed up the
oscillator; a resistor to VCC will slow it down. See Applica­tions Information for resistor selection details.

I

(Pin 12/NA): Current Limit Set. I

MAX

sets the thresh-

MAX

old for the internal current limit comparator. If IFB drops
below I
limit. I

with G1 on, the LTC1430 will go into current

MAX

has a 12µA pull-down to GND. It can be adjusted

MAX

with an external resistor to PVCC or an external voltage
source.

IFB (Pin 13/NA): Current Limit Sense. Connect to the
switched node at the source of M1 and the drain of M2
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging IFB. This pin can be
taken up to 18V above GND without damage.

VCC (Pin 14/Pin 7): Power Supply. All low power internal
circuits draw their supply from this pin. Connect to a clean
power supply, separate from the main PVCC supply at the
drain of M1. This pin requires a 4.7µF bypass capacitor.
8-lead parts have VCC and PV

tied together at pin 7 and

CC2

require a 10µF bypass to GND.

PV

(Pin 15/Pin 7): Power VCC for Driver 2. This is the

CC2

power supply input for G2. G2 will swing from GND to
PV

. PV

CC2

supply. The 8-lead parts have VCC and PV

is usually connected to the main high power

CC2

tied together

CC2

at pin 7 and require a 10µF bypass to GND.
G2 (Pin 16/Pin 8): Driver Output 2. Connect this pin to the

gate of the lower N-channel MOSFET, M2. This output will
swing from PV

to PGND. It will always be low when G1

CC2

is high.

4

BLOCK DIAGRA

SHDN

W

DELAY

50µs

INTERNAL
SHUTDOWN

LTC1430

FREQSET

COMP

V

CC

SS

I

MAX

TEST CIRCUITS

+

4.7µF

12µA

12µA

100Ω

0.1µF

SHUTDOWN

C1
220pF

+

R

7.5k

C

I

LIM

–

1µF

0.01µF

C

C

4700pF

+

PVCC = 5V

PV

CC2

V

CC

SS

LTC1430

FREQSET
SHDN
COMP

SENSE

FB MIN

+

–

+

1.26V

1N4148

PV

CC1

G1

I

MAX

I

FB

G2NC

PGND

GND

+

SENSE

FB NC

–

PWM

40mV

+

+

C

IN

220µF
×4

M1A, M1B
2 IN PARALLEL

0.1µF

M1A, M1B, M2: MOTOROLA MTD20N03HL

: AVX-TPSE227M010R0100

C

IN

: AVX-TPSE337M006R0100

C

OUT

2.7µH/15A

M2

+

C
330µF
×6

OUT

PV

CC1

G1

PV

CC2

G2

PGND

MAX

I

FB

+

LTC1430 • BD

NC

LTC1430 • F01

FB

SENSE

SENSE

V

OUT

+

–

1.61k

1k

+

40mV

3.3V

20.1k

12.4k

FB MEASUREMENT

LTC1430

SENSE

FB

–

SENSE

NC

Figure 1

V

GND

CC

5V

PV

CC1

LTC1430

PV

CC2

PGND

G1

G2

10µF 0.1µF

10,000pF

10,000pF

Figure 3

G1 RISE/FALL

G2 RISE/FALL

LTC1430 • TC03

PV

LTC1430

SENSE

PV

CC1IFB

CC

G1

NC

G2

NC

FB

NC

+

–

LTC1430 • TC02

V

V

SHDN

CC

SHDN

V

CCPVCC2

I

NC

MAX

FREQSET

NC

COMP

NC

SS

NC

GND PGND SENSE

Figure 2

5

LTC1430

U

WUU

APPLICATIO S I FOR ATIO

OVERVIEW

The LTC1430 is a voltage feedback PWM switching regu­lator controller (see Block Diagram) designed for use in
high power, low voltage step-down (buck) converters. It
includes an onboard PWM generator, a precision refer­ence trimmed to ±0.5%, two high power MOSFET gate
drivers and all necessary feedback and control circuitry to
form a complete switching regulator circuit. The PWM
loop nominally runs at 200kHz.

The 16-lead versions of the LTC1430 include a current
limit sensing circuit that uses the upper external power
MOSFET as a current sensing element, eliminating the
need for an external sense resistor.

Also included in the 16-lead version is an internal soft­start feature that requires only a single external capacitor
to operate. In addition, 16-lead parts feature an adjustable
oscillator which can run at frequencies from 50kHz to
beyond 500kHz, allowing added flexibility in external com­ponent selection. The 8-lead versions do not include
current limit, internal soft-start or frequency adjustability.

THEORY OF OPERATION

Primary Feedback Loop

The LTC1430 senses the output voltage of the circuit at the
output capacitor with the SENSE+ and SENSE– pins and
feeds this voltage back to the internal transconductance
amplifier FB. FB compares the resistor-divided output
voltage to the internal 1.26V reference and outputs an
error signal to the PWM comparator. This is then com­pared to a fixed frequency sawtooth waveform generated
by the internal oscillator to generate a pulse width modu­lated signal. This PWM signal is fed back to the external
MOSFETs through G1 and G2, closing the loop. Loop
compensation is achieved with an external compensation
network at COMP, the output node of the FB transconduc­tance amplifier.

MIN, MAX Feedback Loops

Two additional comparators in the feedback loop provide
high speed fault correction in situations where the FB
amplifier may not respond quickly enough. MIN compares
the feedback signal to a voltage 40mV (3%) below the

internal reference. At this point, the MIN comparator
overrides the FB amplifier and forces the loop to full duty
cycle, set by the internal oscillator at about 90%. Similarly,
the MAX comparator monitors the output voltage at 3%
above the internal reference and forces the output to 0%
duty cycle when tripped. These two comparators prevent
extreme output perturbations with fast output transients,
while allowing the main feedback loop to be optimally
compensated for stability.

Current Limit Loop

The 16-lead LTC1430 devices include yet another feed­back loop to control operation in current limit. The current
limit loop is disabled in 8-lead devices. The I
monitors the voltage drop across external MOSFET M1
with the IFB pin during the portion of the cycle when G1 is
high. It compares this voltage to the voltage at the I
As the peak current rises, the drop across M1 due to its
R
that M1’s drain current has exceeded the maximum level,
I

LIM

capacitor, cutting the duty cycle and controlling the output
current level. At the same time, the I
generates a signal to disable the MIN comparator to
prevent it from conflicting with the current limit circuit. If
the internal feedback node drops below about 0.8V, indi­cating a severe output overload, the circuitry will force the
internal oscillator to slow down by a factor of as much as

100. If desired, the turn on time of the current limit loop
can be controlled by adjusting the size of the soft-start
capacitor, allowing the LTC1430 to withstand short over­current conditions without limiting.

By using the R
the current limit circuit eliminates the sense resistor that
would otherwise be required and minimizes the number of
components in the external high current path. Because
power MOSFET R
with temperature, the LTC1430 current limit is not de­signed to be accurate; it is meant to prevent damage to the
power supply circuitry during fault conditions. The actual
current level where the limiting circuit begins to take effect
may vary from unit to unit, depending on the power
MOSFETs used. See Soft-Start and Current Limit for more
details on current limit operation.

increases. When IFB drops below I

DS(ON)

starts to pull current out of the external soft-start

of M1 to measure the output current,

DS(ON)

is not tightly controlled and varies

DS(ON)

amplifier

LIM

MAX

, indicating

MAX

comparator

LIM

pin.

6

LTC1430

U

WUU

APPLICATIO S I FOR ATIO

MOSFET Gate Drive

Gate drive for the top N-channel MOSFET M1 is supplied
from PV
power supply input) by at least one power MOSFET
V

GS(ON)

allows PV
up to 13V maximum. This higher voltage can be supplied
with a separate supply, or it can be generated using a
simple charge pump as shown in Figure 4. When using a
separate PV
inrush current if PV
90% maximum duty cycle ensures that the charge pump
will always provide sufficient gate drive to M1. Gate drive
for the bottom MOSFET M2 is provided through PV
16-lead devices or VCC/PV
can usually be driven directly from PVCC with 16-lead
parts, although it can also be charge pumped or connected
to an alternate supply if desired. The 8-lead parts require
an RC filter from PVCC to ensure proper operation; see
Input Supply Considerations.

EXTERNAL COMPONENT SELECTION

Power MOSFETs

Two N-channel power MOSFETs are required for most
LTC1430 circuits. These should be selected based prima­rily on threshold and on-resistance considerations; ther­mal dissipation is often a secondary concern in high

. This supply must be above PVCC ( the main

CC1

for efficient operation. An internal level shifter

to operate at voltages above VCC and PVCC,

CC1

supply, the PVCC input may exhibit a large

CC1

is present during power up. The

CC1

for

CC2

for 8-lead devices. PV

CC2

CC2

efficiency designs. Required MOSFET threshold should be
determined based on the available power supply voltages
and/or the complexity of the gate drive charge pump
scheme. In 5V input designs where an auxiliary 12V supply
is available to power PV
with R

specified at VGS = 5V or 6V can be used with

DS(ON)

CC1

and PV

, standard MOSFETs

CC2

good results. The current drawn from this supply varies
with the MOSFETs used and the LTC1430’s operating
frequency, but is generally less than 50mA.

LTC1430 designs that use a doubler charge pump to
generate gate drive for M1 and run from PVCC voltages
below 7V cannot provide enough gate drive voltage to fully
enhance standard power MOSFETs. When run from 5V, a
doubler circuit may work with standard MOSFETs, but the
MOSFET RON may be quite high, raising the dissipation in
the FETs and costing efficiency. Logic level FETs are a
better choice for 5V PVCC systems; they can be fully
enhanced with a doubler charge pump and will operate at
maximum efficiency. Doubler designs running from PV

CC

voltages near 4V will begin to run into efficiency problems
even with logic level FETs; such designs should be built
with tripler charge pumps (see Figure 5) or with newer,
super low threshold MOSFETs. Note that doubler charge
pump designs running from more than 7V and all tripler
charge pump designs should include a zener clamp diode
DZ at PV

to prevent transients from exceeding the

CC1

absolute maximum rating at that pin.

OPTIONAL

USE FOR PV

D

Z

12V
1N5242

≥ 7V

CC

CC2

PV

PV

LTC1430

1N4148

CC1

G1

G2

Figure 4. Doubling Charge Pump

0.1µF

PV

CC

M1

L1

V

OUT

+

M2

C

OUT

LTC1430 • F04

D
12V
1N5242

10µF

Z

PV

LTC1430

1N5817

CC2

1N5817

PV

CC1

PV

CC

1N5817

0.1µF

0.1µF

G1

G2

M1

M2

L1

V

OUT

+

C

OUT

LTC1430 • F05

Figure 5. Tripling Charge Pump

7

LTC1430

U

WUU

APPLICATIO S I FOR ATIO

Once the threshold voltage has been selected, RON should
be chosen based on input and output voltage, allowable
power dissipation and maximum required output current.
In a typical LTC1430 buck converter circuit operating in
continuous mode, the average inductor current is equal to
the output load current. This current is always flowing
through either M1 or M2 with the power dissipation split
up according to the duty cycle:

V

DC M

()

DC M

()

The RON required for a given conduction loss can now be
calculated by rearranging the relation P = I2R:

RM

()

ON

OUT

1

=

V

IN

V

21

=−

=

1

OUT

V

IN

VV

−

()

IN OUT

V

IN

1

•

•

1

()

MAX

1

()

2

2

PM

=

=

MAX

DC M I

()

VP M

•

IN MAX

VI

OUT MAX

Note that the required RON for M2 is roughly twice that of
M1 in this example. This application might specify a single

0.03Ω device for M2 and parallel two more of the same
devices to form M1. Note also that while the required R

ON

values suggest large MOSFETs, the dissipation numbers
are only 1.1W per device or less—large TO-220 packages
and heat sinks are not necessarily required in high effi­ciency applications. Siliconix Si4410DY (in SO-8) and
Motorola MTD20N03HL (in DPAK) are two small, surface
mount devices with RON values of 0.03Ω or below with 5V
of gate drive; both work well in LTC1430 circuits with up
to 10A output current. A higher P

value will generally

MAX

decrease MOSFET cost and circuit efficiency and increase
MOSFET heat sink requirements.

Inductor

The inductor is often the largest component in an LTC1430
design and should be chosen carefully. Inductor value and
type should be chosen based on output slew rate require­ments and expected peak current. Inductor value is prima­rily controlled by the required current slew rate. The
maximum rate of rise of the current in the inductor is set
by its value, the input-to-output voltage differential and the
maximum duty cycle of the LTC1430. In a typical 5V to

3.3V application, the maximum rise time will be:

PM

()

RM

()

2

ON

P

should be calculated based primarily on required

MAX

MAX

=

DC M I

()

VP M

IN MAX

=

VV I

()

IN OUT MAX

2

•

MAX

•

2

()

2

2

2

•

−

efficiency. A typical high efficiency circuit designed for 5V
in, 3.3V at 10A out might require no more than 3%
efficiency loss at full load for each MOSFET. Assuming
roughly 90% efficiency at this current level, this gives a
P

value of (3.3V • 10A/0.9) • 0.03 = 1.1W per FET and

MAX

a required RON of:

VW

.

511

RM

()

1

ON

RM

()

2

ON

=

•

VA

.

33 10

•

VW

511

=

533 10

()

•

VVA

.

−

.

0 017

=Ω

2

.

•

=Ω

0 032

2

.

90

()

IN OUT

•

L

AMPS

SECOND

153%.

=

AsI

µ

L

−

VV

where L is the inductor value in µH. A 2µH inductor would
have a 0.76A/µs rise time in this application, resulting in a

6.5µs delay in responding to a 5A load current step. During
this 6.5µs, the difference between the inductor current and
the output current must be made up by the output capaci­tor, causing a temporary droop at the output. To minimize
this effect, the inductor value should usually be in the 1µH
to 5µH range for most typical 5V to 3.xV LTC1430 circuits.
Different combinations of input and output voltages and
expected loads may require different values.

Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency
requirements. Peak current in the inductor will be equal to
the maximum output load current added to half the peak­to- peak inductor ripple current. Ripple current is set by the

8

LTC1430

U

WUU

APPLICATIO S I FOR ATIO

inductor value, the input and output voltage and the
operating frequency. If the efficiency is high and can be
approximately equal to 1, the ripple current is approxi­mately equal to:

VV

−

()

∆=

DC

f

OSC

L = inductor value

Solving this equation with our typical 5V to 3.3V applica­tion, we get:

200 2

Peak inductor current at 10A load:

10

The inductor core must be adequate to withstand this peak
current without saturating, and the copper resistance in
the winding should be kept as low as possible to minimize
resistive power loss. Note that the current may rise above
this maximum level in circuits under current limit or under
fault conditions in unlimited circuits; the inductor should
be sized to withstand this additional current.

Input and Output Capacitors

A typical LTC1430 design puts significant demands on
both the input and output capacitors. Under normal steady
load operation, a buck converter like the LTC1430 draws
square waves of current from the input supply at the
switching frequency, with the peak value equal to the
output current and the minimum value near zero. Most of
this current must come from the input bypass capacitor,
since few raw supplies can provide the current slew rate to
feed such a load directly. The resulting RMS current flow
in the input capacitor will heat it up, causing premature
capacitor failure in extreme cases. Maximum RMS current
occurs with 50% PWM duty cycle, giving an RMS current

fL

OSC

V

OUT

=

V

IN

= LTC1430 oscillator frequency

17 066

..

•

kHz H

•µ

28

A

2

IN OUT

I

•

•

DC

A

28

.

=

11 4A

A+=..

−

PP

value equal to I
adequate ripple current rating must be used to ensure
reliable operation. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
(3 months) lifetime; further derating of the input capacitor
ripple current beyond the manufacturer’s specification is
recommended to extend the useful life of the circuit.

The output capacitor in a buck converter sees much less
ripple current under steady-state conditions than the input
capacitor. Peak-to-peak current is equal to that in the
inductor, usually a fraction of the total load current. Output
capacitor duty places a premium not on power dissipation
but on ESR. During an output load transient, the output
capacitor must supply all of the additional load current
demanded by the load until the LTC1430 can adjust the
inductor current to the new value. ESR in the output
capacitor results in a step in the output voltage equal to the
ESR value multiplied by the change in load current. A 5A
load step with a 0.05Ω ESR output capacitor will result in
a 250mV output voltage shift; this is a 7.6% output voltage
shift for a 3.3V supply! Because of the strong relationship
between output capacitor ESR and output load transient
response, the output capacitor is usually chosen for ESR,
not for capacitance value; a capacitor with suitable ESR
will usually have a larger capacitance value than is needed
to control steady-state output ripple.

Electrolytic capacitors rated for use in switching power
supplies with specified ripple current ratings and ESR can
be used effectively in LTC1430 applications. OS-CON
electrolytic capacitors from Sanyo give excellent perfor­mance and have a very high performance/size ratio for an
electrolytic capacitor. Surface mount applications can use
either electrolytic or dry tantalum capacitors. Tantalum
capacitors must be surge tested and specified for use in
switching power supplies; low cost, generic tantalums are
known to have very short lives followed by explosive
deaths in switching power supply applications. AVX TPS
series surface mount devices are popular tantalum capaci­tors that work well in LTC1430 applications. A common
way to lower ESR and raise ripple current capability is to
parallel several capacitors. A typical LTC1430 application
might require an input capacitor with a 5A ripple current
capacity and 2% output shift with a 10A output load step,
which requires a 0.007Ω output capacitor ESR. Sanyo

/2. A low ESR input capacitor with an

OUT

9

LTC1430

INTERNAL

CIRCUITRY

V

CC

/PV

CC2

LTC1430 (8-LEAD)

PV

CC1

M1

L1

M2

G1

G2

PV

CC

C

OUT

V

OUT

LTC1430 • F07

+

U

WUU

APPLICATIO S I FOR ATIO

OS-CON part number 10SA220M (220µF/10V) capacitors
feature 2.3A allowable ripple current at 85°C and 0.035Ω
ESR; three in parallel at the input and six at the output will
meet the above requirements.

Input Supply Considerations/Charge Pump

The 16-lead LTC1430 requires four supply voltages to
operate: PVCC for the main power input, PV
for MOSFET gate drive and a clean, low ripple VCC for the
LTC1430 internal circuitry (Figure 6). In many applica­tions, PVCC and PV

can be tied together and fed from

CC2

a common high power supply, provided that the supply
voltage is high enough to fully enhance the gate of external
MOSFET M2. This can be the 5V system supply if a logic
level MOSFET is used for M2. VCC can usually be filtered
with an RC from this same high power supply; the low
quiescent current (typically 350µA) allows the use of
relatively large filter resistors and correspondingly small
filter capacitors. 100Ω and 4.7µF usually provide ad-
equate filtering for VCC.

V

CC

INTERNAL

CIRCUITRY

LTC1430 (16-LEAD)

PV

Figure 6. 16-Lead Power Supplies

CC2

PV

CC1

PV

CC

G1

M1

G2

M2

The 8-lead versions of the LTC1430 have the PV
VCC pins tied together inside the package (Figure 7). This
pin, brought out as VCC/PV

, has the same low ripple

CC2

requirements as the 16-lead part, but must also be able to
supply the gate drive current to M2. This can be obtained
by using a larger RC filter from the PVCC pin; 22Ω and 10µF
work well here. The 10µF capacitor must be VERY close to
the part (preferably right underneath the unit) or output
regulation may suffer.

CC1

L1

and PV

+

C

CC2

CC2

V

OUT

OUT

LTC1430 • F06

and

For both versions of the LTC1430, PV
than PVCC by at least one external MOSFET V

must be higher

CC1

GS(ON)

to fully
enhance the gate of M1. This higher voltage can be
provided with a separate supply (typically 12V) which
should power up after PVCC, or it can be generated with a
simple charge pump (Figure 4). The charge pump consists
of a 1N4148 diode from PVCC to PV
capacitor from PV

to the switching node at the drain of

CC1

M2. This circuit provides 2PVCC – VF to PV

and a 0.1µF

CC1

while M1 is

CC1

ON and PVCC – VF while M1 is OFF where VF is the ON
voltage of the 1N4148 diode. Ringing at the drain of M2
can cause transients above 2PVCC at PV

; if PVCC is

CC1

higher than 7V, a 12V zener diode should be included from
PV

to PGND to prevent transients from damaging the

CC1

circuitry at PV

or the gate of M1.

CC2

More complex charge pumps can be constructed with the
16-lead versions of the LTC1430 to provide additional
voltages for use with standard threshold MOSFETs or very
low PVCC voltages. A tripling charge pump (Figure 5) can
provide 2PVCC and 3PVCC voltages. These can be con­nected to PV

and PV

CC2

respectively, allowing stan-

CC1

dard threshold MOSFETs to be used with 5V at PVCC or 5V
logic level threshold MOSFETs to be used with 3.3V at
PVCC. VCC can be driven from the same potential as PV

CC2

,
allowing the entire system to run from a single 3.3V
supply. Tripling charge pumps require the use of Schottky
diodes to minimize forward drop across the diodes at
start-up. The tripling charge pump circuit will tend to
rectify any ringing at the drain of M2 and can provide well
more than 3PVCC at PV

; all tripling (or higher multiply-

CC1

ing factor) circuits should include a 12V zener clamp diode
DZ to prevent overvoltage at PV

CC1

.

10

Figure 7. 8-Lead Power Supplies

LTC1430

U

WUU

APPLICATIO S I FOR ATIO

Compensation and Transient Response

The LTC1430 voltage feedback loop is compensated at the
COMP pin; this is the output node of the internal gm error
amplifier. The loop can generally be compensated prop­erly with an RC network from COMP to GND and an
additional small C from COMP to GND (Figure 8). Loop
stability is affected by inductor and output capacitor
values and by other factors. Optimum loop response can
be obtained by using a network analyzer to find the loop
poles and zeros; nearly as effective and a lot easier is to
empirically tweak the RC values until the transient recovery
looks right with an output load step. Table 1 shows
recommended compensation components for 5V to 3.3V
applications based on the inductor and output capacitor
values. The values were calculated using multiple paral­leled 330µF AVX TPS series surface mount tantalum
capacitors as the output capacitor.

Table 1. Recommended Compensation Network for 5V to 3.3V
Application Using Multiple 330µF AVX Output Capacitors

L1 (µH) C

1 990 1.8 0.022 820
1 1980 3.6 0.01 470
1 4950 9.1 0.0047 150
1 9900 18 0.0022 82

2.7 990 3.6 0.01 470

2.7 1980 7.5 0.0047 220

2.7 4950 18 0.0022 82

2.7 9900 39 0.001 39

5.6 990 9.1 0.0047 150

5.6 1980 18 0.0022 82

5.6 4950 47 820pF 33

5.6 9900 91 470pF 15
10 990 18 0.0022 82
10 1980 39 0.001 39
10 4950 91 470pF 15
10 9900 180 220pF 10

Output transient response is set by three major factors: the
time constant of the inductor and the output capacitor, the
more impact on overall transient recovery time than the
third; unless the loop compensation is way off, more
improvement can be had by optimizing the inductor and
the output capacitor than by fiddling with the loop com-

(µF) RC (kΩ)C

OUT

(µF) C1 (pF)

C

pensation components. In general, a smaller value induc­tor will improve transient response at the expense of ripple
and inductor core saturation rating. Minimizing output
capacitor ESR will also help optimize output transient
response. See Input and Output Capacitors for more
information.

LTC1430

COMP

R

C

C

GND SGND

Figure 8. Compensation Pin Hook-Up

C1C

LTC1430 • F08

Soft-Start and Current Limit

The 16-lead versions of the LTC1430 include a soft-start
circuit at the SS pin; this circuit is used both for initial start­up and during current limit operation. The soft-start and
current limit circuitry is disabled in 8-lead versions. SS
requires an external capacitor to GND with the value
determined by the required soft-start time. An internal
12µA current source is included to charge the external
capacitor. Soft-start functions by clamping the maximum
voltage that the COMP pin can swing to, thereby control­ling the duty cycle (Figure 9). The LTC1430 will begin to
operate at low duty cycle as the SS pin rises to about 2V
below VCC. As SS continues to rise, the duty cycle will
increase until the error amplifier takes over and begins to
regulate the output. When SS reaches 1V below VCC the
LTC1430 will be in full operation. An internal switch shorts
the SS pin to GND during shutdown.

The LTC1430 detects the output current by watching the
voltage at IFB while M1 is ON. The I
this voltage to the voltage at I

MAX

amplifier compares

LIM

(Figure 10). In the ON
state, M1 has a known resistance; by calculating back­wards, the voltage generated at IFB by the maximum
output current in M1 can be determined. As IFB falls below
I

, I

MAX

will begin to sink current from the soft-start pin,

LIM

11

LTC1430

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

causing the voltage at SS to fall. As SS falls, it will limit the
output duty cycle, limiting the current at the output.
Eventually the system will reach equilibrium, where the
pull-up current at the SS pin matches the pull-down
current in the I

amplifier; the LTC1430 will stay in this

LIM

state until the overcurrent condition disappears. At this
time IFB will rise, I

will stop sinking current and the

LIM

internal pull-up will recharge the soft-start capacitor,
restoring normal operation. Note that the IFB pin requires
an external 1k series resistor to prevent voltage transients
at the drain of M2 from damaging internal structures.

The I
the difference between IFB and I

amplifier pulls current out of SS in proportion to

LIM

. Under mild overload

MAX

conditions, the SS pin will fall gradually, creating a time
delay before current limit takes effect. Very short, mild
overloads may not trip the current limit circuit at all.
Longer overload conditions will allow the SS pin to reach
a steady level, and the output will remain at a reduced
voltage until the overload is removed. Serious overloads
will generate a larger overdrive at I

, allowing it to pull SS

LIM

down more quickly and preventing damage to the output
components.

The I

amplifier output is disabled when M1 is OFF to

LIM

prevent the low IFB voltage in this condition from activating
the current limit. It is re-enabled a fixed 170ns after M1

turns on; this allows for the IFB node to slew back high and
the I

amplifier to settle to the correct value. As the

LIM

LTC1430 goes deeper into current limit, it will reach a point
where the M1 on-time needs to be cut to below 170ns to
control the output current. This conflicts with the mini­mum settling time needed for proper operation of the I

LIM

amplifier. At this point, a secondary current limit circuit
begins to reduce the internal oscillator frequency, length­ening the off-time of M1 while the on-time remains con­stant at 170ns. This further reduces the duty cycle, allow­ing the LTC1430 to maintain control over the output
current.

Under extreme output overloads or short circuits, the I

LIM

amplifier will pull the SS pin more than 2V below VCC in a
single switching cycle, cutting the duty cycle to zero. At
this point all switching stops, the output current decays
through M2 and the LTC1430 runs a partial soft-start cycle
and restarts. If the short is still present the cycle will
repeat. Peak currents can be quite high in this condition,
but the average current is controlled and a properly
designed circuit can withstand short circuits indefinitely
with only moderate heat rise in the output FETs. In addi­tion, the soft-start cycle repeat frequency can drop into the
low kHz range, causing vibrations in the inductor which
provide an audible alarm that something is wrong.

12

V

CC

LTC1430

FB

12µA

LTC1430 • F09

COMP

SS

C

SS

Figure 9. Soft-Start Clamps COMP Pin

0.1µF

R

IMAX

I

MAX

+

12µA

SS

C

SS

Figure 10. Current Limit Operation

I

LIM

V

CC

12µA

LTC1430

–

LTC1430 • F10

I

FB

PV

CC

1k

LTC1430

U

O

PPLICATI

A

Oscillator Frequency

The LTC1430 includes an onboard current controlled
oscillator which will typically free-run at 200kHz. An
internal 20µA current is summed with any current in or out
of the FREQSET pin (pin 11), setting the oscillator fre­quency to approximately 10kHz/µA. FREQSET is internally
servoed to the LTC1430 reference voltage (1.26V). With
FREQSET floating, the oscillator is biased from the internal
20µA source and runs at 200kHz. Connecting a 50k
resistor from FREQSET to ground will sink an additional
25µA from FREQSET, causing the internal oscillator to run
at approximately 450kHz. Sourcing an external 10µA
current into FREQSET will cut the internal frequency to
100kHz. An internal clamp prevents the oscillator from
running slower than about 50kHz. Tying FREQSET to V
will cause it to run at this minimum speed.

Shutdown

The LTC1430 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allows the part to operate normally. A low level at SHDN
stops all internal switching, pulls COMP and SS to ground
internally and turns M1 and M2 off. In shutdown, the
LTC1430 itself will drop below 1µA quiescent current
typically, although off-state leakage in the external
MOSFETs may cause the total PVCC current to be some­what higher, especially at elevated temperatures. When
SHDN rises again, the LTC1430 will rerun a soft-start cycle
and resume normal operation. Holding the LTC1430 in
shutdown during PVCC power up removes any PV
sequencing constraints.

LAYOUT CONSIDERATIONS

Grounding

S

I FOR ATIO

WU

U

CC

CC1

point, right at the LTC1430 GND and PGND pins. This
helps minimize internal ground disturbances in the
LTC1430 by keeping PGND and GND at the same potential,
while preventing excessive current flow from disrupting
the operation of the circuits connected to GND. The PGND
node should be as compact and low impedance as pos­sible, with the negative terminals of the input and output
capacitors, the source of M2, the LTC1430 PGND node,
the output return and the input supply return all clustered
at one point. Figure 11 is a modified schematic showing
the common connections in a proper layout. Note that at
10A current levels or above, current density in the PC
board itself can become a concern; traces carrying high
currents should be as wide as possible.

Output Voltage Sensing

The LTC1430 provides three pins for sensing the output
voltage: SENSE+, SENSE– and FB. SENSE+ and SENSE
connect to an internal resistor divider which is connected
to FB. To set the output of the LTC1430 to 3.3V, connect
SENSE+ to the output as near to the load as practical and
connect SENSE– to the common GND/PGND point. Note
that SENSE– is not a true differential input sense input; it
is just the bottom of the internal divider string. Connecting
SENSE– to the ground near the load will not improve load
regulation. For any other output voltage, the SENSE+ and
SENSE– pins should be floated and an external resistor
string should be connected to FB (Figure 12). As before,
connect the top resistor (R1) to the output as close to the
load as practical and connect the bottom resistor (R2) to
the common GND/PGND point. In both cases, connecting
the top of the resistor divider (either SENSE+ or R1) close
to the load can significantly improve load regulation by
compensating for any drops in PC traces or hookup wires
between the LTC1430 and the load.

–

Proper grounding is critical for the LTC1430 to obtain
specified output regulation. Extremely high peak currents
(as high as several amps) can flow between the bypass
capacitors and the PV
currents can generate significant voltage differences be­tween two points that are nominally both “ground.” As a
general rule, GND and PGND should be totally separated
on the layout, and should be brought together at only one

CC1

, PV

and PGND pins. These

CC2

Power Component Hook-Up/Heat Sinking

As current levels rise much above 1A, the power compo­nents supporting the LTC1430 start to become physically
large (relative to the LTC1430, at least) and can require
special mounting considerations. Input and output ca­pacitors need to carry high peak currents and must have
low ESR; this mandates that the leads be clipped as short
as possible and PC traces be kept wide and short. The

13

LTC1430

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

power inductor will generally be the most massive single
component on the board; it can require a mechanical hold­down in addition to the solder on its leads, especially if it
is a surface mount type.

The power MOSFETs used require some care to ensure
proper operation and reliability. Depending on the current
levels and required efficiency, the MOSFETs chosen may
be as large as TO-220s or as small as SO-8s. High
efficiency circuits may be able to avoid heat sinking the
power devices, especially with TO-220 type MOSFETs. As
an example, a 90% efficient converter working at a steady

3.3V/10A output will dissipate only (33W/90%) • 10% =

3.7W. The power MOSFETs generally account for the

+

SENSE

LTC1430

FB

–

SENSE

LTC1430 • F12

majority of the power lost in the converter; even assuming
that they consume 100% of the power used by the
converter, that’s only 3.7W spread over two or three
devices. A typical SO-8 MOSFET with a RON suitable to
provide 90% efficiency in this design can commonly
dissipate 2W when soldered to an appropriately sized
piece of copper trace on a PC board. Slightly less efficient
or higher output current designs can often get by with
standing a TO-220 MOSFET straight up in an area with
some airflow; such an arrangement can dissipate as much
as 3W without a heat sink. Designs which must work in
high ambient temperatures or which will be routinely
overloaded will generally fare best with a heat sink.

V

OUT

NC

R1

R2

NC

4.7µF

C1
220pF

4700pF

35V

C

Figure 12. Using External Resistors to Set Output Voltages

100Ω

+

PV

V

SS

GND

CC

I

MAX

FREQSET

SHDN
COMP

SS

0.1µF

GND

NC
NC

R

C

7.5k

C

C

0.01µF

LTC1430

SENSE

SENSE

CC2

PV

CC1

G1

I

FB

+

G2

FB

–

PGNDGND

PGND

NC

1µF

1N4148

0.1µF

5V

M1A*

M1B*

M2*

PGND

* MOTOROLA MTD20N03HL

+

TOTAL
880µF
(220µF
10V ×4)

2.7µH/15A

+

3.3V

TOTAL
1980µF
(330µF

6.3V ×6)

LTC1430 • F11

Figure 11. Typical Schematic Showing Layout Considerations

14

PACKAGE DESCRIPTIO

0.300 – 0.325

(7.620 – 8.255)

U

Dimensions in inches (millimeters) unless otherwise noted.

N8 Package

8-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

0.045 – 0.065

(1.143 – 1.651)

0.130 ± 0.005

(3.302 ± 0.127)

876

0.400*

(10.160)

MAX

LTC1430

5

0.065

(1.651)

0.125

(3.175)

MIN

TYP

0.100

(2.54)

0.100
(2.54)

BSC

BSC

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015
+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.300 – 0.325

(7.620 – 8.255)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015

+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.020

(0.508)

MIN

0.130 ± 0.005

(3.302 ± 0.127)

0.125

0.020

(3.175)

MIN

(0.508)

0.018 ± 0.003

(0.457 ± 0.076)

MIN

N Package

14-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

0.045 – 0.065

(1.143 – 1.651)

0.255 ± 0.015*

0.065

(6.477 ± 0.381)

(1.651)

TYP

0.018 ± 0.003

(0.457 ± 0.076)

0.255 ± 0.015*
(6.477 ± 0.381)

1234

15

16

2

1

N8 1098

0.770*
(19.558)

MAX

14

3

12

13

4

11

6

5

910

8

7

N16 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LTC1430

PACKAGE DESCRIPTIO

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

×

°

45

0.016 – 0.050

(0.406 – 1.270)

× 45°

0.016 – 0.050

(0.406 – 1.270)

(1.346 – 1.752)

0° – 8° TYP

0.053 – 0.069

0.014 – 0.019

(0.355 – 0.483)

TYP

U

Dimensions in inches (millimeters) unless otherwise noted.

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.053 – 0.069

(1.346 – 1.752)

0°– 8° TYP

0.014 – 0.019

(0.355 – 0.483)

TYP

S Package

16-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.050

(1.270)

BSC

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

0.004 – 0.010

(0.101 – 0.254)

0.228 – 0.244

(5.791 – 6.197)

0.228 – 0.244

(5.791 – 6.197)

0.189 – 0.197*
(4.801 – 5.004)

7

8

1

2

16

1

14

15

3

2

5

6

3

4

0.386 – 0.394*

(9.804 – 10.008)

13

12

5

4

0.150 – 0.157**
(3.810 – 3.988)

SO8 1298

11

10

7

6

9

0.150 – 0.157**
(3.810 – 3.988)

8

S16 1098

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TM

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No R

Up to 36V, I

V

IN

is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.

SENSE

Up to 40A

OUT

Linear Technology Corporation

16

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

Required

SENSE

, 16-Lead SSOP Package

SENSE

Up to 42A

OUT

1430fa LT/TP 0500 2K REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1995