Datasheet LTC1420 Datasheet (Linear Technology)

FEATURES

LTC1420

12-Bit, 10Msps,

Sampling ADC

U

DESCRIPTIO

■

10Msps Sample Rate

■

Single 5V Supply or ±5V Supplies

■

Integral Nonlinearity Error <0.35LSB

■

Differential Nonlinearity <0.25LSB

■

71dB S/(N + D) and 83dB SFDR at Nyquist

■

100MHz Full-Power Bandwidth Sampling

■

±2.048V, ±1.024V and ±0.512V Bipolar Input Range

■

Input PGA

■

Out-of-Range Indicator

■

True Differential Inputs with 75dB CMRR

■

Power Dissipation: 250mW

■

28-Pin Narrow SSOP Package

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APPLICATIO S

■

Telecommunications

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

■

High Speed Data Acquisition

■

Spectral Analysis

■

Imaging Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

The LTC®1420 is a 10Msps, 12-bit sampling A/D converter
that draws only 250mW from either single 5V or dual ±5V
supplies. This easy-to-use device includes a high dynamic
range sample-and-hold, a precision reference and a PGA
input circuit.

The LTC1420 has a flexible input circuit that allows full­scale input ranges of ±2.048V ±1.024V and ±0.512V. The
input common mode voltage is arbitrary, though a 2.5V
reference is provided for single supply applications. The
input PGA has a digitally selectable 1x or 2x gain.

Maximum DC specs include ±1LSB INL and ±1LSB DNL
over temperature. Outstanding AC performance includes
71dB S/(N + D) and 83dB SFDR at the Nyquist input
frequency of 5MHz.

The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 100MHz
bandwidth. The 75dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source. A
separate output logic supply allows direct connection to
3V components.

TYPICAL APPLICATIO

1µF 1µF

28 7 23 22

GAIN

A

+

1

IN

+

V

IN

–A

2

IN

–

V

3

CM

1µF

1µF

4

5

SENSE

V

REF

1µF

MODE SELECT

SS

0V OR –5V

2.048V

GND

U

5V5V

1µF

V

DD

PIPELINED 12-BIT ADCS/H

DIGITAL CORRECTION

LOGIC

2.5V

REFERENCE

5V

V

DD

OV

DD

OUTPUT

BUFFERS

OGNDGNDGNDV
21

24825 6

D11 (MSB)

D0 (LSB)

CLK

OPTIONAL 3V
LOGIC SUPPLY

OF

27

10

20

26

1420 TA01

DIGITAL
OUTPUT

10MHz CLK

Typical INL Curve

1.00

0.75

0.50

0.25

0

INL (LSBs)

–0.25

–0.50

–0.75

–1.00

0 1024 2048 3072 4096

CODE

1420 TA02

1

LTC1420

1
2
3
4
5
6
7
8

9
10
11
12
13
14

TOP VIEW

GN PACKAGE

28-LEAD PLASTIC SSOP

28
27
26
25
24
23
22
21
20
19
18
17
16
15

+A

IN

–A

IN

V

CM

SENSE

V

REF

GND

V

DD

GND

D11 (MSB)

D10

D9
D8
D7
D6

GAIN
OF
CLK
V

SS

GND
V

DD

OV

DD

OGND
D0
D1
D2
D3
D4
D5

WW

W

ABSOLUTE AXI U RATI GS

U

UUW

PACKAGE/ORDER I FOR ATIO

0VDD = VDD (Notes 1, 2)

Supply Voltage (VDD)................................................. 6V

Negative Supply Voltage (VSS) ................................ – 6V

Total Supply Voltage (VDD to VSS) ........................... 12V

Analog Input Voltage

ORDER PART

NUMBER

LTC1420CGN
LTC1420IGN

(Note 3) .............................(VSS – 0.3V) to (VDD + 0.3V)

Digital Input Voltage

(Note 4) .............................(VSS – 0.3V) to (VDD + 0.3V)

Digital Output Voltage........(VSS – 0.3V) to (VDD + 0.3V)

Power Dissipation.............................................. 500mW

Operating Temperature Range

LTC1420C ............................................... 0°C to 70°C

LTC1420I............................................ –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

Consult factory for Military grade parts.

T

= 110°C, θJA = 110°C/W

JMAX

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CONVERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. With Internal 4.096V Reference. Specifications are guaranteed for both
dual supply and single supply operation. (Note 5)

The ● denotes the specifications which apply over the full operating

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 12 Bits
Integral Linearity Error (Note 7) ● ±0.35 ±1 LSB
Differential Linearity Error ● ±0.25 ±1 LSB
Offset Error (Note 8) ±5 12 LSB

● 16 LSB

Full-Scale Error ±10 30 LSB
Full-Scale Tempco I

= 0 ±15 ppm/°C

OUT(REF)

UU

A ALOG I PUT

specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

I

IN

C

IN

t

ACQ

t

AP

t

jitter

CMRR Analog Input Common Mode Rejection Ratio –2.048V < (–AIN = +AIN) < 2.048V 75 dB

2

Analog Input Range (Note 9) V

– (–AIN)V

+A

IN

Analog Input Leakage Current ● ±20 µA
Analog Input Capacitance Between Conversions 12 pF

Sample-and-Hold Acquisition Time 30 ns
Sample-and-Hold Aperture Delay Time –250 ps
Sample-and-Hold Aperture Delay Time Jitter 0.6 ps

The ● denotes the specifications which apply over the full operating temperature range, otherwise

= 4.096V (SENSE = 0V), GAIN = 5V (1×) ● ±2.048 V

REF

= 4.096V (SENSE = 0V), GAIN = 0V (2×) ● ±1.024 V

REF

V

= 2.048V (SENSE = V

REF

= 2.048V (SENSE = V

V

REF

External V
External V

(SENSE = 5V), GAIN = 5V (1×) ● ±V

REF

(SENSE = 5V), GAIN = 0V (2×) ● ±V

REF

During Conversions 6 pF

), GAIN = 5V (1×) ● ±1.024 V

REF

), GAIN = 0V (2×) ● ±0.512 V

REF

/2 V

REF

/4 V

REF

LTC1420

UW

DY A IC ACCURACY

otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, f
–AIN = 0V. (Note 6)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

S/(N + D) Signal-to-Noise Plus Distortion Ratio 1MHz Input Signal ● 68.5 71.4 dB

THD Total Harmonic Distortion 1MHz Input Signal, First 5 Harmonics ● –84 –77 dB

SFDR Peak Harmonic or Spurious Noise 1MHz Input Signal ● – 85 – 78.5 dB

IMD Intermodulation Distortion f

Full-Power Bandwidth 100 MHz
Input Referred Noise ±2.048V Input Range 0.22 LSB

Overvoltage Recovery Time 1.5x FS Input to 0 (Settling to 1LSB) 15 ns
Full-Scale Step Acquisition Time Settling to 1LSB 15 ns

The ● denotes the specifications which apply over the full operating temperature range,

= 10MHz, V

SAMPLE

5MHz Input Signal

5MHz Input Signal, First 5 Harmonics

5MHz Input Signal

= 29.37kHz, f

IN1

±1.024V Input Range, 2x Mode (SENSE = GAIN = 0V) 0.33 LSB

= 32.446kHz –80 dB

IN2

= 4.096V. +AIN = –0.1dBFS single ended input,

REF

● 68 71.0 dB

● –81 –73 dB

● –83 –75 dB

RMS
RMS

UU U

INTERNAL REFERENCE CHARACTERISTICS

TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage I
VCM Output Tempco I
VCM Line Regulation 4.75V ≤ VDD ≤ 5.25V 0.6 mV/V

VCM Output Resistance 0.1mA ≤ I
V

Output Voltage SENSE = GND, I

REF

V

Output Tempco ±15 ppm/°C

REF

= 0 2.475 2.50 2.525 V

OUT

= 0 ±15 ppm/°C

OUT

–5.25V ≤ V

SENSE = V
SENSE = V

≤ –4.75V 0.03 mV/V

SS

 ≤ 0.1mA 8 Ω

OUT

= 0 4.096 V

OUT

, I

= 0 2.048 V

REF

OUT

DD

Drive V

External Reference

with V

REF

UU

DIGITAL I PUTS A D DIGITAL OUTPUTS

operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single
supply operation. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IN

C

IN

V

OH

V

OL

I

SOURCE

I

SINK

High Level Input Voltage V

Low Level Input Voltage VDD = 4.75V, VSS = 0V ● 0.8 V

Digital Input Current VIN = 0V to V
Digital Input Capacitance 1.8 pF
High Level Output Voltage 0VDD = 4.75V, IO = –10µA 4.74 V

Low Level Output Voltage 0VDD = 4.75V, IO = 160µA 0.05 V

Output Source Current V
Output Sink Current V

= 5.25V, VSS = 0V ● 2.4 V

DD

V

= 5.25V, VSS = –5V ● 3.5 V

DD

= 4.75V, VSS = –5V ● 1V

V

DD

DD

= 4.75V, IO = –200µA ● 4.0 4.71 V

0V

DD

= 2.7V, IO = –10µA 2.6 V

0V

DD

0VDD = 2.7V, IO = –200µA ● 2.3 V

= 4.75V, IO = 1.6mA ● 0.10 0.4 V

0V

DD

0VDD = 2.7V, IO = 160µA 0.05 V

= 2.7V, IO = 1.6mA ● 0.10 0.4 V

0V

DD

= 0V 50 mA

OUT

= V

OUT

DD

The ● denotes the specifications which apply over the full

● ±10 µA

35 mA

3

LTC1420

WU

POWER REQUIRE E TS

range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V
OV
V

I
I
P

DD

DD

SS

DD

SS

D

Positive Supply Voltage (Note 10) 4.75 5.25 V
Output Supply Voltage (Note 10) 2.7 5.25 V
Negative Supply Voltage Dual Supply Mode – 5.25 –4.75 V

Positive Supply Current ● 48 58 mA
Negative Supply Current ● 1.4 2.5 mA
Power Dissipation ● 250 300 mW

The ● denotes the specifications which apply over the full operating temperature

Single Supply Mode 0 V

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

SAMPLE

t

CONV

t

ACQ

t

H

t

L

t

AP

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below V
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.

Note 4: When these pin voltages are taken below V
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. GAIN is not clamped to VDD. When CLK
is taken above V
can handle input currents of greater than 100mA above V
latchup.

Maximum Sampling Frequency ● 0.02 10 MHz
Conversion Time ● 70 90 ns
Acquisition Time ● 10 30 ns
CLK High Time ● 20 50 ns
CLK Low Time ● 20 50 ns
Aperature Delay of Sample-and-Hold –250 ps

, it will be clamped by an internal diode. The CLK pin

DD

The ● denotes the specifications which apply over the full operating temperature

or above VDD, they

SS

they will be clamped

SS

without

DD

Note 5: V
otherwise specified.

Note 6: Dynamic specifications are guaranteed for dual supply operation
with a single-ended +A
dynamic specifications, refer to the Typical Performance Characteristics.

Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.

Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and
1111 1111 1111.

Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.

= 5V, VSS = –5V or 0V, f

DD

input and –AIN grounded. For single supply

IN

= 10MHz, tr = tf = 5ns unless

SAMPLE

4

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1420

S/(N+D) vs Input Frequency
and Amplitude

75

VIN = 0dB

70

VIN = –6dB

65

DUAL SUPPLIES

60

±2.048V RANGE

S/(N + D) (dB)

GAIN = 1×

55

50

0.1

VIN = –20dB

1

INPUT FREQUENCY (MHz)

S/(N+D) vs Input Frequency
and Amplitude

75

70

65

60

S/(N + D) (dB)

55

50

0.1

VIN = 0dB

VIN = –6dB

VIN = –20dB

1

INPUT FREQUENCY (MHz)

10

1420 G01

SINGLE SUPPLY
±1.024V RANGE
GAIN = 2×

10

1420 G02

100

100

Spurious-Free Dynamic Range
vs Input Amplitude

100

90

80

70

60

SFDR (dBc AND dBFS)

50

40

–50

–40 –30 –20 –10

dBFS

dBc

INPUT AMPLITUDE (dBFS)

Spurious-Free Dynamic Range
vs Input Amplitude

100

90

80

70

60

SFDR (dBc AND dBFS)

50

40

–50

–40 –30 –20 –10

dBFS

dBc

INPUT AMPLITUDE (dBFS)

DUAL SUPPLIES
±2.048V RANGE
GAIN = 1×

= 5MHz

f

IN

1420 G03

SINGLE SUPPLY
±1.024V RANGE
GAIN = 2×

= 5MHz

f

IN

1420 G05

Distortion vs Input Frequency

–50

DUAL SUPPLIES
±2.048V RANGE

–55

GAIN = 1×

–60

= 0dBFS

A

IN

–65

–70

–75

–80

DISTORTION (dB)

–85

–90

0

–95

0

THD

2ND

3RD

1 100

INPUT FREQUENCY (MHz)

10

1420 G04

Distortion vs Input Frequency

–50

SINGLE SUPPLY
±1.024V RANGE

–55

GAIN = 2×

–60

= 0dBFS

A

IN

–65

–70

–75

–80

DISTORTION (dB)

–85

–90

0

–95

0

THD

1 100

INPUT FREQUENCY (MHz)

3RD

2ND

10

1420 G06

SFDR vs Input Frequency,
Differential Input Grounded Input Histogram

–50

DUAL SUPPLIES

–55

±2.048V RANGE
GAIN = 1×

–60

= 0dBFS

A

IN

–65
–70

–75

SFDR (dB)

–80

–85
–90
–95

–100

0.1

1

INPUT FREQUENCY (MHz)

10

100

1420 F07

SFDR vs Input Frequency,
Differential Input

–50

SINGLE SUPPLY

–55

±1.024V RANGE
GAIN = 2×

–60

= 0dBFS

A

IN

–65
–70

–75

SFDR (dB)

–80
–85
–90

–95

–100

0.1

1

INPUT FREQUENCY (MHz)

= 4.096V

V

REF

GAIN = 1×

HITS

1570

10

1420 F08

100

N – 1

410554

CODE

1572

N

N + 1

1420 F09

5

LTC1420

FREQUENCY (MHz)

0

–120

AMPLITUDE (dB)

–100

–80

–60

–40

–20

0

1234

1420 G13

5

f

SAMPLE

= 10Msps

f

IN

= 5.048828125MHz
SFDR = 83.2dB
SINAD = 71dB
V

IN

= 4V

P-P

±5V SUPPLIES

UW

TYPICAL PERFOR A CE CHARACTERISTICS

IDD vs Clock Frequency

52

50

48

V

= 4.096V

REF

46

(mA)

DD

I

44

42

40

0

2468

CLOCK FREQUENCY (MHz)

CMRR vs Input Frequency

90

80

70

60

50

40

CMRR (dB)

30

20

10

0

0.01

0.1 10

INPUT FREQUENCY (MHz)

V

REF

1

= 2.048V

1420 G10

1420 G12

ISS vs Clock Frequency

1.4

1.2

1.0

0.8

(mA)

SS

I

0.6

0.4

0.2

10

0

24 10

0

CLOCK FREQUENCY (MHz)

86

1420 G11

LTC1420 Nonaveraged 4096 Point FFT

PIN FUNCTIONS

+AIN (Pin 1):
–AIN (Pin 2): Negative Analog Input.
VCM (Pin 3): 2.5V Reference Output.Optional input com-

mon mode for single supply operation. Bypass to GND
with a 1µF to 10µF ceramic.

SENSE (Pin 4): Reference Programming Pin. Ground
selects V
SENSE to VDD to drive V

V

10µF ceramic.

6

UUU

Positive Analog Input.

(Pin 5): DAC Reference. Bypass to GND with a 1µF to

REF

= 4.096V. Short to V

REF

REF

for 2.048V. Connect

REF

with an external reference.

GND (Pin 6): DAC Reference Ground.
VDD (Pin 7): Analog 5V Supply. Bypass to GND with a 1µF

to 10µF ceramic.

GND (Pin 8): Analog Power Ground.
D11 to D0 (Pins 9 to 20): Data Outputs. The output format

is two’s complement.

OGND (Pin 21): Output Logic Ground. Tie to GND.
OVDD (Pin 22): Positive Supply for the Output Logic.

Connect to Pin 23 for 5V logic. If not shorted to Pin 23,
bypass to GND with a 1µF ceramic.

LTC1420

U

UU

PIN FUNCTIONS

VDD (Pin 23): Analog 5V Supply. Bypass to GND with a 1µF
ceramic.

GND (Pin 24): Analog Power Ground.
VSS (Pin 25): Negative Supply. Can be –5V or 0V. If VSS is

not shorted to GND, bypass to GND with a 1µF ceramic.

UU

W

FUNCTIONAL BLOCK DIAGRA

GAIN

+

A

IN

PIPELINED 12-BIT ADCS/H

–A

IN

V

CM

DIGITAL CORRECTION

REFERENCE

2.048V

SENSE

V

REF

MODE SELECT

CLK (Pin 26): Conversion Start Signal. This active high
signal starts a conversion on its rising edge.

OF (Pin 27): Overflow Output. This signal is high when the
digital output is 011111111111 or 100000000000.

GAIN (Pin 28): Gain Select for Input PGA. 5V selects an
input gain of 1, 0V selects a gain of 2.

DD

OPTIONAL 3V
LOGIC SUPPLY

OF

D11 (MSB)

D0 (LSB)

CLK

5V

2.5V

LOGIC

V

DD

(PIN 7)

V

DD

(PIN 23) OV

OUTPUT
BUFFERS

UWW

TI I G DIAGRA

0V OR –5V

ANALOG

INPUT

CLK

DATA

OUTPUT

GND
(PIN 24)

t

ACQ

GND
(PIN 8)

N + 2

V

SS

N

t

H

t

N – 3

t

CLOCK

CONV

GND
(PIN 6)

N + 1

t

L

N – 2 N – 1 N

OGND

N + 3

1420 BD

1420 TD

7

LTC1420

U

WUU

APPLICATIONS INFORMATION

Conversion Details

The LTC1420 is a high performance 12-bit A/D converter
that operates up to 10Msps. It is a complete solution with
an on-chip sample-and-hold, a 12-bit pipelined CMOS
ADC, a low drift programmable reference and an input
programmable gain amplifier. The digital output is paral­lel, with a 12-bit two’s complement output and an out-of­range (overflow) bit.

The rising edge of the CLK begins a conversion. The
differential analog inputs are simultaneously sampled and
passed on to the pipelined A/D. After two more conversion
starts (plus a 70ns conversion time) the digital outputs are
updated with the conversion result and will be ready for
capture on the third rising clock edge. Thus, even though
a new conversion is begun every time CLK goes high, each
result takes three clock cycles to reach the output.

The analog signals that are passed from stage to stage in
the pipelined A/D are stored on capacitors. The signals on
these capacitors will be lost if the delay between conver­sions is too long. For accurate conversion results, the part
should be clocked faster than 20kHz.

In some pipelined A/D converters if there is no clock
present, dynamic logic on the chip will droop and the
power consumption sharply increases. The LTC1420
doesn’t have this problem. If the part is not clocked for
500µs, an internal timer will refresh the dynamic logic.
Thus, the clock can be turned off for long periods of time
to save power.

Power Supplies

The LTC1420 will operate from either a single 5V or dual
±5V supply, making it easy to interface the analog input to
single or dual supply systems. The digital output drivers
have their own power supply pin (OVDD) which can be set
from 3V to 5V, allowing direct connection to either 3V or
5V digital systems. For single supply operation, VSS should
be connected to analog ground. For dual supply operation,
VSS should be connected to – 5V. Both VDD pins should be
connected to a clean 5V analog supply. (Don’t connect V
to a noisy system digital supply.)

DD

Analog Input Ranges

The LTC1420 has a flexible analog input with a wide
selection of input ranges. The input range is always
differential and is set by the voltages at the V

and the

REF

GAIN pins (Figure 1). The input range of the A/D core is
fixed at ±V

/2. The reference voltage, V

REF

, is either set

REF

by the on-chip voltage reference or directly driven by an
external voltage. The GAIN pin is a digital input that
controls the gain of a preamplifier in the sample-and-hold
circuit. The gain of this PGA can be set to 1× or 2×. Table␣ 1
gives the input range in terms of V

Table 1

GAIN PIN PGA GAIN (V

5V (Logic H) 1× –V
OV (Logic L) 2× –V

GAIN

1x/2x

+A

IN

+

V

IN

–A

IN

–

V

REF

Figure 1. Analog Input Circuit

and GAIN.

REF

INPUT RANGE

IN

REF

REF

±V

REF

+

= A

– A

IN

/2 < VIN < V
/4 < VIN < V

ADC

/2PGA S/H

CORE

1420 F01

IN

REF

REF

–

)

/2
/4

Internal Reference

Figure 2 shows a simplified schematic of the LTC1420
reference circuitry. An on-chip temperature compensated
bandgap reference (VCM) is factory trimmed to 2.500V.
The voltage at the V
to ±V

/2. An internal voltage divider converts VCM to

REF

pin sets the input span of the ADC

REF

2.048V, which is connected to a reference amplifier. The
reference programming pin, SENSE, controls how the
reference amplifier drives the V

pin. If SENSE is tied to

REF

ground, the reference amplifier feedback is connected to
the R1/R2 voltage divider, thus making V
SENSE is tied to V
connected to SENSE thus making V

, the reference amplifier feedback is

REF

REF

= 4.096V. If

REF

= 2.048V. If SENSE

is tied to VDD, the reference amplifier is disconnected from

8

LTC1420

1420 F03b

1µF

1µF

V

REF

LTC1420

SENSE

V

CM

2.048V

–

+

5k

5k

LTC1450

U

WUU

APPLICATIONS INFORMATION

V

and V

REF

two additional resistors, V
between 2.048V and 4.5V.

An external reference or a DAC can be used to drive V
over a 0V to 5V range (Figures 3a and 3b). The input
impedance of the V
required for high accuracy. Driving V
useful in applications where the peak input signal ampli­tude may vary. The input span of the ADC can then be
adjusted to match the peak input signal, maximizing the
signal-to-noise ratio.

Both the VCM and V
capacitors to ground. For best performance, 1µF or larger
ceramic capacitors are recommended. For the case of
external circuitry driving V
used at V
this case, a 0.05µF or larger ceramic capacitor is accept-
able.

can be driven by an external voltage. With

REF

can be set to any voltage

REF

pin is 1k, so a buffer may be

REF

with a DAC is

REF

pins must be bypassed with

REF

, a smaller capacitor can be

REF

so the input range can be changed quickly. In

REF

REF

V

REF

SENSE

V

CM

1µF

1µF

R1
5k

R2
5k

LOGIC

2.5V

REFERENCE

Figure 2. Reference Circuit

TO
ADC

+

1k

–

2.048V

1420 F02

The VCM pin is a low output impedance 2.5V reference that
can be used by external circuitry. For single 5V supply
applications it is convenient to connect – AIN directly to the
VCM pin.

Driving the Analog Inputs

The differential inputs of the LTC1420 are easy to drive.
The inputs may be driven differentially or single-ended
(i.␣ e., the – AIN input is held at a fixed value). The – AIN and
+AIN inputs are simultaneously sampled and any com­mon mode signal is reduced by the high common mode
rejection of the sample-and-hold circuit. Any common
mode input value is acceptable as long as the input pins
stay between VDD and VSS. During conversion, the analog
inputs are high impedance. At the end of conversion, the
inputs draw a small current spike while charging the
sample-and-hold.

For superior dynamic performance in dual supply mode,
the LTC1420 should be operated with the analog inputs
centered at ground, and in single supply mode the inputs
should be centered at 2.5V. If required, the analog inputs
can be driven differentially via a transformer. Refer to
Table 2 for a summary of the analog input and reference
configurations and their relative advantages.

5V

V

IN

V

LT1019A-2.5

OUT

1µF

1µF

V

REF

SENSE5V

V

CM

LTC1420

1420 F03a

Figure 3a. Using the LT1019-2.5 As an
External Reference; Input Range = ±1.25V

Figure 3b. Driving V

with a DAC

REF

9

LTC1420

U

WUU

APPLICATIONS INFORMATION

Table 2. Comparison of Analog Input Configurations

SUPPLIES COUPLING V

REF

GAIN A

+

IN

±5V DC 4.096V 1×±2.048 0 Best SNR, THD
5V DC 4.096V 2× 2.5 ± 1.024 2.5 Best SINAD, THD for Single Supply
5V DC 2.048V 1× 2.5 ± 1.024 2.5 Worse Noise than Above Case
5V DC 4.096V 1× 2.5 ± 2.048 2.5 Best Single Supply Noise, THD Is Not Optimal
5V DC 4.096V 1× 0 to 4.096 2.048 Same As Above
±5V AC 4.096V 1×±1.024 ±1.024 Very Best SNR, THD

(Transformer)

5V AC 4.096V 1× 2.5 ± 1.024 2.5 ± 1.024 Very Best SNR, THD for Single Supply

(Transformer)

DC Coupling the Input

In most applications the analog input signal can be directly
coupled to the LTC1420 inputs. If the input signal is
centered around ground, such as when dual supply op
amps are used, simply connect –AIN to ground and
connect VSS to –5V (Figure 4). In a single power supply
system with the input signal centered around 2.5V, con­nect – AIN to VCM and VSS to ground (Figure 5). If the input
signal is not centered around ground or 2.5V, the voltage
for – AIN must be generated externally by a resistor divider
or a voltage reference (Figure 6).

5V

AC Coupling the Input

The analog inputs to the LTC1420 can also be AC coupled

0V

V

IN

+A

IN

LTC1420

–A

IN

through a capacitor, though in most cases it is simpler to
directly couple the input to the ADC. Figure 7 shows an
example where the input signal is centered around ground
and the ADC operates from a single 5V supply. Note that

V

CM

V

1µF

SS

1420 F04

–5V

Figure 4. DC Coupling a Ground
Centered Signal (Dual Supply System)

5V

2.5V

V

IN

1µF

+A

–A

V

CM

IN

LTC1420

IN

V

SS

1420 F05

the performance would improve if the ADC was operated
from a dual supply and the input was directly coupled (as
in Figure 4). With AC coupling the DC resistance to ground
should be roughly matched for + AIN and – AIN to maintain
offset accuracy.

0V

–

A

IN

4.096V

0V

5V

COMMENTS

V

IN

2.048V

+A

IN

LTC1420

–A

IN

SENSE

5V

V

SS

1420 F06

Figure 6. DC Coupling a 0V to 4.096V Signal

5V

C

V

IN

RR

C

1µF

+A

–A

V

CM

IN

LTC1420

IN

V

SS

1420 F07

10

Figure 5. DC Coupling a Signal Centered
Around 2.5V (Single Supply System)

Figure 7. AC Coupling to the LTC1420. Note That the Input Signal

Can Almost Always Be Directly Coupled with Better Performance

LTC1420

+A

IN

V

IN

LTC1420

–A

IN

470pF

30Ω

U

WUU

APPLICATIONS INFORMATION

Differential Operation

The THD and SFDR performance of the LTC1420 can be
improved by using a center tap RF transformer to drive the
inputs differentially. Though the signal can no longer be
DC coupled, the improvement in dynamic performance
makes this an attractive solution for some applications.
Typical connections for single and dual supply systems
are shown in Figures 8a and 8b. Good choices for trans­formers are the Mini Circuits T1-1T (1:1 turns ratio) and
T4-6T (1:4 turns ratio). For best results, the transformer
should be located close to the LTC1420 on the printed
circuit board.

5V

V

IN

MINI CIRCUITS

T1-1T

15Ω

470pF

15Ω

1µF

+A

–A

V

IN

IN

CM

LTC1420

V

SS

1420 F08a

The second requirement is that the closed-loop bandwidth
must be greater than 100MHz to ensure adequate small­signal settling for full throughput rate. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions.

The best choice for an op amp to drive the LTC1420 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifica­tions are most critical and time domain applications where
DC accuracy and settling time are most critical.

Input Filtering

The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1420 noise and distortion. The small-signal band­width of the sample-and-hold circuit is 100MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications.

Figure 8a. Single Supply Transformer Coupled Input

For example, Figure 9 shows a 470pF capacitor from + A

IN

to –AIN and a 30Ω source resistor to limit the input

5V

MINI CIRCUITS

T1-1T

V

IN

Figure 8b. Dual Supply Transformer Coupled Input

15Ω

470pF

15Ω

1µF

+A

IN

LTC1420

–A

IN

V

CM

V

–5V

SS

1420 F08b

bandwidth to 11.3MHz. The 470pF capacitor also acts as
a charge reservoir for the input sample-and-hold and
isolates the amplifier driving VIN from the ADC’s small
current glitch. In undersampling applications, an input
capacitor this large may prohibitively limit the input band­width. If this is the case, use as large an input capacitance
as possible. High quality capacitors and resistors should
be used since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self-heating and from damage that may

Choosing an Input Amplifier

occur during soldering. Metal film surface mount resis­tors are much less susceptible to both problems.

Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 100MHz, then the
output impedance at 100MHz must be less than 100Ω.

Figure 9. RC Input Filter

11

LTC1420

U

WUU

APPLICATIONS INFORMATION

Digital Outputs and Overflow Bit (OF)

Figure 10 shows the ideal input/output characteristics for
the LTC1420. The output data is two’s complement binary
for all input ranges and for both single and dual supply
operation. One LSB = V
binary output, invert the MSB (D11). The overflow bit (OF)
indicates when the analog input is outside the input range
of the converter. OF is high when the output code is 1000
0000 0000 or 0111 1111 1111.

011…111
011…110
011…101

OUTPUT CODE

100…010
100…001
100…000

–(FS – 1LSB) FS – 1LSB

Figure 10. LTC1420 Transfer Characteristics

Full-Scale and Offset Adjustment

In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error should be adjusted before full-scale error. Figure 11
shows a method for error adjustment for a dual supply,

4.096V application. For zero offset error apply –0.5mV
(i.␣ e., – 0.5LSB) at + AIN and adjust R1 until the output code
flickers between 0000 0000 0000 and 1111 1111 1111.
For full-scale adjustment, apply an input voltage of 2.0465V
(FS – 1.5LSBs) at + AIN and adjust R2 until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.

Digital Output Drivers

The LTC1420 output drivers can interface to logic operat­ing from 3V to 5V by setting OVDD to the logic power
supply. If 5V output is desired, OVDD can be shorted to V
and share its decoupling capacitor. Otherwise, OVDD re­quires its own 1µF decoupling capacitor. To prevent digital

/4096. To create a straight

REF

INPUT VOLTAGE (V)

1420 F10

1

OVERFLOW
BIT

0

DD

noise from affecting performance, the load capacitance on
the digital outputs should be minimized. If large capacitive
loads are required (>30pF), external buffers or 100Ω
resistors in series with the digital outputs are suggested.

5V

+A

V

5V

R1

50k

–5V

Figure 11. Offset and Full-Scale Adjust Circuit

IN

24k

100Ω

10k1µF

R2

1k

10k

IN

–A

IN

V

REF

SENSE

LTC1420

V

SS

–5V

1420 F11

Timing

The conversion start is controlled by the rising edge of the
CLK pin. Once a conversion is started, it cannot be stopped
or restarted until the conversion cycle is complete. Output
data is updated at the end of conversion, or about 70ns
after a conversion is begun. There is an additional two
cycle pipeline delay, so the data for a given conversion is
output two full clock cycles plus 70ns after the convert
start. Thus, output data can be latched on the third CLK
rising edge after the rising edge that samples the input.

Clock Input

The LTC1420 only uses the rising edge of the CLK pin for
internal timing, and CLK doesn’t necessarily need to have
a 50% duty cycle. For optimal AC performance, the rise
time of the CLK should be less than 5ns. If the available
clock has a rise time slower than 5ns, it can be locally sped
up with a logic gate. With single supply operation, the
clock can be driven with 5V CMOS, 3V CMOS or TTL logic
levels. With dual power supplies, the clock should be
driven with 5V CMOS levels.

As with all fast ADCs, the noise performance of the
LTC1420 is sensitive to clock jitter when high speed inputs

12

LTC1420

U

WUU

APPLICATIONS INFORMATION

are present. The SNR performance of an ADC when the
performance is limited by jitter is given by:

SNR = –20log (2πfINtJ)dB

where fIN is the frequency of an input sine wave and tJ is
the root-mean-square jitter due to the clock, the analog
input and the A/D aperture jitter. To minimize clock jitter,
use a clean clock source such as a crystal oscillator, treat
the clock signals as sensitive analog traces and use
dedicated packages with good supply bypassing for any
clock drivers.

Board Layout

To obtain the best performance from the LTC1420, a
printed circuit board with a ground plane is required.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track.

An analog ground plane separate from the logic system
ground should be placed under and around the ADC.
Pins␣ 6, 8 and 24 (GND), Pin 21 (OGND) and all other
analog grounds should be connected to this ground plane.
In single supply mode, Pin 25 (VSS) should also be

connected to this ground plane. All bypass capacitors for
the LTC1420 should also be connected to this ground
plane (Figure 12). The digital system ground should be
connected to the analog ground plane at only one point,
near the OGND pin.

The analog ground plane should be as close to the ADC as
possible. Care should be taken to avoid making holes in the
analog ground plane under and around the part. To ac­complish this, we recommend placing vias for power and
signal traces outside the area containing the part and the
decoupling capacitors (Figure 13).

Supply Bypassing

High quality, low series resistance ceramic 1µF capacitors
should be used at both VDD pins, VCM and V

. If VSS is

REF

connected to –5V it should also be bypassed to ground
with 1µF. In single supply operation, VSS should be
shorted to the ground plane as close to the part as
possible. If OVDD is not shorted to Pin 23 (VDD), it also
requires a 1µF decoupling capacitor to ground. Surface
mount capacitors such as the AVX 0805ZC105KAT pro­vide excellent bypassing in a small board space. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.

ANALOG

INPUT

CIRCUITRY

+
–

470pF

1

+A

IN

–A

2

LTC1420

V

IN

V

CM

3

1µF

GND

REF

5

1µF

ANALOG GROUND PLANE

V

6

GND

DD

7

1µF

V

DD

8

23

1µF

Figure 12. Power Supply Grounding

LTC1420

PLACE NON-GROUND

VIAS AWAY FROM

GROUND PLANE AND

BYPASS CAPACITORS

AVOID BREAKING GROUND PLANE

IN THIS AREA

Figure 13. Cross Section of LTC1420 Printed Circuit Board

OV

DIGITAL
SYSTEM

24

BYPASS
CAPACITOR

ANALOG
GROUND
PLANE

1420 F13

V

OGND

SS

25

21

1µF

1420 F12

GND

DD

22

1µF

13

LTC1420

J1

BNC

E6

1 AGND

(J5)

(SMB)

1

+A

IN

2

1

2

R15

51Ω

OPT

5 4 3 2

J2

BNC

(J6)

(SMB)

1

–A

IN

2

R16

51Ω

OPT

5 4 3 2

2C

2D8

2D7

GND

2D6

2D5

V

CC

2D4

2D3

GND

2D2

2D1

1D8

1D7

GND

1D6

1D5

V

CC

1D4

1D3

GND

1D2

1D1

1C

2OE

2Q8

2Q7

GND

2Q6

2Q5

V

CC

2Q4

2Q3

GND

2Q2

2Q1

1Q8

1Q7

GND

1Q6

1Q5

V

CC

1Q4

1Q3

GND

1Q2

1Q1

1OE

2526272829303132333435363738394041424344454647

48

24232221201918171615141312111098765432

1

D5D4D3D2D1D0OGND

OV

DD

VDDGND

VSSCLKOFGAIN

D6D7D8

D9

D10

D11 (MSB)

GND

V

DD

GND

V

REF

SENSE

V

CM

–AIN+A

IN

15161718192021

22

2324252627

28

1413121110

9

8765432

1

V

CC

V

CC

V

CC

24

5

3U3

NC7S04M5

J3

BNC

(J7)

(SMB)

J4

HD2X8-079

1

1

CLOCK

2

R17

51Ω

2

C7

0.1µF

12

11R1 2

100 X 15 PLCS

D0

U2, 74ACT16373DL

U1, LTC1420

C11 0.1µF

21

C9 0.1µF

21

21

12

C1 1µF

12

C3 1µF

C2 1µF

12

C10 0.1µF

12R2 2 D1

13R3 2 D2

14R4 2 D3

15R5 2 D4

16R6 2 D5

17R7 2 D6

18R8 2 D7

19R9 2 D8

110R10 2 D9

111R11 2 D10

112R12 2 D11

113R21 2

114R13 2 OF

115

1

2

3

4

5

6

789

10

1112131415

16

16

R14 2 CLK

D11

2 3 4 5

1420 F14

1

2

R20

0Ω

12

12

JP1

JP2

213

JP7

JP3

12

12

12

JP4

JP5

JP6

1

R19

0Ω

2

1

R18

20Ω

2

C6

470pF

21

C4 1µF

21

C5 1µF

E7

D1

MBR0520LT1

1 GAIN

E5

1

V

SS

E4

1

V

DD

E3

1

OV

DD

E2

1

OGND

21

C8 0.1µF

21

C12 1µF

E1

1

V

CC

V

CC

U

WUU

APPLICATIONS INFORMATION

Figure 14. LTC1420 Demo Board Schematic

14

LTC1420

U

WUU

APPLICATIONS INFORMATION

Figure 15. Top Silkscreen Layer for LTC1420 Demo Board

Figure 16. Top Layer for LTC1420 Demo Board

15

LTC1420

U

WUU

APPLICATIONS INFORMATION

Figure 17. Ground Plane Layer for LTC1420 Demo Board

16

Figure 18. Power Plane Layer for LTC1420 Demo Board

LTC1420

U

APPLICATIONS INFORMATION

WUU

Figure 19. Bottom Layer for LTC1420 Demo Board

17

LTC1420

TYPICAL APPLICATIONS

Single Supply, 10Msps, 12-Bit ADC with 3V Logic Outputs

ANALOG INPUT

(2.5V ±1.024V)

5V

1µF

U

1µF

30Ω

1µF

470pF

NPO

LTC1420

1

+A

IN

2

–A

IN

3

V

CM

4

SENSE

5

V

REF

6

GND

7

V

DD

8

GND

9

D11

10

D10

11

D9

12

D8

13

D7

14

D6

GAIN

CLK

V

GND

V

OV

OGND

28

27

OF

26

10MHz CLOCK

25

SS

24

23

DD

22

DD

21

20

D0

19

D1

18

D2

17

D3

16

D4

15

D5

3V

1µF

5V

1µF

0V TO 3V
12-BIT
PARALLEL DATA
PLUS OVERFLOW

ANALOG INPUT

(±2.048V)

Dual Supply, 10Msps, 12-Bit ADC with 71dB SINAD

30Ω

470pF, NPO

1µF

1µF

5V

1µF

LTC1420

1

+A

IN

2

–A

IN

3

V

CM

4

SENSE

5

V

REF

6

GND

7

V

DD

8

GND

9

D11

10

D10

11

D9

12

D8

13

D7

14

D6

GAIN

CLK

V

GND

V

OV

OGND

28

5V

27

OF

26

10MHz CLOCK

25

SS

24

23

DD

22

DD

21

20

D0

19

D1

18

D2

17

D3

16

D4

15

D5

1420 TA03

–5V

1µF

5V

1µF

12-BIT
PARALLEL DATA
PLUS OVERFLOW

18

1420 TA04

PACKAGE DESCRIPTION

LTC1420

U

Dimensions in inches (millimeters) unless otherwise specified.

GN Package

28-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.015

± 0.004

(0.38 ± 0.10)

0.0075 – 0.0098
(0.191 – 0.249)

0.016 – 0.050

(0.406 – 1.270)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0° – 8° TYP

× 45°

0.229 – 0.244

(5.817 – 6.198)

0.053 – 0.069

(1.351 – 1.748)

0.008 – 0.012

(0.203 – 0.305)

12

3

0.386 – 0.393*
(9.804 – 9.982)

5

4

678 9 10 11 12

0.0250

(0.635)

BSC

0.033

202122232425262728

19

18

16

17

13 14

(0.838)

15

(0.102 – 0.249)

REF

0.150 – 0.157**
(3.810 – 3.988)

0.004 – 0.009

GN28 (SSOP) 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the
interconnection of its circuits as described herein will not infringe on existing patent rights.

However,

19

LTC1420

TYPICAL APPLICATION

U

Single 3.3V Supply, 10Msps, 12-Bit ADC

3.3V

15µF

15Ω

ANALOG INPUT

(2.048V

1.4MHz BOOST REGULATOR

4.7µH

+

SHDN

V

IN

SHDN FB

SW

LT1613

GND

100k

32.4k

15µF

+

)

P-P

–

5V

+

0.1µF0.1µF

15Ω

470pF, NPO

1µF

1µF

1µF

LTC1420

1

+A

IN

2

–A

IN

3

V

CM

4

SENSE

5

V

REF

6

GND

7

V

DD

8

GND

9

D11

10

D10

11

D9

12

D8

13

D7

14

D6

GAIN

CLK

V

GND

V

OV

OGND

28

27

26

25

24

23

22

21

20

19

18

17

16

15

OVERFLOW BIT

10MHz CLOCK

3.3V

1µF

5V

1µF

0V TO 3.3V
12-BIT DATA

1420 TA05

TO PIN 7

OF

SS

DD

DD

D0

D1

D2

D3

D4

D5

4096 Point FFT of Above Circuit with a 1MHz Input. Note That There

Are No Spurs From the 1.4MHz Boost Regulator

0

–20

–40

–60

AMPLITUDE (dB)

–80

–100

–120

0

1234

f

SAMPLE

= 1.0083MHz, 2V

f

IN

SFDR = 83dB
SINAD = 69.8dB

FREQUENCY (MHz)

= 10Msps

P-P

5

1420 TA06

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1405 12-Bit, 5Msps, Sampling ADC with Parallel Output Pin Compatible with the LTC1420
LTC1412 12-Bit, 3Msps, Sampling ADC with Parallel Output Best Dynamic Performance, SINAD = 72dB at Nyquist
LTC1415 Single 5V, 12-Bit, 1.25Msps with Parallel Output 55mW Power Dissipation, 72dB SINAD
LT1019 Precision Bandgap Reference 0.05% Max Initial Accuracy, 5ppm/°C Max Drift

20

Linear T echnolog y Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

1420f LT/TP 1299 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1999