LTC1410
12-Bit, 1.25Msps Sampling
A/D Converter with Shutdown
EATU
F
■
1.25Msps Sample Rate
■
Power Dissipation: 160mW
■
71dB S/(N + D) and 82dB THD at Nyquist
■
No Pipeline Delay
■
Nap (7mW) and Sleep (10µW) Shutdown Modes
■
Operates with Internal 15ppm/°C Reference
RE
S
or External Reference
■
True Differential Inputs Reject Common Mode Noise
■
20MHz Full Power Bandwidth Sampling
■
±2.5V Bipolar Input Range
■
28-Pin SO Wide Package
U
O
PPLICATI
A
■
Telecommunications
■
Digital Signal Processing
■
Multiplexed Data Acquisition Systems
■
High Speed Data Acquisition
■
Spectrum Analysis
■
Imaging Systems
S
DUESCRIPTIO
The LTC®1410 is a 0.65µs, 1.25Msps, 12-bit sampling
A/D converter that draws only 160mW from ±5V supplies.
This easy-to-use device includes a high dynamic range
sample-and-hold, a precision reference and requires no
external components. Two digitally selectable power shutdown modes provide flexibility for low power systems.
The LTC1410’s full-scale input range is ±2.5V. Maximum
DC specifications include ±1LSB INL and ±1LSB DNL over
temperature. Outstanding AC performance includes 71dB
S/(N + D) and 82dB THD at the Nyquist input frequency of
625kHz.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 20MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
The ADC has a µ P compatible, 12-bit parallel output port.
There is no pipeline delay in the conversion results. A
separate convert start input and a data ready signal (BUSY)
ease connections to FIFOs, DSPs and microprocessors.
10µF
+
U
O
A
PPLICATITYPICAL
Complete 1.25MHz, 12-Bit Sampling A/D Converter
DIFFERENTIAL
ANALOG INPUT
(–2.5V TO 2.5V)
2.50V
OUTPUT
V
REF
0.1µF
12-BIT
PARALLEL
BUS
10
11
12
13
14
1
+A
2
–A
3
V
4
REFCOMP
5
AGND
6
D11(MSB)
7
D10
8
D9
9
D8
D7
D6
D5
D4
DGND
REF
IN
IN
LTC1410
NAP/SLP
AV
DV
V
BUSY
CONVST
RD
SHDN
OGND
28
DD
27
26
25
24
23
22
21
20
19
18
17
16
15
–5V
10µF
µP CONTROL
LINES
1410 TA01
DD
SS
CS
D0
D1
D2
D3
10µF
0.1µF
, LTC and LT are registered trademarks of Linear Technology Corporation.
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
5V
+
0.1µF
12 74
10
8
6
EFFECTIVE BITS
4
2
f
SAMPLE
0
1k
NYQUIST
= 1.25MHz
10k 100k 1M 10M
INPUT FREQUENCY (Hz)
LTC1410 • TA02
68
62
56
S/(N + D) (dB)
50
1
LTC1410
W
O
A
AVDD = DVDD = VDD (Notes 1, 2)
LUTEXI T
S
A
WUW
ARB
U
G
I
S
Supply Voltage (VDD)................................................ 6V
Negative Supply Voltage (VSS) ............................... –6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) .................................. VSS – 0.3V to VDD + 0.3V
Digital Input Voltage (Note 4) ............ VSS – 0.3V to 10V
Digital Output Voltage................... – 0.3V to VDD + 0.3V
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1410C .............................................. 0°C to 70°C
LTC1410I........................................... –40°C to 85°C
Storage Temperature Range................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
PACKAGE
1
+A
IN
2
–A
IN
3
V
REF
AGND
D10
D9
D8
D7
D6
D5
D4
DGND
G PACKAGE
T
JMAX
T
4
5
6
7
8
9
10
11
12
13
14
= 110°C, θJA = 90°C/W (SW)
= 110°C, θJA = 95°C/W (G)
JMAX
REFCOMP
D11(MSB)
28-LEAD PLASTIC SSOP
/
O
RDER I FOR ATIO
TOP VIEW
28
AV
DD
27
DV
DD
26
V
SS
25
BUSY
24
CS
23
CONVST
22
RD
21
SHDN
20
NAP/SLP
19
OGND
18
D0
17
D1
16
D2
15
D3
SW PACKAGE
28-LEAD PLASTIC SO WIDE
PART NUMBER
LTC1410CG
LTC1410CSW
LTC1410IG
LTC1410ISW
WU
U
ORDER
Consult factory for Military grade parts.
U
U
IN
IN
ACQ
AP
VERTER
CCHARA TERIST
ICS
The ● denotes specifications which apply over the full operating
● ±8 LSB
= 0 ● ±15 ppm/°C
OUT(REF)
U
PUT
LOG
Analog Input Range (Note 9) 4.75V ≤ VDD ≤ 5.25V, –5.25V ≤ VSS ≤ –4.75V ● ±2.5 V
Analog Input Leakage Current CS = High ● ±1 µA
Analog Input Capacitance Between Conversions 17 pF
Sample-and-Hold Acquisition Time ● 50 100 ns
Sample-and-Hold Aperture Delay Time –1.5 ns
Sample-and-Hold Aperture Delay Time Jitter 5 ps
IA
The ● denotes specifications which apply over the full operating temperature range, otherwise
During Conversions 5 pF
RMS
CO
temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) ● 12 Bits
Integral Linearity Error (Note 7) ● ±0.3 ±1 LSB
Differential Linearity Error ● ±0.3 ±1 LSB
Offset Error (Note 8) ±2 ±6 LSB
Full-Scale Error ±15 LSB
Full-Scale Tempco I
A
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
I
IN
C
t
t
t
jitter
CMRR Analog Input Common Mode Rejection Ratio –2.5V < (–AIN = AIN) < 2.5V 60 dB
2
LTC1410
W
U
DY
A
ACCURAC Y
IC
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
S/(N + D) Signal-to-(Noise + Distortion) Ratio 100kHz Input Signal (Note 12) ● 70 72.5 dB
THD Total Harmonic Distortion 100kHz Input Signal, First 5 Harmonics –85 dB
Peak Harmonic or Spurious Noise 600kHz Input Signal ● –84 –74 dB
IMD Intermodulation Distortion f
Full Power Bandwidth 20 MHz
Full Linear Bandwidth (S/(N + D) ≥ 68dB) 2.5 MHz
U
UU
I TER AL REFERE CE CHARACTERISTICS
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
Output Voltage I
REF
V
Output Tempco I
REF
V
Line Regulation 4.75V ≤ VDD ≤ 5.25V 0.01 LSB/V
REF
V
Output Resistance I
REF
COMP Output Voltage I
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
OZ
C
OZ
I
SOURCE
I
SINK
High Level Input Voltage V
Low Level Input Voltage VDD = 4.75V ● 0.8 V
Digital Input Current VIN = 0V to V
Digital Input Capacitance 5pF
High Level Output Voltage VDD = 4.75V
Low Level Output Voltage VDD = 4.75V
High-Z Output Leakage D11 to D0 V
High-Z Output Capacitance D11 to D0 CS High (Note 9 ) ● 15 pF
Output Source Current V
Output Sink Current V
POWER REQUIRE E TS
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
V
SS
I
DD
I
SS
Positive Supply Voltage (Notes 10, 11) 4.75 5.25 V
Negative Supply Voltage (Note 10) –4.75 –5.25 V
Positive Supply Current CS = RD = CONVST = 5V ● 12 16 mA
Nap Mode SHDN = 0V, NAP/SLP = 5V 1.5 2.3 mA
Sleep Mode SHDN = 0V, NAP/SLP = 0V 1 100 µA
Negative Supply Current CS = RD = CONVST = 5V ● 20 30 mA
Nap Mode SHDN = 0V, NAP/SLP = 5V 10 200 µA
Sleep Mode SHDN = 0V, NAP/SLP = 0V 1 100 µA
The ● denotes specifications which apply over the full operating temperature range,
600kHz Input Signal (Note 12)
600kHz Input Signal, First 5 Harmonics
= 29.37kHz, f
IN1
= 32.446kHz –84 dB
IN2
● 68 71.0 dB
● –82 –74 dB
The ● denotes specifications which apply over the full
= 0 2.480 2.500 2.520 V
OUT
= 0 ±15 ppm/°C
OUT
–5.25V ≤ V
OUT
= 0 4.06 V
OUT
≤ –4.75V 0.01 LSB/V
SS
≤ 0.1mA 2 kΩ
U
The ● denotes specifications which apply over the full
= 5.25V ● 2.4 V
DD
● ±10 µA
10 mA
W
U
DD
= –10µA 4.5 V
I
O
IO = –200µA ● 4.0 V
= 160µA 0.05 V
I
O
IO = 1.6mA ● 0.10 0.4 V
= 0V to VDD, CS High ● ±10 µA
OUT
= 0V –10 mA
OUT
= V
OUT
DD
The ● denotes specifications which apply over the full operating temperature range,
3
LTC1410
U
W
POWER REQUIRE E TS
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
P
D
W
Power Dissipation 160 230 mW
Nap Mode SHDN = 0V, NAP/SLP = 5V 7.5 12 mW
Sleep Mode SHDN = 0V, NAP/SLP = 0V 0.01 1 mW
U
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
t
CONV
t
ACQ
t
ACQ+CONV
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
Maximum Sampling Frequency ● 1.25 MHz
Conversion Time ● 650 750 ns
Acquisition Time ● 50 100 ns
Throughput Time ● 800 ns
(Acquisition + Conversion)
CS to RD Setup Time (Notes 9, 10) ● 0ns
CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● 10 ns
NAP/SLP↓ to SHDN ↓ Setup Time (Notes 9, 10) ● 10 ns
SHDN↑ to CONVST↓ Wake-Up Time (Note 10) 200 ns
CONVST Low Time (Notes 10, 11) ● 40 ns
CONVST to BUSY Delay CL = 25pF 10 ns
Data Ready Before BUSY↑ 20 35 ns
Delay Between Conversions (Note 10) ● 40 ns
Wait Time RD↓ After BUSY↑ (Note 10) ● –5 ns
Data Access Time After RD↓ CL = 25pF 15 25 ns
Bus Relinquish Time 820 ns
RD Low Time ● t
CONVST High Time ● 40 ns
Aperture Delay of Sample-and-Hold –1.5 ns
The ● denotes specifications which apply over the full operating temperature range,
The ● denotes specifications which apply over the full operating temperature
● 50 ns
● 15 ns
● 35 ns
C
= 100pF 20 35 ns
L
Commercial ● 25 ns
Industrial
● 50 ns
● 30 ns
10
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
and AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below V
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
Note 4: When these pin voltages are taken below VSS, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
Note 5: V
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a singleended +AIN input with –AIN grounded.
without latchup. These pins are not clamped to VDD.
SS
= 5V, VSS = –5V, f
DD
or above VDD without latchup.
SS
= 1.25MHz, tr = tf = 5ns unless
SAMPLE
or above VDD, they
SS
4
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 425ns after the
start of the conversion or after BUSY rises.
Note 12: Signal-to-noise ratio (SNR) is measured at 100kHz and distortion
is measured at 600kHz. These results are used to calculate signal-to-noise
plus distortion (SINAD).
UW
TYPICAL PERFORMAN CE CHAR ACTERISTICS
LTC1410
S/(N + D) vs Input Frequency
and Amplitude
80
70
60
50
40
30
20
10
SIGNAL/(NOISE + DISTORTION) (dB)
VIN = 0dB
VIN = –20dB
VIN = –60dB
f
= 1.25MHz
SAMPLE
0
1k
10k 100k
INPUT FREQUENCY (Hz)
Spurious-Free Dynamic Range vs
Input Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
SPURIOUS-FREE DYNAMIC RANGE (dB)
–100
10k
100k 1M 10M
INPUT FREQUENCY (Hz)
Integral Nonlinearity vs
Output Code
1.0
0.5
0
INL ERROR (LSB)
–0.5
–1.0
512 1536 2560
0
1024
2048
OUTPUT CODE
1M 10M
1410 G01
1410 G04
3072
3504
4096
1410 G07
Signal-to-Noise Ratio vs
Input Frequency
80
70
60
50
40
30
20
SIGNAL-TO-NOISE RATIO (dB)
10
0
1k
10k 100k
INPUT FREQUENCY (Hz)
1M 10M
1410 G02
Intermodulation Distortion Plot
0
–20
–40
–60
–80
AMPLITUDE (dB)
–100
–120
0
100
f
SAMPLE
= 88.19580078kHz
f
IN1
= 111.9995117kHz
f
IN2
200 300 400
FREQUENCY (kHz)
= 1.25MHz
500 600
1410 G05
Power Supply Feedthrough
vs Ripple Frequency
0
V
= 0.1V
RIPPLE
–20
–40
–60
V
–80
–100
–120
1k 100k 1M 10M
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
SS
V
DD
DGND
10k
RIPPLE FREQUENCY (Hz)
1410 G08
Distortion vs Input Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
–100
1k
2ND
10k 100k
INPUT FREQUENCY (Hz)
3RD
1M 10M
Differential Nonlinearity vs
Output Code
1.0
0.5
0
DNL ERROR (LSB)
–0.5
–1.0
512 1536 2560
0
1024
2048
OUTPUT CODE
3072
Input Common Mode Rejection
vs Input Frequency
80
70
60
50
40
30
20
COMMON MODE REJECTION (dB)
10
0
1k
10k 100k
INPUT FREQUENCY (Hz)
1M 10M
THD
3504
1410 G03
4096
1410 G06
1410 G09
5
LTC1410
UU U
PI FU CTIO S
+AIN (Pin 1): Positive Analog Input, ±2.5V.
–AIN (Pin 2): Negative Analog Input, ±2.5V.
V
(Pin 3): 2.50V Reference Output.
REF
REFCOMP (Pin 4): 4.06V Reference Bypass Pin. By-
pass to AGND with 10µ F tantalum in parallel with 0.1µ F
ceramic.
AGND (Pin 5): Analog Ground.
D11 to D4 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D3 to D0 (Pins 15 to 18): Three-State Data Outputs.
OGND (Pin 19): Digital Ground for Output Drivers. Tie
to AGND.
NAP/SLP (Pin 20): Power Shutdown Mode. Selects the
mode invoked by the SHDN pin. Low selects Sleep
mode and high selects quick wake-up Nap mode.
UU W
FU CTIO AL BLOCK DIAGRA
SHDN (Pin 21): Power Shutdown Input. A low logic
level will invoke the Shutdown mode selected by the
NAP/SLP pin.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): The Chip Select input must be low for the
ADC to recognize CONVST and RD inputs.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
VSS (Pin 26): –5V Negative Supply. Bypass to AGND
with 10µF tantalum in parallel 0.1µF ceramic.
DVDD (Pin 27): 5V Positive Supply. Short to Pin 28.
AVDD (Pin 28): 5V Positive Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic.
+A
–A
V
REF
REFCOMP
(4V)
AGND
DGND
C
SAMPLE
IN
AV
DV
V
DD
DD
SS
C
SAMPLE
IN
2k
2.5V REF
ZEROING SWITCHES
+
12-BIT CAPACITIVE DAC
COMPREF AMP
–
INTERNAL
CLOCK
SUCCESSIVE APPROXIMATION
REGISTER
CONTROL LOGIC
NAP/SLP
12
OUTPUT LATCHES
BUSY
CSCONVST RDSHDN
D11
•
•
•
D0
LTC1410 • BD
6
TEST CIRCUITS
SAMPLE
HOLD
+C
SAMPLE
–C
SAMPLE
•
•
•
D11
D0
ZEROING SWITCHES
+A
IN
+C
DAC
+V
DAC
–C
DAC
–V
DAC
–A
IN
12
1410 F01
COMP
+
–
OUTPUT
LATCHES
SAR
SAMPLE
HOLD
HOLD
HOLD
LTC1410
Load Circuits for Access Timing
5V
1k
DBN
1k C
(A) Hi-Z TO V
AND VOL TO V
OH
L
OH
DBN
(B) Hi-Z TO VOL AND VOH TO V
U
WUU
C
L
OL
1410 TC01
APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1410 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Load Circuits for Output Float Delay
5V
1k
DBN
1k 100pF 100pF
(A) V
TO Hi-Z (B) VOL TO Hi-Z
OH
DBN
1410 TC02
onto the summing junctions. This input charge is successively compared with the binarily-weighted charges supplied by the differential capacitive DAC. Bit decisions are
made by the high speed comparator. At the end of a
conversion, the differential DAC output balances the +A
IN
and –AIN input charges. The SAR contents (a 12-bit data
word) which represent the difference of +AIN and –AIN are
loaded into the 12-bit output latches.
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the +AIN and –AIN inputs are
connected to the sample-and-hold capacitors (C
SAMPLE
)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum duration of 100ns will provide enough time for
the sample-and-hold capacitors to acquire the analog
signal. During the convert phase the comparator zeroing
switches open, putting the comparator into compare
mode. The input switches connect the C
to ground, transferring the differential analog input charge
SAMPLE
capacitors
Figure 1. Simplified Block Diagram
7
LTC1410
U
WUU
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
The LTC1410 has excellent high speed sampling capability. Fast Four Transform (FFT) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental.
0
–20
–40
–60
–80
AMPLITUDE (dB)
–100
–120
0
200 300 400
100
FREQUENCY (kHz)
Figure 2a. LTC1410 Nonaveraged 4096 Point FFT, 100kHz Input
0
f
= 1.25MHz
SAMPLE
= 599.975kHz
f
IN
–20
SFDR = 84.7dB
SINAD = 71.7dB
–40
–60
–80
AMPLITUDE (dB)
–100
f
= 1.25MHz
SAMPLE
= 100.098kHz
f
IN
SFDR = 90.1dB
SINAD = 72.4dB
500 600
1410 F02a
to frequencies from above DC and below half the sampling
frequency. Figures 2a and 2b shows a typical spectral
content with a 1.25MHz sampling rate for 100kHz and
600kHz inputs. The dynamic performance is excellent for
input frequencies up to the Nyquist limit of 625kHz and
beyond.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement
of the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 1.25MHz the LTC1410 maintains very good ENOBs
up to the Nyquist input frequency of 625kHz and beyond.
Refer to Figure 3.
12 74
68
10
8
6
EFFECTIVE BITS
4
2
f
SAMPLE
0
1k
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
NYQUIST
= 1.25MHz
10k 100k 1M 10M
INPUT FREQUENCY (Hz)
LTC1410 • TA02
62
56
S/(N + D) (dB)
50
–120
0
200 300 400
100
FREQUENCY (kHz)
500 600
1410 F02b
Figure 2b. LTC1410 Nonaveraged 4096 Point FFT, 600kHz Input
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
8
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD
=
20
2
VV
+++
V . . .V
log
2
324
V
1
2
2
n
LTC1410
U
WUU
APPLICATIONS INFORMATION
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs Input Frequency is
shown in Figure 4. The LTC1410 has good distortion
performance up to the Nyquist frequency and beyond.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
–100
1k
2ND
10k 100k
INPUT FREQUENCY (Hz)
Figure 4. Distortion vs Input Frequency
3RD
1M 10M
THD
1410 G03
0
–20
–40
–60
–80
AMPLITUDE (dB)
–100
–120
0
)
)
(f
(f
a
b
(2f
(2f
)
a–fb
)
(f
b–fa
100
(f
(2f
)
a+fb
b–fa
(2f
)
(2f
a
200 300 400
FREQUENCY (MHz)
)
)
a+fb
(f
+2fb)
)
a
b
(3fa)
(3fb)
f
= 1.25MHz
SAMPLE
= 88.19580078kHz
f
IN1
= 111.9995117kHz
f
IN2
500 600
1410 F05
Figure 5. Intermodulation Distortion Plot
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibel relative to the RMS value of
a full-scale input signal.
Intermodulation Distortion (IMD)
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce Intermodulation Distortion in addition to THD.
IMD is the change in one sinusoidal input caused by the
presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include
(fa + fb). If the two input sine waves are equal in magnitude,
the value (in decibels) of the 2nd order IMD products can
be expressed by the following formula:
f
±
()
a
b
f
a
IMD f f
+
=
()
ab
20 log
Amplitude at f
Amplitude at
Full Power and Full Linear Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1410 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist frequency. The
noise floor stays very low at high frequencies; S/(N + D)
does not become dominated by distortion until frequencies far beyond Nyquist.
Driving the Analog Input
The differential analog inputs of the LTC1410 are easy to
drive. The inputs may be driven differentially or as a
single-ended input (i.e., the –AIN input is grounded). The
+AIN and –AIN inputs are sampled at the same instant.
Any unwanted signal that is common mode to both
inputs will be reduced by the common mode rejection of
the sample-and-hold circuit. The inputs draw only one
small current spike while charging the sample-and-hold
9
LTC1410
1
2
3
+A
IN
–A
IN
LTC1410
4.06V
0.1µF
10µF
R2
40k
R1
2k
ANALOG
INPUT
2.500V
1410 F08a
REFCOMP
AGND
V
REF
4
5
R3
64k
+
–
BANDGAP
REFERENCE
U
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APPLICATIONS INFORMATION
capacitors at the end of conversion. During conversion
the analog inputs draw only a small leakage current. If the
source impedance of the driving circuit is low then the
LTC1410 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For
minimum acquisition time with high source impedance,
a buffer amplifier should be used. The only requirement
is that the amplifier driving the analog input(s) must
settle after the small current spike before the next conversion starts (settling time must be 100ns for full throughput rate).
10
1
0.1
ACQUISITION TIME (µs)
sample-and-hold circuit is 20MHz. Any noise that is present
at the analog inputs will be summed over this entire
bandwidth. Noisy input circuitry should be filtered prior to
the analog inputs to minimize noise. A simple 1-pole RC
filter is usually sufficient. For example, Figure 7 shows a
1000pF capacitor from +AIN to ground and a 100Ω source
resistor will limit the input bandwidth to 1.6MHz. Simple
RC filters work well for AC applications, but they will limit
the transient response. For full speed operation, amplifiers
with fast settling and low noise should be chosen.
ANALOG
INPUT
100Ω
10µF
1000pF
0.1µF
1
2
3
4
5
+A
IN
–A
IN
V
REF
REFCOMP
AGND
LTC1410
1410 F07
0.01
10
100
SOURCE RESISTANCE (Ω)
1k 10k
100k
1410 F06
Figure 6. Acquisition Time vs Source Resistance
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, choose an amplifier
that has a low output impedance (<100Ω) at the closedloop bandwidth frequency. For example, if an amplifier is
used in a gain of +1 and has a closed-loop bandwidth of
50MHz, then the output impedance at 50MHz must be
less than 100Ω. The second requirement is that the
closed-loop bandwidth must be greater than 20MHz to
ensure adequate small-signal settling for full throughput
rate. If slower op amps are used, more settling time can
be provided by increasing the time between conversions.
Suitable devices capable of driving the ADC’s inputs
include the LT®1360, LT1220, LT1223, LT1224 and
LT1227 op amps.
The noise and the distortion of the input amplifier must
also be considered since they will add to the LTC1410
noise and distortion. The small-signal bandwidth of the
10
Figure 7. RC Input Filter
Internal Reference
The LTC1410 has an on-chip, temperature compensated,
curvature corrected, bandgap reference which is factory
trimmed to 2.500V. It is connected internally to a reference
amplifier and is available at V
(Pin 3). See Figure 8a. A
REF
2k resistor is in series with the output so that it can be
Figure 8a. LTC1410 Reference Circuit
LTC1410
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APPLICATIONS INFORMATION
easily overdriven in applications where an external reference is required. The reference amplifier provides buffering between the internal reference and the capacitive DAC.
The reference amplifier compensation pin REFCOMP
(Pin 4), must be bypassed with a capacitor to ground. The
reference amplifier is stable with capacitors of 1µF or
greater. For the best noise performance, a 10µ F tantalum
in parallel with 0.1µF ceramic is recommended.
The V
(Figure 8b), a DAC or other means to provide input span
adjustment. The V
to 2.75V for specified linearity.
Full-Scale and Offset Adjustment
Figure 9 shows the ideal input/output characteristics for
the LTC1410. The code transitions occur midway between
successive integer LSB values (i.e., –FS + 0.5LSB,
–FS + 1.5LSB, –FS + 2.5LSB, . . . FS – 1.5LSB,
FS – 0.5LSB).The output is two’s complement binary
with 1LSB = [(+FS) – (–FS)]/4096 = 5V/4096 = 1.22mV.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 10
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the –AIN input. For zero offset error apply
–0.61mV (i.e., –0.5LSB) at +AIN and adjust the offset at
the –AIN input until the output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjustment, an input voltage of 2.49817V (FS – 1.5LSBs) is
pin can be driven with an external reference
REF
should be kept in the range of 2.25V
REF
5V
V
IN
LT1019A-2.5
V
OUT
ANALOG
10µF
INPUT
0.1µF
1
+A
IN
2
–A
IN
3
V
REF
4
REFCOMP
5
AGND
LTC1410
1410 F08b
Figure 8b. Using the LT1019-2.5 as an External Reference
applied to AIN and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
011...111
011...110
000...001
000...000
111...111
111...110
OUTPUT CODE
100...001
100...000
INPUT VOLTAGE, (+AIN) – (–AIN) (V)
BIPOLAR
ZERO
0V
–1
LSB
FS = 2.5V
1LSB =
1
LSB
2FS
4096
FS – LSB–FS
1410 F09
Figure 9. LTC1410 Transfer Characteristics
R1
50k
–5V
R5
47k
10µF
50k
R2
47k
ANALOG
R6
24k
0.1µF
100Ω
INPUT
R4
1
+A
2
–A
3
V
4
REFCOMP
5
AGND
IN
IN
REF
LTC1410
1410 F10
R3
Figure 10. Offset and Full-Scale Adjust Circuit
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1410, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. Particular care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
11
LTC1410
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APPLICATIONS INFORMATION
High quality tantalum and ceramic bypass capacitors
should be used at the VDD, VSS and REFCOMP pins as
shown in the Typical Application on the first page of this
data sheet. Bypass capacitors must be located as close to
the pins as possible. The traces connecting the pins and
bypass capacitors must be kept short and should be made
as wide as possible.
The LTC1410 has differential inputs to minimize noise
coupling. Common mode noise on the + AIN and – A
leads will be rejected by the input CMRR. The –AIN input
can be used as a ground sense for the + AIN input; the
LTC1410 will hold and convert the difference voltage
between +AIN and –AIN. The leads to +AIN (Pin 1) and –A
(Pin 2) should be kept as short as possible. In applications
where this is not possible, the +AIN and –AIN traces should
be run side by side to equalize coupling.
A single point analog ground separate from the logic
system ground should be established with an analog
ground plane at Pin 5 (AGND) or as close as possible to the
ADC. Pin 14 and Pin 19 (ADC’s DGND) and all other analog
grounds should be connected to this single analog ground
point. No other digital grounds should be connected to this
analog ground point. Low impedance analog and digital
power supply common returns are essential to low noise
operation of the ADC and the foil width for these tracks
should be as wide as possible. In applications where the
IN
IN
ADC data outputs and control signals are connected to a
continuously active microprocessor bus, it is possible to
get errors in the conversion results. These errors are due
to feedthrough from the microprocessor to the successive
approximation comparator. The problem can be eliminated by forcing the microprocessor into a wait state
during conversion or by using three-state buffers to isolate the ADC data bus.
DIGITAL INTERFACE
The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.65µs and a maximum conversion time over the
full operating temperature range of 0.75µs. No external
adjustments are required. The guaranteed maximum acquisition time is 100ns. In addition, throughput time of
800ns and a minimum sampling rate of 1.25Msps is
guaranteed.
12
ANALOG
INPUT
CIRCUITRY
1
+A
IN
–A
+
–
IN
2
10µF
REFCOMP
AGND
4
0.1µF
Figure 11. Power Supply Grounding Practice
LTC1410
V
SS
26 1914
10µF
0.1µF
10µF
AV
DVDDDGND OGND
DD
28 27
0.1µF
DIGITAL
SYSTEM
1410 F11
LTC1410
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APPLICATIONS INFORMATION
Power Shutdown
The LTC1410 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The
Nap mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from Nap to active is 200ns. In Sleep mode all bias
currents are shut down and only leakage current remains––about 1µA. Wake-up time from Sleep mode is
NAP/SLP
t
3
SHDN
Figure 12a. NAP/SLP to SHDN Timing
SHDN
t
4
CONVST
Figure 12b. SHDN to CONVST Wake-Up Timing
much slower since the reference circuit must power up
and settle to 0.01% for full 12-bit accuracy. Sleep mode
wake-up time is dependent on the value of the capacitor
connected to the REFCOMP (Pin 4). The wake-up time is
10ms with the recommended 10µF capacitor.
Shutdown is controlled by Pin 21 (SHDN), the ADC is in
shutdown when it is low. The shutdown mode is selected
with Pin 20 (NAP/SLP); high selects Nap.
CS
t
2
CONVST
t
1
RD
1410 F12a
1410 F12b
1410 F12
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
Figures 14 through 18 show several different modes of
operation. In modes 1a and 1b (Figures 14 and 15) CS
and RD are both tied low. The falling edge of CONVST
starts the conversion. The data outputs are always enabled
and data can be latched with the BUSY rising edge. Mode
1a shows operation with a narrow logic low CONVST
pulse. Mode 1b shows a narrow logic high CONVST pulse.
In mode 2 (Figure 16) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared MPU
databus.
In slow memory and ROM modes (Figures 17 and 18) CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low
forcing the processor into a wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results appear on the data outputs; BUSY goes high releasing the
processor and the processor takes RD (= CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
Figure 13. CS to CONVST Setup Timing
13
LTC1410
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APPLICATIONS INFORMATION
CS = RD = 0
CONVST
BUSY
DATA
DATA (N – 1)
DB11 TO DB0
Figure 14. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = )
CS = RD = 0
t
13
CONVST
t
6
t
t
5
t
6
t
CONV
CONV
t
5
t
7
t
8
DATA N
DB11 TO DB0
t
8
DATA (N + 1)
DB11 TO DB0
t
6
1410 F14
BUSY
t
7
DATA
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
Figure 15. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = )
t
13
t
8
t
9
t
12
t
10
t
11
DATA N
DB11 TO DB0
CONVST
BUSY
RD
DATA
t
CONV
t
5
t
6
DATA (N + 1)
DB11 TO DB0
1410 F16
1410 F15
14
Figure 16. Mode 2. CONVST Starts a Conversion. Data is Read by RD
LTC1410
PPLICATI
A
RD = CONVST
BUSY
DATA
RD = CONVST
BUSY
DATA
U
O
S
I FOR ATIO
t
6
t
10
t
6
WU
t
CONV
DATA (N – 1)
DB11 TO DB0
Figure 17. Slow Memory Mode Timing
t
CONV
t
11
t
10
DATA (N – 1)
DB11 TO DB0
U
t
7
DATA N
DB11 TO DB0
t
8
t
11
DATA N
DB11 TO DB0
t
8
DATA N
DB11 TO DB0
DATA (N + 1)
DB11-DB0
1410 F17
1410 F18
PACKAGEDESCRIPTI
0.205 – 0.212**
(5.20 – 5.38)
0.005 – 0.009
(0.13 – 0.22)
*
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.022 – 0.037
(0.55 – 0.95)
O
Figure 18. ROM Mode Timing
U
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 – 0.407*
(10.07 – 10.33)
2526 22 21 20 19 181716 1523242728
0.301 – 0.311
(7.65 – 7.90)
12345678 9 10 11 12 1413
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.0256
(0.65)
BSC
0.010 – 0.015
(0.25 – 0.38)
0.002 – 0.008
(0.05 – 0.21)
G28 SSOP 0694
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1410
PACKAGEDESCRIPTI
U
O
Dimensions in inches (millimeters) unless otherwise noted.
SW Package
28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.697 – 0.712*
(17.70 – 18.08)
2526
2728
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
0.010 – 0.029
(0.254 – 0.737)
0.009 – 0.013
(0.229 – 0.330)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
*
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
**
NOTE 1
× 45°
0.016 – 0.050
(0.406 – 1.270)
0° – 8° TYP
0.093 – 0.104
(2.362 – 2.642)
0.050
(1.270)
2345678
1
TYP
0.014 – 0.019
(0.356 – 0.482)
TYP
22 21 20 19 18
910
11 12
16 152324
17
0.394 – 0.419
(10.007 – 10.643)
1413
0.037 – 0.045
(0.940 – 1.143)
0.004 – 0.012
(0.102 – 0.305)
S28 (WIDE) 0996
RELATED PARTS
12-Bit Sampling A/D Converters
PART NUMBER DESCRIPTION COMMENTS
LTC1273/75/76 Complete 5V Sampling 12-Bit ADCs Lower Power and Cost Effective for f
with 70dB SINAD at Nyquist
LTC1274/77 Low Power 12-Bit ADCs with Nap Lowest Power for f
SAMPLE
≤ 100ksps
and Sleep Mode Shutdown
LTC1278/79 High Speed Sampling 12-Bit ADCs Cost Effective 12-Bit ADCs –– Best for 2-Pair HDSL,
with Shutdown f
≤ 500ksps/600ksps
SAMPLE
LTC1282 Complete 3V 12-Bit ADCs with Fully Specified for 3V-Powered Applications, f
12mW Power Dissipation
Linear Technology Corporation
16
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
≤ 300ksps
SAMPLE
SAMPLE
1410fa LT/TP 0399 2K REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1995
≤ 140ksps
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