Datasheet LTC1405 Datasheet (Linear Technology)

Final Electrical Specifications

FEATURES

LTC1405

12-Bit, 5Msps,

Sampling ADC

January 2000

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DESCRIPTIO

■

5Msps Sample Rate

■

Low Power Dissipation: 115mW

■

Single 5V Supply or ±5V Supplies

■

Integral Nonlinearity Error <0.35LSB

■

Differential Nonlinearity <0.25LSB

■

71.3dB S/(N + D) and 85dB SFDR at Nyquist

■

100MHz Full-Power Bandwidth Sampling

■

±2.048V, ±1.024V and ±0.512V Bipolar Input Range

■

Input PGA

■

Out-of-Range Indicator

■

True Differential Inputs with 75dB CMRR

■

28-Pin Narrow SSOP Package

■

Pin-Compatible 10Msps Version (LTC1420)

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APPLICATIO S

■

Telecommunications

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

■

High Speed Data Acquisition

■

Spectral Analysis

■

Imaging Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

The LTC®1405 is a 5Msps, 12-bit sampling A/D converter
that draws only 115mW from either single 5V or dual ±5V
supplies. This easy-to-use device includes a high dynamic
range sample-and-hold, a precision reference and a PGA
input circuit.

The LTC1405 has a flexible input circuit that allows full­scale input ranges of ±2.048V, ±1.024V and ±0.512V. The
input common mode range is rail-to-rail and a common
mode bias voltage is provided for single supply applica­tions. The input PGA has a digitally selectable 1x or 2x
gain.

Maximum DC specs include ±1LSB INL and ±1LSB DNL
over temperature. Outstanding AC performance includes

71.3dB S/(N + D) and 85dB SFDR at the Nyquist input
frequency of 2.5MHz.

The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 100MHz
bandwidth. The 75dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source. A
separate output logic supply allows direct connection to
3V components.

TYPICAL APPLICATIO

5V

GAIN

+

A

IN

S/H

–A

IN

V

CM

1µF

SENSE

V

REF

1µF

1µF

MODE SELECT

SS

0V OR –5V

U

5V

1µF

AV

DD

PIPELINED 12-BIT ADC

DIGITAL CORRECTION

LOGIC

2.5V

REFERENCE

2.048V

AGND

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the
interconnection of its circuits as described herein will not infringe on existing patent rights.

1µF

5V

DV

OV

DD

OUTPUT

BUFFERS

OGND

DGNDV

OPTIONAL 3V
LOGIC SUPPLY

1µF

DD

OF
D11 (MSB)

D0 (LSB)

5MHz CLK

1405 TA01

1.00

0.75

0.50

0.25
0

INL (LSBs)

–0.25
–0.50
–0.75
–1.00

0 1024 2048 3072 4096

However,

Typical INL Curve

CODE

1405 TA02

1

LTC1405

WW

W

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ABSOLUTE AXI U RATI GS

AVDD = DVDD = 0VDD = VDD (Notes 1, 2)

Supply Voltage (VDD)................................................. 6V

Negative Supply Voltage (VSS) ................................ –6V

Total Supply Voltage (VDD to VSS) ........................... 12V

Analog Input Voltage

(Note 3) .............................(VSS – 0.3V) to (VDD + 0.3V)

Digital Input Voltage

(Note 4) .............................(VSS – 0.3V) to (VDD + 0.3V)

Digital Output Voltage........(VSS – 0.3V) to (VDD + 0.3V)

Power Dissipation.............................................. 500mW

Operating Temperature Range

LTC1405C ...............................................0°C to 70°C

LTC1405I............................................ –40°C to 85°C

Storage Temperature Range................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

1

+A

IN

2

–A

IN

3

V

CM

4

SENSE

5

V

REF

6

AGND

7

AV

DD

8

AGND

D11 (MSB)

Consult factory for Military grade parts.

9

10

D10

11

D9

12

D8

13

D7

14

D6

GN PACKAGE

28-LEAD PLASTIC SSOP

T

= 110°C, θJA = 110°C/W

JMAX

GAIN

28

OF

27

CLK

26

V

25

SS

DGND

24

DV

23

DD

OV

22

DD

OGND

21

D0

20

D1

19

D2

18

D3

17

D4

16

D5

15

ORDER PART

NUMBER

LTC1405CGN
LTC1405IGN

U

CO VERTER CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
With Internal 4.096V Reference. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 12 Bits
Integral Linearity Error (Note 7) ● ±0.35 ±1 LSB
Differential Linearity Error ● ±0.25 ±1 LSB
Offset Error (Note 8) ±5 12 LSB

● 16 LSB

Full-Scale Error ±10 30 LSB
Full-Scale Tempco I

A

U

LOG

IA

U
PUT

The ● denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

I
C

t

IN

IN

IN

ACQ

Analog Input Range (Note 9) V

– (–AIN)V

+A

IN

Analog Input Leakage Current ● ±10 µA
Analog Input Capacitance Between Conversions 12 pF

Sample-and-Hold Acquisition Time 50 ns

= 0 ±15 ppm/°C

OUT(REF)

= 4.096V (SENSE = 0V), GAIN = 5V ● ±2.048 V

REF

= 4.096V (SENSE = 0V), GAIN = 0V ● ±1.024 V

REF

= 2.048V (SENSE = V

V

REF

V

= 2.048V (SENSE = V

REF

External V
External V

During Conversions 6 pF

(SENSE = 5V), GAIN = 5V ● ±V

REF

(SENSE = 5V), GAIN = 0V ● ±V

REF

), GAIN = 5V ● ±1.024 V

REF

), GAIN = 0V ● ±0.512 V

REF

/2 V

REF

/4 V

REF

2

LTC1405

U

AP
jitter

LOG

Sample-and-Hold Aperture Delay Time –250 ps
Sample-and-Hold Aperture Delay Time Jitter 0.6 ps

W

U

IC

A

Full-Power Bandwidth 100 MHz
Input Referred Noise ±2.048V Input Range 0.22 LSB

A

specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t
t
CMRR Analog Input Common Mode Rejection Ratio –2.048V < (–AIN = +AIN) < 2.048V 75 dB

DY

otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, f
–AIN = 0V. (Note 6)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

S/(N + D) Signal-to-Noise Plus Distortion Ratio 1MHz Input Signal ● 69.0 71.6 dB

THD Total Harmonic Distortion 1MHz Input Signal, First 5 Harmonics ● –87 –78.5 dB

SFDR Peak Harmonic or Spurious Noise 1MHz Input Signal ● –89 –79.5 dB

IMD Intermodulation Distortion f

U

IA

PUT

The ● denotes the specifications which apply over the full operating temperature range, otherwise

ACCURAC Y

The ● denotes the specifications which apply over the full operating temperature range,

= 5MHz, V

SAMPLE

2.5MHz Input Signal

2.5MHz Input Signal, First 5 Harmonics

2.5MHz Input Signal
= 29.37kHz, f

IN1

±1.024V Input Range, 2x Mode (SENSE = GAIN = 0V) 0.33 LSB

= 32.446kHz –80 dB

IN2

= 4.096V. +AIN = –0.1dBFS single ended input,

REF

● 68.7 71.3 dB

● –83 –77.0 dB

● –85 –78.0 dB

RMS
RMS

U

UU

I TER AL REFERE CE CHARACTERISTICS

TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage I
VCM Output Tempco I
VCM Line Regulation 4.75V ≤ VDD ≤ 5.25V 0.6 mV/V

VCM Output Resistance 0.1mA ≤ I
V

Output Voltage SENSE = GND, I

REF

V

Output Tempco ±15 ppm/°C

REF

= 0 2.475 2.500 2.525 V

OUT

= 0 ±15 ppm/°C

OUT

–5.25V ≤ V

SENSE = V
SENSE = V

≤ –4.75V 0.03 mV/V

SS

 ≤ 0.1mA 8 Ω

OUT

= 0 4.096 V

OUT

, I

= 0 2.048 V

REF

OUT

DD

Drive V

External Reference

with V

REF

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DIGITAL I PUTS AND OUTPUTS

temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply
operation. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

High Level Input Voltage V

V

Low Level Input Voltage VDD = 4.75V, VSS = 0V ● 0.8 V

V

The ● denotes the specifications which apply over the full operating

= 5.25V, VSS = 0V ● 2.4 V

DD

= 5.25V, VSS = –5V ● 3.5 V

DD

= 4.75V, VSS = –5V ● 1V

DD

3

LTC1405

UU

DIGITAL I PUTS AND OUTPUTS

temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply
operation. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

IN

C

IN

V

OH

V

OL

I

SOURCE

I

SINK

POWER REQUIRE E TS

range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 5)

Digital Input Current VIN = 0V to V
Digital Input Capacitance 1.8 pF
High Level Output Voltage 0VDD = 4.75V, IO = –10µA 4.74 V

Low Level Output Voltage 0VDD = 4.75V, IO = 160µA 0.05 V

Output Source Current V
Output Sink Current V

U

W

The ● denotes the specifications which apply over the full operating temperature

The ● denotes the specifications which apply over the full operating

DD

= 4.75V, IO = –200µA ● 4.0 4.71 V

0V

DD

= 2.7V, IO = –10µA 2.6 V

0V

DD

0V

= 2.7V, IO = –200µA ● 2.3 V

DD

= 4.75V, IO = 1.6mA ● 0.10 0.4 V

0V

DD

= 2.7V, IO = 160µA 0.05 V

0V

DD

0V

= 2.7V, IO = 1.6mA ● 0.10 0.4 V

DD

= 0V 50 mA

OUT

= V

OUT

DD

● ±10 µA

35 mA

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

DD

V

SS

I

DD

I

SS

P

D

W

TI I G CHARACTERISTICS

Positive Supply Voltage (Note 10) 4.75 5.25 V
Negative Supply Voltage Dual Supply Mode –5.25 –4.75 V

Single Supply Mode 0 V
Positive Supply Current ● 23 28 mA
Negative Supply Current ● 0.8 1.2 mA
Power Dissipation ● 115 145 mW

U

The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

SAMPLE

t

CONV

t

ACQ

t

H

t

L

t

AD

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below V
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.

Sampling Frequency ● 0.02 5 MHz
Conversion Time ● 150 180 ns
Acquisition Time ● 20 50 ns
CLK High Time (Note 9) ● 20 100 ns
CLK Low Time (Note 9) ● 20 100 ns
Aperture Delay of Sample-and-Hold –250 ps

they will be clamped

SS

without

DD

or above VDD, they

SS

Note 4: When these pin voltages are taken below V
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. GAIN is not clamped to VDD. When CLK
is taken above V
can handle input currents of greater than 100mA above V
latchup.

Note 5: V
otherwise specified.

DD

, it will be clamped by an internal diode. The CLK pin

DD

= 5V, VSS = –5V or 0V, f

= 5MHz, tr = tf = 5ns unless

SAMPLE

4

ELECTRICAL CHARACTERISTICS

LTC1405

Note 6: Dynamic specifications are guaranteed for dual supply operation
with a single-ended +A
dynamic specifications, refer to the Typical Performance Characteristics.

Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.

input and –AIN grounded. For single supply

IN

UUU

PI FU CTIO S

+AIN (Pin 1):
–AIN (Pin 2): Negative Analog Input.
VCM (Pin 3): 2.5V Reference Output.Optional input com-

mon mode for single supply operation. Bypass to GND
with a 1µF to 10µF ceramic.

SENSE (Pin 4): Reference Programming Pin. Ground
selects V
SENSE to VDD to drive V

V

(Pin 5): DAC Reference. Bypass to GND with a 1µF to

REF

10µF ceramic.
GND (Pin 6): DAC Reference Ground.

Positive Analog Input.

= 4.096V. Short to V

REF

REF

for 2.048V. Connect

REF

with an external reference.

Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and
1111 1111 1111.

Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.

OGND (Pin 21): Output Logic Ground. Tie to GND.
OVDD (Pin 22): Positive Supply for the Output Logic.

Connect to Pin 23 for 5V logic. If not shorted to Pin 23,
bypass to GND with a 1µF ceramic.

VDD (Pin 23): Analog 5V Supply. Bypass to GND with a 1µF
ceramic.

GND (Pin 24): Analog Power Ground.
VSS (Pin 25): Negative Supply. Can be –5V or 0V. If VSS is

not shorted to GND, bypass to GND with a 1µF ceramic.
CLK (Pin 26): Conversion Start Signal. This active high

signal starts a conversion on its rising edge.

VDD (Pin 7): Analog 5V Supply. Bypass to GND with a 1µF
to 10µF ceramic.

GND (Pin 8): Analog Power Ground.
D11 to D0 (Pins 9 to 20): Data Outputs. The output format

is two’s complement.

OF (Pin 27): Overflow Output. This signal is high when the
digital output is 011111111111 or 100000000000.

GAIN (Pin 28): Gain Select for Input PGA. 5V selects an
input gain of 1, 0V selects a gain of 2.

5

LTC1405

UU

W

FU CTIO AL BLOCK DIAGRA

GAIN

A

+

IN

–A

IN

V

CM

MODE SELECT

SENSE

V

REF

2.048V

V

0V OR –5V

SS

GND
(PIN 6)

5V

V

DD

(PIN 7)

PIPELINED 12-BIT ADCS/H

DIGITAL CORRECTION

LOGIC

2.5V

REFERENCE

GND
(PIN 8)

V

DD

(PIN 23) OV

OUTPUT

BUFFERS

GND
(PIN 24)

OPTIONAL 3V
LOGIC SUPPLY

DD

OF
D11 (MSB)

D0 (LSB)

CLK

1405 FBD

OGND

UWW

TI I G DIAGRA

ANALOG

INPUT

CLK

DATA

OUTPUT

t

CLOCK

H

CONV

N + 1

N + 2

t

L

t

ACQ

N – 2 N – 1 N

N + 3

1405 TD

N

t

t

N – 3

6

LTC1405

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WUU

APPLICATIO S I FOR ATIO

Conversion Details

The LTC1405 is a high performance 12-bit A/D converter
that operates up to 5Msps. It is a complete solution with
an on-chip sample-and-hold, a 12-bit pipelined CMOS
ADC, a low drift programmable reference and an input
programmable gain amplifier. The digital output is paral­lel, with a 12-bit two’s complement output and an out-of­range (overflow) bit.

The rising edge of the CLK begins a conversion. The
differential analog inputs are simultaneously sampled and
passed on to the pipelined A/D. After two more conversion
starts (plus a 150ns conversion time) the digital outputs
are updated with the conversion result and will be ready for
capture on the third rising clock edge. Thus even though
a new conversion is begun every time CLK goes high, each
result takes three clock cycles to reach the output.

The analog signals that are passed from stage to stage in
the pipelined A/D are stored on capacitors. The signals on
these capacitors will be lost if the delay between conver­sions is too long. For accurate conversion results, the part
should be clocked faster than 20kHz.

In some pipelined A/D converters if there is no clock
present, dynamic logic on the chip will droop and the
power consumption sharply increases. The LTC1405
doesn’t have this problem. If the part is not clocked for
1ms, an internal timer will refresh the dynamic logic. Thus
the clock can be turned off for long periods of time to save
power.

Power Supplies

The LTC1405 will operate from either a single 5V or dual
±5V supply, making it easy to interface the analog input to
single or dual supply systems. The digital output drivers
have their own power supply pin (OVDD) which can be set
from 3V to 5V, allowing direct connection to either 3V or
5V digital systems. For single supply operation, VSS should
be connected to analog ground. For dual supply operation,
VSS should be connected to –5V. Both VDD pins should be
connected to a clean 5V analog supply. (Don’t connect V
to a noisy system digital supply.)

DD

Analog Input Ranges

The LTC1405 has a flexible analog input with a wide
selection of input ranges. The input range is always
differential and is set by the voltages at the V

and the

REF

GAIN pins (Figure 1). The input range of the A/D core is
fixed at ±V

/2. The reference voltage, V

REF

, is either set

REF

by the on-chip voltage reference or directly driven by an
external voltage. The GAIN pin is a digital input that
controls the gain of a preamplifier in the sample-and-hold
circuit. The gain of this PGA can be set to 1x or 2x. Table 1
gives the input range in terms of V

Table 1

GAIN PIN PGA GAIN (V

5V (Logic H) 1x –V
OV (Logic L) 2x –V

GAIN

1x/2x

+A

IN

+

V

IN

–A

IN

–

V

REF

Figure 1. Analog Input Circuit

and GAIN.

REF

INPUT RANGE

IN

REF
REF

/2PGA S/H

±V

REF

+

= A

– A

IN

/2 < VIN < V
/4 < VIN < V

ADC

CORE

IN

REF
REF

1405 F01

–

)

/2
/4

Internal Reference

Figure 2 shows a simplified schematic of the LTC1405
reference circuitry. An on-chip temperature compensated
bandgap reference (VCM) is factory trimmed to 2.500V.
The voltage at the V
to ±V

/2. An internal voltage divider converts VCM to

REF

pin sets the input span of the ADC

REF

2.048V, which is connected to a reference amplifier. The
reference programming pin, SENSE, controls how the
reference amplifier drives the V

pin. If SENSE is tied to

REF

ground, the reference amplifier feedback is connected to
the R1/R2 voltage divider, thus making V
SENSE is tied to V
connected to SENSE thus making V

, the reference amplifier feedback is

REF

REF

= 4.096V. If

REF

= 2.048V. If SENSE
is tied to VDD, the reference amplifier is disconnected from
V

and V

REF

two additional resistors, V

can be driven by an external voltage. With

REF

can be set to any voltage

REF

between 2.048V and 4.5V.

7

LTC1405

1405 F03b

1µF

1µF

V

REF

LTC1405

SENSE

V

CM

2.048V

–

+

5k

5k

LTC1450

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APPLICATIO S I FOR ATIO

An external reference or a DAC can be used to drive V
over a 0V to 5V range (Figures 3a and 3b). The input
impedance of the V
required for high accuracy. Driving V

pin is 2kΩ, so a buffer may be

REF

with a DAC is

REF

useful in applications where the peak input signal ampli­tude may vary. The input span of the ADC can then be
adjusted to match the peak input signal, maximizing the
signal-to-noise ratio.

Both the VCM and V

pins must be bypassed with

REF

capacitors to ground. For best performance, 1µF or larger
ceramic capacitors are recommended. For the case of
external circuitry driving V
used at V

so the input range can be changed quickly. In

REF

, a smaller capacitor can be

REF

this case, a 0.05µF or larger ceramic capacitor is accept-
able.

The VCM pin is a low output impedance 2.5V reference that
can be used by external circuitry. For single 5V supply
applications it is convenient to connect A

–

directly to the

IN

VCM pin.

REF

V

REF

SENSE

V

CM

1µF

1µF

R1
10k

R2
10k

LOGIC

2.5V

REFERENCE

Figure 2. Reference Circuit

TO
ADC

+

2k

–

2.048V

1405 F02

Driving the Analog Inputs

The differential inputs of the LTC1405 are easy to drive.
The inputs may be driven differentially or single-ended
(i. e., the A

+

A

inputs are simultaneously sampled and any common

IN

–

input is held at a fixed value). The A

IN

IN

–

and

mode signal is reduced by the high common mode rejec­tion of the sample-and-hold circuit. Any common mode
input value is acceptable as long as the input pins stay
between VDD and VSS. During conversion the analog
inputs are high impedance. At the end of conversion the
inputs draw a small current spike while charging the
sample-and-hold.

For superior dynamic performance in dual supply mode,
the LTC1405 should be operated with the analog inputs
centered at ground, and in single supply mode the inputs
should be centered at 2.5V. If required, the analog inputs
can be driven differentially via a transformer. Refer to
Table 2 for a summary of the analog input and reference
configurations and their relative advantages.

5V

V

IN

V

LT1019A-2.5

OUT

1µF

1µF

V

REF

SENSE5V

V

CM

LTC1405

1405 F03a

Figure 3a. Using the LT1019-2.5 As an
External Reference; Input Range = ±1.25V

Figure 3b. Driving V

with a DAC

REF

8

LTC1405

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APPLICATIO S I FOR ATIO

Table 2. Comparison of Analog Input Configurations

SUPPLIES COUPLING V

REF

GAIN A

+

IN

±5V DC 4.096V 1x ±2.048 0 Best SNR, THD
5V DC 4.096V 2x 2.5 ± 1.024 2.5 Best SINAD, THD for Single Supply
5V DC 2.048V 1x 2.5 ± 1.024 2.5 Worse Noise than Above Case
5V DC 4.096V 1x 2.5 ± 2.048 2.5 Best Single Supply Noise, THD Is Not Optimal
5V DC 4.096V 1x 0 to 4.096 2.048 Same As Above
±5V AC 4.096V 1x ±1.024 ±1.024 Very Best SNR, THD

(Transformer)

5V AC 4.096V 1x 2.5 ± 1.024 2.5 ± 1.024 Very Best SNR, THD for Single Supply

(Transformer)

DC Coupling the Input

In most applications the analog input signal can be directly
coupled to the LTC1405 inputs. If the input signal is
centered around ground, such as when dual supply op
amps are used, simply connect A

–

to ground and con-

IN

nect VSS to – 5V (Figure 4). In a single power supply
system with the input signal centered around 2.5V, con­nect A

–

to VCM and VSS to ground (Figure 5). If the input

IN

signal is not centered around ground or 2.5V, the voltage

–

for A
or a voltage reference (Figure 6).

must be generated externally by a resistor divider

IN

5V

AC Coupling the Input

The analog inputs to the LTC1405 can also be AC coupled

0V

V

IN

+A

–A

IN

LTC1405

IN

through a capacitor, though in most cases it is simpler to
directly couple the input to the ADC. Figure 7 shows an
example where the input signal is centered around ground
and the ADC operates from a single 5V supply. Note that

V

CM

V

1µF

SS

1405 F04

–5V

Figure 4. DC Coupling a Ground
Centered Signal (Dual Supply System)

the performance would improve if the ADC was operated
from a dual supply and the input was directly coupled (as
in Figure 4). With AC coupling the DC resistance to ground
should be roughly matched for A
offset accuracy.

–

A

IN

4.096V

0V
5V

COMMENTS

V

IN

2.048V

+A

IN

LTC1405

–A

IN

SENSE

5V

V

SS

1405 F06

Figure 6. DC Coupling a 0V to 4.096V Signal

IN

+

and A

–

to maintain

IN

5V

2.5V

V

IN

1µF

+A

–A

V

CM

IN

LTC1405

IN

V

SS

1405 F05

Figure 5. DC Coupling a Signal Centered
Around 2.5V (Single Supply System)

5V

C

0V

V

IN

RR

C

1µF

+A

–A

V

IN

IN

CM

LTC1405

V

SS

1405 F07

Figure 7. AC Coupling to the LTC1405. Note That the Input Signal

Can Almost Always Be Directly Coupled with Better Performance

9

LTC1405

+A

IN

V

IN

LTC1405

1405 F09

–A

IN

1000pF

30Ω

U

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APPLICATIO S I FOR ATIO

Differential Operation

The THD and SFDR performance of the LTC1405 can be
improved by using a center tap RF transformer to drive the
inputs differentially. Though the signal can no longer be
DC coupled, the improvement in dynamic performance
makes this an attractive solution for some applications.
Typical connections for single and dual supply systems
are shown in Figures 8a and 8b. Good choices for trans­formers are the Mini Circuits T1-1T (1:1 turns ratio) and
T4-6T (1:4 turns ratio). For best results the transformer
should be located close to the LTC1405 on the printed
circuit board.

5V

V

IN

MINI CIRCUITS

T1-1T

15Ω

1000pF

15Ω

1µF

+A

–A

V

IN

IN

CM

LTC1405

V

SS

1405 F08a

must be greater than 50MHz to ensure adequate small­signal settling for full throughput rate. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions.

The best choice for an op amp to drive the LTC1405 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifica­tions are most critical and time domain applications where
DC accuracy and settling time are most critical.

Input Filtering

The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1405 noise and distortion. The small-signal band­width of the sample-and-hold circuit is 100MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications.

Figure 8a. Single Supply Transformer Coupled Input

For example, Figure 9 shows a 1000pF capacitor from
+AIN to –AIN and a 30Ω source resistor to limit the input

5V

V

IN

MINI CIRCUITS

T1-1T

15Ω

1000pF

15Ω

1µF

+A

–A

V

CM

IN

LTC1405

IN

V

SS

–5V

1405 F08b

Figure 8b. Dual Supply Transformer Coupled Input

bandwidth to 5.3MHz. The 1000pF capacitor also acts as
a charge reservoir for the input sample-and-hold and
isolates the amplifier driving VIN from the ADC’s small
current glitch. In undersampling applications, an input
capacitor this large may prohibitively limit the input band­width. If this is the case, use as large an input capacitance
as possible. High quality capacitors and resistors should
be used since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self-heating and from damage that may

Choosing an Input Amplifier

Choosing an input amplifier is easy if a few requirements

occur during soldering. Metal film surface mount resis­tors are much less susceptible to both problems.

are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the

Figure 9. RC Input Filter

output impedance at 50MHz must be less than 100Ω. The
second requirement is that the closed-loop bandwidth

10

LTC1405

U

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APPLICATIO S I FOR ATIO

Digital Outputs and Overflow Bit (OF)

Figure 10 shows the ideal input/output characteristics for
the LTC1405. The output data is two’s complement binary
for all input ranges and for both single and dual supply
operation. One LSB = V
binary output, invert the MSB (D11). The overflow bit (OF)
indicates when the analog input is outside the input range
of the converter. OF is high when the output code is 1000
0000 0000 or 0111 1111 1111.

011…111
011…110
011…101

OUTPUT CODE

100…010
100…001
100…000

–(FS – 1LSB) FS – 1LSB

Figure 10. LTC1405 Transfer Characteristics

Full-Scale and Offset Adjustment

In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error should be adjusted before full-scale error. Figure 11
shows a method for error adjustment for a dual supply,

4.096V application. For zero offset error apply – 0.5mV
(i. e., –0.5LSB) at +AIN and adjust R1 until the output code
flickers between 0000 0000 0000 and 1111 1111 1111.
For full-scale adjustment, apply an input voltage of 2.0465V
(FS – 1.5LSBs) at +AIN and adjust R2 until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.

Digital Output Drivers

The LTC1405 output drivers can interface to logic operat­ing from 3V to 5V by setting OVDD to the logic power
supply. If 5V output is desired, OVDD can be shorted to V
and share its decoupling capacitor. Otherwise, OVDD re­quires its own 1µF decoupling capacitor. To prevent digital

/4.096. To create a straight

REF

1
0

INPUT VOLTAGE (V)

1405 F10

OVERFLOW
BIT

DD

noise from affecting performance, the load capacitance on
the digital outputs should be minimized. If large capacitive
loads are required, (>30pF) external buffers or 100Ω
resistors in series with the digital outputs are suggested.

5V

+A

V

5V

R1

50k

–5V

Figure 11. Offset and Full-Scale Adjust Circuit

IN

24k

100Ω

10k1µF

R2

1k

10k

IN

LTC1405

–A

IN

V

REF

SENSE

V

–5V

SS

1405 F11

Timing

The conversion start is controlled by the rising edge of the
CLK pin. Once a conversion is started it cannot be stopped
or restarted until the conversion cycle is complete. Output
data is updated at the end of conversion, or about 150ns
after a conversion is begun. There is an additional two
cycle pipeline delay, so the data for a given conversion is
output two full clock cycles plus 150ns after the convert
start. Thus output data can be latched on the third CLK
rising edge after the rising edge that samples the input.

Clock Input

The LTC1405 only uses the rising edge of the CLK pin for
internal timing, and CLK doesn’t necessarily need to have
a 50% duty cycle. For optimal AC performance the rise
time of the CLK should be less than 5ns. If the available
clock has a rise time slower than 5ns, it can be locally sped
up with a logic gate. With single supply operation the clock
can be driven with 5V CMOS, 3V CMOS or TTL logic levels.
With dual power supplies the clock should be driven with
5V CMOS levels.

As with all fast ADCs, the noise performance of the
LTC1405 is sensitive to clock jitter when high speed inputs

11

LTC1405

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APPLICATIO S I FOR ATIO

are present. The SNR performance of an ADC when the
performance is limited by jitter is given by:

SNR = –20log (2πfINtJ)dB

where fIN is the frequency of an input sine wave and tJ is
the root-mean-square jitter due to the clock, the analog
input and the A/D aperture jitter. To minimize clock jitter,
use a clean clock source such as a crystal oscillator, treat
the clock signals as sensitive analog traces and use
dedicated packages with good supply bypassing for any
clock drivers.

Board Layout

To obtain the best performance from the LTC1405, a
printed circuit board with a ground plane is required.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track.

An analog ground plane separate from the logic system
ground should be placed under and around the ADC.
Pins 6, 8 and 24 (GND), Pin 21 (OGND) and all other
analog grounds should be connected to this ground plane.
In single supply mode, Pin 25 (VSS) should also be

connected to this ground plane. All bypass capacitors for
the LTC1405 should also be connected to this ground
plane (Figure 12). The digital system ground should be
connected to the analog ground plane at only one point,
near the OGND pin.

The analog ground plane should be as close to the ADC as
possible. Care should be taken to avoid making holes in the
analog ground plane under and around the part. To ac­complish this, we recommend placing vias for power and
signal traces outside the area containing the part and the
decoupling capacitors (Figure 13).

Supply Bypassing

High quality, low series resistance ceramic 1µF capacitors
should be used at both VDD pins, VCM and V

. If VSS is

REF

connected to –5V it should also be bypassed to ground
with 1µF. In single supply operation VSS should be shorted
to the ground plane as close to the part as possible. If OV

DD

is not shorted to Pin 23 (VDD) it also requires a 1µF
decoupling capacitor to ground. Surface mount capaci­tors such as the AVX 0805ZC105KAT provide excellent
bypassing in a small board space. The traces connecting
the pins and the bypass capacitors must be kept short and
should be made as wide as possible.

ANALOG

CIRCUITRY

12

INPUT

+

–

1000pF

1

+A

IN

–A

2

BYPASS CAPACITORS

LTC1405

V

IN

CM

V

3

1µF

GND

REF

5

1µF

ANALOG GROUND PLANE

V

6

GND

DD

7

1µF

V

OV

DD

8

23

1µF

Figure 12. Power Supply Grounding

LTC1405

PLACE NON-GROUND

VIAS AWAY FROM

GROUND PLANE AND

AVOID BREAKING GROUND PLANE

IN THIS AREA

Figure 13. Cross Section of LTC1405 Printed Circuit Board

DIGITAL
SYSTEM

GND

DD

1µF

24

BYPASS
CAPACITOR

ANALOG
GROUND
PLANE

1405 F13

22

OGND

V

SS

25

21

1µF

1405 F12

LTC1405

J1

BNC

E6

1AGND

(J5)

(SMB)

1

+A

IN

2

1

2

R15

51Ω

OPT

5 4 3 2

J2

BNC

(J6)

(SMB)

1

–A

IN

2

R16

51Ω

OPT

5

4 3 2

2C

2D8

2D7

GND

2D6

2D5

V

CC

2D4

2D3

GND

2D2

2D1

1D8

1D7

GND

1D6

1D5

V

CC

1D4

1D3

GND

1D2

1D1

1C

2OE

2Q8

2Q7

GND

2Q6

2Q5

V

CC

2Q4

2Q3

GND

2Q2

2Q1

1Q8

1Q7

GND

1Q6

1Q5

V

CC

1Q4

1Q3

GND

1Q2

1Q1

1OE

2526272829303132333435363738394041424344454647

48

24232221201918171615141312111098765432

1

D5D4D3D2D1D0OGND

OV

DDDVDD

DGND

VSSCLKOFGAIN

D6D7D8

D9

D10

D11 (MSB)

AGND

AV

DD

AGND

V

REF

SENSE

V

CM

–AIN+A

IN

15161718192021

22

2324252627

28

1413121110

9

8765432

1

V

CC

V

CC

V

CC

24

5

3U3

NC7S04M5

J3

BNC

(J7)

(SMB)

J4

HD2X8-079

1

1

CLOCK

2

R17

51Ω

2

C7

0.1µF

12

11R1 2

100 X 15 PLCS

D0

U2, 74ACT16373DL

U1, LTC1405

C11 0.1µF

21

C9 0.1µF

21

21

12

C1 1µF

12

C3 1µF

C2 1µF

12

C10 0.1µF

12R2 2 D1

13R3 2 D2

14R4 2 D3

15R5 2 D4

16R6 2 D5

17R7 2 D6

18R8 2 D7

19R9 2 D8

110R10 2 D9

111R11 2 D10

112R12 2 D11

113R21 2

114R13 2 OF

115

1

2

3

4

5

6

789

10

1112131415

16

16

R14 2 CLK

D11

2 3

4 5

1405 F14

1

2

R20

0Ω

12

12

JP1

JP2

213

JP7

JP3

12

12

12

JP4

JP5

JP6

1

R19

0Ω

2

1

R18

20Ω

2

C6

470pF

21

C4 1µF

21

C5 1µF

E7

D1

MBR0520LT1

1 GAIN

E5

1

V

SS

E4

1

V

DD

E3

1

OV

DD

E2

1

OGND

21

C8 0.1µF

21

C12 1µF

E1

1

V

CC

V

CC

U

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APPLICATIO S I FOR ATIO

Figure 14. LTC1405 Demo Board Schematic

13

LTC1405

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APPLICATIO S I FOR ATIO

Figure 15. Top Silkscreen Layer for
LTC1405/LTC1420 Demo Board

Figure 16. Top Layer for LTC1405/LTC1420 Demo Board

14

Figure 17. Ground Plane Layer for
LTC1405/LTC1420 Demo Board

Figure 18. Power Plane Layer for LTC1405/LTC1420 Demo Board

LTC1405

U

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APPLICATIO S I FOR ATIO

Figure 19. Bottom Layer for LTC1405/LTC1420 Demo Board

TYPICAL APPLICATIO

ANALOG INPUT

(2.5V ± 1.024V)

30Ω

1µF

5V

1µF

U

Single Supply, 5Msps, 12-Bit ADC with 3V Logic Outputs

LTC1405

1µF

1000pF

NPO

1

+A

IN

2

–A

IN

3

V

CM

4

SENSE

5

V

REF

6

GND

7

V

DD

8

GND

9

D11

10

D10

11

D9

12

D8

13

D7

14

D6

GAIN

CLK

V

GND

V

OV

OGND

28
27

OF

26

5MHz CLOCK

25

SS

24
23

DD

22

DD

21
20

D0

19

D1

18

D2

17

D3

16

D4

15

D5

3V

1µF

1µF

5V

0V TO 3V
12-BIT
PARALLEL DATA
PLUS OVERFLOW

1405 TA03

15

LTC1405

TYPICAL APPLICATIO

U

Dual Supply, 5Msps, 12-Bit ADC with 71.3dB SINAD

ANALOG INPUT

(±2.048V)

5V

1µF

1µF

30Ω

1000pF, NPO

1µF

LTC1405

1

+A

IN

2

–A

IN

3

V

CM

4

SENSE

5

V

REF

6

GND

7

V

DD

8

GND

9

D11

10

D10

11

D9

12

D8

13

D7

14

D6

GAIN

CLK

V

GND

V

OV

OGND

28

5V

27

OF

26

5MHz CLOCK

25

SS

24
23

DD

22

DD

21
20

D0

19

D1

18

D2

17

D3

16

D4

15

D5

5V

1µF

–5V

1µF

12-BIT
PARALLEL DATA
PLUS OVERFLOW

1405 TA04

U

PACKAGE DESCRIPTIO

0.015

± 0.004

0.0075 – 0.0098
(0.191 – 0.249)

0.016 – 0.050

(0.406 – 1.270)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

(0.38 ± 0.10)

0° – 8° TYP

× 45°

0.008 – 0.012

(0.203 – 0.305)

(1.351 – 1.748)

Dimensions in inches (millimeters) unless otherwise specified.

GN Package

28-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.053 – 0.069

0.0250

(0.635)

BSC

0.004 – 0.009

(0.102 – 0.249)

0.229 – 0.244

(5.817 – 6.198)

12

3

0.386 – 0.393*
(9.804 – 9.982)

5

4

678 9 10 11 12

0.033

202122232425262728

19

18

17

16

15

13 14

(0.838)

REF

0.150 – 0.157**
(3.810 – 3.988)

GN28 (SSOP) 1098

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1420 12-Bit, 10Msps, Sampling ADC Pin Compatible with LTC1405
LTC1412 12-Bit, 3Msps, Sampling ADC with Parallel Output Best Dynamic Performance, SINAD = 72dB at Nyquist
LTC1415 Single 5V, 12-Bit, 1.25Msps with Parallel Output 55mW Power Dissipation, 72dB SINAD
LT1019 Precision Bandgap Reference 0.05% Max Initial Accuracy, 5ppm/°C Max Drift

16

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

1405i LT/TP 0100 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2000