Datasheet LTC1403, LTC1403A Datasheet (LINEAR TECHNOLOGY)

FEATURES

FREQUENCY (MHz)

0.1

–80

THD, 2nd, SFDR, 3rd (dB)

–74

–68

–62

–56

1 10 100

1403A TA02

–86
–92
–98

–104

–50

–44

THD

3rd

2nd, SFDR

LTC1403/LTC1403A

Serial 12-Bit/14-Bit, 2.8Msps

Sampling ADCs with Shutdown

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DESCRIPTIO

■

2.8Msps Conversion Rate

■

Low Power Dissipation: 14mW

■

3V Single Supply Operation

■

2.5V Internal Bandgap Reference can be Overdriven

■

3-Wire Serial Interface

■

Sleep (10µW) Shutdown Mode

■

Nap (3mW) Shutdown Mode

■

80dB Common Mode Rejection

■

0V to 2.5V Unipolar Input Range

■

Tiny 10-Lead MS Package

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APPLICATIO S

■

Communications

■

Data Acquisition Systems

■

Uninterrupted Power Supplies

■

Multiphase Motor Control

■

Multiplexed Data Acquisition

The LTC®1403/LTC1403A are 12-bit/14-bit, 2.8Msps se­rial ADCs with differential inputs. The devices draw only

4.7mA from a single 3V supply and come in a tiny 10-lead
MS package. A Sleep shutdown feature lowers power
consumption to 10µW. The combination of speed, low
power and tiny package makes the LTC1403/LTC1403A
suitable for high speed, portable applications.

The 80dB common mode rejection allows users to elimi­nate ground loops and common mode noise by measuring
signals differentially from the source.

The devices convert 0V to 2.5V unipolar inputs differen­tially. The absolute voltage swing for +AIN and –A

IN

extends from ground to the supply voltage.
The serial interface sends out the conversion results

during the 16 clock cycles following CONV↑ for compat­ibility with standard serial interfaces. If two additional
clock cycles for acquisition time are allowed after the data
stream in between conversions, the full sampling rate of

2.8Msps can be achieved with a 50.4MHz clock.

, LTC and LT are registered trademarks of Linear Technology Corporation.

BLOCK DIAGRA

+

A

IN

–

A

IN

10µF

LTC1403A

+

1

S & H

2

–

V

REF

3

GND

4

5 6 11

2.5V

REFERENCE

W

14-BIT ADC

EXPOSED PAD

3V10µF

2nd, 3rd and SFDR
vs Input Frequency

7

V

DD

THREE-

14-BIT LATCH

STAT E

SERIAL

OUTPUT

PORT

14

TIMING

LOGIC

8

10

9

SDO

CONV

SCK

1403A TA01

sn1403a 1403afs

1

LTC1403/LTC1403A

1
2
3
4
5

A

IN

+

A

IN

–

V

REF

GND
GND

10
9
8
7
6

CONV
SCK
SDO
V

DD

GND

TOP VIEW

11

MSE PACKAGE

10-LEAD PLASTIC MSOP

WWWU

ABSOLUTE AXI U RATI GS

(Notes 1, 2)

Supply Voltage (VDD)................................................. 4V

Analog Input Voltage

(Note 3) ....................................–0.3V to (VDD + 0.3V)

Digital Input Voltage ................... – 0.3V to (VDD + 0.3V)

Digital Output Voltage.................. – 0.3V to (VDD + 0.3V)

Power Dissipation.............................................. 100mW

Operation Temperature Range

LTC1403C/LTC1403AC............................ 0°C to 70°C

LTC1403I/LTC1403AI ......................... –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

PACKAGE/ORDER I FOR ATIO

T

= 125°C, θJA = 150°C/W

JMAX

EXPOSED PAD IS GND (PIN 11)

MUST BE SOLDERED TO PCB

Consult LTC Marketing for parts specified with wider operating temperature ranges.

U

CO VERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3V

The ● denotes the specifications which apply over the full operating

UU

W

ORDER PART

NUMBER

LTC1403CMSE
LTC1403IMSE
LTC1403ACMSE
LTC1403AIMSE

MSE PART MARKING

LTBDN
LTBDP
LTADF
LTAFD

LTC1403 LTC1403A

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 12 14 Bits
Integral Linearity Error (Notes 4, 5, 18) ● –2 ±0.25 2 –4 ±0.5 4 LSB
Offset Error (Notes 4, 18) ● –10 ±1 10 –20 ±220 LSB
Gain Error (Note 4, 18) ● –30 ±5 30 –60 ±10 60 LSB
Gain Tempco Internal Reference (Note 4) ±15 ±15 ppm/°C

External Reference ±1 ±1 ppm/°C

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A ALOG I PUT

otherwise specifications are at TA = 25°C. VDD = 3V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

V

CM

I

IN

C

IN

t

ACQ

t

AP

t

JITTER

CMRR Analog Input Common Mode Rejection Ratio fIN = 1MHz, VIN = 0V to 3V –60 dB

Analog Differential Input Range (Notes 3, 9) 2.7V ≤ VDD ≤ 3.3V ● 0 to 2.5 V
Analog Common Mode + Differential 0 to V

Input Range (Note 10)
Analog Input Leakage Current ● 1 µA
Analog Input Capacitance 13 pF
Sample-and-Hold Acquisition Time (Note 6) ● 39 ns
Sample-and-Hold Aperture Delay Time 1 ns
Sample-and-Hold Aperture Delay Time Jitter 0.3 ps

The ● denotes the specifications which apply over the full operating temperature range,

DD

f

= 100MHz, VIN = 0V to 3V –15 dB

IN

V

2

sn1403a 1403afs

LTC1403/LTC1403A

U

W

DY A IC ACCURACY

otherwise specifications are at TA = 25°C. VDD = 3V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

SINAD Signal-to-Noise Plus 100kHz Input Signal 70.5 73.5 dB

Distortion Ratio 1.4MHz Input Signal

100kHz Input Signal, External V
V

DD

750kHz Input Signal, External V
V

DD

THD Total Harmonic 100kHz First 5 Harmonics –87 –90 dB

Distortion 1.4MHz First 5 Harmonics

SFDR Spurious Free 100kHz Input Signal –87 –90 dB

Dynamic Range 1.4MHz Input Signal –83 –86 dB

IMD Intermodulation 1.25V to 2.5V 1.25MHz into A

Distortion 1.2MHz into A
Code-to-Code V

Transition Noise
Full Power Bandwidth VIN = 2.5V
Full Linear Bandwidth S/(N + D) ≥ 68dB 5 5 MHz

REF

The ● denotes the specifications which apply over the full operating temperature range,

LTC1403 LTC1403A

● 68 70.5 70 73.5 dB

= 3.3V, 72 76.3 dB

≥ 3.3V
≥ 3.3V

–

IN

= 2.5V (Note 18) 0.25 1 LSB

, SDO = 11585LSB

P-P

REF

= 3.3V, 72 76.3 dB

REF

● –83 –76 –86 –78 dB

+

, 0V to 1.25V, –82 –82 dB

IN

(Note 15) 50 50 MHz

P-P

RMS

UU U

I TER AL REFERE CE CHARACTERISTICS

full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V

PARAMETER CONDITIONS MIN TYP MAX UNITS

V

Output Voltage I

REF

V

Output Tempco 15 ppm/°C

REF

V

Line Regulation VDD = 2.7V to 3.6V, V

REF

V

Output Resistance Load Current = 0.5mA 0.2 Ω

REF

V

Settling Time 2ms

REF

= 0 2.5 V

OUT

The ● denotes the specifications which apply over the

= 2.5V 600 µV/V

REF

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DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IN

C

IN

V

OH

V

OL

I

OZ

C

OZ

I

SOURCE

I

SINK

High Level Input Voltage VDD = 3.3V ● 2.4 V
Low Level Input Voltage VDD = 2.7V ● 0.6 V
Digital Input Current VIN = 0V to V
Digital Input Capacitance 5pF
High Level Output Voltage VDD = 3V, I
Low Level Output Voltage VDD = 2.7V, I

= 2.7V, I

V

DD

Hi-Z Output Leakage D
Hi-Z Output Capacitance D
Output Short-Circuit Source Current V
Output Short-Circuit Sink Current V

OUT

OUT

V

OUT

OUT

OUT

DD

= –200µA ● 2.5 2.9 V

OUT

OUT
OUT

= 0V to V

= 0V, VDD = 3V 20 mA
= VDD = 3V 15 mA

DD

The ● denotes the specifications which apply over the

● ±10 µA

= 160µA 0.05 V
= 1.6mA ● 0.10 0.4 V

● ±10 µA

1pF

sn1403a 1403afs

3

LTC1403/LTC1403A

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POWER REQUIRE E TS

range, otherwise specifications are at TA = 25°C. (Note 17)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

DD

I

DD

P

D

Supply Voltage 2.7 3.6 V
Positive Supply Voltage Active Mode ● 4.7 7 mA

Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 12 mW

The ● denotes the specifications which apply over the full operating temperature

Nap Mode
Sleep Mode (LTC1403) 2 15 µA
Sleep Mode (LTC1403A) 2 10 µA

● 1.1 1.5 mA

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TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. VDD = 3V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

SAMPLE(MAX)

t

THROUGHPUT

t

SCK

t

CONV

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

12

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: All voltage values are with respect to GND.
Note 3: When these pins are taken below GND or above V

clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V

Note 4: Offset and full-scale specifications are measured for a single­ended A

Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.

Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference

between A

Note 9: The absolute voltage at A
Note 10: If less than 3ns is allowed, the output data will appear one clock

Maximum Sampling Frequency per Channel ● 2.8 MHz
(Conversion Rate)

Minimum Sampling Period (Conversion + Acquisiton Period) ● 357 ns
Clock Period (Note 16) ● 19.8 10000 ns
Conversion Time (Note 6) 16 18 SCLK cycles
Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns
CONV to SCK Setup Time (Notes 6, 10) 3 ns
Nearest SCK Edge Before CONV (Note 6) 0 ns
Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns
SCK to Sample Mode (Note 6) 4 ns
CONV to Hold Mode (Notes 6, 11) 1.2 ns
16th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns
Minimum Delay from SCK to Valid Bits 0 Through 13 (Notes 6, 12) 8 ns
SCK to Hi-Z at SDO (Notes 6, 12) 6 ns
Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns
V

Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms

REF

without latchup.

DD

+

input with A

IN

+

and A

IN

–

grounded and using the internal 2.5V reference.

IN

–

.

IN

IN

+

and A

–

must be within this range.

IN

The ● denotes the specifications which apply over the full operating temperature

cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.

Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)

, they will be

DD

because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.

Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.

Note 13: The time period for acquiring the input signal is started by the
16th rising clock and it is ended by the rising edge of convert.

Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.

Note 15: The full power bandwidth is the frequency where the output code
swing drops to 3dB with a 2.5V

Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read without an arbitrarily long clock.

Note 17: V
Note 18: The LTC1403A is measured and specified with 14-bit Resolution

(1LSB = 152µV) and the LTC1403 is measured and specified with 12-bit
Resolution (1LSB = 610µV).

= 3V, f

DD

SAMPLE

input sine wave.

P-P

= 2.8Msps.

sn1403a 1403afs

4

UW

OUTPUT CODE

0 81924096 12288 16383

INTEGRAL LINEARITY (LSB)

1403A G14

4

3

2

1

0

–1

–2

–3

–4

FREQUENCY (MHz)

0.1

68

SFDR (dB)

56

44

1 10 100

1403A G17

80
74

62

50

86

92

98

104

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1403/LTC1403A

TA = 25°C, VDD = 3V (LTC1403A)

ENOBs and SINAD
vs Input Frequency SFDR vs Input Frequency

12.0

11.5

11.0

10.5

10.0

9.5

ENOBs (BITS)

9.0

8.5

8.0

0.1

1 10 100

FREQUENCY (MHz)

SNR vs Input Frequency

74

71

68

65

62

SNR (dB)

59

56

53

50

0.1

1 10 100

FREQUENCY (MHz)

1.4MHz Input Summed with

1.56MHz Input IMD 4096 Point
FFT Plot

0

2.8Msps

–10

–20

–30

–40

–50

–60

–70

–80

MAGNITUDE (dB)

–90

–100
–110
–120

0 350k 700k 1.05M 1.4M

FREQUENCY (Hz)

1403A G01

1403A G03

1403A G06

THD, 2nd and 3rd vs Input
Frequency

SINAD (dB)

THD, 2nd, 3rd (dB)

–44
–50
–56
–62
–68

–74
–80
–86
–92
–98

–104

0.1

74

71

68

65

62

59

56

53

50

98kHz Sine Wave 4096 Point
FFT Plot

0
–10
–20
–30
–40
–50
–60
–70
–80

MAGNITUDE (dB)

–90

–100
–110
–120

0 350k 700k 1.05M 1.4M

Differential Linearity
vs Output Code

1.0

0.8

0.6

0.4

0.2
0

–0.2
–0.4
–0.6

DIFFERENTIAL LINEARITY (LSB)

–0.8
–1.0

0 81924096 12288 16383

THD

2nd

3rd

1 10 100

FREQUENCY (MHz)

2.8Msps

FREQUENCY (Hz)

OUTPUT CODE

1403A G04

1403A G13

1403A G02

1.3MHz Sine Wave 4096 Point
FFT Plot

0

2.8Msps

–10
–20
–30
–40
–50
–60
–70
–80

MAGNITUDE (dB)

–90
–100
–110
–120

0 350k 700k 1.05M 1.4M

FREQUENCY (Hz)

Integral Linearity
vs Output Code

1403A G05

sn1403a 1403afs

5

LTC1403/LTC1403A

CONVERSION RATE (Msps)

0 2.01.61.20.80.4 2.8 3.22.4 3.6 4.0

V

DD

SUPPLY CURRENT (mA)

1403A G12

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5
0

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Differential and Integral Linearity
vs Conversion Rate SINAD vs Conversion Rate

5

18 CLOCKS PER CONVERSION

4
3
2
1
0

–1

LINEARITY (LSB)

–2
–3
–4
–5

2.0 2.2 3.02.6 3.8 4.02.82.4 3.43.2
CONVERSION RATE (Msps)

MAX INL

TA = 25°C, VDD = 3V (LTC1403 and LTC1403A)

MAX DNL

MIN DNL

MIN INL

3.6

1403A G15

80
79
78
77
76
75

S/(N+D)

74
73
72
71
70

2.0 2.2 3.02.6 3.8 4.02.82.4 3.4 3.63.2

TA = 25°C, VDD = 3V (LTC1403A)

EXTERNAL V

INTERNAL V

INTERNAL V

CONVERSION RATE (Msps)

= 3.3V fIN~fS/3

REF

EXTERNAL V

= 2.5V fIN~fS/40

REF

REF

= 3.3V fIN~fS/40

REF

= 2.5V fIN~fS/3

1403A G16

2.5V

Power Bandwidth CMRR vs Frequency PSRR vs Frequency

P-P

12

6

0

–6

–12

–18

AMPLITUDE (dB)

–24

–30

–36

1M 10M 100M 1G

FREQUENCY (Hz)

Reference Voltage vs Load
Current

2.4902

2.4900

2.4898

(V)

2.4896

REF

V

2.4894

2.4892

2.4890

6

0.4 0.8 1.2 1.6
LOAD CURRENT (mA)

1403A G07

1403A G10

0

–20

–40

–60

CMRR (dB)

–80

–100

–120

100

10k 100k 1M

1k

FREQUENCY (Hz)

10M 100M

1403A G08

–25

–30

–35

–40

–45

–50

PSRR (dB)

–55

–60

–65

–70

110

100 1k 10k 100k 1M

FREQUENCY (Hz)

1403A G09

VDD Supply Current vs

Reference Voltage vs V

2.4902

2.4900

2.4898

(V)

2.4896

REF

V

2.4894

2.4892

2.4890

2.00.20 0.6 1.0 1.4 1.8

2.6 3.6

2.8 3.0 3.2 3.4
VDD (V)

DD

1403A G11

Conversion Rate

sn1403a 1403afs

LTC1403/LTC1403A

U

UU

PI FU CTIO S

+

A

(Pin 1): Noninverting Analog Input. A

IN

fully differentially with respect to A

–

with a 0V to 2.5V

IN

differential swing and a 0V to VDD common mode swing.

–

A

(Pin 2): Inverting Analog Input. A

IN

differentially with respect to A

IN

IN

+

with a –2.5V to 0V

differential swing and a 0V to VDD common mode swing.

V

(Pin 3): 2.5V Internal Reference. Bypass to GND and

REF

to a solid analog ground plane with a 10µF ceramic
capacitor (or 10µF tantalum in parallel with 0.1µF ce-
ramic). Can be overdriven by an external reference be­tween 2.55V and VDD.

GND (Pins 5, 6, 11): Ground and Exposed Pad. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these pins.

VDD (Pin 7): 3V Positive Supply. This single power pin
supplies 3V to the entire chip. Bypass to GND and to a solid
analog ground plane with a 10µF ceramic capacitor (or

+

operates

IN

–

operates fully

10µF tantalum in parallel with 0.1µF ceramic). Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1µF bypass capacitor as close to Pins 6 and 7
as possible.

SDO (Pin 8): Three-State Serial Data Output. Each of
output data words represents the difference between
A

IN

+

and A

–

analog inputs at the start of the previous

IN

conversion.
SCK (Pin 9): External Clock Input. Advances the conver-

sion process and sequences the output data on the rising
edge. Responds to TTL (≤3V) and 3V CMOS levels. One
or more pulses wake from sleep.

CONV (Pin 10): Convert Start. Holds the analog input
signal and starts the conversion on the rising edge.
Responds to TTL (≤3V) and 3V CMOS levels. Two pulses
with SCK in fixed high or fixed low state start Nap mode.
Four or more pulses with SCK in fixed high or fixed low
state start Sleep mode.

BLOCK DIAGRA

+

A

IN

–

A

IN

10µF

W

LTC1403A

+

1

2

–

V

REF

3

GND

4

5 6 11

S & H

2.5V

REFERENCE

14-BIT ADC

EXPOSED PAD

3V10µF

7

V

DD

THREE-

14-BIT LATCH

STAT E

SERIAL

OUTPUT

PORT

14

TIMING

LOGIC

10

8

9

SDO

CONV

SCK

1403A BD

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7

LTC1403/LTC1403A

UWW

TI I G DIAGRA

t

2

t

3

SCK

CONV

INTERNAL

S/H STATUS

SDO

SCK

CONV

INTERNAL

S/H STATUS

SDO

SAMPLE HOLD HOLD

SAMPLE HOLD HOLD

11716 2 3 4 5 6 7 8 9 10 11 12 13

t

4

t

6

t

8

Hi-Z

*BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.

t

2

t

3

11716 2 3 4 5 6 7 8 9 10 11 12 13

t

4

t

6

t

8

Hi-Z

LTC1403 Timing Diagram

t

1

t

14-BIT DATA WORD

CONV

t

THROUGHPUT

10

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X XD9

t

LTC1403A Timing Diagram

t

1

t

14-BIT DATA WORD

CONV

t

THROUGHPUT

10

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

D13 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D11

t

15 16 17 18

14

t

5

t

15 16 17 18

14

t

5

t

t

7

1

t

ACQ

SAMPLE

t

7

SAMPLE

t

9

Hi-Z

1403A TD01

1

t

ACQ

t

9

Hi-Z

1403A TD01b

8

8

8

SLK

CONV

NAP

SLEEP

V

REF

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS

SCK

SDO

Nap Mode and Sleep Mode Waveforms

t

1

SCK to SDO Delay

V

t

8

t

10

IH

V

OH

V

OL

SCK

SDO

t

1

t

12

V

IH

t

9

1403A TD03

90%

10%

1403A TD02

sn1403a 1403afs

LTC1403/LTC1403A

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WUU

APPLICATIO S I FOR ATIO

DRIVING THE ANALOG INPUT

The differential analog inputs of the LTC1403/LTC1403A are
easy to drive. The inputs may be driven differentially or as a
single-ended input (i.e., the A
differential analog inputs, A
same instant. Any unwanted signal that is common to both
inputs of each input pair will be reduced by the common mode
rejection of the sample-and-hold circuit. The inputs draw only
one small current spike while charging the sample-and-hold
capacitors at the end of conversion. During conversion, the
analog inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1403/
LTC1403A inputs can be driven directly. As source imped­ance increases, so will acquisition time. For minimum acqui­sition time with high source impedance, a buffer amplifier
must be used. The main requirement is that the amplifier
driving the analog input(s) must settle after the small current
spike before the next conversion starts (settling time must be
39ns for full throughput rate). Also keep in mind while
choosing an input amplifier, the amount of noise and har­monic distortion added by the amplifier.

CHOOSING AN INPUT AMPLIFIER

Choosing an input amplifier is easy if a few requirements are
taken into consideration. First, to limit the magnitude of the
voltage spike seen by the amplifier from charging the sam­pling capacitor, choose an amplifier that has a low output
impedance (<100Ω) at the closed-loop bandwidth frequency.
For example, if an amplifier is used in a gain of 1 and has a
unity-gain bandwidth of 50MHz, then the output impedance
at 50MHz must be less than 100Ω. The second requirement
is that the closed-loop bandwidth must be greater than
40MHz to ensure adequate small-signal settling for full
throughput rate. If slower op amps are used, more time for
settling can be provided by increasing the time between
conversions. The best choice for an op amp to drive the
LTC1403/LTC1403A will depend on the application. Gener­ally, applications fall into two categories: AC applications
where dynamic specifications are most critical and time
domain applications where DC accuracy and settling time are
most critical. The following list is a summary of the op amps
that are suitable for driving the LTC1403/LTC1403A. (More

–

input is grounded). Both

IN

IN

+

with A

–

, are sampled at the

IN

detailed information is available in the Linear Technology
Databooks and on the LinearViewTM CD-ROM.)

LTC®1566-1: Low Noise 2.3MHz Continuous Time Low­Pass Filter.

LT1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier. 2.7V
to ±15V supplies. Very high A
settling to 0.5LSB for a 4V swing. THD and noise are –93dB
to 40kHz and below 1LSB to 320kHz (AV = 1, 2V
VS = 5V), making the part excellent for AC applications (to 1/
3 Nyquist) where rail-to-rail performance is desired. Quad
version is available as LT1631.

LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier. 2.7V
to ±15V supplies. Very high A
settling to 0.5LSB for a 4V swing. It is suitable for applica­tions with a single 5V supply. THD and noise are
–93dB to 40kHz and below 1LSB to 800kHz (AV = 1,
2V

into 1kΩ, VS = 5V), making the part excellent for AC

P-P

applications where rail-to-rail performance is desired.
version is available as LT1633.

LT1813: Dual 100MHz 750V/µs 3mA Voltage Feedback
Amplifier. 5V to ±5V supplies. Distortion is –86dB to 100kHz
and –77dB to 1MHz with ±5V supplies (2V
Excellent part for fast AC applications with ±5V␣ supplies.

LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/Amplifier,

8.5nV/√Hz.
LT1806/LT1807: 325MHz GBWP, –80dBc Distortion at 5MHz,

Unity-Gain Stable, R-R In and Out, 10mA/Amplifier, 3.5nV/√Hz.
LT1810: 180MHz GBWP, –90dBc Distortion at 5MHz,

Unity-Gain Stable, R-R In and Out, 15mA/Amplifier, 16nV/√Hz.
LT1818/LT1819: 400MHz, 2500V/µs,9mA, Single/Dual Volt-

age Mode Operational Amplifier.
LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz, Unity-

Gain Stable, R-R In and Out, 15mA/Amplifier,

0.95nV/√Hz.
LT6203: 100MHz GBWP, –80dBc Distortion at 1MHz,

Unity-Gain Stable, R-R In and Out, 3mA/Amplifier,

1.9nV/√Hz.
LT6600-10: Amplifier/Filter Differential In/Out with 10MHz

Cutoff.

LinearView is a trademark of Linear Technology Corporation.

, 500µV offset and 520ns

VOL

into 1kΩ,

P-P

, 1.5mV offset and 400ns

VOL

into 500Ω).

P-P

sn1403a 1403afs

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APPLICATIO S I FOR ATIO

51Ω

47pF

10µF

Figure 1. RC Input Filter Figure 2

INPUT FILTERING AND SOURCE IMPEDANCE

The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1403/LTC1403A noise and distortion. The small­signal bandwidth of the sample-and-hold circuit is 50MHz.
Any noise or distortion products that are present at the
analog inputs will be summed over this entire bandwidth.
Noisy input circuitry should be filtered prior to the analog
inputs to minimize noise. A simple 1-pole RC filter is
sufficient for many applications. For example, Figure 1
shows a 47pF capacitor from A
source resistor to limit the input bandwidth to 47MHz. The
47pF capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam­pling-glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silvermica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors
can generate distortion from self heating and from dam­age that may occur during soldering. Metal film surface
mount resistors are much less susceptible to both prob­lems. When high amplitude unwanted signals are close in
frequency to the desired signal frequency, a multiple pole
filter is required. High external source resistance, com­bined with the 13pF of input capacitance, will reduce the
rated 50MHz bandwidth and increase acquisition time
beyond 39ns.

1

+

A

IN

2

–

A

IN

LTC1403/

LTC1403A

3

V

REF

11

GND

1403A F01

+

to ground and a 51Ω

IN

11

3

V

REF

LTC1403/

LTC1403A

GND

1403A F02

3V

REF

10µF

INPUT RANGE

The analog inputs of the LTC1403/LTC1403A may be
driven fully differentially with a single supply. Each input
may swing up to 3V

individually. In the conversion

P-P

range, the noninverting input of each channel is always up
to 2.5V more positive than the inverting input of each
channel. The 0V to 2.5V range is also ideally suited for
single-ended input use with single supply applications.
The common mode range of the inputs extend from
ground to the supply voltage VDD. If the difference be­tween the A

IN

+

and A

–

inputs exceeds 2.5V, the output

IN

code will stay fixed at all ones and if this difference goes
below 0V, the ouput code will stay fixed at all zeros.

INTERNAL REFERENCE

The LTC1403/LTC1403A has an on-chip, temperature com­pensated, bandgap reference that is factory trimmed near

2.5V to obtain 2.5V input span. The reference amplifier
output V

, (Pin 3) must be bypassed with a capacitor to

REF

ground. The reference amplifier is stable with capacitors
of 1µF or greater. For the best noise performance, a 10µF
ceramic or a 10µF tantalum in parallel with a 0.1µF ceramic
is recommended. The V

pin can be overdriven with an

REF

external reference as shown in Figure 2. The voltage of the
external reference must be higher than the 2.5V of the
class A pull-up output of the internal reference. The
recommended range for an external reference is 2.55V to
VDD. An external reference at 2.55V will see a DC quiescent
load of 0.75mA and as much as 3mA during conversion.

10

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0

–20

–40

–60

CMRR (dB)

–80

–100

–120

100

INPUT SPAN VERSUS REFERENCE VOLTAGE

The differential input range has a unipolar voltage span
that equals the difference between the voltage at the
reference buffer output V
ground (Exposed Pad Ground). The differential input
range of the ADC is 0V to 2.5V when using the internal
reference. The internal ADC is referenced to these two
nodes. This relationship also holds true with an external
reference.

DIFFERENTIAL INPUTS

The LTC1403/LTC1403A has a unique differential sample­and-hold circuit that allows inputs from ground to VDD.
The ADC will always convert the unipolar difference of

+

A

IN

–

– A

, independent of the common mode voltage at

IN

CMRR vs Frequency

10k 100k 1M

1k

FREQUENCY (Hz)

Figure 3 Figure 4

at Pin 3, and the voltage at the

REF

10M 100M

1403A F03

LTC1403/LTC1403A Transfer

Characteristic

111...111

111...110

111...101

UNIPOLAR OUTPUT CODE

000...010

000...001

000...000

INPUT VOLTAGE (V)

FS – 1LSB0

1403A F05

the inputs. The common mode rejection holds up at
extremely high frequencies, see Figure 3. The only require­ment is that both inputs not go below ground or exceed
VDD. Integral nonlinearity errors (INL) and differential
nonlinearity errors (DNL) are largely independent of the
common mode voltage. However, the offset error will
vary. The change in offset error is typically less than 0.1%
of the common mode voltage.

Figure 4 shows the ideal input/output characteristics for
the LTC1403/LTC1403A. The code transitions occur mid­way between successive integer LSB values (i.e., 0.5LSB,

1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is natural
binary with 1LSB = 2.5V/16384 = 153µV for the LTC1403A,
and 1LSB = 2.5V/4096 = 610µV for the LTC1403. The
LTC1403A has 1LSB RMS of random white noise.

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Figure 5. Recommended Layout

optimum performance, a 10µF surface mount AVX capaci-
tor with a 0.1µF ceramic is recommended for the VDD and
V

pins. Alternatively, 10µF ceramic chip capacitors

REF

such as Murata GRM235Y5V106Z016 may be used. The
capacitors must be located as close to the pins as possible.
The traces connecting the pins and the bypass capacitors
must be kept short and should be made as wide as
possible.

Figure 5 shows the recommended system ground connec­tions. All analog circuitry grounds should be terminated at
the LTC1403/LTC1403A GND (Pins 4, 5, 6 and exposed
pad). The ground return from the LTC1403/LTC1403A
(Pins 4, 5, 6 and exposed pad) to the power supply should
be low impedance for noise free operation. Digital circuitry
grounds must be connected to the digital supply common.
In applications where the ADC data outputs and control
signals are connected to a continuously active micropro­cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com­parator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus.

Board Layout and Bypassing

Wire wrap boards are not recommended for high resolu­tion and/or high speed A/D converters. To obtain the best
performance from the LTC1403/LTC1403A, a printed cir­cuit board with ground plane is required. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particu­lar, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the two input
wires should be kept matched.

High quality tantalum and ceramic bypass capacitors
should be used at the VDD and V
Block Diagram on the first page of this data sheet. For

pins as shown in the

REF

POWER-DOWN MODES

Upon power-up, the LTC1403/LTC1403A is initialized to
the active state and is ready for conversion. The Nap and
Sleep mode waveforms show the power-down modes for
the LTC1403/LTC1403A. The SCK and CONV inputs con­trol the power-down modes (see Timing Diagrams). Two
rising edges at CONV, without any intervening rising
edges at SCK, put the LTC1403/LTC1403A. in Nap mode
and the power drain drops from 14mW to 6mW. The
internal reference remains powered in Nap mode. One or
more rising edges at SCK wake up the LTC1403/LTC1403A
for service very quickly, and CONV can start an accurate
conversion within a clock cycle. Four rising edges at

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CONV, without any intervening rising edges at SCK, put
the LTC1403/LTC1403A in Sleep mode and the power
drain drops from 16mW to 10µW. One or more rising
edges at SCK wake up the LTC1403/LTC1403A for opera­tion. The internal reference (V
settle with a 10µF load. Note that, using sleep mode more
frequently than every 2ms, compromises the settled accu­racy of the internal reference. Note that, for slower conver­sion rates, the Nap and Sleep modes can be used for
substantial reductions in power consumption.

DIGITAL INTERFACE

The LTC1403/LTC1403A has a 3-wire SPI (Serial Protocol
Interface) interface. The SCK and CONV inputs and SDO
output implement this interface. The SCK and CONV
inputs accept swings from 3V logic and are TTL compat­ible, if the logic swing does not exceed VDD. A detailed
description of the three serial port signals follows:

Conversion Start Input (CONV)

The rising edge of CONV starts a conversion, but subse­quent rising edges at CONV are ignored by the LTC1403/
LTC1403A until the following 16 SCK rising edges have
occurred. It is necessary to have a minimum of 16 rising
edges of the clock input SCK between rising edges of
CONV. But to obtain maximum conversion speed, it is
necessary to allow two more clock periods between con­versions to allow 39ns of acquisition time for the internal
ADC sample-and-hold circuit. With 16 clock periods per
conversion, the maximum conversion rate is limited to

2.8Msps to allow 39ns for acquisition time. In either case,
the output data stream comes out within the first 16 clock
periods to ensure compatibility with processor serial
ports. The duty cycle of CONV can be arbitrarily chosen to
be used as a frame sync signal for the processor serial
port. A simple approach to generate CONV is to create a
pulse that is one SCK wide to drive the LTC1403/LTC1403A
and then buffer this signal with the appropriate number of
inverters to ensure the correct delay driving the frame

) takes 2ms to slew and

REF

sync input of the processor serial port. It is good practice
to drive the LTC1403/LTC1403A CONV input first to avoid
digital noise interference during the sample-to-hold tran­sition triggered by CONV at the start of conversion. It is
also good practice to keep the width of the low portion of
the CONV signal greater than 15ns to avoid introducing
glitches in the front end of the ADC just before the sample­and-hold goes into hold mode at the rising edge of CONV.

Minimizing Jitter on the CONV Input

In high speed applications where high amplitude sinewaves
above 100kHz are sampled, the CONV signal must have as
little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement easily. The challenge is to generate a
CONV signal from this crystal clock without jitter corrup­tion from other digital circuits in the system. A clock
divider and any gates in the signal path from the crystal
clock to the CONV input should not share the same
integrated circuit with other parts of the system. As shown
in the interface circuit examples, the SCK and CONV inputs
should be driven first, with digital buffers used to drive the
serial port interface. Also note that the master clock in the
DSP may already be corrupted with jitter, even if it comes
directly from the DSP crystal. Another problem with high
speed processor clocks is that they often use a low cost,
low speed crystal (i.e., 10MHz) to generate a fast, but
jittery, phase-locked-loop system clock (i.e., 40MHz). The
jitter in these PLL-generated high speed clocks can be
several nanoseconds. Note that if you choose to use the
frame sync signal generated by the DSP port, this signal
will have the same jitter of the DSP’s master clock.

Serial Clock Input (SCK)

The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK starts clocking out
the 12/14 data bits with the MSB sent first. A simple
approach is to generate SCK to drive the LTC1403/

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APPLICATIO S I FOR ATIO

LTC1403A first and then buffer this signal with the appro­priate number of inverters to drive the serial clock input of
the processor serial port. Use the falling edge of the clock
to latch data from the Serial Data Output (SDO) into your
processor serial port. The 14-bit Serial Data will be re­ceived right justified, in a 16-bit word with 16 or more
clocks per frame sync. It is good practice to drive the
LTC1403/LTC1403A SCK input first to avoid digital noise
interference during the internal bit comparison decision
by the internal high speed comparator. Unlike the CONV
input, the SCK input is not sensitive to jitter because the
input signal is already sampled and held constant.

Serial Data Output (SDO)

Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends
out 12/14 bits in the output data stream beginning at the
third rising edge of SCK after the rising edge of CONV. SDO
is always in high impedance mode when it is not sending
out data bits. Please note the delay specification from SCK
to a valid SDO. SDO is always guaranteed to be valid by the
next rising edge of SCK. The 16-bit output data stream is
compatible with the 16-bit or 32-bit serial port of most
processors.

HARDWARE INTERFACE TO TMS320C54x

The LTC1403/LTC1403A is a serial output ADC whose
interface has been designed for high speed buffered serial
ports in fast digital signal processors (DSPs). Figure 6
shows an example of this interface using a TMS320C54X.

The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial data
can be collected in two alternating 1kB segments, in real
time, at the full 2.8Msps conversion rate of the LTC1403/
LTC1403A. The DSP assembly code sets frame sync mode
at the BFSR pin to accept an external positive going pulse
and the serial clock at the BCLKR pin to accept an external
positive edge clock. Buffers near the LTC1403/LTC1403A
may be added to drive long tracks to the DSP to prevent
corruption of the signal to LTC1403/LTC1403A. This con­figuration is adequate to traverse a typical system board,
but source resistors at the buffer outputs and termination
resistors at the DSP, may be needed to match the charac­teristic impedance of very long transmission lines. If you
need to terminate the SDO transmission line, buffer it first
with one or two 74ACTxx gates. The TTL threshold inputs
of the DSP port respond properly to the 3V swing from the
SDO pin.

LTC1403/
LTC1403A

3V 5V

7

V

DD

10

CONV

9

SCK

8

SDO

6

GND

CONV

CLK

0V TO 3V LOGIC SWING

Figure 6. DSP Serial Interface to TMS320C54x

3-WIRE SERIAL
INTERFACELINK

B13 B12

V

CC

BFSR

BCLKR

BDR

TMS320C54x

1403A F09

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; 01-08-01 ******************************************************************
; Files: 014SI.ASM -> 1403A Sine wave collection with Serial Port interface
; bvectors.asm buffered mode to avoid standard mode bug.
; s2k14ini.asm 2k buffer size.
; first element at 1024, last element at 1023, two middles at 2047 and 0000
; unipolar mode
; Works 16 or 64 clock frames.
; negative edge BCLKR
; negative BFSR pulse
; -0 data shifted
; 1' cable from counter to CONV at DUT
; 2' cable from counter to CLK at DUT
; ***************************************************************************

.width 160
.length 110
.title "sineb0 BSP in auto buffer mode"
.mmregs
.setsect ".text", 0x500,0 ;Set address of executable
.setsect "vectors", 0x180,0 ;Set address of incoming 1403 data
.setsect "buffer", 0x800,0 ;Set address of BSP buffer for clearing
.setsect "result", 0x1800,0 ;Set address of result for clearing
.text ;.text marks start of code

start:
;this label seems necessary
;Make sure /PWRDWN is low at J1-9
;to turn off AC01 adc
tim=#0fh
prd=#0fh
tcr = #10h ; stop timer
tspc = #0h ; stop TDM serial port to AC01
pmst = #01a0h ; set up iptr. Processor Mode STatus register
sp = #0700h ; init stack pointer.
dp = #0 ; data page
ar2 = #1800h ; pointer to computed receive buffer.
ar3 = #0800h ; pointer to Buffered Serial Port receive buffer
ar4 = #0h ; reset record counter
call sineinit ; Double clutch the initialization to insure a proper
sinepeek:
call sineinit ; reset. The external frame sync must occur 2.5 clocks
; or more after the port comes out of reset.
wait goto wait

; ----------------Buffered Receive Interrupt Routine ------------------

breceive:
ifr = #10h ; clear interrupt flags
TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer
if (NTC) goto bufull ; if this still the first half get next half
bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))
return_enable
; --------------mask and shift input data ----------------------------

bufull:
b = *ar3+ << -0 ; load acc b with BSP buffer and shift right -0
b = #03FFFh & b ; mask out the TRISTATE bits with #03FFFh
;
*ar2+ = data(#0bh) ; store B to out buffer and advance AR2 pointer
TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h
if (TC) goto start ; restart if out buffer is at 1fffh
goto bufull

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15

LTC1403/LTC1403A

; -------------------dummy bsend return-----------------------­bsend return_enable ;this is also a dummy return to define bsend
;in vector table file BVECTORS.ASM
; ----------------------- end ISR ----------------------------

.copy "c:\dskplus\1403\s2k14ini.asm" ;initialize buffered serial port
.space 16*32 ;clear a chunk at the end to mark the end

;======================================================================
;
; VECTORS
;
;======================================================================
.sect "vectors" ;The vectors start here
.copy "c:\dskplus\1403\bvectors.asm" ;get BSP vectors

.sect "buffer" ;Set address of BSP buffer for clearing
.space 16*0x800
.sect "result" ;Set address of result for clearing
.space 16*0x800

.end

**********************************************************************
* (C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 *
**********************************************************************
* *
* File: s2k14ini.ASM BSP initialization code for the 'C54x DSKplus *
* for use with 1403A in standard mode *
* BSPC and SPC are the same in the 'C542 *
* BSPCE and SPCE seem the same in the 'C542 *
**********************************************************************
.title "Buffered Serial Port Initialization Routine"
ON .set 1
OFF .set !ON
YES .set 1
NO .set !YES
BIT_8 .set 2
BIT_10 .set 1
BIT_12 .set 3
BIT_16 .set 0
GO .set 0x80

**********************************************************************
* This is an example of how to initialize the Buffered Serial Port (BSP).
* The BSP is initialized to require an external CLK and FSX for
* operation. The data format is 16-bits, burst mode, with autobuffering
* enabled.
*
*****************************************************************************************************
*LTC1403 timing from LCC28 socket board with 10MHz crystal. *
*10MHz, divided from 40MHz, forced to CLKIN by 1403 board. *
*Horizontal scale is 25ns/chr or 100ns period at BCLKR *
*Timing measured at DSP pins. Jxx pin labels for jumper cable. *
*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/~~~~~~~~~~~*
*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~*
*BDR Pin J1-26 _---_---_---<B13-B12-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>---_---<B13-B12*
*CLKIN Pin J5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~*
*C542 read 0 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 0 0 B13 B12*
* *

16

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LTC1403/LTC1403A

* negative edge BCLKR
* negative BFSR pulse
* no data shifted
* 1' cable from counter to CONV at DUT
* 2' cable from counter to CLK at DUT
*No right shift is needed to right justify the input data in the main program *
*the two msbs should also be masked *
*****************************************************************************************************
*
Loopback .set NO ;(digital looback mode?) DLB bit
Format .set BIT_16 ;(Data format? 16,12,10,8) FO bit
IntSync .set NO ;(internal Frame syncs generated?) TXM bit
IntCLK .set NO ;(internal clks generated?) MCM bit
BurstMode .set YES ;(if BurstMode=NO, then Continuous) FSM bit
CLKDIV .set 3 ;(3=default value, 1/4 CLOCKOUT)
PCM_Mode .set NO ;(Turn on PCM mode?)
FS_polarity .set YES ;(change polarity)YES=^^^\_/^^^, NO=___/^\___
CLK_polarity .set NO ;(change polarity)for BCLKR YES=_/^, NO=~\_
Frame_ignore .set !YES ;(inverted !YES -ignores frame)
XMTautobuf .set NO ;(transmit autobuffering)
RCVautobuf .set YES ;(receive autobuffering)
XMThalt .set NO ;(transmit buff halt if XMT buff is full)
RCVhalt .set NO ;(receive buff halt if RCV buff is full)
XMTbufAddr .set 0x800 ;(address of transmit buffer)
XMTbufSize .set 0x000 ;(length of transmit buffer)
RCVbufAddr .set 0x800 ;(address of receive buffer)
RCVbufSize .set 0x800 ;(length of receive buffer)works up to 800
*
* See notes in the 'C54x CPU and Peripherals Reference Guide on setting up
* valid buffer start and length values. Page 9-44
*
*
**********************************************************************
.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync <<5)) ,SPCval
.eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format & 1)<<7)|(Frame_ignore<<8)|(PCM_Mode<<9)), SPCEval
.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)), SPCEval

sineinit:
bspc = #SPCval ; places buffered serial port in reset
ifr = #10h ; clear interrupt flags
imr = #210h ; Enable HPINT,enable BRINT0
intm = 0 ; all unmasked interrupts are enabled.
bspce = #SPCEval ; programs BSPCE and ABU
axr = #XMTbufAddr ; initializes transmit buffer start address
bkx = #XMTbufSize ; initializes transmit buffer size
arr = #RCVbufAddr ; initializes receive buffer start address
bkr = #RCVbufSize ; initializes receive buffer size
bspc = #(SPCval | GO) ; bring buffered serial port out of reset
return ;for transmit and receive because GO=0xC0

; ***************************************************************************
; File: BVECTORS.ASM -> Vector Table for the 'C54x DSKplus 10.Jul.96
; BSP vectors and Debugger vectors
; TDM vectors just return
; ***************************************************************************
; The vectors in this table can be configured for processing external and
; internal software interrupts. The DSKplus debugger uses four interrupt
; vectors. These are RESET, TRAP2, INT2, and HPIINT.
; * DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER *
;

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APPLICATIO S I FOR ATIO

; All other vector locations are free to use. When programming always be sure
; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and
; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the
; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.
;
;
;
.title "Vector Table"
.mmregs

reset goto #80h ;00; RESET * DO NOT MODIFY IF USING DEBUGGER *
nop
nop
nmi return_enable ;04; non-maskable external interrupt
nop
nop
nop
trap2 goto #88h ;08; trap2 * DO NOT MODIFY IF USING DEBUGGER *
nop
nop
.space 52*16 ;0C-3F: vectors for software interrupts 18-30
int0 return_enable ;40; external interrupt int0
nop
nop
nop
int1 return_enable ;44; external interrupt int1
nop
nop
nop
int2 return_enable ;48; external interrupt int2
nop
nop
nop
tint return_enable ;4C; internal timer interrupt
nop
nop
nop
brint goto breceive ;50; BSP receive interrupt
nop
nop
nop
bxint goto bsend ;54; BSP transmit interrupt
nop
nop
nop
trint return_enable ;58; TDM receive interrupt
nop
nop
nop
txint return_enable ;5C; TDM transmit interrupt
nop
nop
int3 return_enable ;60; external interrupt int3
nop
nop
nop
hpiint dgoto #0e4h ;64; HPIint * DO NOT MODIFY IF USING DEBUGGER *
nop
nop
.space 24*16 ;68-7F; reserved area

18

sn1403a 1403afs

PACKAGE DESCRIPTIO

2.794 ± 0.102
(.110 ± .004)

U

MSE Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1663)

0.889
(.035 ± .005)

± 0.127

LTC1403/LTC1403A

BOTTOM VIEW OF

EXPOSED PAD OPTION

1

2.06 ± 0.102

(.081 ± .004)

± 0.102

1.83

(.072 ± .004)

5.23

(.206)

MIN

0.305 ± 0.038

(.0120 ± .0015)

TYP

RECOMMENDED SOLDER PAD LAYOUT

0.254

(.010)

GAUGE PLANE

0.18

(.007)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

DETAIL “A”

DETAIL “A”

2.083 ± 0.102
(.082 ± .004)

0.50

(.0197)

BSC

– 6° TYP

0°

0.53 ± 0.152

(.021 ± .006)

3.20 – 3.45

(.126 – .136)

SEATING

PLANE

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

4.90 ± 0.152
(.193 ± .006)

0.17 – 0.27

(.007 – .011)

TYP

1.10

(.043)

MAX

10

12

0.50

(.0197)

BSC

8910

3

7

6

45

0.497 ± 0.076

(.0196 ± .003)

REF

3.00 ± 0.102
(.118 ± .004)

(NOTE 4)

0.86

(.034)

REF

0.127 ± 0.076
(.005 ± .003)

MSOP (MSE) 0603

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

sn1403a 1403afs

19

LTC1403/LTC1403A

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS
ADCs

LTC1608 16-Bit, 500ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD
LTC1604 16-Bit, 333ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD
LTC1609 16-Bit, 250ksps Serial ADC 5V, Configurable Bipolar/Unipolar Inputs
LTC1411 14-Bit, 2.5Msps Parallel ADC 5V, Selectable Spans, 80dB SINAD
LCT1414 14-Bit, 2.2Msps Parallel ADC ±5V Supply, ±2.5V Span, 78dB SINAD
LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, 14mW, MSOP Package
LTC1420 12-Bit, 10Msps Parallel ADC 5V, Selectable Spans, 72dB SINAD
LTC1405 12-Bit, 5Msps Parallel ADC 5V, Selectable Spans, 115mW
LTC1412 12-Bit, 3Msps Parallel ADC ±5V Supply, ±2.5V Span, 72dB SINAD
LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.5V Span
LTC1864/LTC1865 16-Bit, 250ksps Serial ADC 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package

DACs

LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs 87dB SFDR, 20ns Settling Time
LTC1592 16-Bit, Serial SoftSpanTM I

References

LT1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift
LT1461-2.5 Precision Voltage Reference 0.04% Initial Accuracy, 3ppm Drift
LT1460-2.5 Micropower Series Voltage Reference 0.1% Initial Accuracy, 10ppm Drift
SoftSpan is a trademark of Linear Technology Corporation.

DAC ±1LSB INL/DNL, Software Selectable Spans

OUT

20

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

sn1403a 1403afs

LT/TP 1203 1K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2003