Page 1
FEATURES
Final Electrical Specifications
■
Sample Rate: 2.2Msps
■
72dB S/(N + D) and –89dB THD at Nyquist
■
No Missing Codes over Temperature
■
Available in 16-Pin Narrow SSOP Package
■
Single Supply 5V or ±5V Operation
■
Power Dissipation: 90mW (Typ)
■
Nap Mode with Instant Wake-Up: 15mW
■
Sleep Mode: 10µW
■
True Differential Inputs Reject Common Mode Noise
■
80MHz Full Power Bandwidth Sampling
■
Input Range (1mV/LSB): 0V to 4.096V or ±2.048V
■
Internal Reference Can Be Overdriven Externally
■
3-Wire Interface to DSPs and Processors (SPI and
MICROWIRETM Compatible)
U
APPLICATIONS
■
Telecommunications
■
High Speed Data and Signal Acquisition
■
Digitally Multiplexed Data Acquisition Systems
■
Digital Radio Receivers
■
Spectrum Analysis
■
Low Power and Battery-Operated Systems
■
Handheld or Portable Instruments
■
Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corp.
LTC1402
Serial 12-Bit, 2.2Msps
Sampling ADC with Shutdown
U
DESCRIPTION
The LTC®1402 is a 12-bit, 2.2Msps sampling A/D converter. This high performance device includes a high dynamic range sample-and-hold and a precision reference.
It operates from a single 5V supply or dual ±5V supplies
and draws only 90mW from 5V.
The versatile differential input offers a unipolar range of
4.096V and a bipolar range of ±2.048V for dual supply
systems where high performance op amps perform best,
eliminating the need for special translation circuitry.
The high common mode rejection allows users to eliminate ground loops and common mode noise by measuring
signals differentially from the source.
Outstanding AC performance includes 72dB S/(N + D) and
–93dB SFDR at the Nyquist input frequency of 1.1MHz
with dual ±5V supplies and –84dB SFDR with a single 5V
supply.
The LTC1402 has two power saving modes: Nap and
Sleep. Nap mode consumes only 15mW of power and
Sleep can wake up and convert immediately. In Sleep
mode, it typically consumes 10µW of power. Upon power-
up from Sleep mode, a reference ready (REFRDY) signal
is available in the serial data word to indicate that the
reference has settled and the chip is ready to convert.
The 3-wire serial port allows compact and efficient data
transfer to a wide range of microprocessors, microcontrollers and DSPs. A digital output driver power supply pin
allows direct connection to 3V or lower logic.
October 1999
BLOCK DIAGRA
10µF
10µF
GAIN
3
SAMPLE-
AND-HOLD
4
5
7
LTC1402
10µF
+A
IN
–A
IN
V
REF
4.096V
64k
64k
–5V OR 0V
W
5V 3V OR 5V
AVDD11211
12-BIT ADC
–
+
2.048
REFERENCE
AGND1VSS14 13AGND2
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DV
TIMING
LOGIC
OV
OUTPUT
BUFFER
DD
10
D
OUT
8
BIP/UNI
16
CONV
15
SCK
1402 TA01
OGND962 DGND
DD
5 Harmonic THD, 2nd, 3rd and SFDR
vs Input Frequency (Unipolar)
0
–10
–20
–30
f
SAMPLE
–40
–50
–60
–70
–80
–90
THD, SFDR, 2ND 3RD (dB)
–100
–110
–120
4
10
THD
SFDR
2ND
3RD
= 2.22MHz
5
10
INPUT FREQUENCY (Hz)
6
10
1401 G05
7
10
1
Page 2
LTC1402
T
WW
W
U
ABSOLUTE MAXIMUM RATINGS
AVDD = DVDD = OVDD = V
Supply Voltage (VDD)................................................. 6V
Negative Supply Voltage (VSS) ............................... – 6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) ..........................(VSS – 0.3V) to (VDD + 0.3V)
Digital Input Voltage
(Note 4) ..........................(VSS – 0.3V) to (VDD + 0.3V)
Digital Output Voltage......... (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation.............................................. 250mW
Operation Temperature Range
LTC1402C ............................................... 0°C to 70°C
LTC1402I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
(Notes 1, 2)
DD
U
PACKAGE/ORDER INFORMATION
TOP VIEW
AV
1
DD
2
AGND1
+
3
A
IN
–
4
A
IN
5
V
REF
6
AGND2
7
GAIN
8
BIP/UNI
16-LEAD NARROW PLASTIC SSOP
Consult factory for Military grade parts.
GN PACKAGE
T
= 125°C, θJA = 150°C/W
JMAX
CONV
16
15
SCK
14
V
SS
13
DGND
12
DV
DD
11
0V
DD
10
D
OUT
9
OGND
GN PART MARKING
W
ORDER PART
NUMBER
LTC1402CGN
LTC1402IGN
1402
1402I
U
Lead Temperature (Soldering, 10 sec).................. 300°C
U
CONVERTER CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. With internal reference (Note 5).
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) ● 12 Bits
Integral Linearity Error (Note 6) ● ±0.35 ±1LSB
Differential Linearity (Note 6) ● ±0.25 ±1LSB
Offset Error (Note 6) ● ±2 ±10 LSB
Full-Scale Error (Note 6) ● ±10 ±15 LSB
Full-Scale Tempco Internal Reference (Note 6) ±15 ppm/°C
The ● denotes the specifications which apply over the full operating
External Reference ±1 ppm/°C
UU
A ALOG I PU
otherwise specifications are at TA = 25°C. (Note 5)
The ● denotes the specifications which apply over the full operating temperature range,
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
V
CM
I
IN
C
IN
t
ACQ
t
AP
t
JITTER
CMRR Analog Input Common Mode Rejection Ratio fIN = 1MHz, VIN = 2V to –2V –62 dB
Analog Differential Input Range (Notes 3, 11) Bipolar Mode with BIP/UNI High ● ±2.048 V
4.75V ≤ V
–5.25V ≤ V
Unipolar Mode with BIP/UNI Low ● 0 to 4.096 V
4.75V ≤ V
–5.25V ≤ V
Analog Common Mode + Differential Dual ±5V Supply –2.5 to 5 V
Input Range (Note 12) Single 5V Supply 0 to 5 V
Analog Input Leakage Current ● 1 µA
Analog Input Capacitance 10 pF
Sample-and-Hold Acquisition Time ● 60 ns
Sample-and-Hold Aperture Delay Time 2.6 ns
Sample-and-Hold Aperture Delay Time Jitter 1 ps
f
= 100MHz, VIN = 2V to –2V –24 dB
IN
≤ 5.25V V
DD
≤ –4.75V V
SS
≤ 5.25V V
DD
≤ 0V V
SS
2
Page 3
LTC1402
UW
DYNAMIC ACCURACY
otherwise specifications are at TA = 25°C. Bipolar mode with ± 5V supplies and unipolar mode with 5V supply. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
S/(N + D) Signal-to-Noise Plus 100kHz Input Signal 72.5 dB
Distortion Ratio 1.1MHz Input Signal
THD Total Harmonic 100kHz First 5 Harmonics, Bipolar Mode –89 dB
Distortion 1.1MHz First 5 Harmonics, Bipolar Mode
100kHz First 5 Harmonics, Unipolar Mode –87 dB
1.1MHz First 5 Harmonics, Unipolar Mode –82 dB
SFDR Spurious Free 1.1MHz Input Signal in Bipolar Mode –93 dB
Dynamic Range 1.1MHz Input Signal in Unipolar Mode –84 dB
IMD Intermodulation ±1V 1.25MHz into A
Distortion 1.5V to 3.5V 1.25MHz into A
Code-to-Code V
Transition Noise
Full Power Bandwidth VIN = 4V
Full Linear Bandwidth S/(N + D) ≥ 68dB Bipolar Mode 5.0 MHz
Unipolar Mode 3.5 MHz
The ● denotes the specifications which apply over the full operating temperature range,
● 69 72.0 dB
● –89 –74.5 dB
+
, 1.2MHz into A
IN
= 4.096V, 1LSB = 1mV 0.18 LSB
REF
, D
OUT
= 2828
P-P
+
IN
(Note 18) 82 MHz
P-P
–
Bipolar Mode –84 dB
IN
, 1.2MHz into A
–
Unipolar Mode –84 dB
IN
RMS
UU U
INTERNAL REFERENCE CHARACTERISTICS
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
The ● denotes the specifications which apply over the
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
Output Voltage I
REF
V
Output Tempco 15 ppm/°C
REF
V
Line Regulation AVDD = 4.75V to 5.25V, V
REF
V
Output Resistance Load Current = 0.5mA 2 Ω
REF
V
Settling Time 2ms
REF
= 0 4.096 V
OUT
= 4.096V 1 LSB/V
REF
UU
DIGITAL I PUTS A D DIGITAL OUTPUTS
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
OZ
C
OZ
I
SOURCE
I
SINK
High Level Input Voltage VDD = 5.25V ● 2.4 V
Low Level Input Voltage VDD = 4.75V ● 0.8 V
Digital Input Current VIN = 0V to V
Digital Input Capacitance 5pF
High Level Output Voltage OVDD = 4.75V, I
OV
DD
OV
DD
Low Level Output Voltage VDD = 4.75V, I
V
= 4.75V, I
DD
Hi-Z Output Leakage D
Hi-Z Output Capacitance D
Output Short-Circuit Source Current V
Output Short-Circuit Sink Current V
OUT
OUT
V
OUT
OUT
V
OUT
OUT
DD
= 4.75V, I
= 3V, I
= 0V to V
= 0V, OVDD = 5V –40 mA
= 0V, OVDD = 3V –15 mA
= OVDD = 5V 40 mA
OUT
OUT
OUT
OUT
OUT
DD
The ● denotes the specifications which apply over the
● ±10 µA
= –10µA 4.7 V
= –200µA ● 4V
= –200µA ● 2.5 2.9 V
= 160µA 0.05 V
= 1.6mA ● 0.10 0.4 V
● ±10 µA
15 pF
3
Page 4
LTC1402
WU
POWER REQUIRE E TS
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
V
SS
I
DD
I
SS
PD Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 90 150 mW
Positive Supply Voltage 4.75 5.00 5.25 V
Negative Supply Voltage –5.25 –5.00 0 V
Positive Supply Current Active Mode ● 18 30 mA
Negative Supply Current Active, Sleep or Nap Modes with SCK Off ● 2 µA
The ● denotes the specifications which apply over the full operating temperature
Nap Mode
Sleep Mode 2 10 µA
● 35 mA
UW
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
t
THROUGHPUT
t
SCK
t
CONV
t
ACQ
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
8a
t
9
t
10
t
11
t
12
Maximum Sampling Frequency (Conversion Rate) ● 2.2 MHz
Minimum Sampling Period (Conversion + Acquisiton Period) ● 455 ns
Minimum Clock Period ● 28 10000 ns
Conversion Time Greater Than 13 Clocks + 6ns (Note 9) ● 375 ns
Acquisition Time Greater Than 2 Clocks – 6ns (Notes 9, 16) ● 51 ns
Minimum Positive or Negative SCK Pulse Width (Note 9) ● 3.8 6 ns
CONV to SCK Setup Time (Notes 9, 13) ● 7.3 12 ns
SCK After CONV (Note 9) ● 0ns
Minimum Positive or Negative CONV Pulse Width (Note 9) ● 3.5 5 ns
SCK to Sample Mode (Notes 9, 14) ● 914 ns
CONV to Hold Mode (Note 9) ● 3.4 5 ns
Minimum Delay Between Conversions (Note 9) ● 48 ns
Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 9, 15) ● 912 ns
Minimum Delay from SCK to Valid REFREADY (Notes 9, 15) ● 15 20 ns
SCK to Hi-Z at D
Previous D
REFREADY Bit Delay After Sleep-to-Wake Transition (Notes 9, 17) ● 10 ms
V
Settling Time After Sleep-to-Wake Transition (Notes 9, 17) ● 2ms
REF
OUT
Bit Remains Valid After SCK (Notes 9, 15) ● 47 ns
OUT
The ● denotes the specifications which apply over the full operating temperature
(Notes 9, 15) ● 11.4 16 ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together.
Note 3: When these pins are taken below V
clamped by internal diodes. This product can handle input currents greater
than 100mA below V
Note 4: When these pins are taken below VSS, they will be clamped by
internal diodes. This product can handle input currents greater than
100mA below VSS or greater than VDD. These pins are not clamped to VDD.
Note 5: V
specifications and V
= 5V, f
DD
or greater than VDD without latchup.
SS
= 2.2MHz, VSS = 0V for unipolar mode
SAMPLE
= –5V for bipolar specifications.
SS
or above VDD, they will be
SS
4
Note 6: Linearity, offset and full-scale specifications apply for a singleended A
bipolar mode with ±5V supplies.
Note 7: Integral linearity is defined as the deviation of a code from the
straight line passing through the actual endpoints of a transfer curve. The
deviation is measured from the center of quantization band.
Note 8: Bipolar offset is the offset measured from –0.5LSB when the input
flickers between 1000 0000 0000 and 0111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The analog input range is defined as the voltage difference
between A
with a single 5V supply if the absolute voltages of the inputs remain within
the single 5V supply voltage.
+
input with A
IN
+
and A
IN
–
grounded and using the internal reference in
IN
–
. The bipolar ±2.048V input range could be used
IN
Page 5
LTC1402
ELECTRICAL CHARACTERISTICS
Note 12: The absolute voltage at A
+
IN
Note 13: If less than 7.3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 14: Not the same as aperture delay. Aperture delay is smaller (2.6ns)
because the 0.8ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 15: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 16: The Sample mode is started by the 14th rising clock and it is
ended by the rising edge of convert. Because the start of Sample mode is
and A
–
must be within this range.
IN
slower than the end of Sample mode, the sample time is 6ns less than the
delay between the 14th SCK and CONV.
Note 17: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load. The
Sleep mode resets the REFREADY bit in the D
REFREADY bit goes high again 10ms after the V
sequence. The
OUT
has stopped slewing in
REF
wake up. This ensures valid REFREADY bit operation even with higher load
capacitances at V
REF
.
Note 18: The full power bandwidth is the frequency where the output code
swing drops to 2828LSBs with a 4V
input sine wave.
P-P
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = –5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C.
5 Harmonic THD, 2nd, 3rd and
ENOBs and SINAD
vs Input Frequency (Bipolar)
12
11
10
9
8
7
6
5
4
3
EFFECTIVE NUMBER OF BITS
2
1
f
= 2.22MHz
SAMPLE
0
4
10
5
10
INPUT FREQUENCY (Hz)
74
SIGNAL-TO-NOISE + DISTORTION (dB)
68
62
56
50
44
38
32
26
20
14
8
1401 G01
2
7
10
6
10
SFDR vs Input Frequency
(Bipolar)
0
10
f
SAMPLE
4
THD
SFDR
2ND
3RD
= 2.22MHz
5
10
INPUT FREQUENCY (Hz)
–10
–20
–30
–40
–50
–60
–70
–80
–90
THD, SFDR, 2ND 3RD (dB)
–100
–110
–120
(Bipolar Mode Plots Run with Dual ±5V Supplies.
SNR vs Input Frequency (Bipolar)
–2
f
= 2.22MHz
SAMPLE
–8
–14
–20
–26
–32
–38
SNR (dB)
–44
–50
–56
–62
–68
6
10
1401 G02
–74
7
10
4
10
5
10
INPUT FREQUENCY (Hz)
6
10
1401 G03
7
10
ENOBs and SINAD
vs Input Frequency (Unipolar)
12
11
10
9
8
7
6
5
4
3
EFFECTIVE NUMBER OF BITS
2
1
f
= 2.22MHz
SAMPLE
0
4
10
5
10
INPUT FREQUENCY (Hz)
5 Harmonic THD, 2nd, 3rd and
SFDR vs Input Frequency
(Unipolar)
74
SIGNAL-TO-NOISE + DISTORTION (dB)
68
62
56
50
44
38
32
26
20
14
8
1401 G04
2
7
10
6
10
0
10
f
SAMPLE
4
THD
SFDR
2ND
3RD
= 2.22MHz
5
10
INPUT FREQUENCY (Hz)
–10
–20
–30
–40
–50
–60
–70
–80
–90
THD, SFDR, 2ND 3RD (dB)
–100
–110
–120
6
10
1401 G05
7
10
SNR vs Input Frequency (Unipolar)
–2
f
= 2.22MHz
SAMPLE
–8
–14
–20
–26
–32
–38
SNR (dB)
–44
–50
–56
–62
–68
–74
4
10
5
10
INPUT FREQUENCY (Hz)
6
10
1401 G06
7
10
5
Page 6
LTC1402
LOAD CURRENT (mA)
0
4.040
INTERNAL REFERENCE VOLTAGE (V)
4.050
.4.060
4070
4.080
4.090
4.100
0.4 0.8 1.2 1.6
1402 G20
2.0
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = –5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C.
(Bipolar Mode Plots Run with Dual ±5V Supplies.
Sine Wave Spectrum Plot
(Bipolar) ±5V Supply
10
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
Sine Wave Spectrum Plot
(Unipolar) 5V Supply
10
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
2ND
0
4V
Power Bandwidth and
P-P
100mV
P-P
Bandwidth
5
0
–5
–10
AMPLITUDE (dB)
–15
–20
–25
0.1 10 100 1000
6
1
f
SAMPLE
f
= 109592.01Hz
SINE
2048 SAMPLES
4TH
2ND
FREQUENCY (MHz)
3RD
FREQUENCY (MHz)
5TH
3RD
0.55 1.11
f
SAMPLE
= 109592.01Hz
f
SINE
2048 SAMPLES
4TH
5TH
0.55 1.11
Small-Signal
FREQUENCY (MHz)
= 2222222.22Hz
6TH
1402 G09
= 2222222.22Hz
6TH
1402 G12
100mV
P-P
4V
P-P
1402 F07
Sine Wave Spectrum Plot
(Bipolar) Dual ±5V Supply
10
f
= 2222222.22Hz
SAMPLE
0
= 1131727.43Hz
f
SINE
–10
2048 SAMPLES
–20
–30
–40
–50
–60
2ND
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
4TH
6TH
0
0.55 1.11
FREQUENCY (MHz)
Sine Wave Spectrum Plot
(Unipolar) 5V Supply
10
f
= 2222222.22Hz
SAMPLE
0
= 1131727.43Hz
f
SINE
–10
2048 SAMPLES
–20
–30
–40
–50
–60
2ND 3RD
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
4TH
6TH
0
0.55 1.11
FREQUENCY (MHz)
PSRR vs Frequency
0
–10
–20
–30
–40
–50
REJECTION (dB)
–60
–70
–80
V
CC
V
SS
V
DD
DGND
0.1 10 100 1000
1
FREQUENCY (MHz)
5TH
5TH
3RD
1402 G11
1402 G08
1402 G18
IMD Spectrum Plot (Bipolar)
10
f
= 2352941.18Hz
SAMPLE
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
= 1250000Hz ±1V INTO A
f
SINEA
f
= 1199449Hz ±1V INTO A
SINEB
IMD = 83.9dB
2048 SAMPLES
– f
f
A
B
2f
B
fA – f
B
2f
A
0
FREQUENCY (MHz)
0.59 1.18
IMD Spectrum Plot (Unipolar)
10
f
= 2352941.18Hz
SAMPLE
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
= 1250000Hz INTO A
f
SINEA
1.5V TO 3.5V
= 1199449Hz INTO A
f
SINEB
1.5V TO 3.5V
IMD = –84.1dB
2048 SAMPLES
– f
f
A
B
2f
B
fA + f
B
2f
A
0
FREQUENCY (MHz)
2fA – fB, fA + 2f
0.59 1.18
Load Regulation for V
fA + 2f
+
IN
–
IN
2fA + f
3f
,
,
+
IN
–
IN
fA – 2f
A
3f
A
B
B
REF
B
3f
B
2fA – f
B
2fA + f
B
1402 G10
3f
B
B
fA – 2f
B
1402 G13
Page 7
LTC1402
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = –5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C.
(Bipolar Mode Plots Run with Dual ±5V Supplies.
Positive Power Supply Rejection
for V
4.095
4.090
4.085
4.080
4.075
4.070
INTERNAL REFERENCE VOLTAGE (mV)
4.065
REF
4.5
4.75 5.0 5.25 5.5 5.75
VDD (V)
Negative Power Supply Rejection
for V
4.095
4.090
4.085
4.080
4.075
4.070
INTERNAL REFERENCE VOLTAGE (mV)
4.065
REF
–5
–4 –3 –2 –1
VSS (V)
1402 G21
1402 G19
6.0
Differential Nonlinearity
vs Output Code (Bipolar)
1.00
f
= 2.2MHz
SAMPLE
0.75
0.50
0.25
0
DNL (LSB)
–0.25
–0.50
–0.75
–1.00
0
512
1024
1536
2048
CODE
2560
3072
3584
4096
1402 G15
Differential Nonlinearity
vs Output Code (Unipolar)
1.00
f
= 2.2MHz
SAMPLE
0.75
0.50
0.25
0
DNL (LSB)
–0.25
–0.50
–0.75
–1.00
0
512
0
1024
1536
2048
CODE
2560
3072
3584
4096
1402 G17
Integral Nonlinearity
vs Output Code (Bipolar)
1.00
f
= 2.2MHz
SAMPLE
0.75
0.50
0.25
0
INL (LSB)
–0.25
–0.50
–0.75
–1.00
512
0
1024
1536
Integral Nonlinearity
vs Output Code (Unipolar)
1.00
f
= 2.2MHz
SAMPLE
0.75
0.50
0.25
0
INL (LSB)
–0.25
–0.50
–0.75
–1.00
512
0
1024
1536
2048
CODE
2048
CODE
2560
2560
3072
3072
3584
3584
4096
1402 G14
4096
1402 G16
UUU
PIN FUNCTIONS
AVDD (Pin 1): 5V Analog Power Supply. Bypass to AGND1
and solid analog ground plane with 10µF ceramic (or 10µF
tantalum in parallel with 0.1µF ceramic).
AGND1 (Pin 2): Analog Ground. Tie to solid analog ground
plane. The analog ground plane should be solid and have
no cuts near the LTC1402.
+
A
(Pin 3): Positive Analog Signal Input. 0V to 4.096V in
IN
unipolar mode and ±2.048V in bipolar mode when A
grounded. Both of these ranges operate fully differentially
with respect to A
–
. (Note 3)
IN
IN
–
is
–
A
(Pin 4): Negative Analog Signal Input. Can be grounded
IN
or driven differentially with A
+
. Identical to A
IN
+
, except
IN
that it inverts the input signal. (Note 3)
V
(Pin 5): 4.096V Reference Voltage Output. Bypass to
REF
AGND1 and solid analog ground plane with 10µF ceramic
(or 10µF tantalum in parallel with 0.1µF ceramic).
AGND2 (Pin 6): Analog Ground Return for the Reference
and Internal CDAC. AGND2 could be overdriven externally
above ground. Tie to solid analog ground plane.
7
Page 8
LTC1402
UUU
PIN FUNCTIONS
GAIN (Pin 7): Tie to AGND2 to set the reference voltage to
4.096V or tie to V
to set the reference voltage to 2.048V.
REF
(Note 4)
BIP/UNI (Pin 8): Tie to logic low to set the input range to
unipolar mode or tie to logic high to set the input range to
bipolar mode. (Note 4)
OGND (Pin 9): Output Ground for the Output Driver. This
pin can be tied to the digital ground of the system. All other
ground pins should be tied to the analog ground plane.
D
(Pin 10): Three-State Data Output. (Note 3) Each
OUT
output data word represents the analog input at the start
of the previous conversion.
OVDD (Pin 11): Output Data Driver Power. Tie to VDD when
driving 5V logic. Tie to 3V when driving 3V logic.
DVDD (Pin 12): Digital Power for Internal Logic. Bypass to
DGND with 10µF ceramic (or 10µF tantalum in parallel
with 0.1µF ceramic).
DGND (Pin 13): Digital Ground for Internal Logic. Tie to
solid analog ground plane.
VSS (Pin 14): Negative Supply Voltage. Bypass to solid
analog ground plane with 10µF ceramic (or 10µF tantalum
in parallel with 0.1µF ceramic) or tie directly to the solid
analog ground plane for single supply use. Must be set
more negative than either A
IN
+
or A
–
. Set to 0V or –5V.
IN
SCK (Pin 15): External Clock. Advances the conversion
process and sequences the output data at D
OUT
on the
rising edge. Responds to 5V or 3V CMOS and to TTL levels.
(Note 4). One or more pulses wake from Nap or Sleep.
CONV (Pin 16): Holds the input analog signal and starts
the conversion on the rising edge. Responds to 5V or 3V
CMOS and to TTL levels. (Note 4). Two pulses with SCK in
fixed high or fixed low state start Nap Mode. Four pulses
with SCK in fixed high or fixed low state start Sleep mode.
BLOCK DIAGRA
3
+
A
IN
4
–
A
IN
2.048V REF
64k
7
GAIN
5
V
REF
DGND
6
2
13
AGND2
AGND1
W
+
–
64k
INTERNAL
CLOCK
C
SAMPLE
C
SAMPLE
12-BIT CAPACITIVE DAC
SUCCESSIVE APPROXIMATION
REGISTER
CONTROL LOGIC
16 15
SCKCONV
ZEROING SWITCHES
+
COMPREF AMP
–
OUTPUT
DRIVER
1402 BD
1
AV
DD
12
DV
DD
14
V
SS
8
BIP/UNI
10
D
OUT
11
OV
DD
9
OGND
8
Page 9
LTC1402
UW
W
TI I G DIAGRA S
t
2
t
3
SCK
CONV
INTERNAL
S/H STATUS
D
OUT
t
t
SAMPLE SAMPLEHOLD HOLD
123456789101112131415 16 1 2
4
6
t
8a
Hi-Z Hi-Z
REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
D
OUT
REF D11 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D10
REFRDY BIT + 12-BIT DATA WORD
t
CONV
t
THROUGHPUT
Nap Mode and Sleep Mode Waveforms
t
7
t
5
t
ACQ
t
8
REF
1402 TD01
SCK
CONV
NAP
SLEEP
V
REF
REFRDY
t
1
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS A BIT IN THE D
D
SCK
OUT
SCK to D
V
IH
t
8
t
10
V
OH
V
OL
OUT
Delay
SCK
D
OUT
t
1
t
12
t
11
WORD.
OUT
V
IH
t
9
1402 TD03
90%
10%
1402 TD02
9
Page 10
LTC1402
U
WUU
APPLICATIONS INFORMATION
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1402 are easy to
drive. The inputs may be driven differentially or as a singleended input (i.e., the A
–
A
inputs are sampled at the same instant. Any unwanted
IN
signal that is common to both inputs will be reduced by the
common mode rejection of the sample-and-hold circuit.
The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a
small leakage current. If the source impedance of the
driving circuit is low, then the LTC1402 inputs can be
driven directly. As source impedance increases, so will
acquisition time (see Figure 1). For minimum acquisition
time with high source impedance, a buffer amplifier must
be used. The only requirement is that the amplifier driving
the analog input(s) must settle after the small current
spike before the next conversion starts (settling time must
be 50ns for full throughput rate).
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
ACQUISITION TIME (ns)
300
200
100
0
10 1k 10k
Figure 1. Acquisition Time vs Source Resistance
in Bipolar and Unipolar Modes
CHOOSING AN INPUT AMPLIFIER
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (< 100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100Ω. The
–
input is grounded). The A
IN
±5V
5V
100
SOURCE RESISTANCE (Ω)
1402 F01
100k
IN
+
and
second requirement is that the closed-loop bandwidth
must be greater than 40MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps
are used, more time for settling can be provided by
increasing the time between conversions. The best choice
for an op amp to drive the LTC1402 will depend on the
application. Generally, applications fall into two categories: AC applications where dynamic specifications are
most critical, and time domain applications where DC
accuracy and settling time are most critical. The following
list is a summary of the op amps that are suitable for
driving the LTC1402. More detailed information is available in the Linear Technology Databooks and on the
LinearViewTM CD-ROM.
LT®1206: 60MHz Current Feedback Amplifier with Shutdown Pin (Amplifier Draws 200µA While in Shutdown).
±5V to ±15V supplies. Distortion is –80dB to 1MHz
(2V
into 30Ω). Good for AC applications. Dual avail-
P-P
able with shutdown as LT1207. Output swings to within
2VBE of the supply rails.
LT1223: 100MHz Video Current Feedback Amplifier. 6mA
supply current. ±5V to ±15V supplies. Low distortion at
frequencies above 400kHz. Low noise. Good for AC applications.
LT1227: 140MHz Video Current Feedback Amplifier. 10mA
supply current; has shutdown pin (draws 120µA while in
shutdown). ±5V to ±15V supplies. Lowest distortion
(– 92dB) at frequencies above 400kHz. Low noise. Best for
AC applications.
LT1229/LT1230: Dual and Quad 100MHz Current Feedback Amplifiers. ±2V to ±15V supplies. Low noise. Good
AC specifications, 6mA supply current each amplifier.
LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current. ±5V to ±15V supplies. Good AC and DC
specifications. 70ns settling to 0.5LSB.
LT1363: 70MHz, 1000V/µs Op Amps. 6.3mA supply cur-
rent. Good AC and DC specifications. 60ns settling to
0.5LSB.
LT1364/LT1365: Dual and Quad 70MHz, 1000V/µs Op
Amps. 6.3mA supply current per amplifier. 60ns settling
to 0.5LSB.
LinearView is a trademark of Linear Technology Corporation.
10
Page 11
LTC1402
U
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APPLICATIONS INFORMATION
LT1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high A
520ns settling to 0.5LSB for a 4V swing. THD and noise
are –93dB to 40kHz and below 1LSB to 320kHz (AV = 1,
2V
into 1kΩ, VS = 5V), making the part excellent for AC
P-P
applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631.
LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high A
400ns settling to 0.5LSB for a 4V swing. It is suitable for
applications with a single 5V supply. THD and noise are
–93dB to 40kHz and below 1LSB to 800kHz (AV = 1,
2V
into 1kΩ, VS = 5V), making the part excellent for AC
P-P
applications where rail-to-rail performance is desired.
Quad version is available as LT1633.
LT1813: Dual 100MHz 750V/µs 3mA Voltage Feedback
Amplifier. 5V to ±5V supplies. Distortion is –86dB to
100kHz and – 77dB to 1MHz with ±5V supplies (2V
500Ω). Excellent part for fast AC applications with ±5V
supplies.
INPUT FILTERING AND SOURCE IMPEDANCE
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1402 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 80MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 2 shows a 68pF
capacitor from A
+
to ground and a 51Ω source resistor
IN
to limit the input bandwidth to 47MHz. The 68pF capacitor
also acts as a charge reservoir for the input sample-andhold and isolates the ADC input from sampling glitchsensitive circuitry.
High quality capacitors and resistors should be used since
these components can add distortion. NPO and silver mica
type dielectric capacitors have excellent linearity.
Carbon surface mount resistors can generate distortion
from self heating and from damage that may occur during
soldering. Metal film surface mount resistors are much
, 500µV offset and
VOL
, 1.5mV offset and
VOL
P-P
into
ANALOG
INPUT
51Ω
68pF
10µF
3
4
2
5
6
7
+
A
IN
–
A
IN
AGND1
LTC1402
V
REF
AGND2
GAIN
1402 F02
Figure 2. RC Input Filter
less susceptible to both problems. When high amplitude
unwanted signals are close in frequency to the desired signal
frequency, a multiple pole filter is required. Figure 3 shows
a simple implementation using an LTC1560-1 fifth order
elliptic continuous-time 1MHz filter.
–5V
1
2
V
IN
LTC1560-1
3
4
0.1µF
8
7
6
5
5V
0.1µF
Figure 3. 1MHz Fifth Order Elliptic Lowpass Filter
10µF
3
4
2
5
6
7
+
A
IN
–
A
IN
AGND1
LTC1402
V
REF
AGND2
GAIN
1402 F03
BIPOLAR AND UNIPOLAR INPUT RANGES
The ±2V bipolar input range of the LTC1402 is optimized
for low noise and low distortion. Most op amps also
perform best over this same range, allowing direct coupling to the analog inputs and eliminating the need for
special translation circuitry. The inputs of the LTC1402
may also be driven fully differential in bipolar mode with
a single supply. Each input should not swing more than
2V
individually to get the best performance from single
P-P
supply amplifiers.
The 0V to 4V range is ideal for single ended input use with
single supply applications.
11
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LTC1402
U
WUU
APPLICATIONS INFORMATION
INTERNAL REFERENCE
The LTC1402 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmed to 2.048V. It is connected internally to a reference
amplifier, see Figure 4. The reference amplifier amplifies
the voltage at the V
internal reference voltage of 4.096V. This provides buffering for the high speed capacitive DAC. The reference
amplifier output V
capacitor to ground. The reference amplifier is stable with
capacitors of 1µF or greater. For the best noise perfor-
mance, a 10µF ceramic or a 10µF tantalum in parallel with
a 0.1µF ceramic is recommended.
The V
pin can be driven with an external reference as
REF
shown in Figure 5a. The GAIN pin (Pin 7) is tied to the
positive supply to disable the internal reference buffer.
A DAC may also be used to drive V
Figure 6. This is useful in applications where the peak
input signal amplitude may vary. The input span of the
pin by 2 to create the required
REF
, (Pin 5) must be bypassed with a
REF
as shown in
REF
ADC can then be adjusted to match the peak input signal,
maximizing the signal-to-noise ratio. The filtering of the
internal LTC1402 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of
5ms should be allowed after a reference adjustment.
DIFFERENTIAL INPUTS
The LTC1402 has a unique differential sample-and-hold
circuit that allows inputs from –2.5V to 5V. The ADC will
always convert the difference of A
IN
+
– A
–
independent
IN
of the common mode voltage. The common mode rejection holds up at extremely high frequencies, see Figure 7.
The only requirement is that both inputs not exceed
–2.5V or 5V. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the
common mode voltage. However, the bipolar zero error
(BZE) will vary. The change in BZE is typically less than
0.1% of the common mode voltage. Figure 5b shows the
use of bipolar mode with single 5V supply.
4.096V
5
LTC1402
V
REF
REFERENCE
AMP
2.048V
+
–
10µF
7
6
GAIN
AGND2
64k
64k
Figure 4. LTC1402 Reference Circuit
5V
V
IN
LT1019-2.5
V
OUT
ANALOG INPUT
10µF
5V
3
4
5
6
7
BANGAP
REFERENCE
+
A
IN
–
A
IN
LTC1402
V
REF
AGND2
GAIN
1402 F04
1402 F04a
5V
V
IN
LT1019-2.5
2.5V ±2.048V
10µF
V
10µF
3
4
5
6
7
+
A
IN
–
A
IN
V
REF
AGND2
GAIN
LTC1402
IN
Figure 5b. Bipolar Mode with Single Supply
3
+
A
IN
ANALOG INPUT
LTC1450
5V
10µF
4
5
6
7
–
A
IN
V
REF
AGND2
GAIN
LTC1402
BIP
V
SS
1402 F04a
1402 F06
14
Figure 5a. Using the LT1019-2.5 as an External Reference
12
Figure 6. Driving V
with a DAC
REF
Page 13
LTC1402
U
WUU
APPLICATIONS INFORMATION
0
–10
–20
–30
–40
AMPLITUDE (dB)
–50
–60
–70
0.1 10 100 1000
Figure 7. CMRR vs Input Frequency
FULL-SCALE AND OFFSET ADJUSTMENT
Figure 8 shows the ideal input/output characteristics for
the LTC1402 in bipolar mode and unipolar mode. Figure 9a
shows the components required for full-scale error adjustment. Figure 9b includes the components for offset
and full-scale adjustment.
Adjustment in Bipolar Mode with Pin 8 Held High
The code transitions occur midway between successive
integer LSB values (i.e., – FS + 0.5LSB, – FS + 1.5LSB, –FS
+ 2.5LSB,...FS – 2.5LSB, FS – 1.5LSB). The output at D
is two’s complement binary with 1LSB = FS – (–FS)/4096
= 4.096V/4096 = 1.0mV. In applications where absolute
accuracy is important, offset and full-scale errors can be
adjusted to zero. Offset error must be adjusted before fullscale error. In Figure 9b, zero offset is achieved by adjusting the offset applied to the A
error, apply – 0.5mV (i.e., –0.5LSB) to A
offset at the A
flickers between 0000 0000 0000 and 1111 1111 1111.
For full-scale adjustment in Figures 9a and 9b, apply an
input voltage of 2.0465V (FS – 1.5LSB) to A
R5 until the output code flickers between 0111 1111 1110
and 0111 1111 1111.
Adjustment in Unipolar Mode with Pin 8 Held Low
1
FREQUENCY (MHz)
–
IN
–
input using R8 until the output code
IN
1402 F07
input. For zero offset
+
and adjust the
IN
+
and adjust
IN
OUT
011...111
011...110
011...101
BIPOLAR OUTPUT CODE
100...010
100...001
100...000
FS – 1LSB–(FS – 1LSB)
INPUT VOLTAGE (V)
111...111
111...110
111...101
000...010
000...001
000...000
1402 F08
Figure 8. LTC1402 Transfer Characteristic
ANALOG INPUT
0V TO 4.096V
OR ±2.048V
500Ω
R1
51Ω
R2
R3
39k
51Ω
R4
470k
R5
10µF
+
A
3
IN
S/H
–
4
A
IN
2.048V
5
V
REF
REFERENCE
AMP
64k
GAIN
7
AGND26
64k
LTC1402
BANGAP
REFERENCE
Figure 9a. Full-Scale Adjustment Circuit with ±10LSB Range
5V
R7
R4
470k
R6
24k
R2
24k
10µF
+
A
3
IN
S/H
–
A
4
IN
2.048V
V
5
REF
REFERENCE
AMP
64k
GAIN
7
AGND26
64k
LTC1402
BANGAP
REFERENCE
ANALOG INPUT
0V TO 4.096V
OR ±2.048V
OFFSET
R8
ADJ
10k
FULL-SCALE
ADJ
R1
51Ω
R3
51Ω
5V
7.5k
R5
500Ω
UNIPOLAR OUTPUT CODE
1402 F09a
The code transitions occur midway between successive
integer LSB values (i.e., –FS + 0.5LSB, – FS + 1.5LSB,
– FS + 2.5LSB,...FS – 2.5LSB, FS – 1.5LSB). The output at
1402 F09b
Figure 9b. Offset and Full-Scale Adjustment
Circuits with ±10LSB Range
13
Page 14
LTC1402
U
WUU
APPLICATIONS INFORMATION
D
is binary with 1LSB = FS/4096 = 4.096V/4096 =
OUT
1.0mV. In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero.
Offset error must be adjusted before full-scale error. In
Figure 9b, zero offset is achieved by adjusting the offset
applied to the A
– 0.5mV (i.e., –0.5LSB) to A
–
A
input using R8 until the output code flickers between
IN
0000 0000 0000 and 0000 0000 0001. For full-scale adjustment in Figures 9a and 9b, apply an input voltage of
2.0465V (FS – 1.5LSBs) to A
output code flickers between 1111 1111 1110 and 1111
1111 1111.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best
performance from the LTC1402, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 2 (AGND1), Pin 6 (AGND2), Pin 13 (DGND) and all
other analog grounds should be connected directly to an
analog ground plane. Pin 9 (OGND) should be connected
near Pin13 (DGND), where the analog ground plane ties to
the logic system ground. The V
the DVDD bypass capacitor should also be connected to
this analog ground plane, see Figure 10. No other digital
grounds should be connected to this analog ground plane.
–
input. For zero offset error apply
IN
+
and adjust the offset at the
IN
+
and adjust R5 until the
IN
bypass capacitor and
REF
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC and
the foil width for these tracks should be as wide as
possible. The traces connecting the pins and bypass
capacitors must be kept short and should be made as wide
as possible.
The LTC1402 has differential inputs to minimize noise
coupling. Common mode noise on the A
will be rejected by the input CMRR. The A
used as a ground sense for the A
+
input; the LTC1402 will
IN
IN
IN
+
and A
–
hold and convert the difference voltage between A
–
A
. The leads to A
IN
+
(Pin 3) and A
IN
–
(Pin 4) should be
IN
–
leads
IN
input can be
+
and
IN
kept as short as possible. In applications where this is not
possible, the A
IN
+
and A
–
traces should be run side-by-
IN
side to cancel noise coupling.
SUPPLY BYPASSING
High quality, low series resistance 10µF ceramic bypass
capacitors should be used at the VDD and V
REF
pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively, 10µF tantalum capaci-
tors in parallel with 0.1µF ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
POWER-DOWN MODES
Upon power-up, the LTC1402 is initialized to the active
state and is ready for conversion. The Nap and Sleep Mode
waveforms show the power-down modes for the LTC1402.
14
ANALOG
INPUT
CIRCUITRY
12
OV
3
+
A
IN
–
A
IN
REF
4
+
–
AGND2 AGND1V
6145
ANALOG GROUND PLANE
Figure 10. Power Supply Grounding Practice
V
SS
LTC1402
10µF
AVDDDV
2
DGND
DD
11213 9
10µF10µF
DD
D
OUT
OGND
3V TO 5V
10
DIGITAL
SYSTEM
SYSTEM
GROUND
1402 F10
Page 15
LTC1402
U
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APPLICATIONS INFORMATION
The SCK and CONV inputs control the power-down modes
(see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC1402
in Nap mode and the power drain drops from 90mW to
15mW. The internal reference remains powered in Nap
mode. One or more rising edges at SCK wake up the
LTC1402 for service very quickly, and CONV can start an
accurate conversion within a clock cycle. Four rising edges
at CONV, without any intervening rising edges at SCK, put
the LTC1402 in Sleep mode and the power drain drops
from 90mW to 10µW. One or more rising edges at SCK
wake up the LTC1402 for operation. The internal reference
(V
) takes 2ms to slew and settle with a 10µF load, and
REF
the REFREADY bit in the D
10ms to go high after the reference output Pin 5 (V
finished slewing. Figure 11 shows the power consumption
versus the conversion rate. Note that, for slower conversion rates, the Nap and Sleep modes can be used for substantial reductions in power consumption.
100
SUPPLY CURRENT (mA)
0.01
0.001
Figure 11. Power Consumption vs Sample Rate
in Normal Mode, Nap Mode and Sleep Mode
VDD CURRENT
DUAL ±5V
VDD CURRENT
10
1
0.1
0.01 0.1 1
SINGLE 5V
VDD CURRENT
SLEEP MODE
VSS CURRENT
SINGLE 5V
SAMPLE RATE (MHz)
DIGITAL INTERFACE
The LTC1402 has a 3-wire SPI (Serial Protocol Interface)
interface. The SCK and CONV inputs and D
implement this interface. The SCK and CONV inputs are TTL
compatible and also accept swings from 3V or 5V logic. The
amplitude of D
can easily produce 5V logic or 3V logic
OUT
swings by tying the independent output supply Pin 11
(OVDD) to the same supply as system logic. A detailed
description of the three serial port signals follows.
stream takes an additional
OUT
REF
VDD CURRENT
NAP MODE
VSS CURRENT
DUAL ±5V
10
1402 F11
output
OUT
) has
CONV at Pin 16
The rising edge of CONV starts a conversion but subsequent rising edges at CONV, during the following 14 SCK
cycles of conversion, are ignored by the LTC1402. The
duty cycle of CONV can be arbitrarily chosen to be used as
a frame sync signal for the processor serial port. A simple
approach to generate CONV is to create a pulse that is one
SCK wide to drive the LTC1402 and then buffer this signal
with the appropriate number of inverters to drive the frame
sync input of the processor serial port. It is good practice
to drive the LTC1402 CONV input first to avoid digital noise
interference during the sample-to-hold transition triggered
by CONV at the start of conversion. Another point to consider is the level of jitter in the CONV signal if the input
signals have fast transients or sinewaves. Some processors can be programmed to generate a convenient frame
sync pulse at their serial port, but often this signal is derived from a jittery processor phase locked loop clock
multiplier. This is true even if a low jitter crystal clock is the
reference for the processor clock multiplier.
SCK at Pin 15
The rising edge of SCK advances the conversion process
and also udpates each bit in the D
data stream. After
OUT
CONV rises, the second rising edge of SCK sends out the
REFREADY bit. Subsequent edges send out the 12 data
bits, with the MSB sent first. A simple approach is to
generate SCK to drive the LTC1402 and then buffer this
signal with the appropriate number of inverters to drive the
serial clock input of the processor serial port. The rising
edge of SCK is guaranteed to coincide with stable data at
D
. It is good practice to drive the LTC1402 SCK input
OUT
first to avoid digital noise interference during the internal
bit comparison decision by the internal high speed comparator. Unlike the CONV input, the SCK input is not
sensitive to jitter because the input signal is already
sampled and held constant.
D
at Pin 10
OUT
Upon power-up, the D
the high impedance state. The D
impedance until a new conversion is started. D
output is automatically reset to
OUT
output remains in high
OUT
OUT
sends
out 13 bits in the output data stream after the second rising
edge of SCK after the start of conversion with the rising
15
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APPLICATIONS INFORMATION
edge of CONV. Please note the delay specification from
SCK to a valid D
by the next rising edge of SCK.
DIGITAL JITTER AT CONV (PIN 16)
In high speed applications, where high amplitude sinewaves
above 100kHz are sampled, the CONV signal must have as
little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement easily. The challenge is to generate a CONV
signal from this crystal clock without jitter corruption from
other digital circuits in the system. A clock divider and any
gates in the signal path from the crystal clock to the CONV
input should not share the same integrated circuit with
other parts of the system. As shown in the interface circuit
examples, the LTC1402’s SCK and CONV inputs should be
driven first with digital buffers used to drive the serial port
interface. Also note that the master clock in the DSP may
already be corrupted with jitter, even if it comes directly
from the DSP crystal. Another problem with high speed
processor clocks is that they often use a low cost, low
OUT
. D
is always guaranteed to be valid
OUT
speed crystal (i.e., 10MHz) to generated a fast, but jittery,
phase locked loop system clock (i.e., 40MHz). The jitter, in
these PLL-generated high speed clocks, can be several
nanoseconds. Note that if you choose to use the frame
sync signal generated by the DSP port, this signal will have
the same jitter of the DSP’s master clock.
SERIAL TO PARALLEL CONVERSION
You can take advantage of the serial interface of the LTC1402
in a parallel data system to minimize bus wiring congestion in the PC board layout. Figure 12 shows an example
of this interface. It is best to send the SCK and CONV
signals to the LTC1402, and then bus them together across
the board to avoid excessive time skew among the three
signals. It is usually not necessary to buffer D
, if the PC
OUT
track is not too long. Buffering SCK and CONV prevents
jitter from corrupting these signals. The relative phase
between SCK and CONV affects the position of the parallel
word at the output of the 74HC595. The position of the
output word in Figure 12 assumes 16 clocks between each
CONV rising edge, and the CONV pulse is one clock wide.
LTC1402
OV
CONV
SCK
D
OUT
OGND
5V
11
DD
74ACT04
16
15
10
9
CONV
CLK
3-WIRE SERIAL
INTERFACE LINK
12
11
14
13
12
11
14
13
10
SRCLR
RCK
SRCK
74HC595
SER
G
10
SRCLR
RCK
SRCK
74HC595
SER
G
QH′
QH′
15
QA
1
D0
QB
2
D1
QC
3
D2
QD
4
D3
QE
5
D4
QF
6
D5
QG
7
D6
QH
9
15
QA
D7
1
QB
D8
2
QC
D9
3
QD
D10
4
QE
D11
5
QF
REFRDY
6
QG
7
QH
9
1402 F12
16
Figure 12. Serial to Parallel Interface
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HARDWARE INTERFACE TO TMS320C54x
The LTC1402 is a serial output ADC whose interface has
been designed for high speed buffered serial ports in fast
digital signal processors (DSPs). Figure 13 shows an
example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial data
can be collected in two alternating 1kB segments, in real
time, at the full 2.2Msps conversion rate of the LTC1402.
The DSP assembly code sets frame sync mode at the BFSR
pin to accept an external positive going pulse, and the
serial clock at the BCLKR pin to accept an external positive
11
OV
DD
16
CONV
LTC1402
SCK
D
OUT
OGND
15
10
9
CONV
CLK
3-WIRE SERIAL
INTERFACE LINK
edge clock. Buffers near the LTC1402 may be added to
drive long tracks to the DSP to prevent corruption of the
signal to LTC1402. This configuration is adequate to
traverse a typical system board, but source resistors at the
buffer outputs, and termination resistors at the DSP may
be needed to match the characteristic impedance of very
long transmission lines. If you need to terminate the D
OUT
transmission line, buffer it first with one or two 74ACxx
gates. The TTL threshold inputs of the DSP port respond
properly to the 2.5V swing of the terminated transmission
lines. The OVDD supply output driver supply voltage can be
driven directly from the DSP.
5V
V
CC
BFSR
TMS320C54x
BCLKR
REF B11 B10
BDR
1402 F13
Figure 13. DSP Serial Interface to TMS320C54x
; ***************************************************************************
; Files: BSP2KB.ASM ->
; 2kbyte collection into DSKPlus TMS320C542 with Serial Port interface to LTC1402
; first element at 1024, last element at 1023, two middle elements at 2047 and 0000
; bipolar mode
; ***************************************************************************
.width 160
.length 110
.title “sineb0 BSP in auto buffer mode”
.mmregs
.setsect “.text”, 0x500,0 ;Set address of executable
.setsect “vectors”, 0x180,0 ;Set address of incoming 1402 data
.setsect “buffer”, 0x800,0 ;Set address of BSP buffer for clearing
.setsect “result”, 0x1800,0 ;Set address of result for clearing
.text ;.text marks start of code
start: ;Make sure /PWRDWN is low at J1-9 to turn off AC01 adc
tim=#0fh
prd=#0fh
tcr = #10h ; stop timer
tspc = #0h ; stop TDM serial port to AC01
pmst = #01a0h ; set up iptr. Processor Mode STatus register
sp = #0700h ; init stack pointer.
dp = #0 ; data page
ar2 = #1800h ; pointer to computed receive buffer.
ar3 = #0800h ; pointer to Buffered Serial Port receive buffer
ar4 = #0h ; reset record counter
call sineinit ; Double clutch the initialization to insure a proper
sinepeek: ; insert debugger break here to view results
call sineinit ; reset. The external frame sync must occur 2.5 clocks
wait goto wait
; or more after the port comes out of reset.
17
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; ————————Buffered Receive Interrupt Routine —————————
breceive:
ifr = #10h ; clear interrupt flags
TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer
if (NTC) goto bufull ; if this still the first half get next half
bspce = #(2023h + 08000h) ; turn on halt for second half (bspce(bit15))
return_enable
; ———————mask and shift input data after 2k buffer is full——bufull:
b = *ar3+ << -2 ; load acc b with BSP buffer and shift right 2
b = #00FFFh & b ; mask out the REF bit and the 3 other tristate bits
b = #00800h ^ b ; invert BIPOLAR MSB. Comment this line in UNIPOLAR mode
*ar2+ = data(#0bh) ; store B to out buffer and advance AR2 pointer
TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h
if (TC) goto start ; restart if out buffer is at 1fffh
goto bufull
; —————————dummy bsend return————————————
bsend return_enable ;this is a dummy return to define bsend
; ——————————— end ISR ——————————————
;initialize buffered serial port
**********************************************************************
* BSP initialization code for the ‘C54x DSKplus *
* for use with 1402 in standard mode *
* BSPC and SPC are the same in the ‘C542 *
**********************************************************************
ON .set 1
OFF .set !ON
YES .set 1
NO .set !YES
BIT_8 .set 2
BIT_10 .set 1
BIT_12 .set 3
BIT_16 .set 0
GO .set 0x80
**********************************************************************
* This is an example of how to initialize the Buffered Serial Port (BSP).
* The BSP is initialized to require an external CLK and FSX for
* operation. The data format is 16-bits, burst mode, with autobuffering
* enabled.
*
*
*****************************************************************************************************
*Timing at BSP pins in DSKPLUS TMS320c542 board with inverters at BCLKR and BFSR. *
*BFSR Pin JP1-20 ~\___/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\___/~~~~~~~~~~*
*BCLKR Pin JP1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/ *
*BDR Pin JP1-26 -_—_—<REF-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>—_—_—<REF-B11- *
*CLKIN Pin JP5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~ *
* *
*A 2 place right shift is needed to right justify the input data. *
*The REF bit is also be masked in this example *
*****************************************************************************************************
*
Loopback .set NO ;(digital looback mode?) DLB bit
Format .set BIT_16 ;(Data format? 16,12,10,8) FO bit
IntSync .set NO ;(internal Frame syncs generated?) TXM bit
IntCLK .set NO ;(internal clks generated?) MCM bit
BurstMode .set YES ;(if BurstMode=NO, then Continuous) FSM bit
CLKDIV .set 3 ;(3=default value, 1/4 CLOCKOUT)
PCM_Mode .set NO ;(Turn on PCM mode?)
FS_polarity .set NO ;(change polarity)YES=^^^\_/^^^, NO=___/^\___
CLK_polarity .set YES ;(change polarity)for BCLKR YES=_/^, NO=~\_
Frame_ignore .set !YES ;(inverted !YES -ignores frame)
XMTautobuf .set NO ;(transmit autobuffering)
RCVautobuf .set YES ;(receive autobuffering)
XMThalt .set NO ;(transmit buff halt if XMT buff is full)
RCVhalt .set NO ;(receive buff halt if RCV buff is full)
XMTbufAddr .set 0x800 ;(address of transmit buffer)
XMTbufSize .set 0x000 ;(length of transmit buffer)
;in vector table below
18
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APPLICATIONS INFORMATION
RCVbufAddr .set 0x800 ;(address of receive buffer)
RCVbufSize .set 0x800 ;(length of receive buffer)works up to 800
*
*
*
**********************************************************************
.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync <<5)) ,SPCval
.eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format & 1)<<7)|(Frame_ignore<<8)|(PCM_Mode<<9)), SPCEval
.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)), SPCEval
sineinit:
bspc = #SPCval ; places buffered serial port in reset
ifr = #10h ; clear interrupt flags
imr = #210h ; Enable HPINT,enable BRINT0
intm = 0 ; all unmasked interrupts are enabled.
bspce = #SPCEval ; programs BSPCE and ABU
axr = #XMTbufAddr ; initializes transmit buffer start address
bkx = #XMTbufSize ; initializes transmit buffer size
arr = #RCVbufAddr ; initializes receive buffer start address
bkr = #RCVbufSize ; initializes receive buffer size
bspc = #(SPCval | GO) ; bring buffered serial port out of reset
return ;for transmit and receive because GO=0xC0
.space 16*32 ;clear a chunk at the end to mark the end
;======================================================================
;
; VECTORS
;
;======================================================================
.sect “vectors” ;The vectors start here
;get BSP vectors
; ***************************************************************************
; Vector Table for the ‘C54x DSKplus
; BSP vectors and Debugger vectors
; TDM vectors just return
; ***************************************************************************
; The vectors in this table can be configured for processing external and
; internal software interrupts. The DSKplus debugger uses four interrupt
; vectors. These are RESET, TRAP2, INT2, and HPIINT.
; * DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER *
;
; All other vector locations are free to use. When programming always be sure
; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and
; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the
; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.
;
;
;
.mmregs
reset goto #80h ;00; RESET * DO NOT MODIFY IF USING DEBUGGER *
nop
nop
nmi return_enable ;04; non-maskable external interrupt
nop
nop
nop
trap2 goto #88h ;08; trap2 * DO NOT MODIFY IF USING DEBUGGER *
nop
nop
.space 52*16 ;0C-3F: vectors for software interrupts 18-30
int0 return_enable ;40; external interrupt int0
nop
nop
nop
int1 return_enable ;44; external interrupt int1
nop
nop
nop
int2 return_enable ;48; external interrupt int2
nop
nop
nop
19
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LTC1402
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APPLICATIONS INFORMATION
tint return_enable ;4C; internal timer interrupt
nop
nop
nop
brint goto breceive ;50; BSP receive interrupt
nop
nop
nop
bxint goto bsend ;54; BSP transmit interrupt
nop
nop
nop
trint return_enable ;58; TDM receive interrupt
nop
nop
nop
U
± 0.004
Dimensions in inches (millimeters) unless otherwise noted.
16-Lead Plastic SSOP (Narrow 0.150)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
PACKAGE DESCRIPTION
0.015
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0.016 – 0.050
(0.406 – 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0° – 8° TYP
txint return_enable ;5C; TDM transmit interrupt
nop
nop
int3 return_enable ;60; external interrupt int3
nop
nop
nop
hpiint dgoto #0e4h ;64; HPIint * DO NOT MODIFY IF USING
DEBUGGER *
nop
nop
.space 24*16 ;68-7F; reserved area
.sect “buffer” ;Set address of BSP buffer for clearing
.space 16*0x800
.sect “result” ;Set address of result for clearing
.space 16*0x800
.end
GN Package
(LTC DWG # 05-08-1641)
0.0250
(0.635)
BSC
0.004 – 0.0098
(0.102 – 0.249)
0.229 – 0.244
(5.817 – 6.198)
16
15
12
0.189 – 0.196*
(4.801 – 4.978)
14
12 11 10
13
5
4
3
678
9
0.150 – 0.157**
(3.810 – 3.988)
GN16 (SSOP) 1098
0.009
(0.229)
REF
RELATED PARTS
PART NUMBER RESOLUTION SPEED COMMENTS
16-Bit
LTC1604 16 333ksps ±2.5V Input Range, ±5V Supply
LTC1605 16 100ksps ±10V Input Range, Single 5V Supply
14-Bit
LTC1414 14 2.2Msps 175mW, 80dB SINAD and 95dB SFDR
LTC1419 14 800ksps 150mW, 81.5dB SINAD and 95dB SFDR
LTC1416 14 400ksps 75mW, Low Power with Excellent AC Specs
LTC1418 14 200ksps 15mW, Single 5V, Serial/Parallel I/O
12-Bit
LTC1412 12 3Msps 150mW, 72dB SINAD and 82dB SFDR
LTC1410 12 1.25Msps 150mW, 71.5dB SINAD and 84dB THD
LTC1415 12 1.25Msps 55mW, Single 5V Supply
LTC1409 12 800ksps 80mW, 71.5dB SINAD and 84dB THD
LTC1404 12 600ksps High Speed Serial I/O in SO-8 Package
LTC1400 12 400ksps High Speed Serial I/O in SO-8 Package
Linear Technology Corporation
20
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1999
1402i LT/TP 1099 • PRINTED IN USA
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