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FEATURES
■
Software-Selectable Cable Termination for:
RS232 (V.28)
RS423 (V.10)
RS422 (V.11)
RS485
RS449
EIA530
EIA530-A
V.35
V.36
X.21
■
Outputs Won’t Load the Line with Power Off
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APPLICATIONS
LTC1344A
Software-Selectable
Cable Terminator
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DESCRIPTION
The LTC®1344A features six software-selectable
multiprotocol cable terminators. Each terminator can be
configured as an RS422 (V.11) 100Ω minimum differential load, V.35 T-network load or an open circuit for use
with RS232 (V.28) or RS423 (V.10) transceivers that
provide their own termination. When combined with the
LTC1543 and LTC1544, the LTC1344A forms a complete
software-selectable multiprotocol serial port. A data bus
latch feature allows sharing of the select lines between
multiple interface ports.
The LTC1344A is similar to the LTC1344 except for a
difference in the Mode Selection table.
The LTC1344A is available in a 24-lead SSOP.
■
Data Networking
■
CSU and DSU
■
Data Routers
TYPICAL APPLICATION
DTE or DCE Multiprotocol Serial Interface with DB-25 Connector
LL
Daisy-Chained Control Outputs
D4
R3
LTC1544
R2 R1R4
D3
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DTRDSR DCDCTS
D2 D1
RTS
, LTC and LT are registered trademarks of Linear Technology Corporation.
RXCRXD
LTC1543
R1R3
R2
D3
TXDSCTETXC
D2
D1
LTC1344A
CTS B
LL A (141)
DSR A (109)
DSR B
CTS A (106)
DCD A (107)
DCD B
DTR A (108)
DTR B
RTS A (105)
RTS B
SHIELD (101)
DB-25 CONNECTOR
RXD B
SG (102)
RXC A (115)
RXC B
RXD A (104)
TXC A (114)
TXC B
SCTE A (113)
SCTE B
TXD A (103)
TXD B
21424111512179314192062322513 81018 7 16
1344A TA01
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LTC1344A
WW
W
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ABSOLUTE MAXIMUM RA TIN GS
(Note 1)
Positive Supply Voltage (VCC)................................... 7V
Negative Supply Voltage (VEE)........................... –13.2V
Input Voltage
(Logic Inputs).................... (VEE – 0.3V) to (VCC + 0.3V)
Input Voltage (Load Inputs).................................. ±18V
Power Dissipation.............................................. 600mW
Operating Temperature Range
LTC1344AC ............................................ 0°C to 70°C
LTC1344AI ......................................... –40°C to 85°C
Storage Temperature Range................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
/
PACKAGE
M0
V
EE
R1C
R1B
R1A
R2A
R2B
R2C
R3A
R3B
R3C
GND
T
JMAX
Consult factory for Military grade parts.
O
RDER I FOR ATIO
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
G PACKAGE
24-LEAD PLASTIC SSOP
= 150°C, θJA = 100°C/W
24
23
22
21
20
19
18
17
16
15
14
13
M1
M2
DCE/DTE
LATCH
R6B
R6A
R5A
R5B
R4A
R4B
V
CC
GND
WU
ORDER PART
NUMBER
LTC1344ACG
LTC1344AIG
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ELECTRICAL CHARACTERISTICS
VCC = 5V ±5%, VEE = –5V ±5%, TA = T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supplies
I
CC
Terminator Pins
R
V.35
R
V.11
I
LEAK
Logic Inputs
V
IH
V
IL
I
IN
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Supply Current All Digital Pins = GND or V
Differential Mode Impedance All Loads (Figure 1), –2V ≤ VCM ≤ 2V (Commercial) ● 90 104 110 Ω
Common Mode Impedance All Loads (Figure 2), –2V ≤ V
Differential Mode Impedance All Loads (Figure 1), VCM = 0V (Commercial) ● 100 104 110 Ω
High Impedance Leakage Current All Loads, –7V ≤ VCM ≤ 7V ● ±1 ±50 µA
Input High Voltage All Logic Input Pins ● 2V
Input Low Voltage All Logic Input Pins ● 0.8 V
Input Current All Logic Input Pins ● ±10 µA
MIN
to T
(Notes 2, 3) unless otherwise noted.
MAX
CC
≤ 2V (Commercial) ● 135 153 165 Ω
CM
All Loads (Figure 1), –2V ≤ VCM ≤ 2V (Industrial) ● 90 104 115 Ω
All Loads (Figure 2), –2V ≤ V
All Loads (Figure 1), –7V ≤ V
All Loads (Figure 1), VCM = 0V (Industrial) ● 95 104 115 Ω
All Loads (Figure 1), –7V ≤ V
≤ 2V (Industrial) ● 130 153 170 Ω
CM
≤ 7V (Commercial) 100 104 Ω
CM
≤ 7V (Industrial) 100 104 Ω
CM
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are reference to ground unless otherwise
specified.
Note 3: All typicals are given at V
● 0.4 1.0 mA
= 5V, VEE = –5V, TA = 25°C.
CC
2
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VCC VOLTAGE (V)
103
DIFFERENTIAL MODE IMPEDANCE (Ω)
104
105
1344 G03
4.6 4.8 5.0 5.2 5.4
TA = 25°C
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TYPICAL PERFORMANCE CHARACTERISTICS
LTC1344A
V.11 or V.35 Differential Mode
Impedance vs Temperature
120
115
110
105
DIFFERENTIAL MODE IMPEDANCE (Ω)
100
–40
–20 0 40
20
TEMPERATURE (°C)
V.11 or V.35 Differential Mode
Impedance vs Negative Supply
Voltage (VEE)
105
TA = 25°C
VCM = –7V
= –2V
V
CM
VCM = 0V
V
= 7V
CM
60 80 100
1344 G01
V.11 or V.35 Differential Mode
Impedance vs Common Mode
Voltage
108
106
104
102
DIFFERENTIAL MODE IMPEDANCE (Ω)
100
–8
–6 –4 –2 0 2 4 8
COMMON MODE VOLTAGE (V)
V.35 Common Mode Impedance
vs Temperature
165
160
VCM = –2V
V.11 or V.35 Differential Mode
Impedance vs Supply Voltage
(VCC)
TA = 25°C
6
1344 G02
V.35 Common Mode Impedance
vs Common Mode Voltage
158
TA = 25°C
156
104
DIFFERENTIAL MODE IMPEDANCE (Ω)
103
–5.4 –5.2 –5.0 –4.8 –4.6
V.35 Common Mode Impedance
vs Supply Voltage (VCC)
153
TA = 25°C
152
COMMON MODE IMPEDANCE (Ω)
151
4.6 4.8 5.0 5.2 5.4
VEE VOLTAGE (V)
VCC VOLTAGE (V)
1344 G04
1344 G07
155
150
COMMON MODE IMPEDANCE (Ω)
145
–20 0 40
–40
TEMPERATURE (°C)
VCM = 0V
VCM = 2V
20
V.35 Common Mode Inpedance
vs Negative Supply Voltage (VEE)
154
TA = 25°C
153
152
151
COMMON MODE IMPEDANCE (Ω)
150
–5.4
–5.2
–5.0
VEE VOLTAGE (V)
60 80 100
1344 G05
–4.8
–4.6
1344 G08
154
152
COMMON MODE IMPEDANCE (Ω)
150
–2
–1
COMMON MODE VOLTAGE (V)
0
Supply Current vs Temperature
500
420
340
SUPPLY CURRENT (µA)
260
180
–20 0 40 60 80 100
–40
20
TEMPERATURE (°C)
1
2
1344 G06
1344 G09
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LTC1344A
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PIN FUNCTIONS
M0 (Pin 1): TTL Level Mode Select Input. The data on M0
is latched when LATCH is high.
VEE (Pin 2): Negative Supply Voltage Input. Can connect
directly to the LTC1543 VEE pin. Connect a 1µF capacitor
to ground.
R1C (Pin 3): Load 1 Center Tap.
R1B (Pin 4): Load 1 Node B.
R1A (Pin 5): Load 1 Node A.
R2A (Pin 6): Load 2 Node A.
R2B (Pin 7): Load 2 Node B.
R2C (Pin 8): Load 2 Center Tap.
R3A (Pin 9): Load 3 Node A.
R2B (Pin 10): Load 2 Node B.
R3C (Pin 11): Load 3 Center Tap.
GND (Pin 12): Ground Connection for Load 1 to Load 3.
GND (Pin 13): Ground Connection for Load 4 to Load 6.
VCC (Pin 14): Positive Supply Input. 4.75V ≤ VCC ≤ 5.25V.
R4B (Pin 15): Load 4 Node B.
R4A (Pin 16): Load 4 Node A.
R5B (Pin 17): Load 5 Node B.
R5A (Pin 18): Load 5 Node A.
R6A (Pin 19): Load 6 Node A.
R6B (Pin 20): Load 6 Node B.
LATCH (Pin 21): TTL Level Logic Signal Latch Input. When
LATCH is low the input buffers on M0, M1, M2 and DCE/
DTE are transparent. When LATCH is high the logic pins
are latched into their respective input buffers. The data
latch allows the select lines to be shared between multiple
I/O ports.
DCE/DTE (Pin 22): TTL Level Mode Select Input. DCE
mode is selected when high and DTE mode when low. The
data on DCE/DTE is latched when LATCH is high.
M2 (Pin 23): TTL Level Mode Select Input 1. The data on
M2 is latched when LATCH is high.
M1 (Pin 24): TTL Level Mode Select Input 2. The data on
M1 is latched when LATCH is high.
TEST CIRCUITS
A
S1
ON
Ω
B
V
±7V OR ±2V
R1
51.5Ω
R2
51.5Ω
S2
OFF
C
LTC1344A
R3
124Ω
1344 F01
C
R1
51.5Ω
S1
ON
A, B
Ω
V
Figure 2. V.35 Common Mode Impedance MeasurementFigure 1. Differential V.11 or V.35 Impedance Measurement
S2
ON
R2
51.5Ω
±2V
LTC1344A
R3
124Ω
1344 F02
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LTC1344A
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ODE SELECTIO
LTC1344A
MODE NAME DCE/DTE M2 M1 M0 R1 R2 R3 R4 R5 R6
V.10/RS423 X 000ZZZZZZ
RS530A 0 001ZZZV.11 V.11 V.11
1 001ZZZZV.11 V.11
RS530 0 010ZZZV.11 V.11 V.11
1 010ZZZZV.11 V.11
X.21 0 011ZZZV.11 V.11 V.11
1 011ZZZZV.11 V.11
V.35 0 1 0 0 V.35 V.35 Z V.35 V.35 V.35
1 1 0 0 V.35 V.35 V.35 Z V.35 V.35
RS449/V.36 0 101ZZZV.11 V.11 V.11
1 101ZZZZV.11 V.11
V.28/RS232 X 110ZZZZZZ
No Cable X 1 1 1 V.11 V.11 V.11 V.11 V.11 V.11
X = don’t care, 0 = logic low, 1 = logic high
C C C
A
B
ON
R1
51.5Ω
R2
51.5Ω
S2
OFF
S1
LTC1344A LTC1344A LTC1344A
R3
124Ω
V.11 Mode V.35 Mode High-Z Mode
A
B
ON
R1
51.5Ω
S1
R2
51.5Ω
ON
S2
R3
124Ω
A
B
OFF
R1
51.5Ω
S2
S1
OFF
R2
51.5Ω
R3
124Ω
1344 F03
Figure 3. LTC1344A Modes
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LTC1344A
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APPLICATIONS INFORMATION
Multiprotocol Cable Termination
One of the most difficult problems facing the designer of
a multiprotocol serial interface is how to allow the transmitters and receivers for different electrical standards to
share connector pins. In some cases the transmitters and
receivers for each interface standard can be simply tied
together and the appropriate circuitry enabled. But the
biggest problem still remains: how to switch the various
cable termination required by the different standards.
Traditional implementations have included switching resistors with expensive relays or requiring the user to
change termination modules every time the interface
standard has changed. Custom cables have been used
with the termination in the cable head. Another method
uses separate termination built on the board, and a custom
cable which routes the signals to the appropriate termination. Switching the termination using FETs is difficult
because the FETs must remain off even though the signal
voltage is beyond the supply voltage for the FET drivers or
the power is off.
The LTC1344A solves the cable termination switching
problem via software control. The LTC1344A provides
termination for the V.10 (RS423), V.11 (RS422), V.28
(RS232) and V.35 electrical protocols.
BALANCED
INTERCONNECTING
CABLE
A
CC
Figure 4. Typical V.10 Interface
A
LTC1344A
51.5Ω
S1
OFFS2OFF
51.5Ω
B
C
Z
–3.25mA
Figure 5. V.10 Interface Using the LTC1344A
124Ω
–10V
–3V
A
I
Z
LOADGENERATOR
CABLE
TERMINATION
'
'
RECEIVER
Z
Z
3V 10V
V.10
RECEIVER
1344 F04
3.25mA
V
Z
1344 F05
V.10 (RS423) Termination
A typical V.10 unbalanced interface is shown in Figure 4.
A V.10 single-ended generator output A with ground C is
connected to a differential receiver with input A' connected to A and input C' connected to the signal return
ground C. Usually no cable termination is required for V.10
interfaces but the receiver inputs must be compliant with
the impedance curve shown in Figure 5.
In V.10 mode, both switches S1 and S2 are turned off so
the only cable termination is the input impedance of the
V.10 receiver.
6
V.11 (RS422) Termination
A typical V.11 balanced interface is shown in Figure 6. A
V.11 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.11 interface requires a differential termination at the
receiver end that has a minimum value of 100Ω. The
receiver inputs must also be compliant with the impedance curve shown in Figure 7.
In V.11 mode, switch S1 is turned on and S2 is turned off
so the cable is terminated with a 103Ω impedance.
Page 7
LTC1344A
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WUU
APPLICATIONS INFORMATION
BALANCED
INTERCONNECTING
CABLE
A
BB
C
A
'
'
C
'
Figure 6. Typical V.11 Interface
A
LTC1344A
124Ω
I
Z
S1
ONS2OFF
B
C
51.5Ω
51.5Ω
LOADGENERATOR
CABLE
TERMINATION
100Ω
MIN
Z
Z
RECEIVER
V.11
RECEIVER
1344 F06
3.25mA
BALANCED
INTERCONNECTING
CABLE
A
CC'
A
'
LOADGENERATOR
CABLE
TERMINATION
RECEIVER
1344 F08
Figure 8. Typical V.28 Interface
A
V.28
RECEIVER
5k
1344 F09
S1
OFFS2OFF
B
C
51.5Ω
51.5Ω
LTC1344A
124Ω
Figure 9. V.28 Interface Using the LTC1344A
Z
–10V
–3.25mA
–3V
3V 10V
V
Z
1344 F07
Figure 7. V.11 Interface Using the LTC1344A
V.28 (RS232) Termination
A typical V.28 unbalanced interface is shown in Figure 8.
A V.28 single-ended generator output A with ground C is
connected to a single-ended receiver with input A' connected to A, ground C' connected via the signal return
ground to C. The V.28 standard requires a 5k terminating
resistor to ground which is included in almost all compliant receivers as shown in Figure 9. Because the termination is included in the receiver, both switches S1 and S2 in
the LTC1344A are turned off.
V.35 Termination
A typical V.35 balanced interface is shown in Figure 10. A
V.35 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.35 interface requires a T-network termination at the
receiver end and the generator end. In V.35 mode both
switches S1 and S2 in the LTC1344A are turned on as
shown in Figure 11.
The differential impedance measured at the connector
must be 100Ω ±10Ω and the impedance between shorted
terminals A' and B' to ground C' must be 150Ω ±15Ω. The
input impedance of the V.35 receiver is connected in
parallel with the T-network inside the LTC1344A, which
could cause the overall impedance to fail the specification
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LTC1344A
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WUU
APPLICATIONS INFORMATION
BALANCED
INTERCONNECTING
CABLE
TERMINATION
A
'
B
'
C
'
50Ω
50Ω
A
125Ω
B
C
Figure 10. Typical V.35 Interface
A
LTC1344A
51.5Ω
S1
S2
ON
51.5Ω
B
C
Z
–0.8mA
–7V
ON
124Ω
–3V
I
Z
3V 12V
Figure 11. V.35 Receiver Using the LTC1344A
CABLE
125Ω
Z
Z
LOADGENERATOR
50Ω
50Ω
V.35
RECEIVER
RECEIVER
1mA
V
Z
1344 F11
1344 F10
A
V.35
DRIVER
LTC1344A
124Ω
51.5Ω
S2
ON
51.5Ω
C1
100pF
S1
ON
B
C
1344 F12
Figure 12. V.35 Driver Using the LTC1344A
The generator differential impedance must be 50Ω to
150Ω and the impedance between shorted terminals A
and B to ground C must be 150Ω ±15Ω. For the generator
termination, switches S1 and S2 are both on and the top
side of the center resistor is brought out to a pin so it can
be bypassed with an external capacitor to reduce common
mode noise as shown in Figure 12.
Any mismatch in the driver rise and fall times or skew in
the driver propagation delays will force current through
the center termination resistor to ground causing a high
frequency common mode spike on the A and B terminals.
The common mode spike can cause EMI problems that are
reduced by capacitor C1 which shunts much of the common mode energy to ground rather than down the cable.
The LATCH Pin
if the receiver input impedance is on the low side. All of
Linear Technology’s V.35 receivers meet the RS485 input
impedance specification as shown in Figure 11, which
insures compliance with the V.35 specification when used
with the LTC1344A.
8
The LATCH pin (21) allows the select lines (M0, M1, M2
and DCE/DTE) to be shared with multiple LTC1344As,
each with its own LATCH signal. When the LATCH pin is
held low the select line input buffers are transparent. When
the LATCH pin is pulled high, the select line input buffers
latch the state of the Select pins so that changes on the
select lines are ignored until LATCH is pulled low again. If
the latch feature is not used, the LATCH pin should be tied
to ground.
Page 9
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TYPICAL APPLICATIONS N
Controller Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
V
CC
5V
1
DTE_LL/DCE_TM
DTE_TXD/DCE_RXD
DTE_SCTE/DCE_RXC
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
DTE_TM/DCE_LL
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
DTE_RL/DCE_RL
DCE/DTE
C3
1µF
LB
C9, 1µF
C10
1µF
M2
M1
M0
1µF
C1
C5
1µF
100k
2
CHARGE
4
PUMP
3
8
LTC1343
5
D1
6
D2
7
D3
9
D4
10
12
13
R1
14
R2
15
R3
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423SET
R1
40
GND
LB
V
CC
1
V
CC
2
V
DD
3
D1
4
D2
5
D3
LTC1544
6
R1
7
R2
8
R3
10
R4
9
D4
11
M0
12
M1
13
M2
14
DCE/DTE
DCE
23
GND
INVERT
LTC1344A
C6
100pFC7100pF
14
V
C11
1µF
CC
2
V
EE
C12
1µF
44
43
42
41
39
38
37
36
35
34
33
32
31
30
29
28
27
26
21
19
M2
18
M1
17
M0
24
EC
28
V
EE
27
26
25
24
23
22
21
20
19
18
17
16
15
C13
1µF
C2
1µF
C4
+
3.3µF
V
CC
NC
C8
100pF
3 8 11 12 13
5
16109764
15 18 17 19 20 22
LTC1344A
LATCH
DCE/DTEM2M1
23 24
M0
1
21
18
2
14
24
11
15
12
17
9
3
16
25
7
1
4
19
20
23
8
10
6
22
5
13
21
DTE DCE
LL A
TXD A
TXD B
SCTE A
SCTE B
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
TM A LL A
SG
SHIELD
DB-25
CONNECTOR
RTS A
RTS B
DTR A
DTR B
DCD A
DCD B
DSR A
DSR B
CTS A
CTS B
RL A
1344A TA04
TM A
RXD A
RXD B
RXC A
RXC B
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
CTS A
CTS B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
RL A
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Page 10
LTC1344A
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TYPICAL APPLICATIONS N
Cable Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
V
CC
5V
3
DTE_TXD/DCE_RXD
DTE_SCTE/DCE_RXC
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
C10
1µF
C3
1µF
C9, 1µF
1µF
1
C1
C5
1µF
NC
V
CC
NC
10
11
12
13
14
11
12
13
14
2
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
CHARGE
PUMP
LTC1543
D1
D2
D3
M0
M1
M2
DCE/DTE
V
CC
V
DD
D1
D2
D3
LTC1544
D4
M0
M1
M2
DCE/DTE
R1
R2
R3
GND
R1
R2
R3
R4
INVERT
C6
100pFC7100pF
3 8 11 12 13
V
C11
1µF
CC
2
V
EE
5
C12
1µF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
V
EE
27
26
25
24
23
22
21
20
19
18
17
1610
15
C13
1µF
C2
1µF
C4
+
3.3µF
CABLE WIRING FOR MODE SELECTION
MODE PIN 18 PIN 21
V.35 PIN 7 PIN 7
RS449, V.36 NC PIN 7
RS232 PIN 7 NC
NC
C8
100pF
CABLE WIRING FOR
DTE/DCE SELECTION
MODE PIN 25
DTE PIN 7
DCE NC
16109764
15 18 17 19 20 22
LTC1344A
LATCH
DCE/DTEM2M1
23 24141
V
CC
21
M0
DTE
TXD A
TXD B
SCTE A
SCTE B
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
SG
SHIELD
DB-25
CONNECTOR
DCE/DTE
M1
M0
RTS A
RTS B
DTR A
DTR B
DCD A
DCD B
DSR A
DSR B
CTS A
CTS B
DCE
RXD A
RXD B
RXC A
RXC B
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
CTS A
CTS B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
2
14
24
11
15
12
17
9
3
16
7
1
25
21
18
4
19
20
23
8
10
6
22
5
13
10
1344A TA05
Page 11
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
G Package
24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.318 – 0.328*
(8.07 – 8.33)
2122 18 17 16 15 14
19202324
13
LTC1344A
0.301 – 0.311
(7.65 – 7.90)
0.205 – 0.212**
(5.20 – 5.38)
° – 8°
0
0.005 – 0.009
(0.13 – 0.22)
*
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.022 – 0.037
(0.55 – 0.95)
12345678 9 10 11 12
0.0256
(0.65)
BSC
0.010 – 0.015
(0.25 – 0.38)
0.068 – 0.078
(1.73 – 1.99)
0.002 – 0.008
(0.05 – 0.21)
G24 SSOP 0595
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
Page 12
LTC1344A
TYPICAL APPLICATIO
U
Figure 13 shows a typical application for the LTC1344A
using the LTC1543 mixed mode transceiver chip to generate the clock and data signals for a serial interface. The
LTC1344A VEE supply is generated from the LTC1543
charge pump and the select lines M0, M1, M2 and
100pF
3
1
24
23
22
21
C1
1µF
M0
M1
M2
DCE/DTE
LATCH
11
12
13
14
5
6
7
8
9
10
V
V
CC
EE
14
2
426
LTC1543
M0
M1
M2
DCE/DTE
LTC1344A
24
23
22
21
20
19
18
17
16
15
C2
3.3µF
5
4
M0
M1
M2
DCE/DTE
DCE/DTE are shared by both chips. Each driver output and
receiver input is connected to one of the LTC1344A
termination ports. Each electrical protocol can then be
chosen using the digital select lines.
100pF
100pF
11
8
6
12 13
9
7
10
18
15
16
19
17
20
DTE DCE
+
+
RXD
TXD
TXD–RXD
SCTE+RXC
SCTE–RXC
TXC+TXC
TXC–TXC
RXC+SCTE
RXC–SCTE
RXD+TXD
RXD–TXD
–
+
–
+
–
+
–
+
–
1344 F13
Figure 13. Typical Application Using the LTC1344A
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1334 Single Supply RS232/RS485 Transceiver 2 RS485 Dr/Rx or 4 RS232 Dr/Rx Pairs
LTC1343 Multiprotocol Serial Transceiver Software Selectable Mulitprotocol Interface
LTC1345 Single Supply V.35 Transceiver 3 Dr/3 Rx for Data and CLK Signals
LTC1346A Dual Supply V.35 Transceiver 3 Dr/3 Rx for Data and CLK Signals
LTC1543 Multiprotocol Serial Transceiver Software-Selectable Transceiver for Data and CLK Signals
LTC1544 Multiprotocol Serial Transceiver Software-Selectable Transceiver for Control Signals
1344af, sn1344a LT/TP 0898 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1998
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
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