Datasheet LTC1343 Datasheet (Linear Technology)

FEATURES

■

Software-Selectable Transceiver Supports:
RS232, RS449, EIA-530, EIA-530-A, V.35, V.36,
X.21

■

NET1 and NET2 Compliant

■

Software-Selectable Cable Termination Using
the LTC1344

■

4-Driver/4-Receiver Configuration Provides a
Complete 2-Chip DTE or DCE Port

■

Operates from Single 5V Supply

■

Internal Echoed Clock and Loop-Back Logic

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APPLICATIO S

■

Data Networking

■

CSU and DSU

■

Data Routers

, LTC and LT are registered trademarks of Linear Technology Corporation.

LTC1343

Software-Selectable

Multiprotocol Transceiver

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DESCRIPTIO

The LTC®1343 is a 4-driver/4-receiver multiprotocol trans­ceiver that operates from a single 5V supply. Two LTC1343s
form the core of a complete software-selectable DTE or DCE
interface port that supports the RS232, RS449, EIA-530,
EIA-530-A, V.35, V.36 or X.21 protocols. Cable termination
may be implemented using the LTC1344 software-selectable
cable termination chip or by using existing discrete designs.

The LTC1343 runs from a single 5V supply using an internal
charge pump that requires only five space saving surface mount
capacitors. The mode pins are latched internally to allow sharing
of the select lines between multiple interface ports.

Software-selectable echoed clock and loop-back modes help
eliminate the need for external glue logic between the serial
controller and line transceiver. The part features a flow­through architecture to simplify EMI shielding and is available
in the 44-lead SSOP surface mount package.

TYPICAL APPLICATIO

LTC1343

DSR A (107)

DSR B

R1

DCD A (109)

DCD B

DTR B

R3R4R2

CTS A (106)

CTS B

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DTE Multiprotocol Serial Interface with DB-25 Connector

RTSDTRDSR DCDCTS RL

LTC1343

D1

D2

D3D4

DTR A (108)

RTS B

RL A (140)

RTS A (105)

TM A (142)

SGND (102)

SHIELD (101)

R3R4R2

RXD A (104)

RXD B

RXC A (115)

RXC B

R1

TXC A (114)

TXC B

D3D4

SCTE B

TXDSCTETXCRXCRXDTM

D2

TXD A (103)

TXD B

SCTE A (113)

21424111512179314192023622 810513 21 7 1625

LL

D1

18

LL A (141)

LTC1344

DB-25 CONNECTOR

1343 TA01

1

LTC1343

WW

W

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ABSOLUTE MAXIMUM RATINGS

(Note 1)

Supply Voltage ....................................................... 6.5V

Input Voltage

Transmitters ........................... –0.3V to (VCC + 0.3V)

Receivers............................................... –18V to 18V

Logic Pins .............................. –0.3V to (VCC + 0.3V)

Output Voltage

Transmitters ................. (VEE – 0.3V) to (VDD + 0.3V)

Receivers................................ –0.3V to (VCC + 0.3V)

Logic Pins .............................. –0.3V to (VCC + 0.3V)

VEE........................................................ –10V to 0.3V

VDD....................................................... –0.3V to 10V

Short-Circuit Duration

Transmitter Output ..................................... Indefinite

Receiver Output.......................................... Indefinite

VEE.................................................................. 30 sec

Operating Temperature Range

LTC1343C .............................................. 0°C to 70°C

LTC1343I........................................... –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

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PACKAGE/ORDER INFORMATION

V
C1

PWRV

C1

V

D4EN

INVERT

R1EN

R1O
R2O
R3O
R4O

CTRL/CLK

DCE/DTE

LATCH

TOP VIEW

1

DD

+

2

CHARGE PUMP

3

CC

–

4
5

D1

6

D2

7

D3

8

CC

9

D4

10
11
12
13
14
15
16
17

M0

18

M1

19

M2

20
21
22

T

JMAX

D1

D2

D3

D4

R1

R2

R3

R4

GW PACKAGE

44-LEAD PLASTIC SSOP

= 150°C, θJA = 65°C/W

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

+

C2

–

C2
V

EE

PGND
GND
D1 A
D2 A
D2 B
D3 A
D3 B
D4 A
D4 B
R1 A
R1 B
R2 A
R2 B
R3 A
R3 B
R4 A
423 SET
EC
LB

ORDER PART

NUMBER

LTC1343CGW
LTC1343IGW

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Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. V

A

= 5V (Notes 2, 3)

CC

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supplies

I

CC

VCC Supply Current (DCE Mode, V.10 Mode, No Load 12 mA
All Digital Pins = GND or V

) V.10 Mode, Full Load ● 80 150 mA

CC

RS530, RS530-A, X.21 Modes, No Load 80 mA
RS530, RS530-A, X.21 Modes, Full Load

● 160 200 mA

V.35 Mode, No Load 20 mA
V.35 Mode, Full Load

● 115 160 mA

V.28 Mode, No Load 20 mA
V.28 Mode, Full Load
No-Cable Mode

P

D

Internal Power Dissipation (DCE Mode, V.10 Mode, Full Load 400 mW
All Digital Pins = GND or V

) RS530, RS530-A, X.21 Modes, Full Load 680 mW

CC

● 30 90 mA

● 0.05 1 mA

V.35 Mode, Full Load 500 mW
V.28 Mode, Full Load 150 mW

+

V

–

V

Positive Charge Pump Output Voltage Any Mode, No Load ● 8.5 9.1 V

V.28 Mode, with Load

● 8.0 7.0 V

Negative Charge Pump Output Voltage V.28 Mode, Full Load ● –7.8 – 8.4 V

V.35 Mode, Full Load ● – 5.8 –6.7 V
–40°C ≤ T

≤ 85°C ● – 5.5 V

A

V.10, RS530, RS530A, X.21 Modes, Full Load ● –5.0 – 6.1 V
–40°C ≤ TA ≤ 85°C ● – 4.8 V

2

LTC1343

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. V

A

= 5V (Notes 2, 3)

CC

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t

r

Supply Rise Time No-Cable Mode or Power-Up to Turn On 2 ms

Logic Inputs and Outputs

V
V
I

IN

V
V
I

OSR

I

OZR

IH

IL

OH

OL

Logic Input High Voltage ● 2V
Logic Input Low Voltage ● 0.8 V
Logic Input Current ● ±10 µA
Output High Voltage IO = –4mA ● 3 4.5 V
Output Low Voltage IO = 4mA ● 0.3 0.8 V
Output Short-Circuit Current 0V ≤ VO ≤ VCC, 0°C ≤ TA ≤ 70°C ● –60 60 mA

≤ VCC, –40°C ≤ TA ≤ 85°C ● –70 70 mA

0V ≤ V

O

Three-State Output Current M0 = M1 = M2 = VCC, 0V ≤ VO ≤ V

CC

±1 µA

V.11 Driver

V

OD

Differential Output Voltage Open Circuit, RL = 1.95k ● ±6V

= 50Ω (Figure 1), ● ±2V

R

L

VOD at 50Ω > 1/2 VOD at RL = 1.95k

∆V

OD

Change in Magnitude of Differential RL = 50Ω (Figure 1) ● 0.2 V
Output Voltage

V
∆V

OC

OC

Common Mode Output Voltage RL = 50Ω (Figure 1) ● 3.0 V
Change in Magnitude of Common Mode RL = 50Ω (Figure 1) ● 0.2 V

Output Voltage

I

SS

Short-Circuit Current –0.25V ≤ VO ≤ 0.25V, Power Off or ±150 mA

No-Cable Mode or Driver Disabled

I

OZ

Output Leakage Current –0.25V ≤ VO ≤ 0.25V, Power Off or ● ±0.01 ±100 µA

No-Cable Mode or Driver Disabled

tr, t

f

t

PLH

t

PHL

∆t Input to Output Difference, t

t

SKEW

Rise or Fall Time (Figures 2, 6) ● 41325 ns
Input to Output (Figures 2, 6), 0°C ≤ TA ≤ 70°C ● 25 55 80 ns

(Figures 2, 6), –40°C ≤ T

≤ 85°C ● 25 55 90 ns

A

Input to Output (Figures 2, 6), 0°C ≤ TA ≤ 70°C ● 25 55 80 ns

≤ 85°C ● 25 55 90 ns

A

≤ 70°C ● 0317 ns

A

≤ 85°C ● 0325 ns

A

PLH

(Figures 2, 6), –40°C ≤ T

– t

 (Figures 2, 6), 0°C ≤ T

PHL

(Figures 2, 6), –40°C ≤ T

Output to Output Skew (Figures 2, 6) 3 ns

V.11 Receiver

V

∆V

I

IN

R
tr, t
t

PLH

TH

TH

IN

f

Input Threshold Voltage –7V ≤ VCM ≤ 7V, 0°C ≤ TA ≤ 70°C ● – 0.2 0.2 V

–7V ≤ V

≤ 7V, –40°C ≤ TA ≤ 85°C ● – 0.3 0.3 V

CM

Input Hysteresis –7V ≤ VCM ≤ 7V, 0°C ≤ TA ≤ 70°C ● 15 40 mV

–7V ≤ V
Input Current (A, B) –10V ≤ V
Input Impedance –10V ≤ V

≤ 7V, –40°C ≤ TA ≤ 85°C ● 60 mV

CM

≤ 10V ● ±0.50 mA

A, B

≤ 10V ● 20 32 kΩ

A, B

Rise or Fall Time (Figures 2, 7) 15 ns
Input to Output (Figures 2, 7), CTRL = GND, 0°C ≤ TA ≤ 70°C ● 35 80 115 ns

CTRL = V

, 0°C ≤ TA ≤ 70°C 400 ns

CC

(Figures 2, 7), CTRL = GND, –40°C ≤ TA ≤ 85°C ● 25 80 130 ns

CTRL = V

, –40°C ≤ TA ≤ 85°C 400 ns

CC

3

LTC1343

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. V

A

= 5V (Notes 2, 3)

CC

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t

PHL

Input to Output (Figures 2, 7), CTRL = GND, 0°C ≤ TA ≤ 70°C ● 35 80 115 ns

CTRL = V

, 0°C ≤ TA ≤ 70°C 400 ns

CC

(Figures 2, 7), CTRL = GND, –40°C ≤ TA ≤ 85°C ● 25 80 130 ns

, –40°C ≤ TA ≤ 85°C 400 ns

CC

≤ 70°C ● 0517 ns

A

≤ 85°C ● 0525 ns

A

∆t Input to Output Difference, t

PLH

CTRL = V

– t

 (Figures 2, 7), 0°C ≤ T

PHL

(Figures 2, 7), –40°C ≤ T

V.35 Driver

V

I

OH

I

OL

I

OZ

tr, t
t

PLH

OD

f

Differential Output Voltage Open Circuit 6.0 V

With Load, –4.0V ≤ V
Transmitter Output High Current V
Transmitter Output Low Current V

= 0V ● –12.6 – 11 –9.4 mA

A, B

= 0V ● 9.4 11 12.6 mA

A, B

Transmitter Output Leakage Current –0.25V ≤ V

≤ 0.25V ● ±0.01 ±100 µA

A, B

= 4.0V (Figure 3) ● ±0.44 ±0.55 ±0.66 V

CM

Rise or Fall Time (Figures 3, 6) 5 ns
Input to Output (Figures 3, 6), 0°C ≤ TA ≤ 70°C ● 25 45 75 ns

(Figures 3, 6), –40°C ≤ TA ≤ 85°C ● 25 45 90 ns

t

PHL

Input to Output (Figures 3, 6), 0°C ≤ TA ≤ 70°C ● 25 45 75 ns

(Figures 3, 6), –40°C ≤ TA ≤ 85°C ● 25 45 90 ns

∆t Input to Output Difference, t

PLH

– t

 (Figures 3, 6), 0°C ≤ T

PHL

≤ 70°C ● 0517 ns

A

(Figures 3, 6), –40°C ≤ TA ≤ 85°C ● 0525 ns

t

SKEW

Output to Output Skew (Figures 3, 6) 4 ns

V.35 Receiver

V

TH

Differential Receiver Input – 2V ≤ (VA + VB)/2 ≤ 2V (Figure 3) ● –0.2 0.2 V
Threshold Voltage

∆V
I

IN

R
tr, t
t

PLH

TH

IN

f

Receiver Input Hysteresis –2V ≤ (VA + VB)/2 ≤ 2V (Figure 3) ● 11 40 mV
Receiver Input Current (A, B) –10V ≤ V
Receiver Input Impedance –10V ≤ V

≤ 10V ● ±0.50 mA

A, B

≤ 10V ● 20 32 kΩ

A, B

Rise or Fall Time (Figures 3, 7) 15 ns
Input to Output (Figures 3, 7), 0°C ≤ TA ≤ 70°C ● 80 115 ns

(Figures 3, 7), –40°C ≤ TA ≤ 85°C ● 80 130 ns

t

PHL

Input to Output (Figures 3, 7), 0°C ≤ TA ≤ 70°C ● 100 115 ns

(Figures 3, 7), –40°C ≤ TA ≤ 85°C ● 100 130 ns

∆t Input to Output Difference, t

PLH

– t

 (Figures 3, 7), 0°C ≤ T

PHL

≤ 70°C ● 417 ns

A

(Figures 3, 7), –40°C ≤ TA ≤ 85°C ● 425 ns

V.10 Driver

V

O

Output Voltage Open Circuit, RL = 3.9k ±4.0 ±6.0 V

= 450Ω (Figure 4) ±3.6 V

R

L

at 450Ω > 0.9 VO at RL = 3.9k

V

O

Driver 1 Only

I

SS

I

OZ

Short-Circuit Current VO = GND; EIA-530, X.21, EIA-530-A Modes ±150 mA
Output Leakage Current –0.25V ≤ VO ≤ 0.25V, Power Off or ● ±0.1 ±100 µA

No-Cable Mode or Driver Disabled

tr, t

t

PLH

t

PHL

f

Rise or Fall Time (Figures 4, 8), RL = 450Ω, CL = 100pF

R

= 100k 4 µs

423SET

Input to Output (Figures 4, 8), RL = 450Ω, CL = 100pF

R

= 100k 8 µs

423SET

Input to Output (Figures 4, 8), RL = 450Ω, CL = 100pF

R

= 100k 8 µs

423SET

4

LTC1343

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V.10 Receiver

V

TH

∆V

TH

I

IN

R

IN

tr, t

f

t

PLH

t

PHL

V.28 Driver

V

O

I

SS

I

OZ

SR Slew Rate (Figures 4, 8), RL = 3k, CL = 2500pF ● 4.0 30.0 V/µs
t

PLH

t

PHL

V.28 Receiver

V

THL

V

TLH

∆V

TH

R

IN

tr, t

f

t

PLH

t

PHL

Receiver Input Threshold Voltage 0°C ≤ TA ≤ 70°C ● –0.2 0.2 V

Receiver Input Hysteresis ● 11 50 mV
Receiver Input Current –10V ≤ VA ≤ 10V ● ±0.50 mA
Receiver Input Impedance –10V ≤ VA ≤ 10V ● 20 30 kΩ
Rise or Fall Time (Figures 5, 9) 15 ns
Input to Output (Figures 5, 9) 350 ns
Input to Output (Figures 5, 9) 350 ns

Output Voltage Open Circuit ±10 V

Short-Circuit Current VO = GND ● ±150 mA
Output Leakage Current –0.25V ≤ VO ≤ 0.25V, Power Off or ● ±0.01 ±100 µA

Input to Output (Figures 4, 8), RL = 3k, CL = 2500pF ● 1.6 2.5 µs
Input to Output (Figures 4, 8), RL = 3k, CL = 2500pF ● 1.6 2.5 µs

Input Low Threshold Voltage ● 1.4 0.8 V
Input High Threshold Voltage ● 2.0 1.4 V
Receiver Input Hysteresis ● 0.1 0.4 1.0 V
Receiver Input Impedance –15V ≤ VA ≤ 15V ● 357 kΩ
Rise or Fall Time (Figures 5, 9) 15 ns
Input to Output (Figures 5, 9), CTRL = 0V 110 ns

Input to Output (Figures 5, 9), CTRL = 0V 170 ns

The ● denotes specifications which apply over the full operating

= 25°C. V

A

–7V ≤ V

= 3k (Figure 4) ● ±5 7.6 V

R

L

No-Cable Mode or Driver Disabled

CTRL = V

CTRL = V

= 5V (Notes 2, 3)

CC

≤ 7V, –40°C ≤ TA ≤ 85°C ● –0.3 0.3 V

CM

CC

CC

● 330 800 ns

● 480 800 ns

Note 1: Absolute Maximum Ratings are those beyond which the safety of a
device may be impaired.

Note 2: All currents into device pins are positive; all currents out of device
are negative. All voltages are referenced to device ground unless otherwise
specified.

UUU

PIN FUNCTIONS

VDD (Pin 1): Generated Positive Supply Voltage for

RS232. Connect a 1µF capacitor to ground.

C1+ (Pin 2): Capacitor C1 Positive Terminal. Connect a

1µF capacitor between C1+ and C1–.

PWRVCC (Pin 3): Positive Supply for the Charge Pump.

4.75V ≤ PWRVCC ≤ 5.25V. Tie to VCC (Pin 8) and bypass
with a 1µF capacitor to ground.

Note 3: All typicals are given for V
C

= 3.3µF tantalum capacitors and TA = 25°C.

VEE

= 5V, C1 = C2 = C

CC

VCC

= C

VDD

= 1µF,

C1–␣ (Pin 4): Capacitor C1 Negative Terminal.
D1 (Pin 5): TTL Level Driver 1 Input.
D2 (Pin 6): TTL Level Driver 2 Input.
D3 (Pin 7): TTL Level Driver 3 Input. Becomes a CMOS

level output when the chip is in the echoed clock mode
(EC = 0V).

5

LTC1343

UUU

PIN FUNCTIONS

V

(Pin 8): Positive Supply for the Transceivers. 4.75V ≤

CC

VCC ≤ 5.25V. Tie to PWRVCC (Pin 3).

respective input buffers. The data latch allows the logic
lines to be shared between multiple I/O ports.

D4 (Pin 9): TTL Level Driver 4 Input.
D4EN (Pin 10): TTL Level Enable Input for Driver 4. When

high, driver 4 outputs are enabled. When low, driver 4
outputs are forced into a high impedance state. D4EN is
not affected by the LATCH pin.

INVERT (Pin 11): TTL Level Signal Invert Input. When
high, an extra inverter will be added to the driver 4 and
receiver 1 signal path. The data stream will change polar­ity, i.e., a 1 becomes 0 and a 0 becomes a 1. When the pin
is low the data flows through with no polarity change.
INVERT is not affected by the LATCH pin.

R1EN (Pin 12): Logic Level Enable Input for Receiver 1.
When low, receiver 1 output is enabled. When high,
receiver 1 output is forced into a high impedance state.

R1O (Pin 13): CMOS Level Receiver 1 Output.
R2O (Pin 14): CMOS Level Receiver 2 Output.
R3O (Pin 15): CMOS Level Receiver 3 Output.
R4O (Pin 16): CMOS Level Receiver 4 Output.
M0 (Pin 17): TTL Level Mode Select Input 0. The data on

M0 is latched when LATCH is high.

LB (Pin 23): TTL Level Loop-Back Select Input. When low
the chip enters the loop-back configuration and is config­ured for normal operation when LB is high. The data on LB
is latched when LATCH is high.

EC (Pin 24): TTL Level Echoed Clock Select Input. When
low the part enters the echoed clock configuration and is
configured for normal operation when EC is high. The data
on EC is latched when LATCH is high.

423 SET (Pin 25): Analog Input Pin for the RS423 Driver
Output Rise and Fall Time Set Resistor. Connect the
resistor from the pin to ground.

R4 A (Pin 26): Receiver 4 Inverting Input.
R3 B (Pin 27): Receiver 3 Noninverting Input.
R3 A (Pin 28): Receiver 3 Inverting Input.
R2 B (Pin 29): Receiver 2 Noninverting Input.
R2 A (Pin 30): Receiver 2 Inverting Input.
R1 B (Pin 31): Receiver 1 Noninverting Input.
R1 A (Pin 32): Receiver 1 Inverting Input.
D4 B (Pin 33): Driver 4 Noninverting Output.

M1 (Pin 18): TTL Level Mode Select Input 1. The data on

M1 is latched when LATCH is high.
M2 (Pin 19): TTL Level Mode Select Input 2. The data on

M2 is latched when LATCH is high.
CTRL/CLK (Pin 20): TTL Level Mode Select Input. When

the pin is low the chip will be configured for clock and data
signals. When the pin is high the chip will be configured for
control signals. The data on CTRL/CLK is latched when
LATCH is high.

DCE/DTE (Pin 21): TTL Level Mode Select Input. When
high, the DCE mode is selected. When low the DTE mode
is selected. The data on DCE/DTE is latched when LATCH
is high.

LATCH (Pin 22): TTL Level Logic Signal Latch Input. When
low the input buffers on M0, M1, M2, CTRL/CLK, DCE/
DTE, LB and EC are transparent. When LATCH is pulled
high the data on the logic pins is latched into their

D4 A (Pin 34): Driver 4 Inverting Output.
D3 B (Pin 35): Driver 3 Noninverting Output.
D3 A (Pin 36): Driver 3 Inverting Output.
D2 B (Pin 37): Driver 2 Noninverting Output.
D2 A (Pin 38): Driver 2 Inverting Output.
D1 A (Pin 39): Driver 1 Inverting Output.
GND (Pin 40): Signal Ground. Connect to PGND (Pin 41).
PGND (Pin 41): Charge Pump Power Ground. Connect to

the GND (Pin 40).

VEE (Pin 42): Generated Negative Supply Voltage. Connect

a 3.3µF capacitor to ground.

C2– (Pin 43): Capacitor C2 Negative Terminal. Connect a

1µF capacitor between C2+ and C2–.

C2+ (Pin 44): Capacitor C2 Positive Terminal. Connect a

1µF capacitor between C2+ and C2–.

6

TEST CIRCUITS

A

V

OD

B

Figure 1. RS422 Driver Test Circuit Figure 2. RS422 Driver/Receiver AC Test Circuit

R

L

50Ω

R

L

50Ω

LTC1343

C

L

B

R

L

100Ω

A

V

OC

1343 F01

100pF

C
100pF

B

R

L

A

15pF

1343 F02

B

D

V

A

50Ω

125Ω

OD

50Ω

V

CM

125Ω

50Ω

50Ω

B

R

A

15pF

1343 F03

Figure 3. V.35 Driver/Receiver Test Circuit

D

A

R

C

L

L

1343 F04

D

A

A

R

15pF

1343 F04

Figure 4. V.10/V.28 Driver Test Circuit Figure 5. V.10/V.28 Receiver Test Circuit

W

U

ODE SELECTIO

LTC1343 MODE NAME M2 M1 M0 CTRL/CLK D1 D2 D3 D4 R1 R2 R3 R4

V.10, RS423 0 0 0 X V.10 V.10 V.10 V.10 V.10 V.10 V.10 V.10
EIA-530-A Clock and Data 0 0 1 0 V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10
EIA-530-A Control 0 0 1 1 V.10 V.11 V.10 V.11 V.11 V.10 V.11 V.10
Reserved 0 1 0 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10
X.21 0 1 1 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10
V.35 Clock and Data 1 0 0 0 V.28 V.35 V.35 V.35 V.35 V.35 V.35 V.28
V.35 Control 1 0 0 1 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28
EIA-530, RS449, V.36 1 0 1 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10
V.28, RS232 1 1 0 X V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28
No Cable 1 1 1 X Z Z Z Z Z Z Z Z

7

LTC1343

UWW

SWITCHI G TI E WAVEFOR S

B – A

B – A

–V

5V

D

0V

V

O

–V

O

A

B

V

O

1.5V 1.5V

t

PLH

50%

90%
10%

t

r

t

SKEW

f = 1MHz : tr ≤ 10ns : tf ≤ 10ns

= V(A) – V(B)

V

DIFF

1/2 V

O

t

PHL

90%

50%

10%

t

f

t

SKEW

1343 F06

Figure 6. V.11, V.35 Driver Propagation Delays

V

OD2

OD2

V

OH

R

V

OL

0V

t

PLH

1.5V

f = 1MHz : tr ≤ 10ns : tf ≤ 10ns

INPUT

OUTPUT

0V

t

PHL

1.5V

1343 F07

Figure 7. V.11, V.35 Receiver Propagation Delays

3V

D

0V

V

O

A

–V

O

1.5V

t

PHL

3V

0V

–3V

t

f

1.5V

–3V

t

PLH

0V

3V

t

r

1343 F08

8

Figure 8. V.10, V.28 Driver Propagation Delays

V

IH

A

V

IL

V

OH

R

V

OL

1.3V

t

PHL

0.8V

1.7V

t

PLH

2.4V

1343 F09

Figure 9. V.10, V.28 Receiver Propagation Delays

LTC1343

U

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APPLICATIONS INFORMATION

Overview

The LTC1343 is a 4-driver/4-receiver multiprotocol trans­ceiver that operates from a single 5V supply. Two LTC1343s
form the core of a complete software-selectable DTE or
DCE interface port that supports the RS232, RS449,
EIA-530, EIA-530-A, V.35, V.36 or X.21 protocols. Cable
termination may be implemented using the LTC1344

SERIAL

CONTROLLER

TXD

SCTE

LL

LTC1343

D1

D2

D3

D4

TXD

SCTE

software-selectable cable termination chip or by using
existing discrete designs.

A complete DCE-to-DTE interface operating in EIA-530
mode is shown in Figure 10. The first LTC1343 of each port
is used to generate the clock and data signals along with
LL (Local Loop-back) and TM (Test Mode). The second
LTC1343 is used to generate the control signals along with

DCEDTE

LTC1343LTC1344 LTC1344

LL

103Ω

103Ω

R4

R3

R2

R1

SERIAL

CONTROLLER

LL

TXD

SCTE

TXC

RXC

RXD

TM

RL

RTS

DTR

DCD

DSR

R1

R2

R3

R4

LTC1343

D1

D2

D3

D4

R1

R2

103Ω

103Ω

103Ω

TXC

RXC

RXD

TM

RTS

DTR

DCD

DSR

D4

D3

D2

D1

RL

LTC1343

R4

R3

R2

R1

D4

D3

TXC

RXC

RXD

TM

RL

RTS

DTR

DCD

DSR

CTS

R3

RI

R4

CTS

RI

D2

D1

CTS

RI

1343 F10

Figure 10. Complete Multiprotocol Interface in EIA-530 Mode

9

LTC1343

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APPLICATIONS INFORMATION

RL (Remote Loop-back) and RI (Ring Indicate). The
LTC1344 cable termination chip is used only for the clock
and data signals because they must support V.35 cable
termination. The control signals do not need any external
resistors.

Mode Selection

The interface protocol is selected using the mode select
pins M0, M1, M2 and CTRL/CLK (see the Mode Selection
table). The CTRL/CLK pin should be pulled high if the
LTC1343 is being used to generate control signals and
pulled low if used to generate clock and data signals.

For example, if the port is configured as a V.35 interface,
the mode selection pins should be M2 = 1, M1 = 0, M0 = 0.
For the control signals, CTRL/CLK = 1 and the drivers and
receivers will operate in RS232 (V.28) electrical mode. For
the clock and data signals, CTRL/CLK = 0 and the drivers
and receivers will operate in V.35 electrical mode, except
for the single-ended driver and receiver which will operate
in the RS232 (V.28) electrical mode. The DCE/DTE pin

will configure the port for DCE mode when high, and DTE
when low.

The interface protocol may be selected simply by plugging
the appropriate interface cable into the connector. The
mode pins are routed to the connector and are left uncon­nected (1) or wired to ground (0) in the cable as shown in
Figure 11.

The pull-up resistors R1 through R4 will ensure a binary
1 when a pin is left unconnected and that the two LTC1343s
and the LTC1344 enter the no-cable mode when the cable
is removed. In the no-cable mode the LTC1343 supply
current drops to less than 200µA and all LTC1343 driver
outputs and LTC1344 resistive terminations are forced
into a high impedance state. Note that the data latch pin,
LATCH, is shorted to ground for all chips.

The interface protocol may also be selected by the serial
controller or host microprocessor as shown in Figure 12.

The mode selection pins M0, M1, M2 and DCE/DTE can be
shared between multiple interface ports, while each port

21

LATCH

LTC1344

DCE/

M2 M1

DTE

22

(DATA)

LTC1343

20

CTRL/CLK

22

LATCH

DCE/DTE

LTC1343

DCE/DTE

20

CTRL/CLK

V

CC

22

LATCH

M0

M1

M2

M2

M1

M0

(DATA)

17

18

19

21

21

19

18

17

M0 (DATA)

23 24 1

R1, 10k

R2, 10k

R3, 10k

R4, 10k

V

CC

V

CC

V

CC

V

CC

CONNECTOR

NC

NC

CABLE

1343 F11

10

Figure 11: Single Port DCE/V.35 Mode Selection in the Cable

LTC1343

AA

'

CB

'

C

'

GENERATOR

BALANCED

INTERCONNECTING

CABLE

LOAD

CABLE

TERMINATION

RECEIVER

1343 F13

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APPLICATIONS INFORMATION

PORT #1

M0
M1
M2
DCE/DTE

LATCH

PORT #2

M0
M1
M2
DCE/DTE

CONTROLLER

M0
M1
M2

DCE/DTE

LATCH 1
LATCH 2
LATCH 3

LATCH

PORT #3

M0
M1
M2
DCE/DTE

LATCH

CONNECTOR #1CONNECTOR #2CONNECTOR #3

1343 F12

remain off even though the signal voltage is beyond the
supply voltage for the FET drivers or the power is off.

Using the LTC1344 along with the LTC1343 solves the
cable termination switching problem. Via software con­trol, the LTC1344 provides termination for the V.10
(RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical
protocols.

V.10 (RS423) Interface

A typical V.10 unbalanced interface is shown in Figure 13.
A V.10 single-ended generator output A with ground C is
connected to a differential receiver with inputs A' con­nected to A, and input B' connected to the signal return
ground C. The receiver’s ground C' is separate from the
signal return. Usually, no cable termination is required for
V.10 interfaces, but the receiver inputs must be compliant
with the impedance curve shown in Figure 14.

Figure 12: Mode Selection by the Controller

has a unique data latch signal which acts as a write enable.
When the LATCH pin is low the buffers on the M0, M1, M2,
CTRL/CLK, DCE/DTE, LB and EC pins are transparent.
When the LATCH pin is pulled high the buffers latch the
data and changes on the input pins will no longer affect
the chip.

The mode selection may also be accomplished by using
jumpers to connect the mode pins to ground or VCC.

Cable Termination

Traditional implementations have included switching re­sistors with expensive relays, or requiring the user to
change termination modules every time the interface
standard has changed. Custom cables have been used
with the termination in the cable head, or separate termi­nations are built on the board and a custom cable routes
the signals to the appropriate termination. Switching the
terminations with FETs is difficult because the FETs must

–3.25mA

Figure 13. Typical V.10 Interface

I

Z

–10V

–3V

3V 10V

Figure 14. V.10 Receiver Input Impedance

1343 F14

3.25mA

V

Z

11

LTC1343

R3

124Ω

R5

20k

LTC1344

LTC1343

RECEIVER

1343 F17

A

B

A

'

B'

C'

R1

51.5Ω

R8
6k

S2

S3

S4

R2

51.5Ω

R6
10k

R7
10k

GND

R4
20k

S1

U

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APPLICATIONS INFORMATION

The V.10 receiver configuration in the LTC1343 and
LTC1344 is shown in Figure 15. In V.10 mode switches S1
and S2 inside the LTC1344 and S3 inside the LTC1343 are
turned off. Switch S4 inside the LTC1343 shorts the
noninverting receiver input to ground so the B input at the
connector can be left floating. The cable termination is
then the 30k input impedance to ground of the LTC1343
V.10 receiver.

V.11 (RS422) Interface

A typical V.11 balanced interface is shown in Figure 16. A
V.11 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.11 interface has a differential termination at the receiver
end that has a minimum value of 100Ω. The termination
resistor is optional in the V.11 specification, but for the
high speed clock and data lines, the termination is required
to prevent reflections from corrupting the data. The re-

ceiver inputs must also be compliant with the impedance
curve shown in Figure 14.

In V.11 mode, all switches are off except S1 inside the
LTC1344 which connects a 103Ω differential termination
impedance to the cable as shown in Figure 17.

V.28 (RS232) Interface

A typical V.28 unbalanced interface is shown in Figure 18.
A. V.28 single-ended generator output A with ground C is
connected to a single-ended receiver with inputs A' con­nected to A, ground C' connected via the signal return
ground C.

In V.28 mode all switches are off except S3 inside the
LTC1343 which connects a 6k (R8) impedance to ground
in parallel with 20k (R5) plus 10k (R6) for a combined
impedance of 5k as shown in Figure 19. The noninverting
input is disconnected inside the LTC1343 receiver and
connected to a TTL level reference voltage for a 1.4V
receiver trip point.

A

'

A

LTC1344

R1

51.5Ω

S1

R3

S2

124Ω

R2

51.5Ω

B'

C'

B

R8
6k

S3

GND

R5

20k

R4

20k

S4

Figure 15. V.10 Receiver Configuration

BALANCED

INTERCONNECTING

GENERATOR

AA'

B

C

Figure 16. Typical V.11 Interface

CABLE

CABLE

TERMINATION

B'

C'

R6
10k

R7
10k

100Ω
MIN

LOAD

LTC1343

RECEIVER

RECEIVER

1343 F15

1343 F16

Figure 17. V.11 Receiver Configuration

BALANCED

INTERCONNECTING

GENERATOR

CABLE

AA

CC

Figure 18. Typical V.28 Interface

CABLE

TERMINATION

'

'

LOAD

RECEIVER

1343 F18

12

LTC1343

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APPLICATIONS INFORMATION

A

'

A

LTC1344

R1

51.5Ω

S1

R3

S2

124Ω

R2

51.5Ω

B

'

C

'

B

R8
6k

S3

GND

R5

20k

R4

20k

S4

Figure 19. V.28 Receiver Configuration

V.35 Interface

A typical V.35 balanced interface is shown in Figure 20. A
V.35 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.35 interface requires a T or delta network termination at
the receiver end and the generator end. The receiver
differential impedance measured at the connector must be
100Ω␣ ±10Ω, and the impedance between shorted termi­nals (A' and B) and ground C' must be 150Ω ±15Ω.

In V.35 mode, both switches S1 and S2 inside the LTC1344
are on, connecting the T network impedance as shown in
Figure 21. Both switches in the LTC1343 are off. The 30k
input impedance of the receiver is placed in parallel with
the T network termination, but does not affect the overall
input impedance significantly.

R6
10k

R7
10k

LTC1343

RECEIVER

1343 F19

A

'

A

LTC1344

R1

51.5Ω

S1

R2

51.5Ω

B

'

C

'

R3

S2

124Ω

B

R8
6k

S3

GND

R5

20k

R4

20k

S4

R6
10k

R7
10k

LTC1343

RECEIVER

1343 F21

Figure 21. V.35 Receiver Configuration

The generator differential impedance must be 50Ω to
150Ω and the impedance between shorted terminals (A
and B) and ground C must be 150Ω ±15Ω. For the
generator termination, switches S1 and S2 are both on and
the top side of the center resistor is brought out to a pin so
it can be bypassed with an external capacitor to reduce
common mode noise as shown in Figure 22.

Any mismatch in the driver rise and fall times or skew in
the driver propagation delays will force current through
the center termination resistor to ground, causing a high
frequency common mode spike on the A and B terminals.
The common mode spike can cause EMI problems that are
reduced by capacitor C1 which shunts much of the com­mon mode energy to ground rather than down the cable.

A

GENERATOR

50Ω

50Ω

BALANCED

INTERCONNECTING

CABLE

CABLE

TERMINATION

A

A

125Ω

B

C

'

125Ω

'

B

C

'

Figure 20. Typical V.35 Interface

LOAD

50Ω

50Ω

RECEIVER

1343 F20

LTC1344

V.35 DRIVER

124Ω

C1
100pF

S2
ON

51.5Ω

S1
ON

51.5Ω

Figure 22. V.35 Driver Using the LTC1344

B

C

1343 F22

13

LTC1343

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APPLICATIONS INFORMATION

Echoed Clock Mode

The LTC1343 contains the logic to generate the echoed
clock when using a serial controller with only two clock
pins. Figure 23 shows the chip in both the DTE and DCE
echoed clock in EIA-530 mode. The control signals are not
shown. The echoed clock configuration is selected by
pulling the EC pin low. On the DTE side the transmit clock
TXC receiver output is connected to the echoed clock,
SCTE, driver input. The TXC pin on the serial controller is
configured as an input. On the DCE side, the transmit clock
from the serial controller is used to generate both TXC and
RXC. A phase inverter is placed in the TXC signal path on
both the DTE and DCE side to help correct phase problems
with long cables. If the Invert pin is high, the phase of the
data is inverted.

Loop-Back

The LTC1343 contains logic for placing the interface into
a loop-back configuration for testing. Both DTE and DCE
loop-back configurations are supported. Figure 24 shows
a complete DTE interface in the loop-back configuration
with the EC pin pulled high. The loop-back configuration is
selected by pulling the LB pin low. Both the line side and
logic side signals are looped back. The DCE loop-back
configuration is shown in Figure 25.

If the echoed clock mode is selected by pulling EC low, D3
becomes an output and is connected to receiver 2’s output
R3 in DTE mode as shown in Figure 26. In the echoed clock
DCE loop-back mode, driver 4 is connected to driver 3’s
input D3 as shown in Figure 27.

DCEDTE

SERIAL

CONTROLLER

TXD

TXC

INVERT

RXC

RXD

TM

LTC1343

LL

M0M1M2

1 0 1 0 0 1 0 0

D1

D2

D3

D4

CTRL/CLK

DCE/DTELBEC

R1

R2

R3

R4

LATCHM0M1M2DCE/DTE

103Ω

103Ω

103Ω

LATCH

LL

TXD

SCTE

TXC

RXC

RXD

TM

LTC1344

103Ω

103Ω

M0M1M2

DCE/DTE

1 0 1 1 0

LATCH

M0M1M2

1 0 1 0 1 1 0 01 0 1 0 0

R4

R3

R2

R1

D4

D3

D2

D1

CTRL/CLK

LTC1343LTC1344

DCE/DTELBEC

LATCH

SERIAL

CONTROLLER

LL

RXD

RXC

INVERT

TXC

TXD

TM

1343 F23

14

Figure 23. EIA-530 Echoed Clock Configuration

LTC1343

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APPLICATIONS INFORMATION

SERIAL

CONTROLLER

LL

TXD

SCTE

TXC

RXC

RXD

TM

LTC1343 LTC1344

D1

D2

D3

D4

R1

R2

R3

R4

M0M1M2

CTRL/CLK

DCE/DTELBEC

LATCHM0M1M2DCE/DTE

103Ω

103Ω

103Ω

SCTE

LATCH

LL

TXD

RXD

LL

TXD

SCTE

TXCTXC

RXCRXC

RXD

TMTM

103Ω

103Ω

M0M1M2

DCE/DTE

LATCH

R4

R3

R2

R1

D4

D3

D2

D1

M0M1M2

LTC1343LTC1344

CTRL/CLK

DCE/DTELBEC

LATCH

SERIAL

CONTROLLER

LL

TXD

SCTE

TXC

RXC

RXD

TM

RTS

DTR

DCD

DSR

CTS

1 0 1 0 0 0 1 0 1 0 1 0 0

LTC1343

RL

RI

M0M1M2

1 0 1 1 0 0 1 0

D1

D2

D3

D4

CTRL/CLK

DCE/DTELBEC

R1

R2

R3

R4

LATCH

DCD

DSR

CTS

1343 F24

RLRL

RTSRTS

DTRDTR

DCD

DSR

CTS

RIRI

1 0 1 1 0

1 0 1 0 1 0 1 0

LTC1343

R4

R3

R2

R1

D4

D3

D2

D1

M0M1M2

1 0 1 1 1 0 1 0

CTRL/CLK

DCE/DTELBEC

LATCH

RL

RTS

DTR

DCD

DSR

CTS

RI

1343 F25

Figure 24. Normal DTE Loop-Back

Figure 25. Normal DCE Loop-Back

15

LTC1343

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APPLICATIONS INFORMATION

SERIAL

CONTROLLER

LL

TXD

TXC

RXC

RXD

TM

LTC1343 LTC1344

D1

D2

D3

D4

R1

R2

R3

R4

M0M1M2

CTRL/CLK

DCE/DTELBEC

LATCHM0M1M2DCE/DTE

103Ω

103Ω

103Ω

TXCE

LATCH

TXC

RXC

RXD

LLLL

TXDTXD

SCTE

TXC

RXC

RXD

TMTM

103Ω

103Ω

M0M1M2

DCE/DTE

LATCH

R4

R3

R2

R1

D4

D3

D2

D1

M0M1M2

LTC1343LTC1344

CTRL/CLK

DCE/DTELBEC

SERIAL

CONTROLLER

LL

RXD

RXC

TXC

TXD

TM

LATCH

RTS

DTR

DCD

DSR

CTS

1 0 1 0 0 0 0 0 1 0 1 0 0

LTC1343

RL

RI

M0M1M2

1 0 1 1 0 0 1 0

D1

D2

D3

D4

CTRL/CLK

DCE/DTELBEC

RTS

DTR

R1

R2

R3

R4

LATCH

DCD

CTS

RI

1343 F26

1 0 1 1 0

RLRL

RTS

DTR

DCD

DSRDSR

CTS

RI

1 0 1 0 1 0 0 0

LTC1343

R4

R3

R2

R1

D4

D3

D2

D1

M0M1M2

1 0 1 1 1 0 1 0

CTRL/CLK

DCE/DTELBEC

RL

RTS

DTR

DCD

DSR

CTS

RI

LATCH

1343 F27

16

Figure 26. Echoed Clock, DTE Loop-Back

Figure 27. Echoed Clock, DCE Loop-Back

LTC1343

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APPLICATIONS INFORMATION

No-Cable Mode

The no-cable mode (M0 = M1 = M2 = 1) is intended for the
case when the cable is disconnected from the connector.
The charge pump, bias circuitry, drivers and receivers are
turned off, the driver outputs are forced into a high
impedance state, and the supply current drops to less than
200µA. It can also be used to share I/O lines with other
drivers and receivers without loading down the signals.

Charge Pump

The LTC1343 uses an internal capacitive charge pump to
generate VDD and VEE as shown in Figure 28. A voltage
doubler generates about 8V on VDD and a voltage inverter
generates about – 7.5V for VEE. Four 1µF surface mounted
tantalum or ceramic capacitors are required for C1, C2, C3
and C4. The VEE capacitor C5 should be a minimum of

3.3µF. All capacitors are 16V.

Receiver Fail-Safe and Glitch Filter

5V

+

C3
1µF

+

+

C4
1µF

C1
1µF

1

2

3

4

8

V

DD

+

C1

PWRV

–

C1

V

CC

LTC1343

CC

C2

C2

V

PGND

GND

44

+

–

EE

+

43

42

41

40

C2
1µF

C5

+

3.3µF

1343 F28

Figure 28. Charge Pump

100

10

All LTC1343 receivers feature fail-safe operation in all
modes except no-cable mode. If the receiver inputs are left
floating or shorted together by a termination resistor, the
receiver output will always be forced to a logic high.
External pull-up resistors are required on receiver outputs
if fail-safe operation in the no-cable mode is desired.

When the chip is configured for control signals by pulling
the CTRL/CLK pin high, a glitch filter is connected to all
receiver inputs. The filter will reject any glitches at the
receiver inputs less than 300ns.

V.10 Driver Rise and Fall Times

The rise and fall times of the V.10 drivers is programmed
by placing a 1/8W, 5% resistor between the 423 SET (Pin

25) and ground. The graph of Driver Rise and Fall Times
vs Resistor Value is shown in Figure 29.

Enabling the Single-Ended Driver and Receiver

When the LTC1343 is being used to generate the control
signals (CTRL/CLK = high) and the EC pin is pulled low, the
DCE/DTE pin becomes an enable for driver 1 and receiver
4 so their inputs and outputs can be tied together as shown
in Figure 30.

1

DRIVER RISE/FALL TIME (µs)

0.1
1k

10k

100k 1M 5M

RESISTANCE (Ω)

1343 F29

Figure 29. V.10 Driver Rise and Fall Time vs Resistor Value

LTC1343

39

26

1343 F30

DCE/DTE

V

5

21

16

CC

20

24

D1

R4

CTRL/CLK

EC

Figure 30. Single-Ended Driver and Receiver Enable

17

LTC1343

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APPLICATIONS INFORMATION

The EC pin has no affect on the configuration when CTRL/
CLK is high except to allow the DCE/DTE pin to become an
enable. When DCE/DTE is low, the driver 1 output is
enabled. The receiver 4 output goes into three-state and
the input presents a 30kΩ load to ground.

When DCE/DTE is high, the driver 1 output goes into three­state and the receiver 4 output is enabled. The receiver 4
input presents a 30kΩ load to ground in all modes except
when configured for RS232 operation when the input
impedance is 5kΩ to ground.

DTE vs DCE Operation

The DCE/DTE pin does not allow a given LTC1343 pin to be
reconfigured as a driver or receiver. The DCE/DTE pin only
selects the loop-back topology and acts as an enable for
the single-ended driver and receiver for control signals.

However, the LTC1343 can be configured for either DTE or
DCE operation in one of three ways: a dedicated DTE or
DCE port with a connector of appropriate gender, a port
with one connector that can be configured for DTE or DCE
operation by rerouting the signals to the LTC1343 using a
dedicated DTE cable or dedicated DCE cable, or a port with
one connector and one cable using four LTC1343s.

A dedicated DTE port using a DB-25 male connector is
shown in Figure 31. The interface mode is selected by logic
outputs from the controller or from jumpers to either V
or GND on the mode select pins. A dedicated DCE port
using a DB-25 female connector is shown in Figure 32.

A port with one DB-25 connector that can be configured
for either DTE or DCE operation is shown in Figure 33. The
configuration requires separate cables for proper signal
routing in DTE or DCE operation. For example, in DTE
mode, the TXD signal is routed to connector Pins 2 and 14
via driver 2 in the LTC1343. In DCE mode, driver 2 now
routes the RXD signal to Pins 2 and 14.

A combination DTE/DCE port that doesn’t require separate
DCE/DTE cables is shown in Figure 34. In DTE mode, the
top and bottom LTC1343s are enabled and the middle two
are placed in the no-cable mode, which forces all of the

CC

drivers and receivers into a high impedance state. In the
DCE mode, the middle two LTC1343s are enabled and the
top and bottom LTC1343s disabled. With this scheme, any
connector pin can be configured for sending or receiving
signals. Note that only one LTC1344 is required.

Multiprotocol Interface with Ring-Indicate and a
DB-25 Connector

If the RI signal in RS232 mode is implemented, driver 4
and receiver 1 in the control chip can be tied to connector
Pin 22 in order to implement the RI signal in RS232 mode
and DSR B signal for the other modes. Figure 35 shows the
DTE configuration and Figure 36 the DCE configuration. In
DCE mode, the DCE/DTE pin should be driven with a logic
signal from the controller that goes low only when the
interface is in the RS232 mode. Since the receiver 4 input
impedance is greater than 30kΩ in all modes except
RS232, it can be enabled at all other times and not load
down the line. When driver 1 is disabled, it remains in a
high impedance state and does not load the line.

Cable-Selectable Multiprotocol Interface

A cable-selectable multiprotocol DTE/DCE interface is
shown in Figure 37. The control signals LL, RL and TM are
not implemented. The select lines M0, M1 and DCE/DTE
are brought out to the connector. The mode is selected
through the cable by wiring M0 (connector Pin 18), M1
(connector Pin 21) and DCE/DTE (connector Pin 25) to
ground (connector Pin 7) or letting them float. If M0, M1
or DCE/DTE are floating, pull-up resistors R3, R4 and R5
will pull the signals to VCC. The select bit M1 is hard wired
to VCC. When the cable is pulled out, the interface will go
into the no-cable mode.

Multiprotocol Interface with a µDB-26 Connector

The controller-selectable multiprotocol DTE/DCE inter­face with a standard µDB-26 connector is shown in Figure

38. The RL, LL and TM signals are implemented and RI is
mapped to Pin 26 on the connector. A cable-selectable
version is shown in Figure 39. The TM and RL signals have
been dropped, but LL is still implemented.

18

LTC1343

U

WUU

APPLICATIONS INFORMATION

V

CC

5V

TXD

SCTE

TXC

RXC

RXD

RTS

DTR

DCD

DSR

CTS

LATCH

1µF

1µF

C1

C9

C5
1µF

100k

C12
1µF

100k

1
2

+

4

CHARGE

3
8

LTC1343

5

6

7

9

10
12
13

14

15

16
20

CTRL

22

LATCH

11

INVERT

25

423 SET

R1

40

GND

23

LB

1
2

+

4

CHARGE

3
8

LTC1343

5

6

7

9

10
12
13

14

15

16
20

CTRL

22

LATCH

11

INVERT

25

423 SET

R2

40

GND

23

LB

+

C3
1µF

+

LL

TM

+

C11
1µF

V

CC

+

RL

V

CC

LB

M2
M1
M0

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

DCE

DCE

44

+

C2

43

1µF

42

C4

+

3.3µF

41

39

38
37
36
35
34
33

32
31
30
29
28
27

26
21

19

M2

18

M1

17

M0

24

V

EC

CC

44

+

C10

43

1µF

42

C13

3.3µF

+

41

39

38
37
36
35
34
33

32
31
30
29

28
27

26
21
19

M2

18

M1

17

M0

24

EC

C6

100pFC7100pF

14

V

CC

2

V

EE

C8

100pF

13

121138

LTC1344

21

LATCHLATCH

18

LL A (141)

2

TXD A (103)

14

TXD B

24

SCTE A (113)

11

SCTE B

15

TXC A (114)

12

TXC B

17

RXC A (115)

9

RXC B

3

RXD A (104)

16

RXD B

25

TM A (142)

7

SGND (102)

1

SHIELD (101)

21

RL A (140)

4

RTS A (105)

19

RTS B

20

DTR A (108)

23

DTR B

8

DCD A (109)

10

DCD B

6

DSR A (107)

22

DSR B

5

CTS A (106)

13

CTS B

DB-25 MALE
CONNECTOR

1343 F31

DCE/
DTE

20 22 23 24 1

97645

10

1917181516

M0M1M2

Figure 31: Controller-Selectable Multiprotocol DTE Port with DB-25 Connector

19

LTC1343

U

WUU

APPLICATIONS INFORMATION

V

CC

5V

RXD

RXC

TXC

SCTE

TXD

CTS

DSR

DCD

DTR

CTS

LATCH

1µF

100k

1µF

100k

1
2

+

C1

4

CHARGE

3
8

C5
1µF

R1

+

C9

C12
1µF

R2

10
12
13

14

15

16
20
22
11
25

40
23

10
12
13

14

15

16
20
22
11
25

40
23

5

6

7

9

1
2

4
3
8

5

6

7

9

LTC1343

CTRL
LATCH
INVERT
423 SET

GND
LB

CHARGE

LTC1343

CTRL
LATCH
INVERT
423 SET

GND
LB

+

C3
1µF

+

TM

V

CC

LL

+

C11
1µF

V

CC

+

V

CC

RL

LB

M2
M1
M0

V

CC

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

DCE

DCE

44

+

C2

43

1µF

42

C4

3.3µF

+

41

39

38
37
36
35
34
33

32
31
30
29
28
27

26
21

V

CC

19

M2

18

M1

17

M0

24

V

EC

CC

44

+

C10

43

1µF

42

C13

+

3.3µF

41

39

38
37
36
35
34
33

32
31
30
29

28
27

26
21

V

CC

19

M2

18

M1

17

M0

24

EC

14

2

V

CC

V

EE

C6

100pFC7100pF

C8

100pF

13

121138

LTC1344

21

LATCHLATCH

DCE/

DTE

20 22 23 24 1

19171815161097645

V

CC

M0M1M2

DB-25 FEMALE

25

TM A (142)

3

RXD A (104)

16

RXD B

17

RXC A (115)

9

RXC B

15

TXC A (114)

12

TXC B

24

SCTE A (113)

11

SCTE B

2

TXD A (103)

14

TXD B

18

LL A (141)

7

SGND (102)

1

SHIELD (101)

5

CTS A (106)

13

CTS B

6

DSR A (107)

22

DSR B

8

DCD A (109)

10

DCD B

20

DTR A (108)

23

DTR B

4

RTS A (105)

19

RTS B

21

RL A (140)

CONNECTOR

1343 F32

20

Figure 32: Controller-Selectable Multiprotocol DCE Port with DB-25 Connector

LTC1343

U

WUU

APPLICATIONS INFORMATION

V

CC

5V

DTE_LL/DCE_TM

DTE_TXD/DCE_RXD

DTE_SCTE/DEC_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_TM/DCE_LL

DTE_RL/DCE_RL

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

LATCH

DCE/DTE

1µF

100k

1µF

100k

1
2

+

C1

4

CHARGE

3
8

C5
1µF

R1

+

C9

C12
1µF

R2

10
12
13

16
20
22
11
25

40
23

10
12
13

14

15

16
20
22
11
25

40
23

14

15

1
2

4

5

6

7

9

3
8

5

6

7

9

LTC1343

CTRL
LATCH
INVERT
423 SET

GND
LB

CHARGE

LTC1343

CTRL
LATCH
INVERT
423 SET

GND
LB

+

C3
1µF

+

+

C11
1µF

V

CC

+

V

CC

LB

M2
M1
M0

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

DCE

DCE

44
43

42

41

39

38
37
36
35
34
33

32
31
30
29
28
27

26
21
19

M2

18

M1

17

M0

24

EC

44
43

42

41

39

38
37
36
35
34
33

32
31
30
29
28
27

26
21
19

M2

18

M1

17

M0

24

EC

C6

100pFC7100pF

14

V

CC

+

C2
1µF

2

V

EE

C4

+

3.3µF

V

CC

+

C10
1µF

C13

+

3.3µF

C8

100pF

13

121138

LTC1344

21

LATCHLATCH

DCE/

DTE

19171815161097645

20 22 23 24 1

M0M1M2

DB-25 CONNECTOR

DTE DCE

18

LL A

2

TXD A

14

TXD B

24

SCTE A

11

SCTE B

15

TXC A

12

TXC B

17

RXC A

9

RXC B

3

RXD A

16

RXD B

25

TM A

7

SGND

1

SHIELD

21

RL A

4

RTS A

19

RTS B

20

DTR A

23

DTR B

8

DCD A

10

DCD B

6

DSR A

22

DSR B

5

CTS A

13

CTS B

TM A

RXD A
RXD B
RXC A
RXC B

TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B

LL A

RL A
CTS A

CTS B
DSR A
DSR B

DCD A
DCD B
DTR A
DTR B
RTS A
RTS B

1343 F33

Figure 33. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector

21

LTC1343

U

WUU

APPLICATIONS INFORMATION

TM

RXD

RXC

TXC

SCTE

TXD

CTS

DSR

DCD

DTR

RTS

LTC1343

5

6

7

21

DCE

9

10
12

13

14

15

16

LTC1343

5

6

7

21

DCE

9

10
12

V

CC

13

14

15

LL

RL

16

LTC1343

5

6

7

21

V

CC

DCE

9

10
12
13

14

15

16

39

D1

38
37

D2

36

D3

35
34
33

D4

32
31

R1

30
29

R2

28

R3

27

26

R4

39

D1

38
37

D2

36
35

D3

34
33

D4

32
31

R1

30
29

R2

28

R3

27
26

R4

39

D1

38
37

D2

36
35

D3

34
33

D4

32
31

R1

30
29

R2

28

R3

27
26

R4

100pFC7100pF

LTC1344

C6

C8

100pF

13

12

1138

DCE/

DTE

20 22

19171815161097645

DCE/DTE

DB-25 CONNECTOR

25

TM A (142)

3

RXD A (104)

16

RXD B

17

RXC A (115)

9

RXC B

15

TXC A (114)

12

TXC B

24

SCTE A (113)

11

SCTE B

2

TXD A (103)

14

TXD B

18

LL A (141)

7

SGND (102)

5

CTS A (106)

13

CTS B

6

DSR A (107)

22

DSR B

8

DCD A (109)

10

DCD B

1

SHIELD (101)

20

DTR A (108)

23

DTR B

4

RTS A (105)

19

RTS B

21

RL A (140)

22

LTC1343

5

6

7

21

DCE

9

10
12
13

14

15

16

39

D1

38
37

D2

36
35

D3

34
33

D4

32
31

R1

30
29

R2

28

R3

27

26

R4

Figure 34. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25

1343 F34

LTC1343

U

WUU

APPLICATIONS INFORMATION

V

CC

5V

TXD

SCTE

TXC

RXC

RXD

RTS

DTR

DCD

DSR

CTS

LATCH

1µF

1µF

C1

C9

C5
1µF

100k

C12
1µF

100k

1
2

+

4

CHARGE

3
8

LTC1343

5

6

7

9

10
12
13

14

15

16

20

CTRL

22

LATCH

11

INVERT

25

423 SET

R1

40

GND

23

LB

1
2

+

4

CHARGE

3
8

LTC1343

5

6

7

9

10
12
13

14

15

16
20

CTRL

22

LATCH

11

INVERT

25

423 SET

R2

40

GND

23

LB

+

C3
1µF

+

LL

TM

+

C11
1µF

V

CC

+

RL

RI

LB

M2
M1
M0

V

CC

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

DCE

DCE

44

+

C2

43

1µF

42

C4

+

3.3µF

41

39

38
37
36
35
34
33

32
31
30
29
28
27

26
21

19

M2

18

M1

17

M0

24

EC

V

CC

44

+

C10

43

1µF

42

C13

+

3.3µF

41

39

38
37
36
35
34
33

32
31
30
29

28
27

26
21

19

M2

18

M1

17

M0

24

V

EC

CC

14

2

V

CC

V

EE

C6

100pFC7100pF

C8

100pF

13

121138

LTC1344

21

LATCHLATCH

DCE/

DTE

20 22 23 24 1

97645

10

1917181516

M0M1M2

DB-25 MALE
CONNECTOR

18

LL A (141)

2

TXD A (103)

14

TXD B

24

SCTE A (113)

11

SCTE B

15

TXC A (114)

12

TXC B

17

RXC A (115)

9

RXC B

3

RXD A (104)

16

RXD B

25

TM A (142)

7

SGND (102)

1

SHIELD (101)

21

RL A (140)

4

RTS A (105)

19

RTS B

20

DTR A (108)

23

DTR B

8

DCD A (109)

10

DCD B

6

DSR A (107)

22

DSR B/RI A (125)

5

CTS A (106)

13

CTS B

1343 F35

Figure 35. Controller-Selectable Multiprotocol DTE Port with RI and DB-25 Connector

23

LTC1343

U

WUU

APPLICATIONS INFORMATION

V

CC

5V

RXD

RXC

TXC

SCTE

TXD

CTS

DSR

DCD

DTR

CTX

LATCH

CC

CC

CC

1µF

100k

1µF

100k

1
2

+

C1

4

CHARGE

3
8

C5
1µF

R1

+

C9

C12
1µF

R2

LTC1343

5

6

7

9

10
12
13

14

15

16
20

CTRL

22

LATCH

11

INVERT

25

423 SET

40

GND

23

LB

1
2

4

CHARGE

3
8

LTC1343

5

6

7

9

10
12
13

14

15

16
20

CTRL

22

LATCH

11

INVERT

25

423 SET

40

GND

23

LB

+

C3
1µF

+

TM

V

LL

+

C11
1µF

V

CC

+

RI

V

RL

LB

M2
M1
M0

V

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

DCE

DCE

44

+

C2

43

1µF

42

C4

+

3.3µF

41

39

38
37
36
35
34
33

32

31
30
29
28
27

26

21

V

CC

19

M2

18

M1

17

M0

24

V

EC

CC

44

+

C10

43

1µF

42

C13

+

3.3µF

41

39

38
37
36
35
34
33

32

31
30
29

28
27

26

21

RIEN = RS232

19

M2

18

M1

17

M0

24

EC

C6

100pFC7100pF

14

V

CC

2

V

EE

C8

100pF

13

121138

LTC1344

21

LATCHLATCH

DCE/

DTE

19171815161097645

20 22 23 24 1

V

CC

M0M1M2

DB-25 FEMA;E

CONNECTOR

25

TM A (142)

3

RXD A (104)

16

RXD B

17

RXC A (115)

9

RXC B

15

TXC A (114)

12

TXC B

24

SCTE A (113)

11

SCTE B

2

TXD A (103)

14

TXD B

18

LL A (141)

7

SGND (102)

1

SHIELD (101)

5

CTS A (106)

13

CTS B

6

DSR A (107)

22

DSR B/RI A (125)

8

DCD A (109)

10

DCD B

20

DTR A (108)

23

DTR B

4

RTS A (105)

19

RTS B

21

RL A (140)

1343 F36

24

Figure 36. Controller-Selectable Multiprotocol DCE Port with RI and DB-25 Connector

LTC1343

U

WUU

APPLICATIONS INFORMATION

V

CC

5V

DTE_TXD/DCE_RXD

DTE_SCTE/DEC_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/ DCE_RTS

1µF

1µF

C1

100k

C9

100k

R1

C12
1µF

R2

C5
1µF

1
2

+

4

CHARGE

3
8

LTC1343

5

6

7

9

10
12
13

14

15

16
20

CTRL

22

LATCH

11

INVERT

25

423 SET

40

GND

23

LB

1
2

+

4

CHARGE

3
8

LTC1343

5

6

7

9

10
12
13

14

15

16
20

CTRL

22

LATCH

11

INVERT

25

423 SET

40

GND

23

LB

+

C3
1µF

+

+

C11
1µF

V

CC

+

V

CC

LB

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

DCE

DCE

44
43

42

41

39
38

37
36
35
34
33

32
31
30
29
28
27

26
21
19

M2

18

M1

17

M0

24

EC

44
43

42

41

39

38
37
36
35
34
33

32
31
30
29

28
27

26
21
19

M2

18

M1

17

M0

24

EC

C6

100pFC7100pF

14

V

CC

+

C2
1µF

2

V

EE

C4

+

3.3µF

V

CC

V

CC

+

C10
1µF

C13

3.3µF

+

V

CC

C8

100pF

13

121138

V

V

V

CC

CC

CC

R3
10k

CABLE WIRING FOR MODE SELECTION

MODE PIN 18 PIN 21

V.35 PIN 7 PIN 7

EIA-530, RS449, NC PIN 7

V.36, X.21

RS232 PIN 7 NC

R4
10k

R5
10k

LTC1344

LATCH

DCE/

DTE

20 22 23 24 1

19171815161097645

V

CC

CABLE WIRING FOR DTE/DCE
SELECTION

MODE PIN 25

DTE PIN 7
DCE NC

M0M1M2

21

DB-25 CONNECTOR

2

TXD A

14

TXD B

24

SCTE A

11

SCTE B

15

TXC A

12

TXC B

17

RXC A

9

RXC B

3

RXD A

16

RXD B

7

SGND

1

SHIELD

25

DCE/DTE

21

M1

18

M0

4

RTS A

19

RTS B

20

DTR A

23

DTR B

8

DCD A

10

DCD B

6

DSR A

22

DSR B

5

CTS A

13

CTS B

DTE DCE

RXD A
RXD B
RXC A
RXC B

TXC A
TXC B

SCTE A
SCTE B
TXD A
TXD B

CTS A
CTS B
DSR A
DSR B

DCD A
DCD B
DTR A
DTR B
RTS A
RTS B

1343 F37

Figure 37. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector

25

LTC1343

U

WUU

APPLICATIONS INFORMATION

V

CC

5V

DTE_LL/DCE_TM

DTE_TXD/DCE_RXD

DTE_SCTE/DEC_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_TM/DCE_LL

DTE_RL/DCE_RI

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

DTE_RI/DCE_RL

LATCH

DCE/DTE

1µF

1µF

100k

C9

100k

1
2

+

C1

4

CHARGE

3
8

C5

C12
1µF

1µF

R1

+

R2

10
12
13

14

15

16
20
22
11
25

40
23

10
12
13

14

15

16
20
22
11
25

40
23

5

6

7

9

1
2

4
3
8

5

6

7

9

LTC1343

CTRL
LATCH
INVERT
423 SET

GND
LB

CHARGE

LTC1343

CTRL
LATCH
INVERT
423 SET

GND
LB

+

C3
1µF

+

+

C11
1µF

V

CC

+

V

CC

LB

M2
M1
M0

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

DCE

DCE

44
43

42

41

39

38
37
36
35
34
33

32
31
30
29
28
27

26
21
19

M2

18

M1

17

M0

24

EC

44
43

42

41

39

38
37
36
35
34
33

32
31
30
29

28
27

26
21
19

M2

18

M1

17

M0

24

EC

C6

100pFC7100pF

14

V

CC

+

C2
1µF

2

V

EE

C4

+

3.3µF

V

CC

+

C10
1µF

C13

+

3.3µF

V

CC

C8

100pF

13

121138

LTC1344

21

LATCHLATCH

DCE/

DTE

20 22 23 24 1

19171815161097645

M0M1M2

µDB-26 CONNECTOR

DTE DCE

18

LL A

2

TXD A

14

TXD B

24

SCTE A

11

SCTE B

15

TXC A

12

TXC B

17

RXC A

9

RXC B

3

RXD A

16

RXD B

25

TM A

7

SGND

1

SHIELD

21

RL A

4

RTS A

19

RTS B

20

DTR A

23

DTR B

8

DCD A

10

DCD B

6

DSR A

22

DSR B

5

CTS A

13

CTS B

26

RI A

TM A

RXD A
RXD B
RXC A
RXC B

TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B

LL A

RI A
CTS A

CTS B
DSR A
DSR B

DCD A
DCD B
DTR A
DTR B
RTS A
RTS B

RL A

1343 F38

26

Figure 38. Controller-Selectable Multiprotocol DTE/DCE Port with DB-26 Connector

LTC1343

U

WUU

APPLICATIONS INFORMATION

V

CC

5V

DTE_TXD/DCE_RXD

DTE_SCTE/DEC_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_LL/DCE_LL

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

1µF

1µF

C1

100k

C9

100k

C12
1µF

R2

C5
1µF

R1

1
2

+

4

CHARGE

3
8

LTC1343

5

6

7

9

10
12
13

14

15

16
20

CTRL

22

LATCH

11

INVERT

25

423 SET

40

GND

23

LB

1
2

+

4

CHARGE

3
8

LTC1343

5

6

7

9

10
12
13

14

15

16
20

CTRL

22

LATCH

11

INVERT

25

423 SET

40

GND

23

LB

+

C3
1µF

+

+

C11
1µF

V

CC

+

V

CC

LB

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

PUMP

D1

D2

D3

D4

R1

R2

R3

R4

DCE

DCE

44
43

42

41

39
38

37
36
35
34
33

32
31
30
29
28
27

26
21
19

M2

18

M1

17

M0

24

EC

44
43

42

41

39

38
37
36
35
34
33

32
31
30
29

28
27

26
21
19

M2

18

M1

17

M0

24

EC

C6

100pFC7100pF

14

V

CC

+

C2
1µF

2

V

EE

C4

+

3.3µF

V

CC

V

CC

+

C10
1µF

C13

+

3.3µF

V

CC

C8

100pF

13

121138

V

V

V

CC

CC

CC

R3
10k

CABLE WIRING FOR MODE SELECTION

MODE PIN 18 PIN 21

V.35 PIN 7 PIN 7

EIA-530, RS449, NC PIN 7

V.36, X.21

RS232 PIN 7 NC

R4
10k

R5
10k

LTC1344

LATCH

DCE/

DTE

19171815161097645

20 22 23 24 1

V

CC

CABLE WIRING FOR DTE/DCE
SELECTION

MODE PIN 25

DTE PIN 7
DCE NC

M0M1M2

21

µDB-26 CONNECTOR

DTE DCE

2

TXD A

14

TXD B

24

SCTE A

11

SCTE B

15

TXC A

12

TXC B

17

RXC A

9

RXC B

3

RXD A

16

RXD B

7

SGND

1

SHIELD

25

DCE/DTE

21

M1

18

M0

4

RTS A

19

RTS B

20

DTR A

23

DTR B

8

DCD A

10

DCD B

6

DSR A

22

DSR B

5

CTS A

13

CTS B

26

LL B

RXD A
RXD B
RXC A
RXC B

TXC A
TXC B

SCTE A
SCTE B
TXD A
TXD B

CTS A
CTS B
DSR A
DSR B

DCD A
DCD B
DTR A
DTR B
RTS A
RTS B

LL B

1343 F39

Figure 39. Cable-Selectable Multiprotocol DTE Port with DB-26 Connector

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC1343

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

GW Package

44-Lead Plastic SSOP (Wide 0.300)

(LTC DWG # 05-08-1642)

17.805 – 18.059*
(0.701 – 0.711)

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

10.160 – 10.414
(0.400 – 0.410)

7.417 – 7.595**
(0.292 – 0.299)

0.254 – 0.406

(0.010 – 0.016)

0.231 – 0.3175

(0.0091 – 0.0125)

NOTE: DIMENSIONS ARE IN MILLIMETERS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

*

SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

× 45°

0.610 – 1.016

(0.024 – 0.040)

2.463 – 2.641

(0.097 – 0.104)

0° – 8° TYP

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

**

FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

123456789101112131415161718192021

0.800

(0.0315)

BSC

0.304 – 0.431

(0.012 – 0.017)

22

2.286 – 2.387

(0.090 – 0.094)

0.127 – 0.292

(0.005 – 0.0115)

G44 SSOP 1098

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1321 Dual RS232/RS485 Transceiver 2 RS232 Driver/Receiver Pairs or 2 RS485 Driver/Receiver Pairs
LTC1334 Single 5V RS232/RS485 Multiprotocol Transceiver 2 RS232 Driver/Receiver or 4 RS232 Driver/Receiver Pairs
LTC1344/LTC1344A Software-Selectable Cable Terminator Perfect for Terminating the LTC1343
LTC1345 Single Supply V.35 Transceiver 3 Driver/3 Receiver for Data and Clock Signals
LTC1346A Dual Supply V.35 Transceiver 3 Driver/3 Receiver for Data and Clock Signals
LTC1543 Software-Selectable Multiprotocol Transceiver 3 Driver/3 Receiver for Data and Clock Signals
LTC1544 Software-Selectable Multiprotocol Transceiver 4 Driver/4 Receiver for Control Signals Including LL
LTC1545 Software-Selectable Multiprotocol Transceiver 5 Driver/5 Receiver for Control Signals Including LL, RL, TM

28

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

1343fa LT/TP 0899 2K REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1996