Datasheet LTC1285, LTC1288 Datasheet (Linear Technology)

Download

Page 1

FEATURES

LTC1285/LTC1288

3V Micropower Sampling

12-Bit A/D Converters in

SO-8 Packages

DESCRIPTION

■

12-Bit Resolution

■

8-Pin SO Plastic Package

■

Low Cost

■

Low Supply Current: 160µA Typ

■

Auto Shutdown to 1nA Typ

■

Guaranteed ±3/4LSB Max DNL

■

Single Supply 3V to 6V Operation

■

Differential Inputs (LTC1285)

■

2-Channel MUX (LTC1288)

■

On-Chip Sample-and-Hold

■

100µs Conversion Time

■

Sampling Rates:

7.5ksps (LTC1285)

6.6ksps (LTC1288)

■

I/O Compatible with SPI, Microwire, etc.

APPLICATIONS

■

Pen Screen Digitizing

■

Battery-Operated Systems

■

Remote Data Acquisition

■

Isolated Data Acquisition

■

Battery Monitoring

■

Temperature Measurement

The LTC®1285/LTC1288 are 3V micropower, 12-bit, successive approximation sampling A/D converters. They typically draw only 160µA of supply current when con- verting and automatically power down to a typical supply current of 1nA whenever they are not performing conversions. They are packaged in 8-pin SO packages and operate on 3V to 6V supplies. These 12-bit, switchedcapacitor, successive approximation ADCs include sample-and-holds. The LTC1285 has a single differential analog input. The LTC1288 offers a software selectable 2-channel MUX.

On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three wires. This, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers.

These circuits can be used in ratiometric applications or with an external reference. The high impedance analog inputs and the ability to operate with reduced spans (to

1.5V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIONS N

12µW, S0-8 Package, 12-Bit ADC

Samples at 200Hz and Runs Off a 3V Supply

3V1µF

CLK

OUT

SERIAL DATA LINK

ANALOG INPUT

0V TO 3V RANGE

REF

+IN

LTC1285

–IN

GND

CS/SHDN

MPU

(e.g., 8051)

P1.4 P1.3 P1.2

LTC1285/88 • TA01

Supply Current vs Sample Rate

1000

TA = 25°C

= 2.7V

= 2.5V

REF

= 120kHz

CLK

100

SUPPLY CURRENT (µA)

0.1

1 10 100

SAMPLE FREQUENCY (kHz)

LTC1285/88 • TA02

Page 2

LTC1285/LTC1288

1

2

3

8

7

6

TOP VIEW

CC

CLK D

OUT



REF

 +IN –IN



GND

S8 PACKAGE

8-LEAD PLASTIC SO

CS/SHDN

ABSOLUTE MAXIMUM RATINGS

(Notes 1 and 2)

Supply Voltage (VCC) to GND................................... 12V

Voltage

Analog and Reference ................ –0.3V to V

+ 0.3V

Digital Inputs......................................... –0.3V to 12V

Digital Output ............................. –0.3V to V

+ 0.3V

PACKAGE/ORDER INFORMATION



ORDER PART

NUMBER

LTC1285CN8

ORDER PART

NUMBER

LTC1288CN8

+IN –IN

GND

CS/SHDN

CH0 CH1 GND

TOP VIEW

1



REF

2 3 4

N8 PACKAGE 8-LEAD PDIP

= 150°C, θJA = 130°C/W

JMAX

TOP VIEW

1



2 3 4

N8 PACKAGE 8-LEAD PDIP

= 150°C, θJA = 130°C/W

JMAX

8 7 6 5



8 7 6 5



CLK



OUT



CS/SHDN 

CC (VREF)

CLK



OUT

Power Dissipation.............................................. 500mW

Operating Temperature Range .................... 0°C to 70°C

Storage Temperature Range ................. – 65°C to 150°C

Lead Temperature (Soldering, 10 sec.)................ 300°C

ORDER PART

NUMBER

LTC1285CS8

PART MARKING

1285C

ORDER PART

NUMBER

LTC1288CS8

PART MARKING

1288C

CS/SHDN

CH0 CH1

GND

= 150°C, θJA = 175°C/W

JMAX

TOP VIEW

1

2

3



S8 PACKAGE

8-LEAD PLASTIC SO

= 150°C, θJA = 175°C/W

JMAX

8

7

6

CC (VREF)

CLK D

OUT



Consult factory for Industrial and Military grade parts.

UUUU

RECOM ENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage (Note 3) LTC1285 2.7 6 V

LTC1288 2.7 6 V

CLK

CYC

hDI

suCS

Clock Frequency VCC = 2.7V (Note 4) 120 kHz Total Cycle Time LTC1285, f

LTC1288, f

= 120kHz 125.0 µs

CLK

= 120kHz 141.5 µs

CLK

Hold Time, DIN After CLK↑ VCC = 2.7V 450 ns Setup Time CS↓ Before First CLK↑ (See Operating Sequence) LTC1285, VCC = 2.7V 2 µs

LTC1288, VCC = 2.7V 2 µs

suDI

WHCLK

WLCLK

WHCS

WLCS

Setup Time, DIN Stable Before CLK↑ VCC = 2.7V 600 ns CLK High Time VCC = 2.7V 3.5 µs CLK Low Time VCC = 2.7V 3.5 µs CS High Time Between Data Transfer Cycles VCC = 2.7V 2 µs CS Low Time During Data Transfer LTC1285, f

LTC1288, f

= 120kHz 123.0 µs

CLK

= 120kHz 139.5 µs

CLK

Page 3

LTC1285/LTC1288

UW U

CONVERTER AND MULTIPLEXER CHARACTERISTICS

LTC1285 LTC1288

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 12 12 Bits Integral Linearity Error (Note 6) ● ±3/4 ±2 ±3/4 ±2 LSB Differential Linearity Error ● ±1/4 ±3/4 ±1/4 ±3/4 LSB Offset Error ● ±3/4 ±3 ±3/4 ±3 LSB Gain Error ● ±2 ±8 ±2 ±8 LSB Analog Input Range (Note 7 and 8) ● V REF Input Range (LTC1285) 2.7 ≤ VCC ≤ 6V V

(Notes 7, 8, and 9) V Analog Input Leakage Current (Note 10) ● ±1 ±1 µA

–0.05V to VCC + 0.05V

1.5V to VCC + 0.05V

(Note 5)

DIGITAL AND DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SOURCE

SINK

REF

High Level Input Voltage VCC = 3.6V ● 2V Low Level Input Voltage VCC = 2.7V ● 0.8 V High Level Input Current VIN = V Low Level Input Current VIN = 0V ● –2.5 µA High Level Output Voltage VCC = 2.7V, IO = 10µA ● 2.4 2.64 V

Low Level Output Voltage VCC = 2.7V, IO = 400µA ● 0.4 V Hi-Z Output Leakage CS = High ● ±3 µA Output Source Current V Output Sink Current V Reference Input Resistance CS = V

(LTC1285) CS = V Reference Current (LTC1285) CS = V

Supply Current CS = V

= 2.7V, IO = 360µA ● 2.1 2.30 V

= 0V –10 mA

OUT

= V

OUT

IH IL

≥ 640µs, f

CYC

= 134µs, f

CYC

LTC1285, t LTC1285, t

LTC1288, t LTC1288, t

≤ 25kHz 50 µA

CLK

= 120kHz ● 50 70 µA

CLK

≥ 640µs, f

CYC

= 134µs, f

CYC

≥ 720µs, f

CYC

= 150µs, f

CYC

≤ 25kHz 150 µA

CLK

= 120kHz ● 160 320 µA

CLK

≤ 25kHz 200 µA

CLK

= 120kHz ● 210 390 µA

CLK

(Note 5)

● 2.5 µA

15 mA

2700 MΩ

54 kΩ

● 0.001 2.5 µA

● 0.001 ±3.0 µA

DYNAMIC ACCURACY

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

S/(N +D) Signal-to-Noise Plus Distortion Ratio 1kHz Input Signal 67 dB THD Total Harmonic Distortion (Up to 5th Harmonic) 1kHz Input Signal –80 dB SFDR Spurious-Free Dynamic Range 1kHz Input Signal 88 dB

Peak Harmonic or Spurious Noise 1kHz Input Signal –88 dB

= 7.5kHz (LTC1285), f

SMPL

= 6.6kHz (LTC1288) (Note 5)

SMPL

Page 4

LTC1285/LTC1288

FREQUENCY (kHz)

SUPPLY CURRENT (µA)

60 80

LTC1285/88 • TPC03

100

0.002

120

TA = 25°C V

= 2.7V

REF

= 2.5V

CS = 0 (AFTER CONVERSION)

CS = V

AC CHARACTERISTICS

(Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SMPL

SMPL(MAX)

Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles Maximum Sampling Frequency LTC1285 ● 7.5 kHz

LTC1288 ● 6.6 kHz

CONV

dDO

dis

hDO

Conversion Time See Operating Sequence 12 CLK Cycles Delay Time, CLK↓ to D Delay Time, CS↑ to D Delay Time, CLK↓ to D Time Output Data Remains Valid After CLK↓ C D

Fall Time See Test Circuits ● 60 180 ns

OUT

Rise Time See Test Circuits ● 80 180 ns

OUT

Data Valid See Test Circuits ● 600 1500 ns

OUT

Hi-Z See Test Circuits ● 220 660 ns

OUT

Enable See Test Circuits ● 180 500 ns

OUT

= 100pF 520 ns

LOAD

Input Capacitance Analog Inputs, On Channel 20 pF

Analog Inputs, Off Channel 5 pF Digital Input 5 pF

The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired.

Note 2: All voltage values are with respect to GND. Note 3: These devices are specified at 3V. For 5V specified devices, see

LTC1286 and LTC1298. Note 4: Increased leakage currents at elevated temperatures cause the sample-and-hold to droop, therefore it is recommended that f at 70° andf

Note 5: VCC = 2.7V, V

≥ 1kHz at 25°C.

CLK

REF

= 2.5V and CLK = 120kHz unless otherwise

≥ 75kHz

CLK

specified. Note 6: Linearity error is specified between the actual end points of the

A/D transfer curve.

Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below GND or one diode drop above V

. This spec allows 50mV forward

bias of either diode for 2.7V ≤ VCC ≤ 6V. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV the output code will be correct. To achieve an absolute 0V to 2.7V input voltage range will therefore require a minimum supply voltage of

2.650V over initial tolerance, temperature variations and loading. For 2.7V < V

≤ 6V, reference and analog input range cannot exceed 6.05V. If

reference and analog input range are greater than 6.05V, the output code will not be guaranteed to be correct.

Note 8: The supply voltage range for the LTC1285 and the LTC1288 is from 2.7V to 6V.

Note 9: Recommended operating conditions Note 10: Channel leakage current is measured after the channel selection.

TYPICAL PERFORMANCE CHARACTERISTICS

1000

100

SUPPLY CURRENT (µA)

Supply Current vs Sample Rate

TA = 25°C

= 2.7V

= 2.5V

REF

= 120kHz

CLK

0.1 SAMPLE RATE (kHz)

LTC1288

LTC1285

110

LTC1285/88 • TPC01

Supply Current vs Temperature

250

200

150

100

SUPPLY CURRENT (µA)

VCC = 2.7V

= 2.5V

REF

= 120kHz

CLK

–15

–55

–35 125

TEMPERATURE (°C)

SMPL

LTC1288

LTC1285

= 6.6kHz

= 7.5kHz

105

LTC1285/88 • TPC02

Shutdown Supply Current vs Clock Rate with CS High and CS Low

Page 5

REFERENCE VOLTAGE (V)

1.0

CHANGE IN GAIN (LSB)

–1

–3

–4

–5

–10

–7

1.4

1.8

2.0 2.8

LTC1285/88 • TPC09

–2

–8

–9

–6

1.2 1.6

2.2

2.4

2.6

TA = 25°C V

= 2.7V

CLK

= 120kHz

SMPL

= 7.5kHz

REFERENCE VOLTAGE (V)

0.5

CHANGE IN OFFSET (LSB = 1/4096 × V

REF

)

0.5

1.0

1.5

2.0

2.5

3.0

1.0 1.5 2.0 2.5

LTC1285/88 • TPC06

3.0

TA = 25°C V

= 2.7V

CLK

= 120kHz

SMPL

= 7.5kHz

TYPICAL PERFORMANCE CHARACTERISTICS

LTC1285/LTC1288

Reference Current vs Sample Rate (LTC1285)

= 25°C

= 2.7V

= 2.5V

REF

= 120kHz

CLK

35 30 25 20 15

REFERENCE CURRENT (µA)

5 0

SAMPLE RATE (kHz)

Change in Offset vs Temperature

0.20 VCC = 2.7V

= 2.5V

0.15

REF

= 120kHz

CLK

= f

0.10

SMPL

SMPL(MAX)

0.05

–0.05

–0.10

CHANGE IN OFFSET (LSB)

–0.15

–0.20

10 20 40

TEMPERATURE (°C)

LTC1285/88 • TPC04

50 60 70

LTC1285/88 • TPC07

Reference Current vs Temperature

VCC = 2.7V

= 2.5V

REF

= 120kHz

CLK

51 50 49 48 47 46

REFERENCE CURRENT (µA)

45 44 43

SMPL

–35 5

–55

= 7.5kHz

–15

TEMPERATURE (°C)

45 125

Change in Linearity vs Reference Voltage

0.50 TA = 25°C

0.45

= 2.7V

= 120kHz

CLK

0.40

0.35

0.30

0.25

0.20

0.15

CHANGE IN LINEARITY (LSB)

0.10

0.05

1.0

= 7.5kHz

SMPL

1.2 1.6

1.4 REFERENCE VOLTAGE (V)

2.0 2.8

2.2

1.8

105

LTC1285/88 • TPC05

2.4

2.6

LTC1285/88 • TPC08

Change in Offset vs Reference Voltage



Change in Gain vs Reference Voltage

Differential Nonlinearity vs Code

TA = 25°C

= 2.7V

= 2.5V

REF

= 120kHz

0.5

CLK

–0.5

DIFFERENTIAL NONLINEARITY ERROR (LSB)

–1

512 1024 1536 2048

2560 3072 3584 4096

CODE

LTC1285/88 • TPC11

Effective Bits and S/(N + D) vs Input Frequency

12 11 10

9 8 7 6

5 4 3

TA = 25°C

= 2.7V

EFFECTIVE NUMBER OF BITS (ENOBs)

= 120kHz

CLK

INPUT FREQUENCY (kHz)

10 100

LTC1285/88 • TPC12

S/(N + D) (dB) 68 62 56 50

Page 6

LTC1285/LTC1288

INPUT FREQUENCY (Hz)

ATTENUATION (%)

40 50

1k 100k 1M 10M

LTC1285/86 • TPC15

100

10k

TA = 25°C V

= 2.7V

REF

= 2.5V

SMPL

= f

SMPL(MAX)

RIPPLE FREQUENCY (Hz)

–80

FEEDTHROUGH (dB)

–60

–40 –50

–20

–90

–70

–30

–10

1k 100k 1M 10M

LTC1285/86 • TPC18

–100

10k

TA = 25°C V

= 2.7V (V

RIPPLE

= 1mV)

REF

= 2.5V

CLK

= 120kHZ

SUPPLY VOLTAGE (V)

2.5

100

CLOCK FREQUENCY (kHz)

120

160

180

200

300

240

3.5

4.5

5.0

LTC1285/88 • TPC21

140

260

280

220

3.0

4.0

5.5

6.0

TA = 25°C V

REF

= 2.5V

TYPICAL PERFORMANCE CHARACTERISTICS

Spurious-Free Dynamic Range vs Input Frequency

100

90 80 70 60 50 40 30

TA = 25°C

= 2.7V

= 2.5V

REF

SPURIOUS-FREE DYNAMIC RANGE (dB)

= f

SMPL

SMPL(MAX)

10 100

INPUT FREQUENCY (kHz)

4096 Point FFT Plot

TA = 25°C

= 2.7V

–20

–40

–60

= 2.5V

REF

= 3.05kHz

= 120kHz

CLK

SMPL

= 7.5kHz

LTC1285/88 • G13

S/(N + D) vs Input Level

TA = 25°C

= 2.7V

= 2.5V

REF

= 1kHz

SIGNAL-TO-NOISE PLUS DISTORTION (dB)

= f

SMPL

SMPL(MAX)

–40 0

–45

–35

–30

INPUT LEVEL (dB)

–25

–20

–15

LTC1285/88 • TPC14

Intermodulation Distortion

TA = 25°C

= 2.7V

–20

–40

–60

= 2.5V

REF

f1 = 2.05kHz f2 = 3.05kHz

= 7.5kHz

SMPL

–10

–5

Attenuation vs Input Frequency

Power Supply Feedthrough vs Ripple Frequency

–80

MAGNITUDE (dB)

–100

–120

1.0 2.0

0.5 1.5 FREQUENCY (kHz)

Maximum Clock Frequency vs Source Resistance

200 180 160 140

120 100

80 60

CLOCK FREQUENCY (kHz)

40 20

0.1

+INPUTV

–INPUT

–

SOURCE

SOURCE RESISTANCE (kΩ)

–80

MAGNITUDE (dB)

–100

3.0

2.5

TA = 25°C V V

110

LTC1285/88 • G19

3.5

LTC1285/88 • TPC16

= 2.7V

= 2.5V

REF

4.0

–120

10000

1000

S & H ACQUISITION TIME (ns)

100

3.0

0.5 1.5

1.0 2.0 FREQUENCY (kHz)

2.5

LTC1285/88 • TPC17

Sample-and-Hold Acquisition Time vs Source Resistance

TA = 25°C

= 2.7V

= 2.5V

REF

SOURCE

1

SOURCE RESISTANCE (Ω)

100 100010 10000

LTC1285/88 • TPC20

3.5

+INPUTV

–INPUT

4.0

Maximum Clock Frequency vs Supply Voltage

Page 7

TEMPERATURE (°C)

–55

LEAKAGE CURRENT (nA)

100

1000

105

LTC1285/88 • TPC24

0.1

0.01 –15

–35 125

VCC = 2.7V V

REF

= 2.5V

ON CHANNEL

OFF CHANNEL

TYPICAL PERFORMANCE CHARACTERISTICS

LTC1285/LTC1288

Minimum Clock Frequency for 0.1 LSB Error vs Temperature

120

VCC = 2.7V

= 2.5V

REF

100

CLOCK FREQUENCY (kHz)

2 0

20 30

TEMPERATURE (°C)

60 70

LTC1285/88 • TPC22

Digital Input Logic Threshold vs Supply Voltage

3.0 TA = 25°C

2.5

2.0

1.5

1.0

0.5

DIGITAL INPUT LOGIC THRESHOLD VOLTAGE (V)

2.5

3.0 3.5 SUPPLY VOLTAGE (V)

UUU

PIN FUNCTIONS

LTC1285

(Pin 1): Reference Input. The reference input defines

REF

the span of the A/D converter.

IN+ (Pin 2): Positive Analog Input. IN– (Pin 3): Negative Analog Input. GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane. CS/SHDN (Pin 5): Chip Select Input. A logic low on this

input enables the LTC1285. A logic high on this input disables and powers down the LTC1285.

Input Channel Leakage Current vs Temperature

4.5 5.5 6.0

4.0 5.0

LTC1285/88 • TPC23

LTC1288

CS/SHDN (Pin 1): Chip Select Input. A logic low on this

input enables the LTC1288. A logic high on this input disables and powers down the LTC1288.

CH0 (Pin 2): Analog Input. CH1 (Pin 3): Analog Input. GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane. DIN (Pin 5): Digital Data Input. The multiplexer address is

shifted into this input.

(Pin 6): Digital Data Output. The A/D conversion

OUT

result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial

data transfer and determines conversion speed. VCC (Pin 8): Power Supply Voltage. This pin provides

power to the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane.

(Pin 6): Digital Data Output. The A/D conversion

OUT

result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the

serial data transfer and determines conversion speed.

VCC/V

(Pin 8): Power Supply and Reference Voltage.

REF

This pin provides power and defines the span of the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane.

Page 8

LTC1285/LTC1288

OUT

LTC1285/88 • TC02

BLOCK DIAGRAM

VCC (VCC/V

REF

CS/SHDN

)

(DIN)



CLK

IN+ (CH0)

–



TEST CIRCUITS

Load Circuit for t

SHUTDOWN CIRCUIT

SAMPLE

(CH1)

GND

PIN NAMES IN PARENTHESES REFER TO THE LTC1288

, tr and t

dDO

BIAS AND 

–

MICROPOWER COMPARATOR

CAPACITIVE DAC

Voltage Waveforms for D

REF

SERIAL PORT

SAR

LTC1285/88 • BD

OUT

Rise and Fall Times, tr, t

OUT

1.4V

OUT

100pF

Voltage Waveforms for D

CLK

OUT

dDO

OUT

TEST POINT

LTC1285/88 • TC01

Delay Times, t

LTC1285/88 • TC03

dDO

Load Circuit for t

TEST POINT

OUT

100pF

dis

and t

VCC t

WAVEFORM 2, t

dis

WAVEFORM 1

dis

LTC1285/88 • TC04



Page 9



TEST CIRCUITS

LTC1285/LTC1288

Voltage Waveforms for t

OUT

WAVEFORM 1

(SEE NOTE 1)

OUT

WAVEFORM 2

(SEE NOTE 2)

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.

LTC1288

dis

START

dis

LTC1285

90%

10%

LTC1285/88 • TC05

CLK

OUT

Voltage Waveforms for t

B11

LTC1285/88 • TC06

CLK

OUT

1234

B11

LTC1285/88 • TC07

Page 10

LTC1285/LTC1288

WUU

APPLICATION INFORMATION

OVERVIEW

The LTC1285 and LTC1288 are 3V micropower, 12-bit, successive approximation sampling A/D converters. The LTC1285 typically draws 160µA of supply current when sampling at 7.5kHz while the LTC1288 nominally consumes 210µ A of supply current when sampling at 6.6 kHz. The extra 50µ A of supply current on the LTC1288 comes from the reference input which is intentionally tied to the supply. Supply current drops linearly as the sample rate is reduced (see Supply Current vs Sample Rate). The ADCs automatically power down when not performing conversions, drawing only leakage current. They are packaged in 8-pin SO and DIP packages. The LTC1285 and LTC1288 operate on a single supply from 2.7V to 6V.

Both the LTC1285 and the LTC1288 contain a 12-bit, switched-capacitor ADC, a sample-and-hold, and a serial port (see Block Diagram). Although they share the same

basic design, the LTC1285 and LTC1288 differ in some respects. The LTC1285 has a differential input and has an external reference input pin. It can measure signals floating on a DC common-mode voltage and can operate with reduced spans to 1.5V. Reducing the spans allows it to achieve 366µ V resolution. The LTC1288 has a two-channel input multiplexer and can convert either channel with respect to ground or the difference between the two. The reference input is tied to the supply pin.

SERIAL INTERFACE

The 2-channel LTC1288 communicates with microprocessors and other external circuitry via a synchronous, half duplex, 4-wire serial interface. The single channel LTC1285 uses a 3-wire interface (see Operating Sequence in Figures 1 and 2).

CYC

DATA

POWER DOWN

HI-Z

NULL 

BIT

B11

B10 B9 B8

POWER DOWN

DATA

B11*

HI-Z

LTC1285/88 • F01

B10

B9B8

suCS

CLK

NULL 

OUT

CLK

OUT

HI-Z

BIT

SMPL

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,  THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY.

suCS

NULL

HI-Z

BIT

SMPL

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,  THE ADC WILL OUTPUT ZEROS INDEFINITELY.

: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT

DATA

 BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.

B10B11

(MSB)

B10B11

(MSB)

B8B9

CONV

B4 B3 B2 B1

B0*

CYC

B2 B2B1

B3 B3 B4 B5 B6 B7

B0 B1

Figure 1. LTC1285 Operating Sequence

Page 11

LTC1285/LTC1288

WUU

APPLICATION INFORMATION

MSB-First Data (MSBF = 0)

suCS

CLK

OUT

HI-Z

SGL/

DIFF

suCS

SGL/

DIFF

SMPL

ODD/ SIGN

MSBF

HI-Z

SMPL

MSBF

NULL

BIT

NULL

BIT

(MSB)

B8B9

CYC

B8B9

B10B11

CONV

DON’T CARE

CONV

START

MSB-First Data (MSBF = 1)

CLK

START

OUT

CYC

B2B2B1 B0 B1

B4 B3 B2 B1

DON’T CARE

B0*

DATA

B3 B4 B5 B6 B7

POWER DOWN

HI-Z

POWER DOWN

DATA

HI-Z

B11



B10

B9B8

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,  THE ADC WILL OUTPUT ZEROS INDEFINITELY.

: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT

DATA

 BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.

Figure 2. LTC1288 Operating Sequence Example: Differential Inputs (CH+, CH–)

LTC1285/88 • F02

Page 12

LTC1285/LTC1288

ODD/ SIGN

MSBFSTART

MUX

ADDRESS

MSB FIRST/

LSB FIRST

LTC1285/88 • AI02

SGL/

DIFF

WUU

APPLICATION INFORMATION

Data Transfer

The CLK synchronizes the data transfer with each bit being transmitted on the falling CLK edge and captured on the rising CLK edge in both transmitting and receiving systems.

The LTC1285 does not require a configuration input word and has no DIN pin. A falling CS initiates data transfer as shown in the LTC1285 operating sequence. After CS falls the second CLK pulse enables D A/D conversion result is output on the D CS high resets the LTC1285 for the next data exchange.

The LTC1288 first receives input data and then transmits back the A/D conversion result (half duplex). Because of the half duplex operation, DIN and D together allowing transmission over just 3 wires: CS, CLK and DATA (DIN/D

OUT

Data transfer is initiated by a falling chip select (CS) signal. After CS falls the LTC1288 looks for a start bit. After the start bit is received, the 3-bit input word is shifted into the DIN input which configures the LTC1288 and starts the conversion. After one null bit, the result of the conversion is output on the D

line. At the end of the data exchange

OUT

CS should be brought high. This resets the LTC1288 in preparation for the next data exchange.

. After one null bit the

OUT

line. Bringing

OUT

may be tied

OUT

the rising edge of the clock. The input data words are defined as follows:

Start Bit

The first “logical one” clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer. The LTC1288 will ignore all leading zeros which precede this logical one. After the start bit is received, the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle.

Multiplexer (MUX) Address

The bits of the input word following the START bit assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of the following tables. In single-ended mode, all input channels are measured with respect to GND.

DIN 1 DIN 2

SHIFT MUX

ADDRESS IN

1 NULL BIT

1 D

OUT

SHIFT A/D CONVERSION RESULT OUT

OUT

LTC1285/88 • AI01

Input Data Word

The LTC1285 requires no DIN word. It is permanently configured to have a single differential input. The conversion result appears on the D

line. The data format is

OUT

MSB first followed by the LSB sequence. This provides easy interface to MSB or LSB first serial ports. For MSB first data the CS signal can be taken high after B0 (see Figure 1). The LTC1288 clocks data into the DIN input on

LTC1288 Channel Selection

SINGLE-ENDED

MUX MODE

DIFFERENTIAL

MUX MODE



MUX ADDRESS

SGL/DIFF

1 1 0 0

ODD/SIGN

CHANNEL #

0

+

1



0

+

–

1

GND



–

+

–



LTC1285/88 • AI03

MSB First/LSB First (MSBF)

The output data of the LTC1288 is programmed for MSB first or LSB first sequence using the MSBF bit. When the MSBF bit is a logical one, data will appear on the D

line in MSB first format. Logical zeros will be

OUT

filled in indefinitely following the last data bit. When the MSBF bit is a logical zero, LSB first data will follow the normal MSB first data on the D

line (see Operating

OUT

Sequence).

Page 13

LTC1285/LTC1288

SAMPLE FREQUENCY (kHz)

0.1

SUPPLY CURRENT (µA)

100

1000

1 10 100

LTC1285/88 • F04

TA = 25°C V

= 2.7V

REF

= 2.5V

CLK

= 120kHz

WUU

APPLICATION INFORMATION

Transfer Curve

The LTC1285/LTC1288 are permanently configured for unipolar only. The input span and code assignment for this conversion type are shown in the following figures.

Transfer Curve

1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 0

•

•

0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0

OUTPUT CODE

1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1LSB

1LSB =

REF

4096

REF

–2LSB

REF

Output Code

INPUT VOLTAGE

= 5.000V)



•

INPUT VOLTAGE

– 1LSB

REF

– 2LSB

REF



•



•



•

1LSB



REF



4.99878V

4.99756V

•

0.00122V 0V

LTC1285/88 • AI05

V –1LSB

LTC1285/88 • AI04

REF

either an input or an output. The LTC1288 will take control of the data line and drive it low on the 4th falling CLK edge after the start bit is received (see Figure 3). Therefore the processor port line must be switched to an input before this happens to avoid a conflict.

In the Typical Applications section, there is an example of interfacing the LTC1288 with D

and D

tied together to

OUT

the Intel 8051 MPU.

ACHIEVING MICROPOWER PERFORMANCE

With typical operating currents of 160µA and automatic

shutdown between conversions, the LTC1285/LTC1288 achieves extremely low power consumption over a wide range of sample rates (see Figure 4). The auto-shutdown allows the supply curve to drop with reduced sample rate.

Operation with DIN and D

Tied Together

OUT

The LTC1288 can be operated with DIN and D together. This eliminates one of the lines required to communicate to the microprocessor (MPU). Data is transmitted in both directions on a single wire. The processor pin connected to this data line should be configurable as

IN/DOUT

CLK

DATA

)

START SGL/DIFF ODD/SIGN MSBF B11 B10

MPU CONTROLS DATA LINE AND SENDS

MUX ADDRESS TO LTC1288

PROCESSOR MUST RELEASE DATA LINE AFTER 

4TH RISING CLK AND BEFORE THE 4TH FALLING CLK

Figure 3. LTC1288 Operation with DIN and D

2 3 4

OUT

tied

Figure 4. Automatic Power Shutdown Between Conversions Allows Power Consumption to Drop with Sample Rate

MSBF BIT LATCHED

BY LTC1288

•••

LTC1288 CONTROLS DATA LINE AND SENDS

A/D RESULT BACK TO MPU

LTC1288 TAKES CONTROL OF DATA LINE ON 4TH FALLING CLK

Tied Together

OUT

LTC1285/88 F03

Page 14

LTC1285/LTC1288

WUU

APPLICATION INFORMATION

Several things must be taken into account to achieve such a low power consumption.

Shutdown

The LTC1285/LTC1288 are equipped with automatic shutdown features. They draw power when the CS pin is low and shut down completely when that pin is high. The bias circuit and comparator powers down and the reference input becomes high impedance at the end of each conversion leaving the CLK running to clock out the LSB first data or zeroes (see Figures 1 and 2). If the CS is not running railto-rail, the input logic buffer will draw current. This current may be large compared to the typical supply current. To obtain the lowest supply current, bring the CS pin to ground when it is low and to supply voltage when it is high.

When the CS pin is high (= supply voltage), the converter is in shutdown mode and draws only leakage current. The status of the DIN and CLK input have no effect on supply current during this time. There is no need to stop DIN and CLK with CS = high; they can continue to run without drawing current.

Minimize CS Low Time

In systems that have significant time between conversions, lowest power drain will occur with the minimum CS low time. Bringing CS low, transferring data as quickly as possible, and then bringing it back high will result in the

TA = 25°C

= 2.7V

= 2.5V

REF

7 6 5 4 3 2

SUPPLY CURRENT (µA)

0.002 0

Figure 5. Shutdown Current with CS High is 1nA Typically, Regardless of the Clock. Shutdown Current with CS = Ground Varies From 1µA at 1kHz to 9µA at 120kHz

CS = 0 (AFTER CONVERSION)

CS = V

60 80

FREQUENCY (kHz)

100

LTC1285/88 • TPC03

120

lowest current drain. This minimizes the amount of time the device draws power. After a conversion the ADC automatically shuts down even if CS is held low (see Figures 1 and 2). If the clock is left running to clock out LSB-data or zero, the logic will draw a small current. Figure 5 shows that the typical supply current with CS = ground varies from 1µ A at 1kHz to 9µA at 120kHz. When CS = VCC, the logic is gated off and no supply current is drawn regardless of the clock frequency.

OUT

Capacitive loading on the digital output can increase power consumption. A 100pF capacitor on the D

OUT

can add more than 16.2µA to the supply current at a 120kHz clock frequency. An extra 16.2µ A or so of current goes into charging and discharging the load capacitor. The same goes for digital lines driven at a high frequency by any logic. The C × V × f currents must be evaluated and the troublesome ones minimized.

OPERATING ON OTHER THAN 3V SUPPLIES

Both the LTC1285 and the LTC1288 operate from a 2.7V to 6V supply. To operate the LTC1285/LTC1288 on other than 3V supplies a few things must be kept in mind.

Input Logic Levels

The input logic levels of CS, CLK and DIN are made to meet TTL on a 3V supply. When the supply voltage varies, the input logic levels also change. For the LTC1285/ LTC1288 to sample and convert correctly, the digital inputs have to be in the proper logical low and high levels relative to the operating supply voltage (see typical curve of Digital Input Logic Threshold vs Supply Voltage). If achieving micropower consumption is desirable, the digital inputs must go rail-to-rail between supply voltage and ground (see ACHIEVING MICROPOWER PERFORMANCE section).

Clock Frequency

The maximum recommended clock frequency is 120kHz for the LTC1285/LTC1288 running off a 3V supply. With the supply voltage changing, the maximum clock frequency for the devices also changes (see the typical curve

Page 15

LTC1285/LTC1288

WUU

APPLICATION INFORMATION

of Maximum Clock Rate vs Supply Voltage). If the maximum clock frequency is used, care must be taken to ensure that the device converts correctly.

Mixed Supplies

It is possible to have a microprocessor running off a 5V supply and communicate with the LTC1285/LTC1288 operating on a 3V supply. The inputs of CS, CLK and D of the LTC1285/LTC1288 have no problem to take a voltage swing from 0V to 5V. With the LTC1285 operating on a 3V supply, the output of D

may only go between

OUT

0V and 3V. The 3V output level is higher enough to trip a TTL input of the MPU. Figure 6 shows a 3V powered LTC1285 interfacing a 5V system.

4.7µF

MPU

(e.g. 8051)

DIFFERENTIAL INPUTS

COMMON-MODE RANGE

0V TO 3V

+IN

–IN

GND

REF

LTC1285

CLK

OUT

Figure 6. Interfacing a 3V Powered LTC1285 to a 5V System

P1.4 P1.3 P1.2

LTC1285/88 • F06



BOARD LAYOUT CONSIDERATIONS

Grounding and Bypassing

The LTC1285/LTC1288 are easy to use if some care is taken. They should be used with an analog ground plane and single point grounding techniques. The GND pin should be tied directly to the ground plane.

The VCC pin should be bypassed to the ground plane with a 10µ F tantalum capacitor with leads as short as possible. If the power supply is clean, the LTC1285/LTC1288 can also operate with smaller 1µF or less surface mount or ceramic bypass capacitors. All analog inputs should be referenced directly to the single point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry.

SAMPLE-AND-HOLD

Both the LTC1285 and the LTC1288 provide a built-in sample-and-hold (S&H) function to acquire signals. The S&H of the LTC1285 acquires input signals from “+” input relative to “–” input during the t

time (see Figure 1).

SMPL

However, the S&H of the LTC1288 can sample input signals in the single-ended mode or in the differential inputs during the t

time (see Figure 7).

SMPL

CLK

OUT

"+" INPUT

"–" INPUT

SAMPLE HOLD

"+" INPUT MUST SETTLE DURING

THIS TIME

SMPL

SGL/DIFFSTART MSBF DON’T CARE

1ST BIT TEST "–" INPUT MUST

SETTLE DURING THIS TIME

CONV

B11

LTC1285/88 • F07

Figure 7. LTC1288 “+” and “–” Input Settling Windows

Page 16

LTC1285/LTC1288

WUU

APPLICATION INFORMATION

Single-Ended Inputs

The sample-and-hold of the LTC1288 allows conversion of rapidly varying signals. The input voltage is sampled during the t interval begins as the bit preceding the MSBF bit is shifted in and continues until the falling CLK edge after the MSBF bit is received. On this falling edge, the S&H goes into hold mode and the conversion begins.

Differential Inputs

With differential inputs, the ADC no longer converts just a single voltage but rather the difference between two voltages. In this case, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. However, the voltage on the selected “–” input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the differencing operation may not be performed accurately. The conversion time is 12 CLK cycles. Therefore, a change in the “–” input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the “–” input this error would be:

ERROR (MAX)

Where f(“–”) is the frequency of the “–” input voltage, V

is its peak amplitude and f

PEAK

CLK. In most cases V 60Hz signal on the “–” input to generate a 1/4LSB error (152µV) with the converter running at CLK = 120kHz, its peak value would have to be 4.03mV.

ANALOG INPUTS

Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1285/ LTC1288 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. However, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins.

time as shown in Figure 7. The sampling

SMPL

= V

× 2 × π × f(“–”) × 12/f

PEAK

is the frequency of the

CLK

will not be significant. For a

ERROR

CLK

“+” Input Settling

The input capacitor of the LTC1285 is switched onto “+” input during the t the input signal within that time. However, the input capacitor of the LTC1288 is switched onto “+” input during the sample phase (t sample phase is 1 1/2 CLK cycles before conversion starts. The voltage on the “+” input must settle completely within t respectively. Minimizing R the input settling time. If a large “+” input source resistance must be used, the sample time can be increased by using a slower CLK frequency.

“–” Input Settling

At the end of the t “–” input and conversion starts (see Figures 1 and 7). During the conversion, the “+” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. However, it is critical that the “–” input voltage settles completely during the first CLK cycle of the conversion time and be free of noise. Minimizing R and C2 will improve settling time. If a large “–” input source resistance must be used, the time allowed for settling can be extended by using a slower CLK frequency.

Input Op Amps

When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figure 7). Again, the“+” and “–” input sampling times can be extended as described above to accommodate slower op amps. Most op amps, including the LT1006 and LT1413 single supply op amps, can be made to settle well even with the minimum settling windows of 12.5µs (“+” input) which occur at the maximum clock rate of 120kHz.

Source Resistance

The analog inputs of the LTC1285/LTC1288 look like a 20pF capacitor (CIN) in series with a 500Ω resistor (RON) as shown in Figure 8. CIN gets switched between the

SMPLE

time (see Figure 1) and samples

SMPL

, see Figure 7). The

SMPL

for the LTC1285 and the LTC1288

SOURCE

, the input capacitor switches to the

SMPL

and C1 will improve

SOURCE

–

Page 17

LTC1285/LTC1288

WUU

APPLICATION INFORMATION

selected “+” and “–” inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within the allowed time.

“+”

INPUT

R VIN + 

VIN – 

SOURCE

C1 

“–”

–

INPUT

C2 

RON = 500Ω

Figure 8. Analog Input Equivalent Circuit

RC Input Filtering

It is possible to filter the inputs with an RC network as shown in Figure 9. For large values of CF (e.g., 1µ F), the capacitive input switching currents are averaged into a net DC current. Therefore, a filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 20pF × VIN/t

CYC

proportional to VIN. When running at the minimum cycle time of 133.3µ s, the input current equals 0.375µA at V = 2.5V. In this case, a filter resistor of 160Ω will cause

0.1LSB of full-scale error. If a larger filter resistor must be used, errors can be eliminated by increasing the cycle time.

LTC1285 LTC1288

= 20pF

LTC1285/88 • F08

and is roughly

Input Leakage Current

Input leakage currents can also create errors if the source resistance gets too large. For instance, the maximum input leakage specification of 1µA (at 125°C) flowing through a source resistance of 240Ω will cause a voltage drop of 240µV or 0.4LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve of Input Channel Leakage Current vs Temperature).

REFERENCE INPUTS

The reference input of the LTC1285 is effectively a 50kΩ resistor from the time CS goes low to the end of the conversion. The reference input becomes a high impedence node at any other time (see Figure 10). Since the voltage on the reference input defines the voltage span of the A/D converter, the reference input should be driven by a reference with low R or a voltage source with low R



OUT



REF



Figure 10. Reference Input Equivalent Circuit

(ex. LT1004, LT1019 and LT1021)

OUT

REF

1

GND

4



LTC1285

LTC1285/88 • F10

Reduced Reference Operation

FILTER



FILTER

R VIN 



Figure 9. RC Input Filtering

+”

“

LTC1285

“

–”

LTC1285/88 • F09

The minimum reference voltage of the LTC1288 is limited to 2.7V because the VCC supply and reference are internally tied together. However, the LTC1285 can operate with reference voltages below 1.5V.

The effective resolution of the LTC1285 can be increased by reducing the input span of the converter. The LTC1285 exhibits good linearity and gain over a wide range of reference voltages (see typical curves of Change in Linearity vs Reference Voltage and Change in Gain vs Reference

Page 18

LTC1285/LTC1288

FREQUENCY (kHz)

–120

MAGNITUDE (dB)

–100

–80

–60

–40

1.0 2.0

3.0

4.0

LTC1285/88 • TPC16

–20

0.5 1.5

2.5

3.5

TA = 25°C V

= 2.7V

REF

= 2.5V

= 3.05kHz

CLK

= 120kHz

SMPL

= 7.5kHz

WUU

APPLICATION INFORMATION

Voltage). However, care must be taken when operating at low values of V and the resulting higher accuracy requirement placed on the converter. The following factors must be considered when operating at low V

1. Offset

2. Noise

3. Conversion speed (CLK frequency)

Offset with Reduced V

The offset of the LTC1285 has a larger effect on the output code. When the ADC is operated with reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Change in Offset vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 122µV which is 0.2LSB with a 2.5V reference becomes 1LSB with a 1V reference and 5LSBs with a 0.2V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the “–” input of the LTC1285.

Noise with Reduced V

The total input referred noise of the LTC1285 can be reduced to approximately 400µV peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 2.5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced.

because of the reduced LSB step size

REF

values:

REF

noise becomes equal to 3.3LSBs and a stable code may be difficult to achieve. In this case averaging multiple readings may be necessary.

This noise data was taken in a very clean setup. Any setup induced noise (noise or ripple on VCC, V

or VIN) will add

REF

to the internal noise. The lower the reference voltage to be used the more critical it becomes to have a clean, noise free setup.

Conversion Speed with Reduced V

REF

With reduced reference voltages, the LSB step size is reduced and the LTC1285 internal comparator overdrive is reduced. Therefore, it may be necessary to reduce the maximum CLK frequency when low values of V

are used.

REF

DYNAMIC PERFORMANCE

The LTC1285/LTC1288 have exceptional sampling capability. Fast Fourier Transform (FFT) test techniques are used to characterize the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 11 shows a typical LTC1285 plot.

For operation with a 2.5V reference, the 400µ V noise is only 0.66LSB peak-to-peak. In this case, the LTC1285 noise will contribute a little bit of uncertainty to the output code. However, for reduced references the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 1.25V reference this same 400µV noise is 1.32LSB peak-to-peak. This will reduce the range of input voltages over which a stable output code can be achieved by 1LSB. If the reference is further reduced to 1V, the 400µ V

Figure 11. LTC1285 Non-Averaged, 4096 Point FFT Plot

Page 19

LTC1285/LTC1288

WUU

APPLICATION INFORMATION

Signal-to-Noise Ratio

he Signal-to-Noise plus Distortion Ratio (S/N + D) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the ADC’s output. The output is band limited to frequencies above DC and below one half the sampling frequency. Figure 12 shows a typical spectral content with a 7.5kHz sampling rate.

12 11 10

9 8 7 6 5 4 3

TA = 25°C

= 2.7V

EFFECTIVE NUMBER OF BITS (ENOBs)

= 120kHz

CLK

Figure 12. Effective Bits and S/(N + D) vs Input Frequency

10 100

INPUT FREQUENCY (kHz)

LTC1285/88 • TPC12

Effective Number of Bits

The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to S/(N+D) by the equation:

ENOB = [S/(N + D) – 1.76]/6.02

where S/(N + D) is expressed in dB. At the maximum sampling rate of 7.5kHz with a 2.7V supply, the LTC1285 maintains above 10.7 ENOBs at 10kHz input frequency. Above 10kHz the ENOBs gradually decline, as shown in Figure 12, due to increasing second harmonic distortion. The noise floor remains low.

74 68 62

56 50

S/(N + D) (dB)

THD =

20log

++++

VVV V

22324

...

where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through the Nth harmonics. The typical THD specification in the Dynamic Accuracy table includes the 2nd through 5th harmonics. With a 1kHz input signal, the LTC1285/LTC1288 have typical THD of 80dB with VCC = 2.7V.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.

If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa – fb) while 3rd order IMD terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine waves are equal in magnitudes, the value (in dB) of the 2nd order IMD products can be expressed by the following formula:

IMD f f

()

20log



mplitude f f

 

amplitude at f



()



 



For input frequencies of 2.05kHz and 3.05kHz, the IMD of the LTC1285/LTC1288 is 72dB with a 2.7V supply.

Total Harmonic Distortion

Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half of the sampling frequency. THD is defined as:

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in dBs relative to the RMS value of a fullscale input signal.

Page 20

LTC1285/LTC1288

TYPICAL APPLICATIONS N

MICROPROCESSOR INTERFACES

The LTC1285/LTC1288 can interface directly without external hardware to most popular microprocessor (MPU) synchronous serial formats (see Table 1). If an MPU without a dedicated serial port is used, then 3 or 4 of the MPU's parallel port lines can be programmed to form the serial link to the LTC1285/LTC1288. Included here is one serial interface example and one example showing a parallel port programmed to form the serial interface.

Motorola SPI (MC68HC11)

The MC68HC11 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSB

-first and in 8-bit increments. The DIN word sent to the data register starts with the SPI process. With three 8-bit transfers, the A/D result is read into the MPU. The second 8-bit transfer clocks B11 through B8 of the A/D conversion result into the processor. The third 8-bit transfer clocks the remaining bits, B7 through B0, into the MPU. The data is right justified into two memory locations. ANDing the second byte with OF

clears the four most significant

HEX

bits. This operation was not included in the code. It can be inserted in the data gathering loop or outside the loop when the data is processed.

MC68HC11 Code

In this example the D

word configures the input MUX for

a single-ended input to be applied to CHO. The conversion result is output MSB-first.

Table 1. Microprocessor with Hardware Serial Interfaces Compatible with the LTC1286/LTC1298

PART NUMBER TYPE OF INTERFACE

Motorola

MC6805S2,S3 SPI MC68HC11 SPI MC68HC05 SPI

RCA

CDP68HC05 SPI

Hitachi

HD6305 SCI Synchronous HD63705 SCI Synchronous HD6301 SCI Synchronous HD63701 SCI Synchronous HD6303 SCI Synchronous HD64180 CSI/O

National Semiconductor

COP400 Family MICROWIRE COP800 Family MICROWIRE/PLUS NS8050U MICROWIRE/PLUS HPC16000 Family MICROWIRE/PLUS

Texas Instruments

TMS7002 Serial Port TMS7042 Serial Port TMS70C02 Serial Port TMS70C42 Serial Port TMS32011* Serial Port TMS32020 Serial Port

Intel

8051 Bit Manipulation on Parallel Port

* Requires external hardware

†

MICROWIRE and MICROWIRE/PLUS are trademarks of National Semiconductor Corp.

†

† †

Page 21

TYPICAL APPLICATIONS N

Timing Diagram for Interface to the MC68HC11

CLK

OUT

START

SGL/ DIFF

ODD/ SIGN

MSBF

LTC1285/LTC1288

DON'T CARE

B3B7 B6 B5 B4 B2 B0B1B11 B10 B9 B8

MPU

TRANSMIT

WORD

MPU

RECEIVED

WORD

000

BYTE 1

0000

????????

SGL/ DIFF

ODD/ SIGN

Hardware and Software Interface to the MC68HC11

FROM LTC1298 STORED IN MC68HC11 RAM

OUT

MSB

#62

#63

B7 B5

LABEL MNEMONIC OPERAND COMMENTS

LDAA #$50 CONFIGURATION DATA FOR SPCR STAA $1028 LOAD DATA INTO SPCR ($1028) LDAA #$1B CONFIG. DATA FOR PORT D DDR STAA $1009 LOAD DATA INTO PORT D DDR LDAA #$01 LOAD DIN WORD INTO ACC A STAA $50 LOAD DIN DATA INTO $50 LDAA #$A0 LOAD DIN WORD INTO ACC A STAA $51 LOAD DIN DATA INTO $51 LDAA #$00 LOAD DUMMY DIN WORD INTO

STAA $52 LOAD DUMMY DIN DATA INTO $52 LDX #$1000 LOAD INDEX REGISTER X WITH

LOOP BCLR $08,X,#$01 D0 GOES LOW (CS GOES LOW)

LDAA $50 LOAD DIN INTO ACC A FROM $50 STAA $102A LOAD DIN INTO SPI, START SCK LDAA $1029 CHECK SPI STATUS REG

0 B11

LSB

B10

B2 B1

B9 B8

ACC A

$1000

MSBF

BYTE 1

BYTE 2

B11

ANALOG

INPUTS

B10

CH0

LTC1288

CH1

CLK

OUT

BYTE 3 (DUMMY)

B5 B3

BYTE 3

SCK

MISO

MOSI

MC68HC11

LTC1285/88 • TA04

LABEL MNEMONIC OPERAND COMMENTS

WAIT1 BPL WAIT1 CHECK IF TRANSFER IS DONE

LDAA $51 LOAD DIN INTO ACC A FROM $51 STAA $102A LOAD DIN INTO SPI, START SCK

WAIT2 LDAA $1029 CHECK SPI STATUS REG

BPL WAIT2 CHECK IF TRANSFER IS DONE LDAA $102A LOAD LTC1288 MSBs INTO ACC A STAA $62 STORE MSBs IN $62 LDAA $52 LOAD DUMMY INTO ACC A

FROM $52

STAA $102A LOAD DUMMY DIN INTO SPI,

START SCK

WAIT3 LDAA $1029 CHECK SPI STATUS REG

BPL WAIT3 CHECK IF TRANSFER IS DONE BSET $08,X#$01 DO GOES HIGH (CS GOES HIGH) LDAA $102A LOAD LTC1288 LSBs IN ACC STAA $63 STORE LSBs IN $63 JMP LOOP START NEXT CONVERSION

LTC1285/88 • TA03



Page 22

LTC1285/LTC1288

TYPICAL APPLICATIONS N

Interfacing to the Parallel Port of the INTEL 8051 Family

The Intel 8051 has been chosen to demonstrate the interface between the LTC1288 and parallel port microprocessors. Normally the CS, CLK and DIN signals would be generated on 3 port lines and the D

signal read on

OUT

a 4th port line. This works very well. However, we will demonstrate here an interface with the DIN and D

OUT

of the LTC1288 tied together as described in the SERIAL INTERFACE section. This saves one wire.

The 8051 first sends the start bit and MUX address to the LTC1288 over the data line connected to P1.2. Then P1.2 is reconfigured as an input (by writing to it a one) and the 8051 reads back the 12-bit A/D result over the same data line.

ANALOG

INPUTS

LTC1288

CS

CLK



OUT

MUX ADDRESS

A/D RESULT

P1.4 P1.3 P1.2 

8051

LTC1285/88 • TA01

LABEL MNEMONIC OPERAND COMMENTS

MOV A, #FFH DIN word for LTC1288 SETB P1.4 Make sure CS is high CLR P1.4 CS goes low

LOOP 1 RLC A Rotate D

LOOP 2 MOV C, P1.2 Read data bit into Carry

LOOP 3 MOV C, P1.2 Read data bit into Carry

LOOP 4 RRC A Rotate right into Acc.

MOV R4, #04 Load counter

CLR P1.3 SCLK goes low MOV P1.2, C Output DIN bit to LTC1288 SETB P1.3 SCLK goes high DJNZ R4, LOOP 1 Next bit MOV P1, #04 Bit 2 becomes an input CLR P1.3 SCLK goes low MOV R4, #09 Load counter

RLC A Rotate data bit into Acc. SETB P1.3 SCLK goes high CLR P1.3 SCLK goes low DJNZ R4, LOOP 2 Next bit MOV R2, A Store MSBs in R2 CLR A Clear Acc. MOV R4, #04 Load counter

RLC A Rotate data bit into Acc. SETB P1.3 SCLK goes high CLR P1.3 SCLK goes low DJNZ R4, LOOP 3 Next bit MOV R4, #04 Load counter

DJNZ R4, LOOP 4 Next Rotate MOV R3, A Store LSBs in R3 SETB P1.4 CS goes high

bit into Carry

FROM 1288 STORED IN 8501 RAM

OUT

MSB

R2 B11 B10 B9 B8 B7 B6 B5 B4

LSB

R3 B3 B2 B1 B0 0 0 0 0

MSBF BIT LATCHED 

SGL/ DIFFSTART

INTO LTC1288

MSBF B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

ODD/ 

SIGN

CLK

(

DATA 

)

OUT

8051 P1.2 OUTPUTS DATA 

TO LTC1288

AS IN INPUT AFTER THE 4TH RISING CLK

8051 P1.2 RECONFIGURED

AND BEFORE THE 4TH FALLING CLK

LTC1288 SENDS A/D RESULT

LTC1288 TAKES CONTROL OF DATA

LINE ON 4TH FALLING CLK

BACK TO 8051 P1.2

LTC1285/88 • TA07

Page 23

TYPICAL APPLICATIONS N

LTC1285/LTC1288

A “Quick Look” Circuit for the LTC1285

Users can get a quick look at the function and timing of the LT1285 by using the following simple circuit (Figure 13). V

is tied to VCC. VIN is applied to the +IN input and the

REF

–IN input is tied to the ground. CS is driven at 1/16 the clock rate by the 74C161 and D output data from the D

OUT

outputs the data. The

OUT

pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of CS (Figure 14). Note the LSB data is partially clocked out before CS goes high.

VCC

CLK

OUT

CS



2.7V



TO OSCILLOSCOPE

CLR CLK A B

74HC161

C D P GND

CLOCK IN 120kHz



RC QA QB QC QD

T

LOAD

LTC1285/88 • F13

4.7µF



REF

+IN

LTC1285

–IN

GND

Micropower Battery Voltage Monitor

A common problem in battery systems is battery voltage monitoring. This circuit monitors the 10 cell stack of NiCad or NiMH batteries found in laptop computers. It draws only 40µA from the 2.7V supply at f

= 0.1kHz and 30µ A to

SMPL

62µ A from the battery. The 12-bits of resolution of the LTC1285 are positioned over the desired range of 8V to 16V. This is easily accomplished by using the ADC’s differential inputs. Tying the –input to the reference gives an ADC input span of V

REF

to 2V

(1.2V to 2.4V). The

REF

resistor divider then scales the input voltage for 8V to 16V.

BATTERY MONITOR 

INPUT 8V TO 16V

220k

39k

LT1004-1.2

0.1µF

1µF

3Ω

+IN

–IN 

LTC1285

REF

2.7V

GND

CS

CLK

LTC1285/88 • F15

OUT

Figure 13. “Quick Look” Circuit for the LTC1285

NULL

BIT

MSB

(B11)

VERTICAL: 2V/DIV HORIZONTAL: 20µs/DIV

LSB (B0)

Figure 14. Scope Trace the LTC1285 “Quick Look” Circuit Showing A/D Output 101010101010 (AAA

HEX

)

Figure 15. Micropower Battery Voltage Monitor

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Page 24

LTC1285/LTC1288

PACKAGE DESCRIPTION

0.300 – 0.325

(7.620 – 8.255)

Dimensions in inches (millimeters) unless otherwise noted.

N8 Package

8-Lead Plastic DIP

0.045 – 0.065

(1.143 – 1.651)

0.130 ± 0.005

(3.302 ± 0.127)

0.400*

(10.160)

MAX

876

0.065

(1.651)

0.009 – 0.015

(0.229 – 0.381)

+0.025

0.325

–0.015

+0.635

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH  

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD  FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE  

× 45°

0.016 – 0.050

0.406 – 1.270

TYP

0.005

(0.127)

MIN

0.100 ± 0.010

(2.540 ± 0.254)

0.053 – 0.069

(1.346 – 1.752)

0°– 8° TYP

0.014 – 0.019

(0.355 – 0.483)

0.125

(3.175)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

S8 Package

8-Lead Plastic SOIC

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC



0.015

(0.380)

MIN

0.228 – 0.244

(5.791 – 6.197)

0.255 ± 0.015* (6.477 ± 0.381)



0.189 – 0.197* (4.801 – 5.004)

0.150 – 0.157** (3.810 – 3.988)

SO8 0695

N8 0695

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1096/LTC1098 8-Pin SOIC, Micropower 8-Bit ADC Low Power, Small Size, Low Cost LTC1196/LTC1198 8-Pin SOIC, 1Msps 8-bit ADC Low Power, Small Size, Low Cost LTC1282 3V High Speed Parallel 12-Bit ADC Complete, V LTC1289 Multiplexed 3V, 1A 12-Bit ADC 8-Channel, 12-Bit Serial I/O LTC1522 16-Pin SOIC, 3V Micropower 12-Bit ADC 4-Channel, 12-Bit Serial I/O

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7487

(408) 432-1900

●

FAX

: (408) 434-0507

●

TELEX

: 499-3977

, CLK, Sample-and-Hold, 140ksps

REF

LT/GP 0894 10K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1994