Datasheet LTC1286IS8, LTC1286CN8, LTC1286, LTC1298IN8, LTC1298CS8 Datasheet (Linear Technology)

FEATURES

LTC1286/LTC1298

Micropower Sampling

12-Bit A/D Converters In

S0-8 Packages

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DESCRIPTION

■

12-Bit Resolution

■

8-Pin SOIC Plastic Package

■

Low Cost

■

Low Supply Current: 250µA Typ.

■

Auto Shutdown to 1nA Typ.

■

Guaranteed ±3/4LSB Max DNL

■

Single Supply 5V to 9V Operation

■

On-Chip Sample-and-Hold

■

60µs Conversion Time

■

Sampling Rates:

12.5 ksps (LTC1286)

11.1 ksps (LTC1298)

■

I/O Compatible with SPI, Microwire, etc.

■

Differential Inputs (LTC1286)

■

2-Channel MUX (LTC1298)

■

3V Versions Available: LTC1285/LTC1288

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APPLICATIONS

■

Battery-Operated Systems

■

Remote Data Acquisition

■

Battery Monitoring

■

Handheld Terminal Interface

■

Temperature Measurement

■

Isolated Data Acquisition

The LTC1286/LTC1298 are micropower, 12-bit, succes­sive approximation sampling A/D converters. They typi­cally draw only 250µ A of supply current when converting
and automatically power down to a typical supply current
of 1nA whenever they are not performing conversions.
They are packaged in 8-pin SO packages and operate on
5V to 9V supplies. These 12-bit, switched-capacitor, suc­cessive approximation ADCs include sample-and-holds.
The LTC1286 has a single differential analog input. The
LTC1298 offers a software selectable 2-channel MUX.

On-chip serial ports allow efficient data transfer to a wide
range of microprocessors and microcontrollers over three
wires. This, coupled with micropower consumption, makes
remote location possible and facilitates transmitting data
through isolation barriers.

These circuits can be used in ratiometric applications or
with an external reference. The high impedance analog
inputs and the ability to operate with reduced spans (to

1.5V full scale) allow direct connection to sensors and
transducers in many applications, eliminating the need for
gain stages.

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TYPICAL APPLICATIONS N

25µW, S0-8 Package, 12-Bit ADC

Samples at 200Hz and Runs Off a 5V Supply

5V4.7µF

8

V

CC

7

CLK

6

D

OUT

5

SERIAL DATA LINK

ANALOG INPUT

0V TO 5V RANGE

1

V

REF

2

+IN

LTC1286

3

–IN

4

GND



CS/SHDN

MPU

(e.g., 8051)

P1.4
P1.3
P1.2

LTC1286/98 • TA01

Supply Current vs Sample Rate

1000

TA = 25°C

= V

V
f

100

10

SUPPLY CURRENT (µA)

1

0.1k

= 5V

CC

REF

= 200kHz

CLK

1k 10k 100k

SAMPLE FREQUENCY (Hz)

LTC1286/98 • TA02

1

LTC1286/LTC1298

WW

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ABSOLUTE MAXIMUM RATINGS

(Notes 1 and 2)

Supply Voltage (VCC) to GND................................... 12V

Voltage

Analog and Reference ................ –0.3V to V

CC

+ 0.3V

Digital Inputs.........................................–0.3V to 12V

Digital Output ............................. –0.3V to V

CC

+ 0.3V

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PACKAGE/ORDER INFORMATION

TOP VIEW

V

REF

+IN
–IN

GND

CS/SHDN

CH0
CH1
GND

1



2
3
4

N8 PACKAGE

8-LEAD PLASTIC DIP

T

= 150°C, θJA = 130°C/W

JMAX

TOP VIEW

1



2
3
4

N8 PACKAGE

8-LEAD PLASTIC DIP

T

= 150°C, θJA = 130°C/W

JMAX

8
7
6
5



8
7
6
5



V

CC

CLK
D

OUT



CS/SHDN


V

CC (VREF)

CLK
D

OUT

D

IN

Consult factory for military grade parts.









ORDER PART

NUMBER

LTC1286CN8
LTC1286IN8

ORDER PART

NUMBER

LTC1298CN8
LTC1298IN8

Power Dissipation.............................................. 500mW

Operating Temperature Range

LTC1286C/LTC1298C............................. 0°C to 70°C

LTC1286I/LTC1298I ........................... –40°C to 85°C

Storage Temperature Range ................. – 65°C to 150°C

Lead Temperature (Soldering, 10 sec.)................ 300°C

UU

V

REF

+IN
–IN

GND

CS/SHDN

CH0
CH1

GND

TOP VIEW

1



2

3



4

S8 PACKAGE

8-LEAD PLASTIC SOIC

T

= 150°C, θJA = 175°C/W

JMAX

TOP VIEW

1

2

3



4

S8 PACKAGE

8-LEAD PLASTIC SOIC

= 150°C, θJA = 175°C/W

T

JMAX

8

7

6

5

8

7

6

5

V

CC

CLK
D



OUT

CS/SHDN

V

CC (VREF)

CLK
D



OUT

D

IN

ORDER PART

NUMBER

LTC1286CS8
LTC1286IS8

PART MARKING

1286C

1286I

ORDER PART

NUMBER

LTC1298CS8
LTC1298IS8

PART MARKING

1298C

1298I

UUUU

W

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RECOM ENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

CC

Supply Voltage (Note 3) LTC1286 4.5 9.0 V

LTC1298 4.5 5.5 V

f

CLK

t

CYC

t

hDI

t

suCS

t

suDI

t

WHCLK

t

WLCLK

t

WHCS

t

WLCS

Clock Frequency VCC = 5V (Note 4) 200 kHz
Total Cycle Time LTC1286, f

LTC1298, f

= 200kHz 80 µs

CLK

= 200kHz 90 µs

CLK

Hold Time, DIN After CLK↑ VCC = 5V 150 ns
Setup Time CS↓ Before First CLK↑ (See Operating Sequence) LTC1286, VCC = 5V 2 µs

LTC1298, V

= 5V 2 µs

CC

Setup Time, DIN Stable Before CLK↑ VCC = 5V 400 ns
CLK High Time VCC = 5V 2 µs
CLK Low Time VCC = 5V 2 µs
CS High Time Between Data Transfer Cycles VCC = 5V 2 µs
CS Low Time During Data Transfer LTC1286, f

LTC1298, f

= 200kHz 75 µs

CLK

= 200kHz 85 µs

CLK

2

LTC1286/LTC1298

UW U

CONVERTER AND MULTIPLEXER CHARACTERISTICS

LTC1286 LTC1298

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 12 12 Bits
Integral Linearity Error (Note 6) ● ±3/4 ±2 ±3/4 ±2 LSB
Differential Linearity Error ● ±1/4 ±3/4 ±1/4 ±3/4 LSB
Offset Error ● 3/4 ±33/4±3 LSB
Gain Error ● ±2 ±8 ±2 ±8 LSB
Analog Input Range (Note 7 and 8) ● V
REF Input Range (LTC1286) 4.5 ≤ VCC ≤ 5.5V V

(Notes 7, 8, and 9) 5.5V < VCC ≤ 9V V
Analog Input Leakage Current (Note 10) ● ±1 ±1 µA

–0.05V to V

1.5V to VCC + 0.05V

1.5V to 5.55V

(Note 5)

+ 0.05V

CC

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DIGITAL AND DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IH

I

IL

V

OH

V

OL

I

OZ

I

SOURCE

I

SINK

R

REF

I

REF

I

CC

High Level Input Voltage VCC = 5.25V ● 2V
Low Level Input Voltage VCC = 4.75V ● 0.8 V
High Level Input Current VIN = V
Low Level Input Current VIN = 0V ● –2.5 µA
High Level Output Voltage VCC = 4.75V, IO = 10µA ● 4.0 4.64 V

Low Level Output Voltage VCC = 4.75V, IO = 1.6mA ● 0.4 V
Hi-Z Output Leakage CS = High ● ±3 µA
Output Source Current V
Output Sink Current V
Reference Input Resistance CS = V

(LTC1286) CS = GND 55 kΩ
Reference Current (LTC1286) CS = V

Supply Current CS = V

CC

= 4.75V, IO = 360µA ● 2.4 4.62 V

V

CC

= 0V –25 mA

OUT

= V

OUT

CC

CC

CC

≥ 640µs, f

t

CYC

t

= 80µs, f

CYC

CC

LTC1286, t
LTC1286, t

LTC1298, t
LTC1298, t

≤ 25kHz ● 90 140 µA

CLK

= 200kHz ● 90 140 µA

CLK

≥ 640µs, f

CYC

= 80µs, f

CYC

≥ 720µs, f

CYC

= 90µs, f

CYC

≤ 25kHz ● 200 400 µA

CLK

= 200kHz ● 250 500 µ A

CLK

≤ 25kHz ● 290 490 µA

CLK

= 200kHz ● 340 640 µ A

CLK

(Note 5)

● 2.5 µA

45 mA

5000 MΩ

● 0.001 2.5 µA

● 0.001 ±3.0 µA

UW

f

DYNAMIC ACCURACY

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

S/(N +D) Signal-to-Noise Plus Distortion Ratio 1kHz/7kHz Input Signal 71/68 dB
THD Total Harmonic Distortion (Up to 5th Harmonic) 1kHz/7kHz Input Signal –84/–80 dB
SFDR Spurious-Free Dynamic Range 1kHz/7kHz Input Signal 90/86 dB

Peak Harmonic or Spurious Noise 1kHz/7kHz Input Signal – 90/–86 dB

= 12.5kHz (LTC1286), f

SMPL

= 11.1kHz (LTC1298) (Note 5)

SMPL

3

LTC1286/LTC1298

FREQUENCY (kHz)

1

0.002

SUPPLY CURRENT (µA)

5

1

0

15

20

25

35

20

100

140

LT1286/98 G01

10

30

80

180

200

40

60

120 160

CS = 0
(AFTER CONVERSION)

TA = 25°C
V

CC

= V

REF

= 5V

CS = V

CC

AC CHARACTERISTICS

(Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t

SMPL

f

SMPL(MAX)

Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles
Maximum Sampling Frequency LTC1286 ● 12.5 kHz

LTC1298 ● 11.1 kHz

t

CONV

t

dDO

t

dis

t

en

t

hDO

t

f

t

r

C

IN

Conversion Time See Operating Sequence 12 CLK Cycles
Delay Time, CLK↓ to D
Delay Time, CS↑ to D
Delay Time, CLK↓ to D
Time Output Data Remains Valid After CLK↓ C
D

Fall Time See Test Circuits ● 20 75 ns

OUT

D

Rise Time See Test Circuits ● 20 75 ns

OUT

Data Valid See Test Circuits ● 250 600 ns

OUT

Hi-Z See Test Circuits ● 135 300 ns

OUT

Enable See Test Circuits ● 75 200 ns

OUT

= 100pF 230 ns

LOAD

Input Capacitance Analog Inputs, On Channel 20 pF

Analog Inputs, Off Channel 5 pF
Digital Input 5 pF

The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.

Note 2: All voltage values are with respect to GND.
Note 3: These devices are specified at 5V. For 3V specified devices, see

LTC1285 and LTC1288.
Note 4: Increased leakage currents at elevated temperatures cause the S/H
to droop, therefore it is recommended that f
75kHz at 70° and f

Note 5: VCC = 5V, V

≥ 1kHz at 25°C.

CLK

= 5V and CLK = 200kHz unless otherwise specified.

REF

≥ 120kHz at 85°C, f

CLK

CLK

≥

Note 6: Linearity error is specified between the actual end points of the
A/D transfer curve.

Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below GND or one diode drop above VCC. This spec allows 50mV forward
bias of either diode for 4.5V ≤ V

≤ 5.5V. This means that as long as the

CC

reference or analog input does not exceed the supply voltage by more than
50mV the output code will be correct. To achieve an absolute 0V to 5V
input voltage range will therefore require a minimum supply voltage of

4.950V over initial tolerance, temperature variations and loading. For 5.5V
< V

≤ 9V, reference and analog input range cannot exceed 5.55V. If

CC

reference and analog input range are greater than 5.55V, the output code
will not be guaranteed to be correct.

Note 8: The supply voltage range for the LTC1286 is from 4.5V to 9V, but
the supply voltage range for the LTC1298 is only from 4.5V to 5.5V.

Note 9: Recommended operating conditions
Note 10: Channel leakage current is measured after the channel selection.

TYPICAL PERFORMANCE CHARACTERISTICS

1000

100

10

SUPPLY CURRENT (µA)

1

0.1k

4

TA = 25°C

= V

V
f

= 5V

CC

REF

= 200kHz

CLK

LTC1298

1k 10k 100k

SAMPLE RATE (kHz)

LTC1286

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LT1286/98 G03

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450

400

350

300

SUPPLY CURRENT (µA)

250

200

Supply Current vs Temperature

TA = 25°C

= V

CC

= 200kHz

CLK

REF

–15

= 5V

LTC1298 f

SMPL

LTC1286 f

SMPL

45 125

65

25

TEMPERATURE (°C)

=11.1kHz

=12.5kHz

85

LT1286/98 G04

V
f

–35 5

–55

Shutdown Supply Current vs Clock
Rate with CS High and CS LowSupply Current vs Sample Rate

105

W

REFERENCE VOLTAGE (V)

1

0

CHANGE IN OFFSET (LSB = 1/4096 V

REF

)

0.5

1

1.5

2

23

4

5

LT1286/98 G08

2.5

3

1.5 2.5

3.5

4.5

TA = 25°C
V

CC

= 5V

f

CLK

= 200kHz

f

SMPL

= 12.5kHz



0

–1

–3

–4

–5

–6

–10

–7

–2

–8

–9

REFERENCE VOLTAGE (V)

1

CHANGE IN GAIN (LSB)

23

4

5

LT1286/98 G11

1.5 2.5

3.5

4.5

TA = 25°C
V

CC

= 5V

f

CLK

= 200kHz

f

SMPL

= 12.5kHz





INPUT FREQUENCY (kHz)

1

0

EFFECTIVE NUMBER OF BITS (ENOBs)

8
7

10

9

12
11

10 100 1000

LTC 1286/98 G20

6

50
44

62
56

74
68

38
5
4

3
2

1

TA = 25°C
V

CC

= 5V

f

CLK

= 200kHz

f

SMPL

= 12.5kHz



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TYPICAL PERFORMANCE CHARACTERISTICS

LTC1286/LTC1298

Reference Current vs
Sample Rate (LTC1286)

100

TA = 25°C

90

V

= 5V

CC

= 5V

V

REF

80

= 200kHz

f

CLK

70
60
50
40
30

REFERENCE CURRENT (µA)

20
10

0

0

4

2

FREQUENCY (kHz)

8

6

Change in Offset vs Temperature

0

-0.5

-1

1.5

-2

CHANGE IN OFFSET (LSB)

-2.5

VCC = V
f
f

-3

-55

= 5V

REF

= 200kHz

CLK

= f

SMPL

SMPL (MAX)

-15 25

-35 5
TEMPERATURE (°C)

45

10

12

LT1286/98 G06

65

LT1286/98 G09

Change in Offset vs

Reference Current vs Temperature

95

VCC = V
f

94.5
f

T


94

93.5

93

REFERENCE CURRENT (µA)

92.5

92

14

–55

REF

= 12.5kHz

SMPL

= 200kHz

CLK

= 25°C

A

–15

–35 5

= 5V

45 125

25

TEMPERATURE (°C)

65

85

105

LT1286/98 G07

Change In Linearity vs
Reference Voltage

–0.5

–0.45

–0.4

–0.35

–0.3

–.25

–0.2

–0.15

CHANGE IN LINEARITY (LSB)

–0.1

–0.05

0

85

1

23

1.5 2.5
REFERENCE VOLTAGE (V)

TA = 25°C

= 5V

V

CC

= 200kHz

f

CLK

= 12.5kHz

f

SMPL



4

3.5

4.5

LT1286/98 G10

5

Reference Voltage

Change In Gain vs
Reference Voltage

Peak-to-Peak ADC Noise vs
Reference Voltage

2

TA = 25°C

= 5V

V

CC

f

= 200kHz

CLK



1.5

1

ADC NOISE IN LBSs

0.5

0

1

2

REFERENCE VOLTAGE (V)

3

4

LT1286/98 G15

Differential Nonlinearity vs Code

1.0

0.80

0.60

0.40

0.20

0.00

–0.20
–0.40

–0.60
–0.80

DIFFERENTIAL NONLINEARITY ERROR (LBS)

–1.0

5

0

2048

CODE

Effective Bits and S/(N + D)
vs Input Frequency

4096

5

LTC1286/LTC1298

INPUT FREQUENCY (Hz)

1 10k

100

ATTENUATION (%)

80
90

60
70

40
50

20
30

100k 1M 10M

LTC 1286/98 G26

0

10

TA = 25°C
V

CC

= V

REF =

5V

f

SMPL

= 12.5kHz

RIPPLE FREQUENCY (kHz)

FEEDTHROUGH (dB)

–50

0

1 100 1000 10000

LTC 1286/98 G22

–100

10

TA = 25°C
V

CC

= 5V (V

RIPPLE

= 20mV)

V

REF

= 5V

f

CLK

= 200kHz



W

U

TYPICAL PERFORMANCE CHARACTERISTICS

Spurious Free Dynamic Range
vs Frequency

100

90
80
70
60

50
40
30
20

TA = 25°C

= V

V

CC

10

SPURIOUS FREE DYNAMIC RANGE (dB)

f

SMPL

0

1k

5V

REF =

= 12.5kHz

10k 100k 1M

INPUT FREQUENCY (Hz)

4096 Point FFT Plot

0

TA = 25°C

= V

CC

= 5kHz

IN

= 200kHz

CLK
SMPL

= 5V

REF

= 12.5kHz

V

–20

f
f

–40

f



–60



–80

MAGNITUDE (dB)

–100

LTC 1286/98 G27

S/(N+D) vs Input Level

80

TA = 25°C

70

= V

V

CC

= 1kHz

f

IN

f

60

SMPL



50

40

30

20

10

SIGNAL-TO-NOISE PLUS DISTORTION (dB)

0

–40

5V

REF =

= 12.5kHz

–30 –20

INPUT LEVEL (dB)

Intermodulation Distortion

0

TA = 25°C

= V

V

CC

–20

= 5kHz

f

1

= 6kHz

f

2

–40

f

SMPL




–60



–80

MAGNITUDE (dB)

–100

5V

REF =

= 12.5kHz

Attenuation vs
Input Frequency

–10 0

LT1286/98 G25

Power Supply Feedthrough
vs Ripple Frequency

–120

–140

0

12

35

FREQUENCY (kHz)

Maximum Clock Frequency vs
Source Resistance

300

250

200

150

100

CLOCK FREQUENCY (kHz)

6

50

TA = 25°C

= V

V

0

0.1

= 5V

CC

REF

SOURCE RESISTANCE (kΩ)

–120

467

LTC 1286/98 G21

+INPUT

V

IN

–INPUT

–

R

SOURCE

110

LT1286/98 G12

–140

10000

1000

S&H ACQUISITION TIME (ns)

100

0

12

FREQUENCY (kHz)

467

35

LTC 1286/98 G24

Sample and Hold Aquisition
Time vs Source Resistance

TA = 25°C

= V

V

= 5V

CC

REF

+

R

SOURCE

V

IN

10 100 1000

10.1 10000

SOURCE RESISTANCE (Ω)

+INPUT

–INPUT

LT1286/98 G16

Maximum Clock Frequency vs
Supply Voltage

300

TA = 25°C

= V

V

290

280

270

CLOCK FREQUENCY (kHz)

260

250

5

= 5V

CC

REF

6

SUPPLY VOLTAGE (V)

7

8

LT1286/98 G13

9

W

TEMPERATURE (°C)

–60

LEAKAGE CURRENT (nA)

1000

100

10

1

0.1

0.01
100

1196/98 G19

–20

20

60

140

–40

0

40 80

120

VCC = 5V
V

REF

= 5V

ON CHANNEL

OFF CHANNEL

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TYPICAL PERFORMANCE CHARACTERISTICS

LTC1286/LTC1298

Minimum Clock Frequency
for 0.1 LSB Error vs Temperature

200

VCC = V


150

100

50

CLOCK FREQUENCY (kHz)

0

–55

–35

REF

–15

= 5V

5

25 45 65 85

TEMPERATURE (°C)

LT1286/98 • G14

Digital Input Logic Threshold
vs Supply Voltage

3

TA = 25°C

2

DIGITAL LOGIC THRESHOLD VOLTAGE (V)

1

4567

3

SUPPLY VOLTAGE (V)

UUU

PIN FUNCTIONS

LTC1286
V

(Pin 1): Reference Input. The reference input defines

REF

the span of the A/D converter.

IN+ (Pin 2): Positive Analog Input.
IN– (Pin 3): Negative Analog Input.
GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane.
CS/SHDN (Pin 5): Chip Select Input. A logic low on this

input enables the LTC1286. A logic high on this input
disables and powers down the LTC1286.

Input Channel Leakage Current
vs Temperature

89

LTC 1286/98 G17

LTC1298
CS/SHDN (Pin 1): Chip Select Input. A logic low on this

input enables the LTC1298. A logic high on this input
disables and powers down the LTC1298.

CH0 (Pin 2): Analog Input.
CH1 (Pin 3): Analog Input.
GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane.
DIN (Pin 5): Digital Data Input. The multiplexer address is

shifted into this input.

D

(Pin 6): Digital Data Output. The A/D conversion

OUT

result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial

data transfer and determines conversion speed.
VCC (Pin 8): Power Supply Voltage. This pin provides

power to the A/D converter. It must be kept free of noise
and ripple by bypassing directly to the analog ground
plane.

D

(Pin 6): Digital Data Output. The A/D conversion

OUT

result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the

serial data transfer and determines conversion speed.

VCC/V

(Pin 8): Power Supply and Reference Voltage.

REF

This pin provides power and defines the span of the A/D
converter. It must be kept free of noise and ripple by
bypassing directly to the analog ground plane.

7

LTC1286/LTC1298

BLOCK DIAGRAM

W

VCC (VCC/V

REF

CS/SHDN

)

(DIN)



CLK

IN+ (CH0)

–

(CH1)

IN



TEST CIRCUITS

Load Circuit for t

D

OUT

1.4V

dDO

3k

100pF

C

, tr and t

SAMPLE

GND

f

TEST POINT

BIAS AND 

SHUTDOWN CIRCUIT

–

+

MICROPOWER
COMPARATOR

CAPACITIVE DAC

SERIAL PORT

SAR

V

REF

PIN NAMES IN PARENTHESES
REFER TO THE LTC1298

Voltage Waveforms for D

D

OUT

t

r

D

OUT

Rise and Fall Times, tr, t

OUT

t

f

f

V

OH

V

OL

LTC1286/98 • TC02

8

Voltage Waveforms for D

CLK

D

OUT

V

IL

t

dDO

Delay Times, t

OUT

LTC1286/98 • TC01

LTC1286/98 • TC03

dDO

Load Circuit for t

TEST POINT

D

V

OH

V

OL

OUT

3k

100pF

dis

and t

VCC t

t

en

WAVEFORM 2, t

dis

WAVEFORM 1

dis

LTC1286/98 • TC04

en





TEST CIRCUITS

LTC1286/LTC1298

Voltage Waveforms for t

CS

D

OUT

WAVEFORM 1

(SEE NOTE 1)

D

OUT

WAVEFORM 2

(SEE NOTE 2)

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.

LTC1298

CS

D

IN

CLK

t

dis

dis

V

IH

START

1234

LTC1286

CS

90%

CLK

10%

D

OUT

LTC1286/98 • TC05

Voltage Waveforms for t

Voltage Waveforms for t

1

en

en

2

B11

V

OL

t

en

LTC1286/98 • TC06

D

OUT

U

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APPLICATION INFORMATION

OVERVIEW

The LTC1286 and LTC1298 are micropower, 12-bit, suc­cessive approximation sampling A/D converters. The
LTC1286 typically draws 250µA of supply current when
sampling at 12.5kHz while the LTC1298 nominally con­sumes 350µA of supply current when sampling at

11.1 kHz. The extra 100µA of supply current on the
LTC1298 comes from the reference input which is inten­tionally tied to the supply. Supply current drops linearly as
the sample rate is reduced (see Supply Current vs Sample
Rate). The ADCs automatically power down when not
performing conversions, drawing only leakage current.
They are packaged in 8-pin SO and DIP packages. The
LTC1286 operates on a single supply from 4.5V to 9V,

V

OL

t

en

B11

LTC1286/98 • TC07

while the LTC1298 operates from a 4.5V to 5.5V supply.
Both the LTC1286 and the LTC1298 contain a 12-bit,

switched-capacitor ADC, a sample-and-hold, and a
serial port (see Block Diagram). Although they share
the same basic design, the LTC1286 and LTC1298
differ in some respects. The LTC1286 has a differential
input and has an external reference input pin. It can
measure signals floating on a DC common-mode volt­age and can operate with reduced spans to 1V. Reduc­ing the spans allows it to achieve 244µ V resolution. The
LTC1298 has a two-channel input multiplexer and can
convert either channel with respect to ground or the
difference between the two. The reference input is tied
to the supply pin.

9

LTC1286/LTC1298

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APPLICATION INFORMATION

SERIAL INTERFACE

The 2-channel LTC1298 communicates with micropro­cessors and other external circuitry via a synchronous,
half duplex, 4-wire serial interface. The single channel
LTC1286 uses a 3-wire interface (see Operating Sequence
in Figures 1 and 2).

Data Transfer

The CLK synchronizes the data transfer with each bit being
transmitted on the falling CLK edge and captured on the
rising CLK edge in both transmitting and receiving systems.

The LTC1286 does not require a configuration input word
and has no DIN pin. A falling CS initiates data transfer as
shown in the LTC1286 operating sequence. After CS falls
the second CLK pulse enables D

CS

. After one null bit the

OUT

t

CYC

A/D conversion result is output on the D

line. Bringing

OUT

CS high resets the LTC1286 for the next data exchange.
The LTC1298 first receives input data and then transmits

back the A/D conversion result (half duplex). Because of
the half duplex operation, DIN and D

may be tied

OUT

together allowing transmission over just 3 wires: CS, CLK
and DATA (DIN/D

OUT

).

Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1298 looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
DIN input which configures the LTC1298 and starts the
conversion. After one null bit, the result of the conversion
is output on the D

line. At the end of the data exchange

OUT

CS should be brought high. This resets the LTC1298 in
preparation for the next data exchange.

t

DATA

POWER
DOWN

HI-Z

NULL 

BIT

B11

B10 B9 B8

POWER DOWN

t

DATA

HI-Z

B11*



LTC1286/98 • F01

B10

B9B8

t

suCS

CLK

NULL 

D

OUT

CS

CLK

D

OUT

HI-Z

BIT

t

SMPL

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, 
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY.

t

suCS

NULL

HI-Z

BIT

t

SMPL

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, 
THE ADC WILL OUTPUT ZEROS INDEFINITELY.

t

: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT

DATA

 BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.

B10B11

(MSB)

B10B11

(MSB)

B8B9

B8B9

B7

t

B7

t

CONV

CONV

B6

B6

B4 B3 B2 B1

B5

B4

B5

B0*

t

CYC

B2 B2B1

B3 B3 B4 B5 B6 B7

B0 B1

10

Figure 1. LTC1286 Operating Sequence

LTC1286/LTC1298

U

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APPLICATION INFORMATION

CS

DIN 1 DIN 2

SHIFT MUX

ADDRESS IN

1 NULL BIT

MSB-First Data (MSBF = 0)

CS

t

suCS

CLK

D

1 D

OUT

SHIFT A/D CONVERSION
RESULT OUT

t

CYC

OUT

2

LTC1096/98 • AI01

POWER DOWN

OUT

SGL/
DIFF

ODD/
SIGN

MSBF

HI-Z

t

SMPL

NULL

BIT

START

D

IN

D

MSB-First Data (MSBF = 1)

CS

t

suCS

CLK

START

D

IN

D

OUT

ODD/
SIGN

MSBF

SGL/

HI-Z

DIFF

t

SMPL

NULL

BIT

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, 
THE ADC WILL OUTPUT ZEROS INDEFINITELY.

t

: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT

DATA

 BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.

(MSB)

(MSB)

DON'T CARE

HI-Z

B11

*



LTC1286/98 • F02

B10

B2B2B1 B0 B1

B3

B4

B4 B3 B2 B1

B5

B0*

B8B9

B6

B7

t

CONV

DON'T CARE

B6

B7

t

CONV

B5

t

B8B9

CYC

B10B11

B10B11

B3 B4 B5 B6 B7

POWER
DOWN

HI-Z

t

DATA

t

DATA

B9B8

Figure 2. LTC1298 Operating Sequence Example: Differential Inputs (CH+, CH–)

11

LTC1286/LTC1298

OUTPUT CODE







•

•

•

1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 0





0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0

INPUT VOLTAGE



V

REF

– 1LSB

V

REF

– 2LSB

•

•

•

1LSB

0V

INPUT VOLTAGE

(V

REF

= 5.000V)



4.99878V

4.99756V

•

•

•

0.00122V
0V

LTC1286/98 • AI05

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APPLICATION INFORMATION

Input Data Word

The LTC1286 requires no DIN word. It is permanently
configured to have a single differential input. The conver­sion result appears on the D
MSB first followed by the LSB sequence. This provides
easy interface to MSB or LSB first serial ports. For MSB
first data the CS signal can be taken high after B0 (see
Figure 1). The LTC1298 clocks data into the DIN input on
the rising edge of the clock. The input data words are
defined as follows:

SGL/
DIFF

ADDRESS

Start Bit

The first “logical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1298 will ignore all leading zeros which
precede this logical one. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputs on the DIN pin are then ignored until the next CS
cycle.

line. The data format is

OUT

ODD/

MSBFSTART

SIGN

MUX

MSB FIRST/

LSB FIRST

LTC1096/9 • AI02

MSBF bit is a logical zero, LSB first data will follow the
normal MSB first data on the D

line. (see Operating

OUT

Sequence)

Transfer Curve

The LTC1286/LTC1298 are permanently configured for
unipolar only. The input span and code assignment for
this conversion type are shown in the following figures.

Transfer Curve

1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 0

•

•

•

0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0

0V

1LSB

1LSB =

V

REF

4096

V

REF

–2LSB

REF

Output Code

V
–1LSB

LTC1286/98 • AI04

REF

V

V

IN

Multiplexer (MUX) Address

The bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the + and
– signs in the selected row of the following tables. In
single-ended mode, all input channels are measured with
respect to GND.

SINGLE-ENDED

DIFFERENTIAL



MSB First/LSB First (MSBF)

The output data of the LTC1298 is programmed for
MSB first or LSB first sequence using the MSBF bit.
When the MSBF bit is a logical one, data will appear on
the D

OUT

filled in indefinitely following the last data bit. When the

12

LTC1298 Channel Selection

MUX ADDRESS

SGL/DIFF

MUX MODE

MUX MODE

line in MSB first format. Logical zeros will be

ODD/SIGN

1
1
0
0

0
1
0
1

CHANNEL #

0

+


+
–

1

GND



–

+

–
–
+

LTC1096/8 • AI03



Operation with DIN and D

The LTC1298 can be operated with DIN and D

Tied Together

OUT

OUT

tied
together. This eliminates one of the lines required to
communicate to the microprocessor (MPU). Data is trans­mitted in both directions on a single wire. The processor
pin connected to this data line should be configurable as
either an input or an output. The LTC1298 will take control
of the data line and drive it low on the 4th falling CLK edge
after the start bit is received (see Figure 3). Therefore the
processor port line must be switched to an input before
this happens to avoid a conflict.

In the Typical Applications section, there is an example of
interfacing the LTC1298 with D

IN

and D

tied together to

OUT

the Intel 8051 MPU.

LTC1286/LTC1298

U

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APPLICATION INFORMATION

CS

1

CLK

DATA (D

IN/DOUT

)

START SGL/DIFF ODD/SIGN MSBF B11 B10

MPU CONTROLS DATA LINE AND SENDS

MUX ADDRESS TO LTC1298

Figure 3. LTC1298 Operation with DIN and D

ACHIEVING MICROPOWER PERFORMANCE

With typical operating currents of 250µA and automatic
shutdown between conversions, the LTC1286/LTC1298
achieves extremely low power consumption over a wide
range of sample rates (see Figure 4). The auto-shutdown
allows the supply curve to drop with reduced sample rate.
Several things must be taken into account to achieve such
a low power consumption.

2 3 4

PROCESSOR MUST RELEASE 

DATA LINE AFTER 4TH RISING CLK 

AND BEFORE THE 4TH FALLING CLK

MSBF BIT LATCHED

BY LTC1298

•••

LTC1298 CONTROLS DATA LINE AND SENDS

A/D RESULT BACK TO MPU

LTC1298 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK

Tied Together

OUT

LTC1286/98 F03

input becomes high impedance at the end of each conver­sion leaving the CLK running to clock out the LSB first data
or zeroes (see Figures 1 and 2). If the CS is not running rail­to-rail, the input logic buffer will draw current. This current
may be large compared to the typical supply current. To
obtain the lowest supply current, bring the CS pin to
ground when it is low and to supply voltage when it is high.

1000

TA = 25°C

= V

CC

REF

= 200kHz

CLK

LTC1298

SAMPLE RATE (kHz)

= 5V

LTC1286

1k 10k 100k

LT1286/98 G03

V
f

100

10

SUPPLY CURRENT (µA)

1

0.1k

Figure 4. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate.

Shutdown

The LTC1286/LTC1298 are equipped with automatic shut­down features. They draw power when the CS pin is low
and shut down completely when that pin is high. The bias
circuit and comparator powers down and the reference

When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the DIN and CLK input have no effect on supply
current during this time. There is no need to stop DIN and
CLK with CS = high; they can continue to run without
drawing current.

Minimize CS Low Time

In systems that have significant time between conver­sions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transferring data as quickly as
possible, and then bringing it back high will result in the
lowest current drain. This minimizes the amount of time
the device draws power. After a conversion the ADC
automatically shuts down even if CS is held low (see
Figures 1 and 2). If the clock is left running to clock out
LSB-data or zero, the logic will draw a small current.
Figure 5 shows that the typical supply current with CS =
ground varies from 1µ A at 1kHz to 35µ A at 200kHz. When
CS = VCC, the logic is gated off and no supply current is
drawn regardless of the clock frequency.

13

LTC1286/LTC1298

+IN

–IN

GND

V

CC

CLK

D

OUT

V

REF

50k

50k

5V

4.7µF

MPU

(e.g. 8051)

5V

P1.4
P1.3
P1.2

LTC1286/98 • F06

DIFFERENTIAL INPUTS

COMMON-MODE RANGE

0V TO 5V

9V

LTC1286

CS



U

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APPLICATION INFORMATION

35

TA = 25°C

30

= V

V

25

20

15

10

5

SUPPLY CURRENT (µA)

1

0.002

0

1

Figure 5. Shutdown current with CS high is 1nA typically,
regardless of the clock. Shutdown current with CS = ground
varies from 1µA at 1kHz to 35µA at 200kHz.

D

Loading

OUT

Capacitive loading on the digital output can increase power
consumption. A 100pF capacitor on the D
more than 50µA to the supply current at a 200kHz clock
frequency. An extra 50µA or so of current goes into
charging and discharging the load capacitor. The same
goes for digital lines driven at a high frequency by any logic.
The C × V × f currents must be evaluated and the trouble­some ones minimized.

OPERATING ON OTHER THAN 5V SUPPLIES (LTC1286)

The LTC1286 operates from 4.5V to 9V supplies and the
LTC1298 operates from a 5V supply. To operate the LTC1286
on other than 5V supplies a few things must be kept in
mind.

= 5V

CC

REF

CS = 0
(AFTER CONVERSION)

CS = V

CC

60

80

40

20

FREQUENCY (kHz)

120 160

100

140

180

LT1286/98 G01

OUT

200

pin can add

Clock Frequency

The maximum recommended clock frequency is 200kHz
for the LTC1286/LTC1298 running off a 5V supply. With
the supply voltage changing, the maximum clock fre­quency for the devices also changes (see the typical curve
of Maximum Clock Rate vs Supply Voltage). If the maxi­mum clock frequency is used, care must be taken to
ensure that the device converts correctly.

Mixed Supplies

It is possible to have a microprocessor running off a 5V
supply and communicate with the LTC1286 operating on
a 9V supply. The requirement to achieve this is that the
outputs of CS and CLK from the MPU have to be able to trip
the equivalent inputs of the LTC1286 and the output of
D

from the LTC1286 must be able to toggle the

OUT

equivalent input of the MPU (see typical curve of Digital
Input Logic Threshold vs Supply Voltage). With the
LTC1286 operating on a 9V supply, the output of D

OUT

may

go between 0V and 9V. The 9V output may damage the
MPU running off a 5V supply. The way to get around this
possibility is to have a resistor divider on D

(Figure 6)

OUT

and connect the center point to the MPU input. It should
be noted that to get full shutdown, the CS input of the
LTC1286 must be driven to the VCC voltage to keep the CS
input buffer from drawing current. An alternative is to
leave CS low after a conversion, clock data until D

OUT

outputs zeros, and then stop the clock low.

Input Logic Levels

The input logic levels of CS, CLK and DIN are made to meet
TTL on a 5V supply. When the supply voltage varies, the
input logic levels also change. For the LTC1286 to sample
and convert correctly, the digital inputs have to be in the
proper logical low and high levels relative to the operating
supply voltage (see typical curve of Digital Input Logic
Threshold vs Supply Voltage). If achieving micropower
consumption is desirable, the digital inputs must go rail-to­rail between supply voltage and ground (see ACHIEVING
MICROPOWER PERFORMANCE section).

14

Figure 6. Interfacing a 9V Powered LTC1286 to a 5V System

LTC1286/LTC1298

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APPLICATION INFORMATION

BOARD LAYOUT CONSIDERATIONS

Grounding and Bypassing

The LTC1286/LTC1298 are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.

The VCC pin should be bypassed to the ground plane with
a 10µ F tantalum capacitor with leads as short as possible.
If the power supply is clean, the LTC1286/LTC1298 can
also operate with smaller 1µF or less surface mount or
ceramic bypass capacitors. All analog inputs should be
referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or routed
away from the reference and analog circuitry.

SAMPLE-AND-HOLD

Both the LTC1286 and the LTC1298 provide a built-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1286 acquires input signals from “+” input
relative to “–” input during the t

time (see Figure 1).

SMPL

However, the S&H of the LTC1298 can sample input
signals in the single-ended mode or in the differential
inputs during the t

time (see Figure 7).

SMPL

Single-Ended Inputs

The sample-and-hold of the LTC1298 allows conversion
of rapidly varying signals. The input voltage is sampled
during the t

time as shown in Figure 7. The sampling

SMPL

interval begins as the bit preceding the MSBF bit is shifted
in and continues until the falling CLK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.

CS

CLK

D

D

OUT

"+" INPUT

"–" INPUT

SAMPLE HOLD

"+" INPUT MUST

SETTLE DURING

THIS TIME

t

SMPL

IN

SGL/DIFFSTART MSBF DON'T CARE

1ST BIT TEST "–" INPUT MUST

SETTLE DURING THIS TIME

t

CONV

B11

LTC1096/8 • F07

Figure 7. LTC1298 “+” and “–” Input Settling Windows

15

LTC1286/LTC1298

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APPLICATION INFORMATION

Differential Inputs

With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt­ages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the volt­age on the selected “–” input must remain constant and be
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be per­formed accurately. The conversion time is 12 CLK cycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:

V

ERROR (MAX)

Where f(“–”) is the frequency of the “–” input voltage,
V

is its peak amplitude and f

PEAK

CLK. In most cases V
60Hz signal on the “–” input to generate a 1/4LSB error
(305µV) with the converter running at CLK = 200kHz, its
peak value would have to be 13.48mV.

ANALOG INPUTS

Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1286/
LTC1298 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used or
if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.

= V

× 2 × π × f(“–”) × 12/f

PEAK

is the frequency of the

CLK

will not be significant. For a

ERROR

CLK

sample time can be increased by using a slower CLK
frequency.

“–” Input Settling

At the end of the t

, the input capacitor switches to the

SMPL

“–” input and conversion starts (see Figures 1 and 7).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage settles completely during the first CLK cycle of the
conversion time and be free of noise. Minimizing R

SOURCE

–

and C2 will improve settling time. If a large “–” input
source resistance must be used, the time allowed for
settling can be extended by using a slower CLK frequency.

Input Op Amps

When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the“+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps, including the LT1006 and
LT1413 single supply op amps, can be made to settle well
even with the minimum settling windows of 6µs (“+”
input) which occur at the maximum clock rate of 200kHz.

Source Resistance

The analog inputs of the LTC1286/LTC1298 look like a
20pF capacitor (CIN) in series with a 500Ω resistor (RON)
as shown in Figure 8. CIN gets switched between the
selected “+” and “–” inputs once during each conversion
cycle. Large external source resistors and capacitances

“+” Input Settling

The input capacitor of the LTC1286 is switched onto “+”
input during the t

time (see Figure 1) and samples the

SMPL

input signal within that time. However, the input capacitor
of the LTC1298 is switched onto “+” input during the
sample phase (t

, see Figure 7). The sample phase is

SMPL

1 1/2 CLK cycles before conversion starts. The voltage on
the “+” input must settle completely within t

SMPLE

for the
LTC1286 and the LTC1298 respectively. Minimizing
R

SOURCE

+

and C1 will improve the input settling time. If a

large “+” input source resistance must be used, the

16

VIN +


VIN –


“+”

+

R

SOURCE

R

SOURCE

Figure 8. Analog Input Equivalent Circuit

INPUT

C1


“–”

–

INPUT

C2


RON = 500Ω

LTC1286/98

C

= 20pF

IN

LTC1286/98 • F08

LTC1286/LTC1298

U

WUU

APPLICATION INFORMATION

will slow the settling of the inputs. It is important that the
overall RC time constants be short enough to allow the
analog inputs to completely settle within the allowed time.

RC Input Filtering

It is possible to filter the inputs with an RC network as
shown in Figure 9. For large values of CF (e.g., 1µF), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately IDC = 20pF × VIN/t
proportional to VIN. When running at the minimum cycle
time of 64µ s, the input current equals 1.56µA at VIN = 5V.
In this case, a filter resistor of 75Ω will cause 0.1LSB of
full-scale error. If a larger filter resistor must be used,
errors can be eliminated by increasing the cycle time.



I

R
VIN


DC

FILTER



C

Figure 9. RC Input Filtering

FILTER

“+”

LTC1286

“–”

Input Leakage Current

Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum
input leakage specification of 1µA (at 125°C) flowing
through a source resistance of 240Ω will cause a voltage
drop of 240µ V or 0.2LSB. This error will be much reduced
at lower temperatures because leakage drops rapidly (see
typical curve of Input Channel Leakage Current vs Tem­perature).

REFERENCE INPUTS

The reference input of the LTC1286 is effectively a 50kΩ
resistor from the time CS goes low to the end of the
conversion. The reference input becomes a high impedence
node at any other time (see Figure 10). Since the voltage
on the reference input defines the voltage span of the A/D

and is roughly

CYC

LTC1286/98 • F09

converter, the reference input should be driven by a
reference with low R
or a voltage source with low R

R



OUT



V



REF



Figure 10. Reference Input Equivalent Circuit

(ex. LT1004, LT1019 and LT1021)

OUT

.

OUT

+

REF

GND

1



4



LTC1286

LTC1286/98 • F10

Reduced Reference Operation

The minimum reference voltage of the LTC1298 is limited
to 4.5V because the VCC supply and reference are inter­nally tied together. However, the LTC1286 can operate
with reference voltages below 1V.

The effective resolution of the LTC1286 can be increased
by reducing the input span of the converter. The LTC1286
exhibits good linearity and gain over a wide range of
reference voltages (see typical curves of Change in Linear­ity vs Reference Voltage and Change in Gain vs Reference
Voltage). However, care must be taken when operating at
low values of V

because of the reduced LSB step size

REF

and the resulting higher accuracy requirement placed on
the converter. The following factors must be considered
when operating at low V

values:

REF

1. Offset

2. Noise

3. Conversion speed (CLK frequency)

Offset with Reduced V

REF

The offset of the LTC1286 has a larger effect on the output
code. When the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The typical curve of Change in Offset vs
Reference Voltage shows how offset in LSBs is related to
reference voltage for a typical value of VOS. For example,
a VOS of 122µV which is 0.1LSB with a 5V reference
becomes 0.5LSB with a 1V reference and 2.5LSBs with a

17

LTC1286/LTC1298

U

WUU

APPLICATION INFORMATION

0.2V reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the “–” input of the LTC1286.

Noise with Reduced V

The total input referred noise of the LTC1286 can be
reduced to approximately 400µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
is insignificant with a 5V reference but will become a larger
fraction of an LSB as the size of the LSB is reduced.

For operation with a 5V reference, the 400µV noise is
only 0.33LSB peak-to-peak. In this case, the LTC1286
noise will contribute virtually no uncertainty to the
output code. However, for reduced references the noise
may become a significant fraction of an LSB and cause
undesirable jitter in the output code. For example, with
a 2.5V reference this same 400µV noise is 0.66LSB
peak-to-peak. This will reduce the range of input volt­ages over which a stable output code can be achieved by
1LSB. If the reference is further reduced to 1V, the 400µ V
noise becomes equal to 1.65LSBs and a stable code may
be difficult to achieve. In this case averaging multiple
readings may be necessary.

This noise data was taken in a very clean setup. Any setup
induced noise (noise or ripple on VCC, V
to the internal noise. The lower the reference voltage to be
used the more critical it becomes to have a clean, noise free
setup.

Conversion Speed with Reduced V

With reduced reference voltages, the LSB step size is
reduced and the LTC1286 internal comparator over­drive is reduced. Therefore, it may be necessary to
reduce the maximum CLK frequency when low values
of V

are used.

REF

DYNAMIC PERFORMANCE

The LTC1286/LTC1298 have exceptional sampling capa­bility. Fast Fourier Transform (FFT) test techniques are
used to characterize the ADC’s frequency response, dis-

REF

or VIN) will add

REF

REF

tortion and noise at the rated throughput. By applying a low
distortion sine wave and analyzing the digital output using
an FFT algorithm, the ADC’s spectral content can be
examined for frequencies outside the fundamental. Figure
11 shows a typical LTC1286 plot.

0

TA = 25°C

= V

CC

REF

= 5kHz

IN

= 200kHz

= 12.5kHz

12

= 5V

467

35

FREQUENCY (kHz)

LTC 1286/98 G21

V

–20

f
f

CLK

–40

f

SMPL




–60



–80

MAGNITUDE (dB)

–100

–120

–140

0

Figure 11. LTC1286 Non-Averaged, 4096 Point FFT Plot

Signal-to-Noise Ratio

T

he Signal-to-Noise plus Distortion Ratio (S/N + D) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre­quency components at the ADC’s output. The output is
band limited to frequencies above DC and below one half
the sampling frequency. Figure 12 shows a typical spec­tral content with a 12.5kHz sampling rate.

Effective Number of Bits

The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to S/(N+D)
by the equation:

ENOB = [S/(N + D) – 1.76]/6.02

where S/(N + D) is expressed in dB. At the maximum
sampling rate of 12.5kHz with a 5V supply, the LTC1286
maintains above 11 ENOBs at 10kHz input frequency.
Above 10kHz the ENOBs gradually decline, as shown in
Figure 12, due to increasing second harmonic distortion.
The noise floor remains low.

18

LTC1286/LTC1298

IMD f f

mplitude f f

ab

ab

±

()

=

±

()















20log

a

amplitude at f

a

U

WUU

APPLICATION INFORMATION

12
11

10

9
8
7
6
5
4

3

TA = 25°C

= 5V

V

CC

2

= 200kHz

f

CLK

EFFECTIVE NUMBER OF BITS (ENOBs)

1

= 12.5kHz

f

SMPL



0



1

Figure 12. Effective Bits and S/(N + D) vs Input Frequency

10 100 1000

INPUT FREQUENCY (kHz)

LTC 1286/98 G20

Total Harmonic Distortion

Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half of the sampling frequency. THD
is defined as:

2

V

1

...

THD =

20log

++++

VVV V

22324

74
68

62
56
50
44
38

2

N

If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func­tion can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
waves are equal in magnitudes, the value (in dB) of the 2nd
order IMD products can be expressed by the following
formula:

For input frequencies of 5kHz and 6kHz, the IMD of the
LTC1286/LTC1298 is 73dB with a 5V supply.

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spec­tral component excluding the input signal and DC. This
value is expressed in dBs relative to the RMS value of a full­scale input signal.

Full-Power and Full-Linear Bandwidth

where V1 is the RMS amplitude of the fundamental fre­quency and V2 through VN are the amplitudes of the
second through the Nth harmonics. The typical THD speci­fication in the Dynamic Accuracy table includes the 2nd
through 5th harmonics. With a 7kHz input signal, the
LTC1286/LTC1298 have typical THD of 80dB with VCC = 5V.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition
to THD. IMD is the change in one sinusoidal input
caused by the presence of another sinusoidal input at a
different frequency.

The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re­duced by 3dB for a full-scale input.

The full-linear bandwidth is the input frequency at which
the effective bits rating of the ADC falls to 11 bits. Beyond
this frequency, distortion of the sampled input signal
increases. The LTC1286/LTC1298 have been designed to
optimize input bandwidth, allowing the ADCs to
undersample input signals with frequencies above the
converters’ Nyquist Frequency.

19

LTC1286/LTC1298

U

TYPICAL APPLICATIONS N

MICROPROCESSOR INTERFACES

The LTC1286/LTC1298 can interface directly without ex­ternal hardware to most popular microprocessor (MPU)
synchronous serial formats (see Table 1). If an MPU
without a dedicated serial port is used, then 3 or 4 of the
MPU's parallel port lines can be programmed to form the
serial link to the LTC1286/LTC1298. Included here is one
serial interface example and one example showing a
parallel port programmed to form the serial interface.

Motorola SPI (MC68HC11)

The MC68HC11 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MSB

-first and in 8-bit increments. The DIN word sent to the data
register starts with the SPI process. With three 8-bit
transfers, the A/D result is read into the MPU. The second
8-bit transfer clocks B11 through B8 of the A/D conversion
result into the processor. The third 8-bit transfer clocks
the remaining bits, B7 through B0, into the MPU. The data
is right justified into two memory locations. ANDing the
second byte with OF

clears the four most significant

HEX

bits. This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.

MC68HC11 Code

In this example the D

word configures the input MUX for

IN

a single-ended input to be applied to CHO. The conversion
result is output MSB-first.

Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1286/LTC1298

PART NUMBER TYPE OF INTERFACE

Motorola

MC6805S2,S3 SPI
MC68HC11 SPI
MC68HC05 SPI

RCA

CDP68HC05 SPI

Hitachi

HD6305 SCI Synchronous
HD63705 SCI Synchronous
HD6301 SCI Synchronous
HD63701 SCI Synchronous
HD6303 SCI Synchronous
HD64180 CSI/O

National Semiconductor

COP400 Family MICROWIRE
COP800 Family MICROWIRE/PLUS
NS8050U MICROWIRE/PLUS
HPC16000 Family MICROWIRE/PLUS

Texas Instruments

TMS7002 Serial Port
TMS7042 Serial Port
TMS70C02 Serial Port
TMS70C42 Serial Port
TMS32011* Serial Port
TMS32020 Serial Port

Intel

8051 Bit Manipulation on Parallel Port

* Requires external hardware

†

MICROWIRE and MICROWIRE/PLUS are trademarks of
National Semiconductor Corp.

†

†

†

†

20

U

TYPICAL APPLICATIONS N

Timing Diagram for Interface to the MC68HC11

CS

CLK

D

IN

D

OUT

START

SGL/

DIFF

ODD/

SIGN

MSBF

LTC1286/LTC1298

DON'T CARE

B3B7 B6 B5 B4 B2 B0B1B11 B10 B9 B8

MPU

TRANSMIT

WORD

MPU

RECEIVED

WORD

000

BYTE 1

BYTE 1

0000

????????

1

SGL/
DIFF

ODD/
SIGN

?

?

Hardware and Software Interface to the MC68HC11

D

FROM LTC1298 STORED IN MC68HC11 RAM

OUT

MSB

0

#62

#63

0

B6

B7 B5

LABEL MNEMONIC OPERAND COMMENTS

LDAA #$50 CONFIGURATION DATA FOR SPCR
STAA $1028 LOAD DATA INTO SPCR ($1028)
LDAA #$1B CONFIG. DATA FOR PORT D DDR
STAA $1009 LOAD DATA INTO PORT D DDR
LDAA #$01 LOAD DIN WORD INTO ACC A
STAA $50 LOAD DIN DATA INTO $50
LDAA #$A0 LOAD DIN WORD INTO ACC A
STAA $51 LOAD DIN DATA INTO $51
LDAA #$00 LOAD DUMMY DIN WORD INTO

STAA $52 LOAD DUMMY DIN DATA INTO $52
LDX #$1000 LOAD INDEX REGISTER X WITH

LOOP BCLR $08,X,#$01 D0 GOES LOW (CS GOES LOW)

LDAA $50 LOAD DIN INTO ACC A FROM $50
STAA $102A LOAD DIN INTO SPI, START SCK
LDAA $1029 CHECK SPI STATUS REG

0

ACC A

$1000

0 B11

LSB

B4

B9 B8

B10

B2 B1

B3

B0

MSBF

?

X

BYTE 2

0

BYTE 2

BYTE 1

BYTE 2

X

B11

ANALOG

INPUTS

X

B10

X

X

B8

B9

CH0

LTC1298

CH1

X

B7

CS

CLK

D

OUT

D

IN

X

XX

X

BYTE 3 (DUMMY)

B6

B5 B3

B4

BYTE 3

X

B2

D0

SCK

MC68HC11

MISO

MOSI

LTC1286/98 AI07

LABEL MNEMONIC OPERAND COMMENTS

WAIT1 BPL WAIT1 CHECK IF TRANSFER IS DONE

LDAA $51 LOAD DIN INTO ACC A FROM $51
STAA $102A LOAD DIN INTO SPI, START SCK

WAIT2 LDAA $1029 CHECK SPI STATUS REG

BPL WAIT2 CHECK IF TRANSFER IS DONE
LDAA $102A LOAD LTC1291 MSBs INTO ACC A
STAA $62 STORE MSBs IN $62
LDAA $52 LOAD DUMMY INTO ACC A

FROM $52

STAA $102A LOAD DUMMY DIN INTO SPI,

START SCK

WAIT3 LDAA $1029 CHECK SPI STATUS REG

BPL WAIT3 CHECK IF TRANSFER IS DONE
BSET $08,X#$01 DO GOES HIGH (CS GOES HIGH)
LDAA $102A LOAD LTC1291 LSBs IN ACC
STAA $63 STORE LSBs IN $63
JMP LOOP START NEXT CONVERSION

X

X

B1

B0

LTC1286/98 AI06



21

LTC1286/LTC1298

U

TYPICAL APPLICATIONS N

Interfacing to the Parallel Port of the INTEL 8051
Family

The Intel 8051 has been chosen to demonstrate the
interface between the LTC1298 and parallel port micro­processors. Normally the CS, CLK and DIN signals would
be generated on 3 port lines and the D

signal read on

OUT

a 4th port line. This works very well. However, we will
demonstrate here an interface with the DIN and D

OUT

of the
LTC1298 tied together as described in the SERIAL INTER­FACE section. This saves one wire.

The 8051 first sends the start bit and MUX address to the
LTC1298 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and the
8051 reads back the 12-bit A/D result over the same data
line.

CS

ANALOG

INPUTS

D

FROM 1298 STORED IN 8501 RAM

OUT

LTC1298

CLK



D

OUT

D

IN

MUX ADDRESS

A/D RESULT

P1.4
P1.3
P1.2


8051

LTC1286/98 TA01

LABEL MNEMONIC OPERAND COMMENTS

MOV A, #FFH DIN word for LTC1298
SETB P1.4 Make sure CS is high
CLR P1.4 CS goes low

LOOP 1 RLC A Rotate D

LOOP 2 MOV C, P1.2 Read data bit into Carry

LOOP 3 MOV C, P1.2 Read data bit into Carry

LOOP 4 RRC A Rotate right into Acc.

MOV R4, #04 Load counter

CLR P1.3 SCLK goes low
MOV P1.2, C Output DIN bit to LTC1298
SETB P1.3 SCLK goes high
DJNZ R4, LOOP 1 Next bit
MOV P1, #04 Bit 2 becomes an input
CLR P1.3 SCLK goes low
MOV R4, #09 Load counter

RLC A Rotate data bit into Acc.
SETB P1.3 SCLK goes high
CLR P1.3 SCLK goes low
DJNZ R4, LOOP 2 Next bit
MOV R2, A Store MSBs in R2
CLR A Clear Acc.
MOV R4, #04 Load counter

RLC A Rotate data bit into Acc.
SETB P1.3 SCLK goes high
CLR P1.3 SCLK goes low
DJNZ R4, LOOP 3 Next bit
MOV R4, #04 Load counter

DJNZ R4, LOOP 4 Next Rotate
MOV R3, A Store LSBs in R3
SETB P1.4 CS goes high

bit into Carry

IN

MSB

R2 B11 B10 B9 B8 B7 B6 B5 B4

LSB

R3 B3 B2 B1 B0 0 0 0 0

MSBF BIT LATCHED 

INTO LTC1298

MSBF B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

ODD/ 

SIGN

D

(

DATA 

/D

IN

CS

CLK

START

)

OUT

8051 P1.2 OUTPUTS DATA 

TO LTC1298

AS IN INPUT AFTER THE 4TH RISING CLK

8051 P1.2 RECONFIGURED

AND BEFORE THE 4TH FALLING CLK

SGL/

DIFF

LTC1298 SENDS A/D RESULT

BACK TO 8051 P1.2

LTC1298 TAKES CONTROL OF DATA
LINE ON 4TH FALLING CLK

LTC1286/98 TA02

22

U

TYPICAL APPLICATIONS N

A “Quick Look” Circuit for the LTC1286

LTC1286/LTC1298

Users can get a quick look at the function and timing of the
LT1286 by using the following simple circuit (Figure 13).
V

is tied to VCC. VIN is applied to the +IN input and the

REF

–IN input is tied to the ground. CS is driven at 1/16 the
clock rate by the 74C161 and D
output data from the D

OUT

outputs the data. The

OUT

pin can be viewed on an
oscilloscope that is set up to trigger on the falling edge of
CS (Figure 14). Note the LSB data is partially clocked out
before CS goes high.

VCC

CLK

D

OUT

CS







5V

TO OSCILLOSCOPE

CLR
CLK
A
B

74C161

C
D
P
GND

CLOCK IN 250kHz

V

CC

RC
QA
QB
QC
QD

LOAD



T

5V

LTC1286/98 F13

4.7µF

V



REF

V

+IN

IN

LTC1286

–IN

GND

Micropower Battery Voltage Monitor

A common problem in battery systems is battery voltage
monitoring. This circuit monitors the 10 cell stack of NiCad
or NiMH batteries found in laptop computers. It draws only
67µA from the 5V supply at f

= 0.1kHz and 25µA to

SMPL

55µA from the battery. The 12-bits of resolution of the
LTC1286 are positioned over the desired range of 8V to
16V. This is easily accomplished by using the ADC’s
differential inputs. Tying the –input to the reference gives
an ADC input span of V

REF

to 2V

(2.5V to 5V). The

REF

resistor divider then scales the input voltage for 8V to 16V.

BATTERY MONITOR 

INPUT 8V TO 16V

200k

91k

39k

LT1004-2.5

0.1µF

1µF

3Ω

+IN

–IN


LTC1286

V

REF

5V

V

CC

GND

CS

CLK

D

OUT

Figure 13. “Quick Look” Circuit for the LTC1286

NULL

BIT

MSB

(B11)

VERTICAL: 5V/DIV
HORIZONTAL: 10µs/DIV

LSB
(B0)

LTC1286/98 F14

Figure 14. Scope Trace the LTC1286 “Quick Look” Circuit
Showing A/D Output 101010101010 (AAA

HEX

)

LTC1286/98 F15

Figure 15. Micropower Battery Voltage Monitor

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of circuits as described herein will not infringe on existing patent rights.

23

LTC1286/LTC1298

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

N8 Package

8-Lead Plastic DIP

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

0.300 – 0.320

(7.620 – 8.128)

0.065

(1.651)

0.009 – 0.015

(0.229 – 0.381)

+0.025

0.325

–0.015
+0.635

8.255

()

–0.381

TYP

0.045 ± 0.015

(1.143 ± 0.381)

(2.540 ± 0.254)

0.045 – 0.065

(1.143 – 1.651)

0.100 ± 0.010

8-Lead Plastic SOIC

0.010 – 0.020

× 45°

0.016 – 0.050

0.406 – 1.270

0.053 – 0.069

(1.346 – 1.752)

0°– 8° TYP

0.014 – 0.019

(0.355 – 0.483)

0.018 ± 0.003

(0.457 ± 0.076)

S8 Package

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN



0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

0.020

(0.508)

MIN

0.228 – 0.244

(5.791 – 6.197)

0.400

(10.160)

MAX

876

12

3

0.189 – 0.197*
(4.801 – 5.004)

7

8

5

4

6

0.250 ± 0.010

(6.350 ± 0.254)



5

0.150 – 0.157*
(3.810 – 3.988)



24

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7487

[phone]

●

FAX

: [phone]

●

TELEX

: 499-3977

1

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).

LT/GP 0394 10K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1994

3

2

4

SO8 0294