Datasheet LTC1282 Datasheet (Linear Technology)

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Page 1

LTC1282

3V 140ksps 12-Bit

Sampling A/D Converter

with Reference

EATU

■

Single Supply 3V or ±3V Operation

■

140ksps Throughput Rate

■

12mW (Typ) Power Dissipation

■

On-Chip 25ppm/°C Reference

■

Internal Synchronized Clock; No Clock Required

■

High Impedance Analog Input

■

69dB S/(N + D) and 77dB THD at Nyquist

■

±0.5LSB INL and ±0.75LSB DNL Max (A Grade)

■

2.7V Guaranteed Minimum Supply Voltage

■

ESD Protected On All Pins

■

24-Pin Narrow PDIP and SW Packages

■

0V to 2.5V or ±1.25V Input Ranges

PPLICATI

■

3V Powered Systems

■

High Speed Data Acquisition

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

■

Audio and Telecom Processing

■

Spectrum Analysis

, LTC and LT are registered trademarks of Linear Technology Corporation.

LTBiCMOS is a trademark of Linear Technology Corporation

U S

DUESCRIPTIO

The LTC®1282 is a 6µs, 140ksps, sampling 12-bit A/D converter that draws only 12mW from a single 3V or dual ±3V supply. This easy-to-use device comes complete with

1.14µ s sample-and-hold, precision reference and internally trimmed clock. Unipolar and bipolar conversion modes provide flexibility for various applications. They are built with LTBiCMOSTM switched capacitor technology.

The LTC1282 has a 25ppm/°C (max) internal reference and converts 0V to 2.5V unipolar inputs from a single 3V supply. With ±3V supplies its input range is ±1.25V with two’s complement output format. Maximum DC specifications include ±0.5LSB INL, ±0.75LSB DNL and 25ppm/°C full-scale drift over temperature. Outstanding AC performance includes 69dB S/(N + D) and 77dB THD at the Nyquist input frequency of 70kHz.

The internal clock is trimmed for 6µs maximum conver- sion time. The clock automatically synchronizes to each sample command eliminating problems with asynchronous clock noise found in competitive devices. A high speed parallel interface eases connections to FIFOs, DSPs and microprocessors.

PPLICATITYPICAL

Single 3V Supply, 140ksps, 12-Bit Sampling A/D Converter

1.20V V

REF

OUTPUT



10µF

8- OR 12-BIT

PARALLEL BUS

ANALOG INPUT

(0V TO 2.5V)

0.1µF

1 2 3 4 5 6 7 8

9 10 11 12

LTC1282

AIN V



REF

AGND D11(MSB) D10 D9 D8 D7 D6 D5 D4 DGND

V V

BUSY

RD

HBEN

NC

NC D0/8 D1/9

D2/10 D3/11

24



DD SS

CS



23 22 21 20 19 18 17 16 15 14 13

µP CONTROL LINES

10µF

1282 TA01

Effective Bits and Signal-to-(Noise + Distortion)

0.1µF

12 11 10

9 8 7 6 5 4 3 2

ENOBs (EFFECTIVE NUMBER OF BITS)

1 0

vs Input Frequency

= 140kHz

SAMPLE

INPUT FREQUENCY (Hz)

10k

NYQUIST

FREQUENCY

100k

LTC1282 • TA02

74 68 62 56

S/(N + D) (dB)

Page 2

LTC1282

(Notes 1 and 2)

LUTEXI T

WUW

ARB

U G

Supply Voltage (VDD).............................................. 12V

Negative Supply Voltage (VSS)................... –6V to GND

Total Supply Voltage (VDD to VSS) .......................... 12V

Analog Input Voltage

(Note 3) .............................. VSS – 0.3V to VDD + 0.3V

Digital Input Voltage (Note 4) ........... VSS – 0.3V to 12V

Digital Output Voltage

(Note 3) .............................. VSS – 0.3V to VDD + 0.3V

Power Dissipation............................................. 500mW

Specified Temperature Range (Note 14)..... 0°C to 70°C

Operating Temperature Range

LTC1282AC, LTC1282BC ......................... 0°C to 70°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

VERTER

CCHARA TERIST

With Internal Reference (Notes 5 and 6)

ICS

PACKAGE



REF

AGND

D11 (MSB)

D10

D9 D8 D7 D6 D5 D4

DGND

N PACKAGE

24-LEAD PDIP

JMAX

Consult factory for Industrial and Military grade parts. (Note 14)

RDER I FOR ATIO

TOP VIEW

1 2 3 4 5 6 7 8

9 10 11 12

24-LEAD PLASTIC SO WIDE

= 110°C, θJA = 100°C/W (N)

= 110°C, θJA = 130°C/W (SW)

VDD

24

23

BUSY

22

CS

21

RD

20

HBEN

19

NC

18

NC

17

D0/8

16

D1/9

15

D2/10

14

D3/11

SW PACKAGE

ORDER

PART NUMBER



LTC1282ACN LTC1282BCN LTC1282ACSW LTC1282BCSW

LTC1282A LTC1282B

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 12 12 Bits Integral Linearity Error (Note 7) ±1/2 ±1 LSB

Commercial Military

Differential Linearity Error Commercial ● ±3/4 ±1 LSB

Military

Offset Error (Note 8) ±3 ±4 LSB

Gain Error ±10 ±15 LSB Gain Error Tempco I Power Supply Rejection (Note 9) VDD ±10% ±0.3 ±0.3 LSB

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

S/(N + D) Signal-to-Noise Plus Distortion Ratio 10kHz/70kHz Input Signal 71/69 dB THD Total Harmonic Distortion 10kHz/70kHz Input Signal, Up to 5th Harmonic –82/–77 dB

IMD Intermodulation Distortion f

ACCURACY

Peak Harmonic or Spurious Noise 10kHz/70kHz Input Signal –82/–77 dB

Full Power Bandwidth 4 MHz Full Linear Bandwidth (S/(N + D) ≥ 68dB) 200 kHz

= 0 ● ±5 ±25 ±10 ±45 ppm/°C

OUT(REF)

(Note 10) VSS ±10% ±0.1 ±0.1 LSB

(Note 5)

● ±1/2 ±1 LSB

● ±3/4 ±1 LSB

● ±1 ±1 LSB

● ±4 ±6 LSB

LTC1282A/LTC1282B

= 19.0kHz, f

IN1

= 20.6kHz –78 dB

IN2

Page 3

LTC1282

U PUT

(Note 5)

LTC1282A/LTC1282B

3V ≤ VDD ≤ 3.6V, –3.3V ≤ VSS ≤ –2.5V (Bipolar Mode) ±1.25 V

During Conversions (Hold Mode) 5 pF

ACQ

LOG

Analog Input Range (Note 11) 2.7V ≤ VDD ≤ 3.6V (Unipolar Mode) 0 to 2.5 V

Analog Input Leakage Current CS = High ● ±1 µA Analog Input Capacitance Between Conversions (Sample Mode) 63 pF

Sample-and-Hold Commercial ● 0.45 1.14 µs Acquisition Time Military ● 1.5 µs

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I C

I TER AL REFERE CE CHARACTERISTICS (Note 5)

LTC1282BLTC1282A

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Output Voltage I

REF

Output Tempco I

REF

Line Regulation 2.7V ≤ VDD ≤ 3.6V 0.55 0.55 LSB/V

REF

Load Regulation 0V ≤ |I

REF

DIGITAL I PUTS A D DIGITAL OUTPUTS

= 0 1.1900 1.200 1.210 1.190 1.200 1.210 V

OUT

= 0 ● ±5 ±25 ±10 ±45 ppm/°C

OUT

–3.6V ≤ V

≤ –2.7V 0.02 0.02 LSB/V

| ≤ 1mA 3 3 LSB/mA

OUT

(Note 5)

LTC1282A/LTC1282B

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SOURCE

SINK

POWER REQUIRE E TS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

High Level Input Voltage V Low Level Input Voltage VDD = 2.7V ● 0.45 V Digital Input Current VIN = 0V to V Digital Input Capacitance 5pF High Level Output Voltage VDD = 2.7V

Low Level Output Voltage VDD = 2.7V

High Z Output Leakage D11-D0/8 V High Z Output Capacitance D11-D0/8 CS High (Note 12 ) ● 15 pF Output Source Current V Output Sink Current V

= 3.6V ● 1.9 V

IO = –10µA 2.6 V IO = –200µA ● 2.3 V

IO = 160µA 0.05 V IO = 1.6mA ● 0.10 0.4 V

= 0V to VDD, CS High ● ±10 µA

OUT

= 0V –4.5 mA

OUT

= V

OUT

● ±10 µA

4.5 mA

(Note 5)

LTC1282A/LTC1282B

Positive Supply Voltage Unipolar Mode (Note 13) 2.7 3.6 V

Bipolar Mode (Note 13) 3.0 3.6 V Negative Supply Voltage Bipolar Operation (Note 13) –3.6 –2.5 V Positive Supply Current f Negative Supply Current f Power Dissipation f

= 140ksps ● 4 7.8 mA

SAMPLE

= 140ksps ● 0.03 0.15 mA

SAMPLE

= 140ksps ● 12 24 mW

SAMPLE

Page 4

LTC1282

TI I G CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SAMPLE(MAX)

CONV

Maximum Sampling Frequency Commercial (Note 13) ● 140 kHz

Conversion Time Commercial ● 6.0 µs

CS to RD Setup Time ● 0ns RD↓ to BUSY↓ Delay CL = 50pF 140 200 ns

Data Access Time After RD↓ CL = 20pF (Note 13) 100 180 ns

RD Pulse Width (Note 13) ● t CS to RD Hold Time (Note 13) ● 0ns Data Setup Time After BUSY↑ (Note 13) 60 85 ns

Bus Relinquish Time (Note 13) 40 60 120 ns

HBEN to RD Setup Time (Note 13) ● 0ns HBEN to RD Hold Time (Note 13) ● 0ns Delay Between RD Operations ● 40 ns Delay Between Conversions Commercial (Note 13) ● 1140 450 ns

Aperture Delay of Sample-and-Hold 30 ns

(Note 5)

LTC1282A/LTC1282B

Military (Note 13) ● 120 kHz

Military ● 6.5 µs

Commercial

Military ● 260 ns

Commercial

Military ● 220 ns

CL = 100pF (Note 13) 110 200 ns

Commercial

Military ● 260 ns

Commercial

Military ● 120 ns

Commercial

Military ● 40 150 ns

Military (Note 13) ● 1500 ns

● 230 ns

● 200 ns

● 240 ns

● 110 ns

● 40 130 ns

The

● indicates specifications which apply over the full operating

temperature range; all other limits and typicals T Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and

AGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below V

will be clamped by internal diodes. This product can handle input currents greater than 60mA below VSS or above VDD without latchup.

Note 4: When these pin voltages are taken below V by internal diodes. This product can handle input currents greater than 60mA below VSS without latchup. These pins are not clamped to VDD.

Note 5: V mode, f

Note 6: Linearity, offset and full-scale specifications apply for unipolar and bipolar modes.

Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.

= 3V, VSS = 0V for unipolar mode and VSS = –3V for bipolar

= 140kHz, tr = tf = 5ns unless otherwise specified.

SAMPLE

= 25°C.

or above VDD, they

they will be clamped

Note 8: Bipolar offset is the different voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111

1111. Note 9: Full-scale change when V

–3V (Bipolar Mode).

Note 10: Full-scale change when VDD = 3V. Note 11: The LTC1282 can perform unipolar and bipolar conversions.

When V mode with input voltage of 0V to 2.5V. When VSS is taken negative (i.e. V

≤ –2.5V), the ADC will convert in bipolar mode with an input voltage of ±1.25V. AIN must not exceed VDD or fall below VSS by more than 50mV for

specified accuracy.

Note 12: Guaranteed by design, not subject to test. Note 13: Recommended operating conditions. Note 14: Commercial grade parts are designed to operate over the

temperature range of –40°C to 85°C but are neither tested nor guaranteed beyond 0°C to 70°C. Industrial grade parts specified and tested over –40°C to 85°C are available on special request. Consult factory.

is grounded (i.e. –0.1V ≤ VSS), the ADC will convert in unipolar

= 0V (Unipolar Mode) or

Page 5

TI I G CHARACTERISTICS

LTC1282

(Note 5)

Slow Memory Mode, Parallel Read Timing Diagram

CONV

BUSY

NEW DATA

DB11 TO DB0

DATA

HOLD

OLD DATA

DB11 TO DB0

TRACK

Slow Memory Mode, Two Byte Read Timing Diagram

HBEN

BUSY

DATA

HOLD



CONV

OLD DATA

DB7 TO DB0

ROM Mode, Parallel Read Timing Diagram

BUSY

DATA

HOLD

TRACK

LTC1282 • TC01

NEW DATA

DB7 TO DB0

OLD DATA 

DB11 TO DB0

CONV

NEW DATA

DB11 TO DB8

CONV

NEW DATA

DB11 TO DB0

LTC1282 • TC02

TRACK

HBEN

BUSY

DATA

HOLD

TRACK

LTC1282 • TC03

ROM Mode, Two Byte Read Timing Diagram

OLD DATA

DB7 TO DB0

CONV

NEW DATA

DB11 TO DB8

NEW DATA

DB7 TO DB0

LTC1282 • TC04

Page 6

LTC1282

TEMPERATURE (°C)

–50

SUPPLY CURRENT (mA)

LTC1282 • TPC03

–25

100

125

SAMPLE

= 160kHz

= 3V



FREQUENCY (Hz)

–120

AMPLITUDE (dB)

–100

–80

–60

–40

20k 40k

60k

80k

LTC1282 • TPC09

–20

10k 30k 50k

70k

SAMPLE

= 160kHz

IN1

= 19.0kHz

IN2

= 20.6kHz

= 3V

UNIPOLAR

LPER

Integral Nonlinearity

ATYPICA

CCHARA TERIST

Differential Nonlinearity

ICS

Supply Current (IDD) vs Temperature

0.5

–0.5

INTEGRAL NONLINEARITY ERROR (LSBs)

–1

512 1024 1536 2048

2560 3072 3584 4096

CODE

Supply Current (IDD) vs Supply Voltage

= 160kHz

SAMPLE

= 25°C



16 14 12 10

8 6

SUPPLY CURRENT (mA)

4 2 0

2.5

SINGLE

SUPPLY

3.5

SUPPLY VOLTAGE (V)

DUAL SUPPLIES

LTC1282 • TPC01

4.5

LTC1282 • TPC04

0.5

–0.5

DIFFERENTIAL NONLINEARITY ERROR (LSBs)

–1

512 1024 1536 2048

ENOBs and S/(N + D) vs Input Frequency

12 11 10

9 8 7 6 5 4 3 2

EFFECTIVE NUMBER OF BITS (ENOBs)

1 0

1k 100k 1M 10M

UNIPOLAR

(0V – 2.5V INPUT)

= 160kHz

SAMPLE

= ±2.7V BIPOLAR

= 3V UNIPOLAR

10k

INPUT FREQUENCY (Hz)

2560 3072 3584 4096

CODE

BIPOLAR (±1.25V INPUT)

LTC1282 • TPC05

LTC1282 • TPC02

74 68 62 56 50

Distortion vs Input Frequency (Unipolar)

S/(N + D) (dB)

= 160kHz

SAMPLE

–10

3V SUPPLY UNIPOLAR

–20 –30 –40 –50 –60 –70 –80 –90

AMPLITUDE (dB BELOW THE FUNDAMENTAL)

–100

1k 100k 1M 10M

10k

INPUT FREQUENCY (Hz)

THD

3rd HARMONIC 2nd HARMONIC

LTC1282 • TPC06

0 –10 –20 –30 –40 –50 –60 –70 –80 –90

AMPLITUDE (dB BELOW THE FUNDAMENTAL)

–100

1k 100k 1M 10M

Distortion vs Input Frequency (Bipolar)

= 140kHz

SAMPLE

±3V SUPPLIES BIPOLAR

THD

10k

INPUT FREQUENCY (Hz)

2nd HARMONIC

3rd HARMONIC

LTC1282 • TPC07

Power Supply Feedthrough vs Ripple Frequency

= 140kHz

SAMPLE

–10



–20 –30 –40 –50

–60

AMPLITUDE OF 

–70 –80

POWER SUPPLY FEEDTHROUGH (dB)

–90

–100

RIPPLE

DGND (V

RIPPLE

10k 100k 1M

RIPPLE FREQUENCY (Hz)

Intermodulation Distortion Plot

= 2.5mV)

= 250mV)

LTC1282 • TPC08

Page 7

LPER

INPUT FREQUENCY (Hz)

–80

AMPLITUDE (dB)

–60

–40

–20

100 10k 100k 1M

LTC1282 • TPC12

–100

–90

–70

–50

–30

–10

SAMPLE

= 160kHz

= 3V

UNIPOLAR

TEMPERATURE (°C)

–50

MAGNITUDE OF OFFSET VOLTAGE CHANGE (LSBs)

LTC1282 • TPC15

–25

100

125

SAMPLE

= 140kHz

= 2.7V

TEMPERATURE (°C)

–50

MAGNITUDE OF

DIFFERENTIAL NONLINEARITY CHANGE (LSBs)

0.2

0.5

LTC1282 • TPC18

0.1

0.4

0.3

–25

100

125

SAMPLE

= 140kHz

= 2.7V

ATYPICA

CCHARA TERIST

LTC1282

ICS

S/(N + D) vs Input Frequency and Amplitude (Unipolar, VDD = 3V)

VIN = 0dB

VIN = –20dB

VIN = –60dB

SIGNAL/(NOISE + DISTORTION) (dB)

1k 100k 1M 10M

10k

INPUT FREQUENCY (Hz)

SAMPLE

UNIPOLAR

Reference Voltage vs Load Current

1.220 VDD = 3V

1.215

1.210

1.205

1.200

1.195

1.190

1.185

REFERENCE VOLTAGE (V)

1.180

1.175

1.170

–5

–4

–3

LOAD CURRENT (mA)

–2

–1

Change in Gain Error vs Temperature

= 140kHz

SAMPLE

= 2.7V

= 160kHz

LTC1282 • TPC10

LTC1282 • TPC13

S/(N + D) vs Input Frequency and Amplitude (Bipolar, ±3V Supplies)

VIN = 0dB

VIN = –20dB

VIN = –60dB

SIGNAL/(NOISE + DISTORTION) (dB)

1k 100k 1M 10M

10k

INPUT FREQUENCY (Hz)

SAMPLE

= 160kHz

LTC1282 • TPC10

S/(N +D) vs Input Frequency vs Source Resistance (Bipolar)

VDD = 3V

SIGNAL/(NOISE + DISTORTION) (dB)

V BIPOLAR

1k 100k 1M 10M

RS = 1k

= –3V

10k

INPUT FREQUENCY (Hz)

RS = 50Ω

RS = 500Ω

RS = 5k

LTC1282 • TPC14

Change in Integral Nonlinearity (INL) vs Temperature

0.5 f

= 140kHz

SAMPLE

= 2.7V

0.4

Spurious Free Dynamic Range vs Input Frequency

Change in Offset Voltage vs Temperature

Change in Differential Nonlinearity (DNL) vs Temperature

MAGNITUDE OF GAIN ERROR CHANGE (LSBs)

–50

–25

TEMPERATURE (°C)

100

LTC1282 • TPC16

125

0.3

0.2

MAGNITUDE OF

0.1

INTEGRAL NONLINEARITY CHANGE (LSBs)

–50

–25

TEMPERATURE (°C)

100

LTC1282 • TPC17

125

Page 8

LTC1282

SUPPLY VOLTAGE (V)

MAGNITUDE OF GAIN ERROR CHANGE (LSBs)

2.5

3 3.5 4

LTC1282 • TPC20

4.5 5

SAMPLE

= 140kHz

LPER

ATYPICA

CCHARA TERIST

ICS

Change in Offset Voltage vs Supply Voltage

= 140kHz

SAMPLE

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1 0

MAGNITUDE OF OFFSET VOLTAGE CHANGE (LSBs)

2.5

3.5 4

SUPPLY VOLTAGE (V)

4.5

LTC1282 • TPC19

Change in Integral Nonlinearity (INL) vs Supply Current

0.5 f

= 140kHz

SAMPLE

0.4

0.3

Change in Gain Error vs Supply Voltage

Change in Differential Nonlinearity (DNL) vs Supply Current

0.5 f

= 140kHz

SAMPLE

0.4

0.3

0.2

MAGNITUDE OF

0.1

INTEGRAL NONLINEARITY CHANGE (LSBs)

3 3.5 4

2.5 SUPPLY VOLTAGE (V)

4.5 5

LTC1282 • TPC21

0.2

MAGNITUDE OF

0.1

DIFFERENTIAL NONLINEARITY CHANGE (LSBs)

3 3.5 4

2.5 SUPPLY VOLTAGE (V)

4.5 5

LTC1282 • TPC22

Page 9

UU U

PI FU CTIO S

(Pin 1): Analog Input. 0V to 2.5V (Unipolar), ±1.25V

(Bipolar).

(Pin 2): +1.20V Reference Output. Bypass to

REF

AGND (10µF tantalum in parallel with 0.1µF ceramic).

AGND (Pin 3): Analog Ground. D11-D4 (Pins 4 to 11): Three-State Data Outputs. D11

is the Most Significant Bit.

DGND (Pin 12): Digital Ground. D3/11-D0/8 (Pins 13 to 16): Three-State Data Outputs. NC (Pins 17 and 18): No Connection. HBEN (Pin 19): High Byte Enable Input. This pin is used

to multiplex the internal 12-bit conversion result into the lower bit outputs (D7 and D0/8). See Table 1. HBEN also disables conversion start when HIGH.

LTC1282

RD (Pin 20): READ Input. This active low signal starts a conversion when CS and HBEN are low. RD also enables the output drivers when CS is low.

CS (Pin 21): The CHIP SELECT Input must be low for the ADC to recognize RD and HBEN inputs.

BUSY (Pin 22): The BUSY Output shows the converter status. It is low when a conversion is in progress.

VSS (Pin 23): Bipolar Mode — Negative Supply, –3V. Bypass to AGND with 0.1µF ceramic.

Unipolar Mode — Tie to DGND.

(Pin 24): Positive Supply, 3V. Bypass to AGND (10µ F

tantalum in parallel with 0.1µF ceramic).

Table 1. Data Bus Output, CS and RD = LOW

Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16

MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8 *D11...D0/8 are the ADC data output pins.

DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.

TEST CIRCUITS

Load Circuits for Output Float Delay

DBN

3k 10pF 10pF

DGND

(A) V

TO Hi-Z (B) VOL TO Hi-Z

DGND

1282 TC02

DBN

Load Circuits for Access Time

3k C

DGND

(A) Hi-Z TO V AND VOL TO VOH, (t6)

, (t3)



DBN

(B) Hi-Z TO V AND V



DGND

, (t3)

TO VOL, (t6)

1282 TC01

DBN

Page 10

LTC1282

UU W

FU TIO AL BLOCK DIAGRA

SAMPLE

HOLD

SAMPLE

COMPARATOR

–

(–3V FOR BIPOLAR MODE,

AGND FOR UNIPOLAR MODE)

12-BIT

CAPACITIVE

DAC

INTERNAL

DGNDAGND

CLOCK

PPLICATI

REF(OUT)

1.2V

REFERENCE

I FOR ATIO

CONVERSION DETAILS

The LTC1282 uses a successive approximation and an internal sample-and-hold circuitry to convert an analog signal to a 12-bit parallel or 2-byte output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. Please refer to the Digital Interface section for the data format.

Conversion start is controlled by the CS, RD and HBEN inputs. At the start of conversion the successive approximation register (SAR) is reset and the three-state data outputs are enabled. Once a conversion cycle has begun it cannot be restarted.

During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN input connects to the sample-and-hold capacitor during the sample phase, and the comparator offset is nulled by the feedback switch. In this sample phase, a minimum delay of 1.14µs will provide enough time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the comparator

SUCCESSIVE 

APPROXIMATION

OUTPUT

LATCHES

CONTROL

LOGIC

D11

•

• D0/8 BUSY CS

RD HBEN

LTC1282 • FBD

feedback switch opens, putting the comparator into the compare mode. The input switch switches C

SAMPLE

ground, injecting the analog input charge to the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the A input charge. The SAR contents (a 12-bit data word) which represent the AIN are loaded into the 12-bit latch.

SAMPLE

HOLD

SAMPLE

DAC

Figure 1. AIN Input

–

COMPARATOR

LTC1282 • F01

S A R

12-BIT LATCH

Page 11

LTC1282

INPUT FREQUENCY (Hz)

EFFECTIVE NUMBER OF BITS (ENOBs)

1k 100k 1M 10M

LTC1282 • F03

10k

S/(N + D) (dB)

SAMPLE

= 160kHz

= ±2.7V BIPOLAR

BIPOLAR (±1.25V INPUT)

PPLICATI

I FOR ATIO

DYNAMIC PERFORMANCE

The LTC1282 has exceptionally high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to characterize the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1282 FFT plot.

Signal-to-(Noise + Distortion) Ratio

The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 2 shows a typical LTC1282 FFT plot.

0

–20

= 160kHz

SAMPLE

= 3V

UNIPOLAR

Figure 3. ENOBs and S/(N + D) vs Input Frequency

Total Harmonic Distortion

Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:

–40

–60

AMPLITUDE (dB)

–80

–100

–120

10 30

Figure 2. LTC1282 Nonaveraged, 1024 Point FFT Plot

Effective Number of Bits

The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to S/(N + D) by the equation:

N = [S/(N + D) – 1.76]/6.02 where N is the Effective Number of Bits of resolution and

S/(N + D) is expressed in dB. At the maximum sampling rate of 140kHz the LTC1282 maintains 11.3 ENOBs at 70kHz input frequency. Refer to Figure 3.

20 40

FREQUENCY (kHz)

LT1282 • F02

THD = 20log

√V

+ V



... + V

2

where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. The typical THD specification in the Dynamic Accuracy table includes the 2nd

through 5th harmonics. With a 70kHz input signal, the LTC1282 has a typical –82dB THD as shown in Figure 4.

= 140kHz

SAMPLE

–10

±3V SUPPLIES BIPOLAR

–20 –30 –40 –50 –60 –70 –80 –90

AMPLITUDE (dB BELOW THE FUNDAMENTAL)

–100

1k 100k 1M 10M

THD

10k

INPUT FREQUENCY (Hz)

3rd HARMONIC

2nd HARMONIC

LTC1282 • F04

Figure 4. Distortion vs Input Frequency (Bipolar)

Page 12

LTC1282

PPLICATI

I FOR ATIO

Intermodulation Distortion

If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.

If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa – fb) while the 3rd order IMD terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb) if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order. IMD products can be expressed by the following formula:

IMD (fa ± fb) = 20log

Amplitude at (fa ± fb)

Amplitude at fa

Figure 5 shows the IMD performance at a 20kHz input.

–20

–40

–60

–80

AMPLITUDE (dB)

SAMPLE

= 19.0kHz

IN1

= 20.6kHz

IN2

= 3V

UNIPOLAR

= 160kHz

Full Power and Full Linear Bandwidth

The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal.

The full linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The LTC1282 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency.

Driving the Analog Input

The analog input of the LTC1282 is easy to drive. It draws only one small current spike while charging the sampleand-hold capacitor at the end of conversion. During conversion the analog input draws no current. The only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. Any op amp that settles in 1.14µs to small current transients will allow maximum speed operation. If slower op amps are used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the ADC’s AIN input include the LT®1190/LT1191, LT1007, LT1220, LT1223 and LT1224 op amps.

The analog input tolerates source resistance very well. Here again, the only requirement is that the analog input must settle before the next conversion starts. For larger source resistance, full accuracy can be obtained if more time is allowed between conversions.

–100

–120

Figure 5. Intermodulation Distortion Plot

20 40

10 30 50

FREQUENCY (kHz)

LTC1282 • F05

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal.

Internal Reference

The LTC1282 has an on-chip, temperature compensated, curvature corrected, bandgap reference which is factory trimmed to 1.20V. It is internally connected to the DAC and is available at pin 2 to provide up to 0.3mA current to an external load.

For minimum code transition noise the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10µ F tantalum in parallel with a

0.1µ F ceramic).

Page 13

LTC1282

PPLICATI

I FOR ATIO

Overdriving the Internal Reference

The V

pin can be driven above its normal value with a

REF

DAC or other means to provide input span adjustment. Figure 6 shows an LT1006 op amp driving the reference pin. The V

pin must be driven to at least 1.25V to

REF

prevent conflict with the internal reference. The reference should be driven to no more than 1.44V in unipolar mode or 2.88V for bipolar mode to keep the input span within the single 3V or ±3V supplies.

INPUT RANGE

±1.033V

REF(OUT)

Figure 6. Driving the V

LT1006

–

≥ 1.25V

REF(OUT)

3Ω

10µF

with the LT1006 Op Amp

REF

LTC1282

REF

AGND

LTC1282 • F06

–3V



natural binary with 1LSB = FS/4096 = 2.5V/4096 = 0.61mV. Figure 9 shows the input/output transfer characteristics for the LTC1282 in bipolar operation. The full scale for LTC1282 in bipolar mode is still 2.5V and 1LSB = 0.61mV.

= 2.5V

111...111

111...110

111...101

111...100

OUTPUT CODE

000...011

000...010

000...001

000...000

Figure 8. LTC1282 Unipolar Transfer Characteristic

1LSB = FS/4096

UNIPOLAR ZERO

1

LSB

INPUT VOLTAGE (V)

FS – 1LSB

LTC1282 • F8

Figure 7 shows a typical reference, the LT1019A-2.5 connected to the LTC1282 operating in bipolar mode. This will provide an improved drift (due to the 5ppm/°C of the LT1019A-2.5) and a ±2.604V full scale.

INPUT RANGE

±2.60V

OUT

LT1019A-2.5

GND

3Ω

LTC1282

REF

10µF

AGND

LTC1282 • F07

–3V

Figure 7. Supplying a 2.5V Reference Voltage to the LTC1282 with the LT1019A-2.5

UNIPOLAR/BIPOLAR OPERATION AND ADJUSTMENT

Figure 8 shows the ideal input/output characteristics for the LTC1282. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB,

1.5LSBs, 2.5LSBs, FS – 1.5LSBs). The output code is

011...111

011...110

000...001

000...000

111...111

111...110

OUTPUT CODE

100...010

100...001

100...000

BIPOLAR

ZERO

FS = 2.5V 1LSB = FS/4096

–1

1

LSB

INPUT VOLTAGE (V)

LSB

FS/2 – 1LSB–FS/2

LTC1282 • F09

Figure 9. LTC1282 Bipolar Transfer Characteristic

Unipolar Offset and Full-Scale Adjustment

In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Figure 10 shows the extra components required for full-scale error adjustment. If both offset and full-scale adjustments are needed, the circuit in Figure 11 can be used. Offset should be adjusted before full scale. To adjust

Page 14

LTC1282

PPLICATI

I FOR ATIO

offset, apply 0.305mV (i.e., 0.5LSB) at V1 and adjust the op amp offset voltage until the LTC1282 output code flickers between 0000 0000 0000 and 0000 0000 0001. For zero full-scale error, apply an analog input of 2.49909V (i.e., FS – 1.5

LSBs or last code transition) at the input and adjust the full-scale trim until the LTC1282 output code flickers between 1111 1111 1110 and 1111 1111 1111.

R1

50Ω

R2 10k

ADDITIONAL PINS OMITTED FOR CLARITY ±20LSB TRIM RANGE

Figure 10. Full-Scale Adjust Circuit

R1

ANALOG

INPUT

0V TO 2.5V

10k

 R2

10k

R9 20Ω

Figure 11. Unipolar Offset and Full-Scale Adjust Circuit

R5 10k

–

FULL-SCALE

R4

100Ω

ADJUST

R4 100k

R3 100k

R6 400Ω

R5

4.3k FULL-SCALE ADJUST

R7

100k

LTC1282

AGND

LTC1282 • F10

R8 10k OFFSET ADJUST

LTC1282

LTC1282 • F11

ANALOG

INPUT

±1.25V

R1

10k



R2 10k

R8 20k OFFSET ADJUST

LTC1282

LTC1282 • F12

–

R4 100k

R5

4.3k FULL-SCALE ADJUST

R3

R7

100k

R6 200Ω

–5V

Figure 12. Bipolar Offset and Full-Scale Adjust Circuit

error adjustment is achieved by trimming the offset adjustment of Figure 12 while the input voltage is 0.5LSB below ground. This is done by applying an input voltage of –0.305mV (– 0.5LSB for LTC1282) to the input in Figure 12 and adjusting R8 until the ADC output code flickers between 0000 0000 0000 and 1111 1111 1111. For fullscale adjustment, an input voltage of 1.24909V (FS –

1.5LSBs for LTC1282) is applied to the input and R5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111.

BOARD LAYOUT AND BYPASSING

The LTC1282 is easy to use. To obtain the best performance from the device, a printed circuit board is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND.

Bipolar Offset and Full-Scale Adjustment

Bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. Figure 10 shows the extra components required for full-scale error adjustment. If both offset and full-scale adjustments are needed, the circuit in Figure 12 can be used. Again, bipolar offset must be adjusted before full-scale error. Bipolar offset

High quality tantalum and ceramic bypass capacitors should be used at the VDD and V

pins as shown in Figure

REF

13. In bipolar mode, a 0.1µF ceramic provides adequate bypassing for the VSS pin. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible.

Page 15

LTC1282

LTC1282

3V ADC

LTC1282 • F14

ADC OUTPUTS

0V TO 3V

ADC INPUTS

0V TO 5V

TTL INPUT LEVELS

CMOS OUTPUT LEVELS

5V

LOGIC

LTC ESD

CLAMP

PPLICATI

Noise:

Input signal leads to AIN and signal return leads

I FOR ATIO

ANALOG

INPUT

CIRCUITRY

–

AGND V

3 2 24 12

ANALOG GROUND PLANE

Figure 13. Power Supply Grounding Practice

LTC1282

REF

0.1µF

from AGND (Pin 3) should be kept as short as possible to minimize input noise coupling. In applications where this is not possible, a shielded cable between source and ADC is recommended. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances

as much as possible.

DIGITAL SYSTEM

VDDDGND

10µF10µF

0.1µF

GROUND CONNECTION TO DIGITAL CIRCUITRY

LTC1282 • F13

DIGITAL INTERFACE

The ADC is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. The HBEN input serves as a data byte select for 8-bit processors and is normally either connected to the microprocessor address bus or grounded.

Connecting to 5V Logic Systems

A single point analog ground separate from the logic system ground should be established with an analog ground plane at pin 3 (AGND) or as close as possible to the ADC, as shown in Figure 13. Pin 12 ( DGND) and all other analog grounds should be connected to this single analog ground point. No other digital grounds should be connected to this analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible.

In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversion or by using three-state buffers to isolate the ADC data bus.

The LTC1282 interfaces well to 5V logic because the ESD clamps on the inputs do not clamp to the positive supply (see Figure 14). Inputs of 0V to 5V do not bother the ADC at all. In addition, the 0V to 3V outputs of the 3V ADC are more than adequate to meet TTL input levels in the 5V logic. (5V logic with CMOS input levels requires a level shift.)

Figure 14. 3V ADC ESD Protection Handles 0V to 5V Swings Easily

Page 16

LTC1282

PPLICATI

I FOR ATIO

Internal Clock

The LTC1282 has an internal clock that eliminates the need for synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of

5.5µs, and a maximum conversion time over the full operating temperature range of 6.0µ s. No external adjustments are required and, with the guaranteed maximum acquisition time of 1.14µs, throughput performance of 140ksps is assured.

Timing and Control

Conversion start and data read operations are controlled by three digital inputs: HBEN, CS and RD. Figure 15 shows the logic structure associated with these inputs. The three signals are internally gated so that a logic “0” is required on all three inputs to initiate a conversion. Once initiated it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output, and this is low while conversion is in progress.

HBEN

LTC1282

FLIP

FLOP

CLEAR

BUSY

CONVERSION  START (RISING EDGE TRIGGER)

initiates a conversion and data is read when conversion is complete. The second is the ROM Mode which does not require microprocessor WAIT states. A READ operation brings CS and RD low which initiates a conversion and reads the previous conversion result.

Data Format

The output format can be either a complete parallel load for 16-bit microprocessors or a two byte load for 8-bit microprocessors. Data is always right justified (i.e., LSB is the most right-hand bit in a 16-bit word). For a two byte read, only data outputs D7...D0/8 are used. Byte selection is governed by the HBEN input which controls an internal digital multiplexer. This multiplexes the 12-bits of conversion data onto the lower D7...D0/8 outputs (4MSBs or 8MSBs) where it can be read in two read cycles. The 4MSBs always appear on D11...D8 whenever the threestate output drivers are turned on.

Slow Memory Mode, Parallel Read (HBEN = LOW)

Figure 16 and Table 2 show the timing diagram and data bus status for Slow Memory Mode, Parallel Read. CS and RD going low trigger a conversion and the ADC acknowledges by taking BUSY low. Data from the previous conversion appears on the three-state data outputs. BUSY returns high at the end of conversion when the output latches have been updated and the conversion result is placed on data outputs D11...D0/8.

ACTIVE HIGH

D11....D0/8 ARE THE ADC DATA OUTPUT PINS

DB11....DB0 ARE THE 12-BIT CONVERSION RESULTS

Figure 15. Internal Logic for Control Inputs CS, RD and HBEN

ENABLE THREE-STATE OUTPUTS

D11....D0/8 = DB11....DB0

ENABLE THREE-STATE OUTPUTS

D11....D8 = DB11....DB8

D7....D4 = LOW

D3/11....D0/8 = DB11....DB8

LTC1282 • F15

There are two modes of operation as outlined by the timing diagrams of Figures 16 to 19. Slow Memory Mode is designed for microprocessors which can be driven into a WAIT state. A READ operation brings CS and RD low which

Slow Memory Mode, Two Byte Read

For a two byte read, only 8 data outputs D7...D0/8 are used. Conversion start procedure and data output status for the first read operation are identical to Slow Memory Mode, Parallel Read. See Figure 17 timing diagram and Table 3 data bus status. At the end of the conversion, the low data byte (D7...D0/8) is read from the ADC. A second READ operation with the HBEN high, places the high byte on data outputs D3/11...D0/8 and disables conversion start.

Note the 4MSBs appear on data output D11...D8 during the two READ operations.

Page 17

LTC1282

PPLICATI

I FOR ATIO

RDCSRD

BUSY

DATA

HOLD

TRACK

CONV

OLD DATA DB11-DB0

NEW DATA

DB11-DB0

LTC1282 • F16

Figure 16. Slow Memory Mode, Parallel Read Timing Diagram

Table 2. Slow Memory Mode, Parallel Read Data Bus Status

Data Outputs D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8

Read DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

HBEN

BUSY

DATA

HOLD

TRACK

CONV

OLD DATA

DB7-DB0

NEW DATA

DB7-DB0

NEW DATA

DB11-DB8

Figure 17. Slow Memory Mode, Two Byte Read Timing Diagram

Table 3. Slow Memory Mode, Two Byte Read Data Bus Status

Data Outputs D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8

First Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Second Read Low Low Low Low DB11 DB10 DB9 DB8

LTC1282 • F17

Page 18

LTC1282

PPLICATI

Table 4. ROM Mode, Parallel Read Data Bus Status

Data Outputs D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8

First Read (Old Data) DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Second Read DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

I FOR ATIO

BUSY

DATA

HOLD

TRACK

Figure 18. ROM Mode, Parallel Read Timing Diagram (HBEN = LOW)

OLD DATA DB11-DB0

CONV

NEW DATA DB11-DB0

CONV

LTC1282 • F18

ROM Mode, Parallel Read (HBEN = LOW)

The ROM Mode avoids placing a microprocessor into a WAIT state. A conversion is started with a READ operation, and the 12 bits of data from the previous conversion are available on data outputs D11...D0/8 (see Figure 18 and Table 4). This data may be disregarded if not required. A second READ operation reads the new data (DB11...DB0) and starts another conversion. A delay at least as long as the ADC’s conversion time plus the 1.0µ s minimum delay between conversions must be allowed between READ operations.

ROM Mode, Two Byte Read

As previously mentioned for a two byte read, only data outputs D7...D0/8 are used. Conversion is started in the normal way with a READ operation and the data output status is the same as the ROM mode, Parallel Read (see Figure 19 timing diagram and Table 5 data bus status). Two more READ operations are required to access the new conversion result. A delay equal to the ADC’s conversion

time must be allowed between conversion start and the second data READ operation. The second READ operation with HBEN high disables conversion start and places the high byte (4MSBs) on data outputs D3/11...D0/8. A third read operation accesses the low data byte (DB7...DB0) and starts another conversion. The 4MSBs appear on data outputs D11...D8 during all three read operations.

MICROPROCESSOR INTERFACING

The LTC1282 allows easy interfacing to digital signal processors as well as modern high speed, 8-bit or 16bit microprocessors. Here are several examples.

TMS320C25

Figure 20 shows an interface between the LTC1282 and the TMS320C25.

The R/W signal of the DSP initiates a conversion and conversion results are read from the LTC1282 using the following instruction:

IN D, PA

Page 19

LTC1282

PPLICATI

HBEN

BUSY

DATA

HOLD

TRACK

I FOR ATIO

OLD DATA

DB7-DB0

CONV

NEW DATA

DB11-DB8

NEW DATA

DB7-DB0

LTC1282 • F19

Figure 19. ROM Mode Two Byte Read Timing Diagram

Table 5. ROM Mode, Two Byte Read Data Bus Status

Data Outputs D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8

First Read (Old Data) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Second Read (New Data) Low Low Low Low DB11 DB10 DB9 DB8 Third Read (New Data) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

A16

TMS320C25

READY

R/W

D16

ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS BUS

ADDRESS

DECODE

DATA BUS

Figure 20. TMS320C25 Interface

CS BUSY

RD D11

D0/8

LTC1282

LTC1282 • F20

HBEN

where D is Data Memory Address and PA is the PORT ADDRESS.

MC68000 Microprocessor

Figure 21 shows a typical interface for the MC68000. The LTC1282 is operating in the Slow Memory Mode. Assuming the LTC1282 is located at address C000, then the following single 16-bit MOVE instruction both starts a conversion and reads the conversion result:

Move.W $C000,D0

At the beginning of the instruction cycle when the ADC address is selected, BUSY and CS assert DTACK so that the MC68000 is forced into a WAIT state. At the end of conversion, BUSY returns high and the conversion result is placed in the D0 register of the microprocessor.

Page 20

LTC1282

DATA BUS

LTC1282 • F23

PORT ADDRESS BUS

D11

DEN

PA0

PA2

TMS32010

ADDRESS

DECODE

D0/8

D11

HBEN

LTC1282

LINEAR CIRCUITRY OMITTED FOR CLARITY

PPLICATI

A23

MC68000

DTACK

R/W

D11

ADDITIONAL PINS OMITTED FOR CLARITY

U S

I FOR ATIO

ADDRESS BUS

ADDRESS

DECODE

DATA BUS

CS BUSY

RD D11

D0/8

LTC1282

HBEN

LTC1282 • F21

Figure 21. MC68000 Interface

8085A/Z80 Microprocessor

Figure 22 shows an LTC1282 interface for the Z80 and 8085A. The LTC1282 is operating in the Slow Memory Mode and a two byte read is required. Not shown in the figure is the 8-bit latch required to demultiplex the 8085A common address/data bus. A0 is used to assert HBEN so that an even address (HBEN = LOW) to the LTC1282 will start a conversion and read the low data byte. An odd address (HBEN = HIGH) will read the high data byte. This is accomplished with the single 16-bit LOAD instruction below.

This is a two byte read instruction which loads the ADC data (address B000) into the HL register pair. During the first read operation, BUSY forces the microprocessor to WAIT for the LTC1282 conversion. No WAIT states are inserted during the second read operation when the microprocessor is reading the high data byte.

TMS32010 Microcomputer

Figure 23 shows an LTC1282/TMS32010 interface. The LTC1282 is operating in the ROM Mode. The interface is designed for a maximum TMS32010 clock frequency of 18MHz but will typically work over the full TMS32010 clock frequency range.

The LTC1282 is mapped at a port address. The following I/O instruction starts a conversion and reads the previous conversion result into data memory.

IN A,PA (PA = PORT ADDRESS)

When conversion is complete, a second I/O instruction reads the up-to-date data into memory and starts another conversion. A delay at least as long as the ADC conversion time must be allowed between I/O instructions.

For the 8085A LHLD (B000) For the Z80 LDHL, (B000)

A15

MREQ

Z80

8085A

WAIT

LINEAR CIRCUITRY OMITTED FOR CLARITY

Figure 22. 8085A and Z80 Interface

ADDRESS BUS

ADDRESS

DECODE

DATA BUS

CS BUSY

RD D7

D0/8

HBEN

LTC1282

Figure 23. TMS32010 Interface

LTC1282 • F22

Page 21

LTC1282

PPLICATI

I FOR ATIO

MUXing with CD4051

The high input impedance of the LTC1282 provides an easy, cheap, fast, and accurate way to multiplex many channels of data through one converter. Figure 24 shows a low cost CD4051, one of the most common multiplexers connected to the LTC1282. The LTC1282’s input draws no DC input current so it can be accurately driven by the unbuffered MUX. The CD4520 counter increments the MUX channel after each sample is taken.

100ps Resolution ∆Time Measurement with LTC1282

Figure 25 shows a circuit that precisely measures the difference in time between two events. It has a 400ns full scale and 100ps resolution. The start signal releases the ramp generator made up of the PNP current source and the

500pF capacitor. The circuit ramps until the stop signal shuts off the current source. The final value of the ramp represents the time between the start and stop

events. The LTC1282 digitizes this final value and outputs the digital data.

NO

BUFFER

REQUIRED

LTC1282

Q2 Q1

COUNTER

BUSY

–3V

ENABLE

CD4520

RESET

D11

•

•

D0 CS

µP OR

DSP

LTC1282 • F24

8 INPUT

CHANNELS

±1.25V

INPUT

VARIES

CD4051

ABC

Figure 24. MUXing the LTC1282 with CD4051

65Ω

1N457

LM134

45.3Ω

1N457

45.3Ω

START↑

STOP↑

3.3V

10µF

12-BIT DATA  OUTPUT

DATA  LATCH SIGNAL

20k

1N4148

100k

2N23692N2369

250pF POLYSTYRENE

1N4148

10k

100pF

0.001µF

10µF

10k

10pF

REF

OUT

LTC1282

VSSGND

RD BUSY

LTC1282 • F25

65Ω

200k

2N5771

74HC74

CLK

CLR

74HC03

430Ω

Figure 25. ∆ Time Measurement with the LTC1282

Page 22

LTC1282

PPLICATI

I FOR ATIO

Other High Speed A/D Converters

LTC makes a family of high speed sampling ADCs for a variety of applications. Both single 5V and ±5V supply devices are available at high speeds. The high speed 12-bit family is summarized below.

300ksps and 500ksps 12-Bit Sampling A/D Converters

2.7µs Conversion 

Built-In

Sample & Hold

2.42V V

OUTPUT

ANALOG INPUT



REF

Reference  Output For

System Use

8- OR 12-BIT

PARALLEL BUS

Parallel Outputs

For The Fastest

Data Transfer Rates

Time

LTC1273/5/6

AIN V

REF

10µF0.1µF

AGND

BUSY D11 (MSB) D10 D9

HBEN D8 D7 D6 D5 D4

D2/10

DGND

D3/11



Reference On Board



10µF



CS

RD

µP CONTROL

LINES  

D0/8 D1/9

Only 75mW

Power  Consumption

0.1µF

No Negative Supply Required for Unipolar Operation

Internal Clock No Crystal Required

Comparison of Specifications and Features

DEVICE SAMPLING S/(N + D) INPUT POWER POWER TYPE FREQ @ NYQUIST RANGE SUPPLY DISSIPATION

LTC1272 250kHz 65dB 0V-5V 5V 75mW LTC1273 300kHz 70dB 0V-5V 5V 75mW LTC1275 300kHz 70dB ±2.5V ±5V 75mW LTC1276 300kHz 70dB ±5V ±5V 75mW LTC1278 500kHz 70dB 0V-5V 5V 75mW

or ±2.5V or ±5V 6mW*

LTC1282 140kHz 68dB 0V-2.5V 3V 12mW

or ±1.25V or ±3V

*6mW power shutdown with instant wake up

Page 23

PACKAGEDESCRIPTI

Dimensions in inches (millimeters) unless otherwise noted.

N Package

24-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

1.265*

(32.131)

MAX

0.255 ± 0.015* (6.477 ± 0.381)

123456

2223

89101911 12

151718

LTC1282

131416

0.300 – 0.325

(7.620 – 8.255)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015 +0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.020

(0.508)

MIN

0.125

(3.175)

MIN

0.130 ± 0.005

(3.302 ± 0.127)

SW Package

24-Lead Plastic Small Outline (Wide 0.300)

(LTC DWG # 05-08-1620)

NOTE 1

0.100 ± 0.010

(2.540 ± 0.254)

2324

0.045 – 0.065

(1.143 – 1.651)

0.598 – 0.614*

(15.190 – 15.600)

22 21 20 19 181716 15

0.018 ± 0.003

(0.457 ± 0.076)

1314

0.065

(1.651)

TYP

N24 1197

0.394 – 0.419

(10.007 – 10.643)

0.291 – 0.299** (7.391 – 7.595)



0.010 – 0.029

(0.254 – 0.737)

0.009 – 0.013

(0.229 – 0.330)

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

*

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

 

NOTE 1

× 45°

0.016 – 0.050

(0.406 – 1.270)

0° – 8° TYP

0.093 – 0.104

(2.362 – 2.642)

2345678

0.050

(1.270)

TYP

0.014 – 0.019

(0.356 – 0.482)

TYP

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

910

11 12

0.037 – 0.045

(0.940 – 1.143)

0.004 – 0.012

(0.102 – 0.305)

S24 (WIDE) 0996

Page 24

LTC1282

RELATED PARTS

PART NUMBER RESOLUTION SPEED COMMENTS 16-Bit

LTC1604 16 333ksps ±2.5V Input Range, ±5V Supply LTC1605 16 100ksps ±10V Input Range, Single 5V Supply

14-Bit

LTC1419 14 800ksps 150mW, 81.5dB SINAD and 95dB SFDR LTC1416 14 400ksps 75mW, Low Power with Excellent AC Specs LTC1418 14 200ksps 15mW, Single 5V, Serial/Parallel I/O

12-Bit

LTC1410 12 1.25Msps 150mW, 71.5dB SINAD and 84dB THD LTC1415 12 1.25Msps 55mW, Single 5V Supply LTC1409 12 800ksps 80mW, 71.5dB SINAD and 84dB THD LTC1279 12 600ksps 60mW, Single 5V or ±5V Supply LTC1404 12 600ksps High Speed Serial I/O in SO-8 Package LTC1278-5 12 500ksps 75mW, Single 5V or ±5V Supply LTC1278-4 12 400ksps 75mW, Single 5V or ±5V Supply LTC1400 12 400ksps High Speed Serial I/O in SO-8 Package

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear-tech.com

LT/TP 1098 2K REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1993