Datasheet LTC1278-4ISW, LTC1278-4IN, LTC1278-4CSW, LTC1278-4CN, LTC1278-5CN Datasheet (Linear Technology)

LTC1278

INPUT FREQUENCY (Hz)

10k

0

EFFECTIVE NUMBER OF BITS

S/(N+D) (dB)

3

5

7

10

100k 1M 2M

LT1278 G4

1

4

6

9

12
11

62
56

74
68

8

2

f

SAMPLE

= 500kHz

NYQUIST

FREQUENCY

12-Bit, 500ksps Sampling

A/D Converter with Shutdown

EATU

F

■

Single Supply 5V or ±5V Operation

■

Two Speed Grades,500ksps (LTC1278-5)

RE

S

400ksps (LTC1278-4)

■

70dB S/(N + D) and 74dB THD at Nyquist

■

No Missing Codes Over Temperature

■

75mW (Typ) Power Dissipation

■

Power Shutdown with Instant Wake-Up

■

Internal Reference Can Be Overdriven Externally

■

Internal Synchronized Clock; No Clock Required

■

High Impedance Analog Input

■

0V to 5V or ±2.5V Input Range

■

New Flexible, Friendly Parallel Interface to DSPs
and FIFOs

■

24-Pin Narrow PDIP and SW Packages

U

O

PPLICATI

A

■

High Speed Data Acquisition

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

■

Audio and Telecom Processing

■

Spectrum Analysis

, LTC and LT are registered trademarks of Linear Technology Corporation.

S

DUESCRIPTIO

The LTC®1278 is a 1.6µ s, 500ksps, sampling 12-bit A/D
converter that draws only 75mW from a single 5V or ±5V
supplies. This easy-to-use device comes complete with
a 200ns sample-and-hold, a precision reference and an
internally trimmed clock. Unipolar and bipolar conver­sion modes add to the flexibility of the ADC. The low
power dissipation is made even more attractive by a

8.5mW power-down feature. Instant wake-up from shut­down allows the converter to be powered down even
during brief inactive periods.

The LTC1278 converts 0V to 5V unipolar inputs from a
single 5V supply and ±2.5V bipolar inputs from ±5V
supplies. Maximum DC specs include ±1LSB INL and
±1LSB DNL. Outstanding guaranteed AC performance
includes 70dB S/(N + D) and 78dB THD at the input
frequency of 100kHz over temperature.

The internal clock is trimmed for 1.6µs conversion time.
The clock automatically synchronizes to each sample
command, eliminating problems with asynchronous clock
noise found in competitive devices. A separate convert
start input and a data ready signal (BUSY) ease connec­tions to FIFOs, DSPs and microprocessors.

Single 5V Supply, 500kHz, 12-Bit Sampling A/D Converter

2.42V

REFERENCE

OUTPUT

10µF

A

PPLICATITYPICAL

+

ANALOG INPUT

(0V TO 5V)

0.1µF

12-BIT

PARALLEL

BUS

10
11
12

1

AIN

2

V

3

AGND

4

D11(MSB)

5

D10

6

D9

7

D8

8

D7

9

D6
D5
D4
DGND

O

LTC1278-5



REF

CONVST

U

AV

BUSY

SHDN

DV

Effective Bits and Signal-to-(Noise + Distortion)

24



DD

23

V



RD

SS

CS



DD

D0
D1
D2
D3

10µF

22
21

µP CONTROL

20

LINES

19

CONVERSION START INPUT

18

POWER DOWN INPUT

17
16
15
14
13

LTC1278 • TA01

5V

+

0.1µF

vs Input Frequency

1

LTC1278

WU

U

PACKAGE

/

O

RDER I FOR ATIO

W

O

A

AVDD = DVDD = VDD (Notes 1, 2)

LUTEXI T

S

A

WUW

ARB

U
G

I

S

Supply Voltage (VDD).............................................. 12V

Negative Supply Voltage (VSS)

Bipolar Operation Only .......................... – 6V to GND

Total Supply Voltage (VDD to VSS)

Bipolar Operation Only ....................................... 12V

Analog Input Voltage (Note 3)

Unipolar Operation ................... – 0.3V to VDD + 0.3V

Bipolar Operation............... VSS – 0.3V to VDD + 0.3V

Digital Input Voltage (Note 4)

Unipolar Operation ................................–0.3V to 12V

Bipolar Operation........................... VSS – 0.3V to 12V

Digital Output Voltage

Unipolar Operation ................... –0.3V to VDD + 0.3V

Bipolar Operation................ VSS – 0.3V to VDD + 0.3V

Power Dissipation............................................. 500mW

Operating Temperature Range

LTC1278-4C, LTC1278-5C ..................... 0°C to 70°C

LTC1278-4I ....................................... –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

TOP VIEW

A



1

IN

V



2

REF

AGND

3

D11 (MSB)

Consult factory for Military grade parts.

4

D10

5

D9

6

D8

7

D7

8

D6

9

D5

10

D4

11

DGND

12

N PACKAGE

24-LEAD PDIP

T

= 110°C, θJA = 100°C/W (N)

JMAX

T

= 110°C, θJA = 130°C/W (SW)

JMAX

24-LEAD PLASTIC SO WIDE

AVDD

24

V

23

SS

BUSY

22

CS

21

RD

20

CONVST

19

SHDN

18

DV

17

D0

16

D1

15

D2

14

D3

13

SW PACKAGE



DD

ORDER

PART NUMBER

LTC1278-4CN
LTC1278-5CN
LTC1278-4IN
LTC1278-4CSW



LTC1278-5CSW
LTC1278-4ISW

U

With Internal Reference (Notes 5, 6)

LTC1278-4/LTC1278-5

● ±6 LSB

LTC1278-4/LTC1278-5

U

IN

IN

VERTER

CCHARA TERIST

= 0 ● ±10 ±45 ppm/°C

OUT(REF)

ICS

U
PUT

LOG

Analog Input Range (Note 9) 4.95V ≤ VDD ≤ 5.25V (Unipolar) ● 0 to 5 V

Analog Input Leakage Current CS = High ● ±1 µA
Analog Input Capacitance Between Conversions (Sample Mode) 45 pF

IA

(Note 5)

4.75V ≤ VDD ≤ 5.25V, –5.25V ≤ VSS ≤ – 2.45V (Bipolar) ● ±2.5 V

During Conversions (Hold Mode) 5 pF

CO

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 12 Bit
Integral Linearity Error (Note 7) ● ±1 LSB
Differential Linearity Error ● ±1 LSB
Offset Error (Note 8) ±4 LSB

Gain Error ±15 LSB
Gain Error Tempco I

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

I

IN

C

2

LTC1278

W

U

IC

DY

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

S/(N + D) Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal ● 70 72 dB

THD Total Harmonic Distortion 100kHz Input Signal ● –80 –78 dB

IMD Intermodulation Distortion f

A

ACCURACY

First 5 Harmonics 250kHz Input Signal –74 dB
Peak Harmonic or Spurious Noise 100kHz Input Signal ● –84 –78 dB

Full Power Bandwidth 4 MHz
Full Linear Bandwidth (S/(N + D) ≥ 68dB) 350 kHz

(Note 5)

LTC1278-4/LTC1278-5

250kHz Input Signal 70 dB

250kHz Input Signal –74 dB

= 99.37kHz, f

IN1

= 249.37kHz, f

f

IN1

= 102.4kHz –82 dB

IN2

= 252.4kHz –70 dB

IN2

U

I TER AL REFERE CE CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

V

REF

V

REF

V

REF

V

REF

DIGITAL I PUTS A D DIGITAL OUTPUTS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IN

C

IN

V

OH

V

OL

I

OZ

C

OZ

I

SOURCE

I

SINK

UU

(Note 5)

LTC1278-4/LTC1278-5

Output Voltage I
Output Tempco I
Line Regulation 4.95V ≤ VDD ≤ 5.25V 0.01 LSB/V

Load Regulation 0V ≤ |I

U

High Level Input Voltage V
Low Level Input Voltage VDD = 4.95V ● 0.8 V
Digital Input Current VIN = 0V to V
Digital Input Capacitance 5pF
High Level Output Voltage VDD = 4.95V

Low Level Output Voltage VDD = 4.95V

High Z Output Leakage D11 to D0 V
High Z Output Capacitance D11 to D0 CS High (Note 9 ) ● 15 pF
Output Source Current V
Output Sink Current V

= 0 2.400 2.420 2.440 V

OUT

= 0 ● ±10 ±45 ppm/°C

OUT

–5.25V ≤ V

≤ –4.95V 0.01 LSB/V

SS

| ≤ 1mA 2 LSB/mA

OUT

U

(Note 5)

LTC1278-4/LTC1278-5

= 5.25V ● 2.4 V

DD

DD

IO = –10µA 4.7 V
IO = –200µA ● 4V

IO = 160µA 0.05 V
IO = 1.6mA ● 0.10 0.4 V

= 0V to VDD, CS High ● ±10 µA

OUT

= 0V –10 mA

OUT

= V

OUT

DD

● ±10 µA

10 mA

3

LTC1278

U

W

POWER REQUIRE E TS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

DD

V

SS

I

DD

I

SS

P

D

Positive Supply Voltage (Notes 10, 11) Unipolar 4.95 5.25 V

Negative Supply Voltage (Note 10) Bipolar Only –2.45 –5.25 V
Positive Supply Current f

Negative Supply Current f
Power Dissipation f

W

U

TI I G CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

SAMPLE(MAX)

t

SAMPLE(MIN)

t

CONV

t

ACQ

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

Maximum Sampling Frequency LTC1278-4 ● 400 kHz

Minimum Throughput Time LTC1278-4 ● 2.5 µs
(Acquisition Time Plus Conversion Time) LTC1278-5 ● 2.0 µs

Conversion Time LTC1278-4 2.0 2.3 µs

Acquisition Time 200 ns
CS↓ to RD↓ Setup Time (Notes 9, 10) ● 0ns
CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● 20 ns
SHDN↑ to CONVST↓ Wake-Up Time (Note 10) 350 ns
CONVST Low Time (Notes 10, 12) ● 40 ns
CONVST↓ to BUSY↓ Delay CL = 100pF 40 110 ns

Data Ready Before BUSY↑ CL = 100pF ● 20 40 ns
Wait Time RD↓ After BUSY↑ Mode 2, (see Figure 14) (Note 9) ● –20 ns
Data Access Time After RD↓ CL = 20pF (Note 9) 50 90 ns

Bus Relinquish Time 20 30 75 ns

RD Low Time (Note 9) ● t
CONVST High Time (Notes 9, 12) ● 40 ns
Aperture Delay of Sample-and-Hold Jitter <50ps 15 ns

(Note 5)

LTC1278-4/LTC1278-5

Bipolar 4.75 5.25 V

= 500ksps ● 15.0 29.5 mA

SAMPLE

SHDN = 0V ● 1.7 3.0 mA

= 500ksps, VSS = –5V ● 0.12 0.30 mA

SAMPLE

= 500ksps ● 75.0 150 mW

SAMPLE

SHDN = 0V ● 8.5 15 mW

(Note 5)

LTC1278-4/LTC1278-5

LTC1278-5 ● 500

LTC1278-5 1.6 1.85 µs

Commercial
Industrial ● 140 ns

Commercial
Industrial ● 120 ns

CL = 100pF 70 125 ns
Commercial
Industrial ● 170 ns

Commercial
Industrial ● 20 90 ns

● 130 ns

● 110 ns

● 150 ns

● 20 85 ns

8

ns

4

W

INPUT FREQUENCY (Hz)

10k

0

EFFECTIVE NUMBER OF BITS

S/(N+D) (dB)

3

5

7

10

100k 1M 2M

LT1278 G4

1

4

6

9

12
11

62
56

74
68

8

2

f

SAMPLE

= 500kHz

NYQUIST

FREQUENCY

U

TI I G CHARACTERISTICS

LTC1278

(Note 5)

The ● indicates specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below V

(ground for unipolar

SS

mode) or above VDD, they will be clamped by internal diodes. This product
can handle input currents greater than 60mA below VSS (ground for
unipolar mode) or above VDD without latch-up.

Note 4: When these pin voltages are taken below V

(ground for unipolar

SS

mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below VSS (ground for unipolar mode)
without latch-up. These pins are not clamped to VDD.

Note 5: AVDD = DVDD = VDD = 5V, (VSS = –5V for bipolar mode), f

SAMPLE

400kHz (LTC1278-4), 500kHz (LTC1278-5), tr = tf = 5ns unless otherwise

Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve. The
deviation is measured from the center of the quantization band.

Note 8: Bipolar offset is the offset voltage measured from –1/2LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.

Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: A

must not exceed VDD or fall below VSS by more than 50mV for

IN

specified accuracy. Therefore the minimum supply voltage for the unipolar
mode is 4.95V. The minimum for the bipolar mode is 4.75V, –2.45V.

Note 12: The falling CONVST edge starts a conversion. If CONVST returns
high at a bit decision point during the conversion it can create small errors.
For best performance ensure that CONVST returns high either within 120ns
after conversion start (i.e., before the first bit decision) or after BUSY rises
(i.e., after the last bit test). See mode 1a and 1b (Figures 12 and 13) timing

=

diagrams.

specified.
Note 6: Linearity, offset and full-scale specifications apply for unipolar and

bipolar modes.

W

U

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity vs
Output Code

1.0
f

SAMPLE

0.5

0

INL ERROR (LSB)

–0.5

–1.0

512 1024 1536 2048

0

= 500kHz

2560 3072 3584 4096

CODE

LT1278 G1

Differential Nonlinearity vs
Output Code

1.0
f

= 500kHz

SAMPLE

0.5



0

DNL ERROR (LSB)

–0.5

–1.0

0

512 1024 1536 2048

CODE

ENOBs and S/(N + D) vs
Input Frequency



2560 3072 3584 4096

LT1278 G2

5

LTC1278

W

U

TYPICAL PERFORMANCE CHARACTERISTICS

S/(N + D) vs Input Frequency
and Amplitude Distortion vs Input Frequency

80

70

60

50

40

30

20

10

SIGNAL/(NOISE + DISTORTION) (dB)

f

SAMPLE

0

1k 100k 1M 10M

VIN = 0dB

V

= –20dB

IN

= –60dB

V

IN

= 500kHz

10k

INPUT FREQUENCY (Hz)

LTC1278 G10

Spurious Free Dynamic Range vs
Input Frequency

0

f

= 500kHz

SAMPLE

–10

–20
–30
–40

–50
–60

–70
–80
–90

SPURIOUS FREE DYNAMIC RANGE (dB)

–100

10k

100k 1M 2M

INPUT FREQUENCY (Hz)

LTLTC1278 G11

Signal-to-Noise Ratio (without
Harmonics) vs Input Frequency

80

70

60

50

40

30

20

SIGNAL TO NOISE RATIO (dB)

10

f

= 500kHz

SAMPLE

0

1k 100k 1M 10M

10k

INPUT FREQUENCY (Hz)

Intermodulation Distortion Plot

0

–20

–40

–60

AMPLITUDE (dB)

–80

–100

–120

0

50k 100k 150k 200k

FREQUENCY (Hz)

f

SAMPLE

= 96.80kHz

f

IN1

= 101.68kHz

f

IN2

LTC1278 G5

= 500kHz

LTC1278 G8

250k

0

f

= 500kHz

SAMPLE

–10
–20
–30
–40

–50
–60

–70
–80
–90

AMPLITUDE (dB BELOW THE FUNDAMENTAL)

–100

10k

2ND HARMONIC

THD

100k 2M1M

INPUT FREQUENCY (Hz)

Acquisition Time vs
Source Impedance

4500

4000

3500

3000

2500

2000

1500

ACQUISITION TIME (ns)

1000

500

0

10

100 1k 10k

R

(Ω)

SOURCE

3RD HARMONIC

LT1278 G6

LTC1278 G9

Supply Current vs Temperature

20

15

10

SUPPLY CURRENT (mA)

5

0

–25 0 25 50

–55

TEMPERATURE (C°)

6

f

= 500kHz

SAMPLE

75 100 125

LTC1278 G3

Power Supply Feedthrough
vs Ripple Frequency

0

f

= 500kHz

SAMPLE

–20

–40

–60

DGND (V

–80

–100

–120

1k

AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)

VSS (V

= 0.1V)

RIPPLE

10k 100k 1M

RIPPLE FREQUENCY (Hz)

RIPPLE

AVDD (V

= 10mV)

RIPPLE

= 1mV)

LTC1278 G7

Reference Voltage vs Load Current

2.435

2.430

2.425

2.420

2.415

REFERENCE VOLTAGE (V)

2.410

2.405
–5

–3 0 1

–4 –2 –1 2

LOAD CURRENT (mA)



LTC1278 G12

UU U

PI FU CTIO S

LTC1278

A

(Pin 1): Analog Input. 0V to 5V (Unipolar), ± 2.5V

IN

(Bipolar).

V

(Pin 2): 2.42V Reference Output. Bypass to AGND

REF

(10µ F tantalum in parallel with 0.1µF ceramic).

AGND (Pin 3): Analog Ground.
D11 to D4 (Pins 11 to 4): Three-State Data Outputs.

D11 is the Most Significant Bit.

DGND (Pin 12): Digital Ground.
D3 to D0 (Pins 13 to 16): Three-State Data Outputs.
DVDD (Pin 17 ): Digital Power Supply, 5V. Tie to AV

DD

pin.

SHDN (Pin 18): Power Shutdown.
CONVST (Pin 19): Conversion Start Signal. This active

low signal starts a conversion on its falling edge (to
recognize CONVST, CS has to be low).

UU W

FU CTIO AL BLOCK DIAGRA

RD (Pin 20): READ Input. This enables the output
drivers when CS is low.

CS (Pin 21): The CHIP SELECT input must be low for the
ADC to recognize CONVST and RD inputs.

BUSY (Pin 22): The BUSY output shows the converter
status. It is low when a conversion is in progress.

VSS (Pin 23): Negative Supply. –5V for bipolar opera­tion. Bypass to AGND with 0.1µF ceramic. Analog
ground for unipolar operation.

AVDD (Pin 24): Positive Supply, 5V. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).

A

V

REF

AGND

DGND

C

SAMPLE

AV

IN

ZEROING

SWITCH

2.42V REF

COMPARATOR

12

OUTPUT LATCHES

BUSY

INTERNAL

CLOCK

12-BIT CAPACITIVE DAC

12

SUCCESSIVE APPROXIMATION

REGISTER

CONTROL LOGIC

CSCONVST RDSHDN

DD

DV

DD

V

SS

(0V FOR UNIPOLAR MODE
OR –5V FOR BIPOLAR MODE)

D11

•

•

•
D0

LTC1278 • BD

7

LTC1278

t

3

SHDN

CONVST

LTC1278 • TC03



TEST CIRCUITS

Load Circuits for Output Float DelayLoad Circuits for Access Timing

DBN

3k C

DGND

A) HIGH-Z TO V
AND V

TO VOH (t6)

OL

L

(t8)

OH

WU W

TI I G DIAGRA S

CS to RD Setup Timing

CS

t

1

RD

LTC1278 • TC01

DBN

B) HIGH-Z TO V
AND V

5V

3k

C

L

DGND

(t8)

OL

TO VOL (t6)

OH

LTC1278 TA08

CS to CONVST Setup Timing

CS

t

2

CONVST

DBN

LTC1278 • TC02

3k 10pF

DGND

A) V

TO HIGH-Z

OH

5V

3k

DBN

10pF

DGND

B) V

TO HIGH-Z

OL

1278 • TA08

SHDN to CONVST Wake-Up Timing

U

WUU

APPLICATIONS INFORMATION

CONVERSION DETAILS

The LTC1278 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces­sors and DSPs. (Please refer to the Digital Interface
section for the data format.)

Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approxi­mation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.

During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN input connects to the sample-and-hold
capacitor during the acquire phase, and the comparator

SAMPLE

C

SAMPLE

A

IN

HOLD

SAMPLE

C

DAC

V

DAC

DAC

SI

–

+

COMPARATOR

S
A
R

12-BIT
LATCH

LTC1278 F1

Figure 1. AIN Input

offset is nulled by the feedback switch. In this acquire
phase, a minimum delay of 200ns will provide enough
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the

8

LTC1278

U

WUU

APPLICATIONS INFORMATION

compare mode. The input switch switches C

SAMPLE

ground, injecting the analog input charge onto the sum­ming junction. This input charge is successively com­pared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the AIN input charge. The SAR contents (a 12-bit
data word) which represent the AIN are loaded into the
12-bit output latches.

DYNAMIC PERFORMANCE

The LTC1278 has excellent high speed sampling capabil­ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and
noise at the rated throughput. By applying a low distor­tion sine wave and analyzing the digital output using an
FFT algorithm, the ADC’s spectral content can be exam­ined for frequencies outside the fundamental. Figure 2
shows a typical LTC1278 FFT plot.

0

–20

–40

–60

AMPLITUDE (dB)

–80

–100

–120

0

50k 100k 150k 200k

FREQUENCY (Hz)

f

SAMPLE

= 97.045kHz

f

IN

= 500kHz ±5V

250k

LTC1278 F2

to

a 500kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to the
Nyquist limit of 250kHz.

Effective Number of Bits

The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:

N = [S/(N + D) – 1.76]/6.02
where N is the Effective Number of Bits of resolution and

S/(N + D) is expressed in dB. At the maximum sampling
rate of 500kHz the LTC1278 maintains very good ENOBs up
to the Nyquist input frequency of 250kHz. Refer to Figure 3.

12
11
10

9
8
7
6
5
4
3

EFFECTIVE NUMBER OF BITS

2
1

f

= 500kHz

SAMPLE

0

10k

Figure 3. Effective Bits and Signal-to-Noise + Distortion vs
Input Frequency

INPUT FREQUENCY (Hz)

NYQUIST

FREQUENCY

100k 1M 2M

74
68
62
56

S/(N+D) (dB)

LT1278 G4

Total Harmonic Distortion

Figure 2. LTC1278 Nonaveraged, 4096 Point FFT Plot

Signal-to-Noise Ratio

The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with

Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:

2

2

THD = 20log

√V

2

+ V

3

+ V

V

1

2

4



... + V

2

N

where V1 is the RMS amplitude of the fundamental fre­quency and V2 through VN are the amplitudes of the
second through Nth harmonics. THD versus input

9

LTC1278

FREQUENCY (Hz)

0

–120

AMPLITUDE (dB)

–100

–80

–60

–40

–20

0

50k 100k 150k 200k

LTC1278 G8

250k

f

SAMPLE

= 500kHz

f

IN1

= 96.80kHz

f

IN2

= 101.68kHz

U

WUU

APPLICATIONS INFORMATION

frequency is shown in Figure 4. The LTC1278 has good
distortion performance up to the Nyquist frequency and
beyond.

0

f

= 500kHz

SAMPLE

–10
–20
–30
–40

–50
–60

–70
–80
–90

AMPLITUDE (dB BELOW THE FUNDAMENTAL)

–100

10k

Figure 4. Distortion vs Input Frequency

Intermodulation Distortion

If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.

If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func­tion can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while the 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
waves are equal in magnitude, the value (in decibels) of
the 2nd order IMD products can be expressed by the
following formula:

IMD (fa ± fb) = 20log

Figure 5 shows the IMD performance at a 100kHz input.

2ND HARMONIC

THD

100k 2M1M

INPUT FREQUENCY (Hz)

Amplitude at (fa ± fb)

3RD HARMONIC

LT1278 G6

Amplitude at fa

Figure 5. Intermodulation Distortion Plot

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spec­tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.

Full Power and Full Linear Bandwidth

The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re­duced by 3dB for a full-scale input signal.

The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1278 has been designed to optimize input bandwidth,
allowing ADC to undersample input signals with frequen­cies above the converter’s Nyquist Frequency. The noise
floor stays very low at high frequencies; S/(N + D) be­comes dominated by distortion at frequencies far beyond
Nyquist.

Driving the Analog Input

The analog input of the LTC1278 is easy to drive. It draws
only one small current spike while charging the sample­and-hold capacitor at the end of conversion. During con­version the analog input draws no current. The only
requirement is that the amplifier driving the analog input
must settle after the small current spike before the next

10

LTC1278

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

conversion starts. Any op amp that settles in 200ns to
small current transients will allow maximum speed opera­tion. If slower op amps are used, more settling time can be
provided by increasing the time between conversions.
Suitable devices capable of driving the ADC’s AIN input
include the LT1360, LT1220, LT1223 and LT1224 op
amps.

Internal Reference

The LTC1278 has an on-chip, temperature compensated,
curvature corrected, bandgap reference, which is factory
trimmed to 2.42V. It is internally connected to the DAC and
is available at Pin 2 to provide up to 1mA current to an
external load.

For minimum code transition noise the reference output
should be decoupled with a capacitor to filter wideband
noise from the reference (10µ F tantalum in parallel with a

0.1µ F ceramic).

INPUT RANGE

±2.58V

(= ±1.033 × V

REF

)

5V

V

IN

V

OUT

LT1019A-2.5

GND

3Ω

10µF

5V

LTC1278

A

IN

V

REF

AGND

–5V

LTC1278 F7

Figure 7. Supplying a 2.5V Reference Voltage to the LTC1278

with the LT1019A-2.5

UNIPOLAR/BIPOLAR OPERATION AND ADJUSTMENT

Figure 8a shows the ideal input/output characteristics for
the LTC1278. The code transitions occur midway between
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,

2.5LSB, ... FS – 1.5LSB). The output code is naturally
binary with 1LSB = FS/4096 = 5V/4096 = 1.22mV. Figure
8b shows the input/output transfer characteristics for the
bipolar mode in two’s complement format.

The V
provide input span adjustment in bipolar mode. The V

pin can be driven with a DAC or other means to

REF

REF

pin must be driven to at least 2.45V to prevent conflict with
the internal reference. The reference should be driven to
no more than 4.8V to keep the input span within the ±5V
supplies.

Figure 6 shows an LT1006 op amp driving the reference
pin. (In the unipolar mode, the input span is already 0V to
5V with the internal reference so driving the reference is
not recommended, since the input span will exceed the
supply and codes will be lost at the full scale.) Figure 7
shows a typical reference, the LT1019A-2.5 connected to
the LTC1278. This will provide an improved drift (equal to
the maximum 5ppm/°C of the LT1019A-2.5) and a ±2.582V
full scale.

INPUT RANGE

±1.033V

REF(OUT)

Figure 6. Driving the V

+

–

LT1006

V

≥ 2.45V

REF(OUT)

3Ω

10µF

with the LT1006 Op Amp

REF

5V

LTC1278

A

IN

V

REF

AGND

–5V

LTC1278 F6

111...111

111...110

111...101

111...100

OUTPUT CODE

000...011

000...010

000...001

000...000
0V

1LSB =

UNIPOLAR
ZERO

1

LSB

=

4096

4096

INPUT VOLTAGE (V)

FS – 1LSB

LTC1278 F8a

5V

FS

Figure 8a. LTC1278 Unipolar Transfer Characteristics

011...111

011...110

000...001

000...000

111...111

111...110

OUTPUT CODE

100...001

100...000

BIPOLAR

ZERO

FS = 5V
1LSB = FS/4096

–1

0V

1

LSB

INPUT VOLTAGE (V)

LSB

FS/2 – 1LSB–FS/2

LTC1278 • F8b

Figure 8b. LTC1278 Bipolar Transfer Characteristics

11

LTC1278

PPLICATI

A

R1

50Ω

V1

R1

ANALOG

INPUT

0V TO 5V

10k

10k

5V

U

O

S

I FOR ATIO

WU

+

A1

–

R2
10k

R3
10k

ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE

R4

100Ω

FULL-SCALE

ADJUST

Figure 9a. Full-Scale Adjust Circuit

+


R2

10k

–

R9
20Ω

R4
100k

R5

4.3k
FULL-SCALE
ADJUST

R3

R7

100k

100k

R6
400Ω

5V

A

IN

LTC1278

AGND

R8
10k
OFFSET
ADJUST

U



LTC1278 F9a

A

IN

LTC1278

LTC1278 F9b



R1

ANALOG

INPUT

10k



R2
10k

+

A

5V

R8
20k
OFFSET
ADJUST

IN

LTC1278

LTC1278 F9c

–

R4
100k

R5

4.3k
FULL-SCALE
ADJUST

R3

R7

100k

100k

R6
200Ω

–5V

Figure 9c. LTC1278 Bipolar Offset and Full-Scale Adjust Circuit

driving the analog input of the LTC1278 while the input
voltage is 1/2LSB below ground. This is done by applying
an input voltage of –0.61mV (– 0.5LSB) to the input in
Figure 9c and adjusting the R8 until the ADC output code
flickers between 0000 0000 0000 and 1111 1111 1111.
For full-scale adjustment, an input voltage of 2.49817V
(FS – 1.5LSBs) is applied to the input and R5 is adjusted
until the output code flickers between 0111 1111 1110
and 0111 1111 1111.

Figure 9b. LTC1278 Unipolar Offset and Full-Scale Adjust Circuit

Unipolar Offset and Full-scale Error Adjustments

In applications where absolute accuracy is important, then
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 9a
shows the extra components required for full-scale error
adjustment. If both offset and full-scale adjustments are
needed, the circuit in Figure 9b can be used. For zero offset
error apply 0.61mV (i.e., 1/2LSB) at the input and adjust
the offset trim until the LTC1278 output code flickers
between 0000 0000 0000 and 0000 0000 0001. For zero
full-scale error apply an analog input of 4.99817V (i.e., FS
– 1 1/2LSB or last code transition) at the input and adjust
R5 until the LTC1278 output code flickers between 1111
1111 1110 and 1111 1111 1111.

Bipolar Offset and Full-scale Error Adjustments

Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Again, bipolar offset must be
adjusted before full-scale error. Bipolar offset error ad­justment is achieved by trimming the offset of the op amp

BOARD LAYOUT AND BYPASSING

Wire wrap boards are not recommended for high resolu­tion or high speed A/D converters. To obtain the best
performance from the LTC1278, a printed circuit board is
required. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by AGND.

High quality tantalum and ceramic bypass capacitors
should be used at the AVDD and V

pins as shown in

REF

Figure 10. For the bipolar mode, a 0.1µ F ceramic provides
adequate bypassing for the VSS pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.

Input signal leads to AIN and signal return leads from
AGND (Pin 3) should be kept as short as possible to
minimize input noise coupling. In applications where this
is not possible, a shielded cable between source and ADC
is recommended.

12

LTC1278

PPLICATI

A

U

O

S

I FOR ATIO

WU

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Also, since any potential difference in grounds between
the signal source and ADC appears as an error voltage in
series with the input signal, attention should be paid to
reducing the ground circuit impedances as much as
possible.

A single point analog ground separate from the logic
system ground should be established with an analog
ground plane at Pin 3 (AGND) or as close as possible to the
ADC. Pin 12 (DGND) and all other analog grounds should
be connected to this single analog ground point. No other
digital grounds should be connected to this analog ground
point. Low impedance analog and digital power supply
common returns are essential to low noise operation of
the ADC and the foil width for these tracks should be as
wide as possible. In applications where the ADC data
outputs and control signals are connected to a continu­ously active microprocessor bus, it is possible to get
errors in conversion results. These errors are due to
feedthrough from the microprocessor to the successive
approximation comparator. The problem can be elimi­nated by forcing the microprocessor into a WAIT state
during conversion or by using three-state buffers to iso­late the ADC data bus.

DIGITAL INTERFACE

The A/D converter is designed to interface with micropro­cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory interfac­ing. A separate CONVST is used to initiate a conversion.

Internal Clock

The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 1.6µs. No external adjustments are required, and
with the typical acquisition time of 250ns, throughput
performance of 500ksps is assured.

Power Shutdown

The LTC1278 provides a shutdown feature that will save
power when the ADC is in inactive periods. To power down
the ADC, Pin 18 (SHDN) needs to be driven low. When in
power shutdown mode, the LTC1278 will not start a
conversion even though the CONVST goes low. All the

ANALOG

INPUT

CIRCUITRY

1

A

IN

AGND V

+

–

RD

CS

CONVST

SHDN

3 2 24 17 12

ANALOG GROUND PLANE

Figure 10. Power Supply Grounding Practice

Figure 11. Internal Logic for Control Inputs CS, RD, CONVST and SHDN

REF

LTC1278

0.1µF

DV

AV

DD



FLIP

FLOP

CLEAR

0.1µF

10µF10µF

DGND

DD

ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS

DB11....DB0

BUSY

CONVERSION 

QD

START (RISING
EDGE TRIGGER)

DIGITAL
SYSTEM

GROUND CONNECTION
TO DIGITAL CIRCUITRY

LTC1278 F10

LTC1278 F11

13

LTC1278

(CONVST = )

(CONVST = )

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

power is off except the Internal Reference which is still
active and provides 2.42V output voltage to the other
circuitry. In this mode the ADC draws 8.5mW instead of
75mW (for minimum power, the logic inputs must be
within 600mV of the supply rails). The wake-up time from
the power shutdown to active state is 350ns.

Timing and Control

Conversion start and data read operations are controlled
by three digital inputs: CS, CONVST and RD. Figure 11
shows the logic structure associated with these inputs. A
logic “0” for CONVST will start a conversion after the ADC
has been selected (i.e., CS is low). Once initiated it cannot
be restarted until the conversion is complete. Converter
status is indicated by the BUSY output, and this is low
while conversion is in progress.

Figures 12 through 16 show several different modes of
operation. In modes 1a and 1b (Figures 12 and 13) CS and
RD are both tied low. The falling CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow low going CONVST pulse. Mode
1b shows high going CONVST pulse.

In mode 2 (Figure 14) CS is tied low. The falling CONVST
signal again starts the conversion. Data outputs are in
three-state until read by MPU with the RD signal. Mode 2
can be used for operation with a shared MPU databus.

In Slow memory and ROM modes (Figures 15 and 16) CS
is tied low and CONVST and RD are tied together. The MPU
starts conversion and read the output with the RD signal.
Conversions are started by the MPU or DSP (no external
sample clock).

In Slow memory mode the processor takes RD (= CONVST)
low and starts the conversion. BUSY goes low forcing the
processor into a WAIT state. The previous conversion
result appears on the data outputs. When the conversion
is complete, the new conversion results appear on the
data outputs; BUSY goes high releasing the processor,
and the processor takes RD (= CONVST) back high and
reads the new conversion data.

In ROM mode, the processor takes RD (= CONVST) low
which starts a conversion and reads the previous conversion
result. After the conversion is complete, the processor can
read the new result (which will initiate another conversion).

t

4

SAMPLE N

t

5

DATA (N-1)

t

CONV

SAMPLE N + 1

t

6

DATA N

DB11 TO DB0

t

5

t

6

DATA N

DB11 TO DB0

DATA (N + 1)
DB11 TO DB0

LTC1278 F12

DATA (N + 1)

DB11 TO DB0

CS = RD = 0

CONVST

BUSY

DATA

Figure 12. Mode 1a. CONVST Starts a Conversion. Data Ouputs Always Enabled.

CS = RD = 0

t

11

CONVST

BUSY

DATA

Figure 13. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled.

DATA (N-1)

DB11 TO DB0

DB11 TO DB0

t

CONV

SAMPLE N SAMPLE N + 1

t

5



LTC1278 F13

14

LTC1278

PPLICATI

A

CS = 0

CONVST

BUSY

DATA

RD

U

O

S

I FOR ATIO

t

CONV

t

4

SAMPLE N

t

5

Figure 14. Mode 2. CONVST Starts a Conversion. Data is Read by RD

WU

t

t

7

11

t

10

t

8

U

t

9

DATA N

DB11 TO DB0

SAMPLE N + 1

DATA (N + 1)

DB11 TO DB0

LTC1278 F14

CS = 0

RD = CONVST

BUSY

DATA

RD = CONVST

CS = 0

BUSY

DATA

t

CONV

SAMPLE N SAMPLE N + 1

t

5

t

8

DATA (N – 1)

DB11 TO DB0

t

6

DATA N

DB11 TO DB0

t

9

Figure 15. Slow Memory Mode

t

CONV

SAMPLE N SAMPLE N + 1

t

5

t

8

t

DATA (N – 1)
DB11 TO DB0

9

DB11 TO DB0

DATA N

DB11 TO DB0

DATA N

DATA (N + 1)

DB11-DB0

LTC1278 F15

LTC1278 F16

Figure 16. ROM Mode Timing

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LTC1278

S24 (WIDE) 0996

NOTE 1

0.598 – 0.614*

(15.190 – 15.600)

22 21 20 19 181716 15

1

2345678

0.394 – 0.419

(10.007 – 10.643)

910

1314

11 12

2324

0.037 – 0.045

(0.940 – 1.143)

0.004 – 0.012

(0.102 – 0.305)

0.093 – 0.104

(2.362 – 2.642)

0.050

(1.270)

TYP

0.014 – 0.019

(0.356 – 0.482)

TYP

0° – 8° TYP

NOTE 1

0.009 – 0.013

(0.229 – 0.330)

0.016 – 0.050

(0.406 – 1.270)

0.291 – 0.299**
(7.391 – 7.595)



× 45°

0.010 – 0.029

(0.254 – 0.737)

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE




*

**

PACKAGEDESCRIPTI

O

U

Dimensions in inches (millimeters) unless otherwise noted.

N Package

24-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

1.265*
(32.131)

MAX

20

7

89101911 12

151718

0.255 ± 0.015*
(6.477 ± 0.381)

24

123456

21

2223

131416

0.300 – 0.325

(7.620 – 8.255)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015

+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.020

(0.508)

MIN

(3.175)

0.125

MIN

0.130 ± 0.005

(3.302 ± 0.127)

SW Package

24-Lead Plastic Small Outline (Wide 0.300)

(LTC DWG # 05-08-1620)

0.100 ± 0.010

(2.540 ± 0.254)

0.045 – 0.065

(1.143 – 1.651)

0.018 ± 0.003

(0.457 ± 0.076)

0.065

(1.651)

TYP

N24 1197

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1274/LTC1277 12-Bit, 10mW, 100ksps A/D Converters with 1µA Shutdown Complete with Clock Reference
LTC1279 12-Bit, 600ksps Sampling A/D Converter with Shutdown 70dB SINAD at Nyquist, Low Power
LTC1400 12-Bit, 400ksps Serial A/D Converter Complete High Speed 12-Bit ADC in SO-8
LTC1409 12-Bit, 800ksps Sampling A/D Converter with Shutdown Fast, Complete Low Power ADC
LTC1415 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown Single 5V Supply, Low Power: 55mW
LTC1419 14-Bit, 800ksps Sampling A/D Converter with Shutdown 81.5dB SINAD, Low Power: 150mW

Linear Technology Corporation

16

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

1278fa LT/GP 0998 REV A 2K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1994