Datasheet LTC1235CS, LTC1235CN Datasheet (Linear Technology)

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Page 1

LTC1235

BACKUP DUTY CYCLE (%)

BATTERY LIFE (NORMALIZED)

LTC1235 TA02

100

LTC1235

LTC695 (WITHOUT CONDITIONAL BATTERY BACKUP)

Microprocessor

Supervisory Circuit

EATU

■

Guaranteed

■

1.5mA Maximum Supply Current

■

Fast (35ns Max.) Onboard Gating of RAM Chip

Reset Assertion at VCC = 1V

Enable Signals

■

Conditional Battery Backup Extends Battery Life

■

4.65V Precision Voltage Monitor

■

Power OK/Reset Time Delay: 200ms

■

External Reset Control

■

Minimum External Component Count

■

1µA Maximum Standby Current

■

Voltage Monitor for Power Fail or Low Battery Warning

■

Thermal Limiting

■

Performance Specified Over Temperature

■

All the LTC695 Features Plus Conditional Battery Backup and External Reset Control

PPLICATI

DUESCRIPTIO

The LTC1235 provides complete power supply monitoring and battery control functions for microprocessor reset, battery backup, RAM write protection, power failure warning and watchdog timing. The LTC1235 has all the LTC695 features plus conditional battery backup and external reset control. When an out-of-tolerance power supply condition occurs, the reset outputs are forced to active states and the Chip Enable output write-protects external memory. The RESET output is guaranteed to remain logic low with VCC as low as 1V. External reset control is provided by a debounced push-button reset input.

The LTC1235 powers the active CMOS RAMs with a charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, provides backup power to the RAMs. The LTC1235 can be programmed by a µP signal to either back up the RAMs or not. This extends the battery life in situations where RAM data need not always be saved when power goes down.

■

Critical µP Power Monitoring

■

Intelligent Instruments

■

Battery-Powered Computers and Controllers

■

Automotive Systems

≥ 7.5V

10µF

51k

10k

THE LTC1235 EXTENDS BATTERY LIFE BY PROVIDING BATTERY POWER ONLY WHEN REQUIRED TO BACK UP RAM DATA. IT SAVES THE BATTERY WHEN NO DATA BACKUP IS NEEDED. THE µP REQUESTS BACKUP WITH THE BACKUP PIN.

LT1086-5

PPLICATITYPICAL

ADJ

OUT

+5V

100µF

0.1µF

+3V

BATT

PFI

PB RST

LTC1235

BACKUP

OUT

RESET

PFO

WDI

For an early warning of impending power failure, the LTC1235 provides an internal comparator with a userdefined threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to the time-out period.

Battery Life vs

Backup Duty Cycle

µP

POWER

µP

SYSTEM

LTC1235 TA1

0.1µF

POWER TO CMOS RAM

I/O LINE µP RESET µP NMI

I/O LINE

Page 2

LTC1235

LUTEXI T

WUW

ARB

Terminal Voltage

VCC.................................................... –0.3V to 6.0V

................................................. –0.3V to 6.0V

BATT

All Other Inputs.................... –0.3V to (VCC + 0.3V)

Input Current

VCC.............................................................. 200mA

............................................................. 50mA

BATT

PACKAGE

BATT

OUT

GND

BATT ON

LOW LINE

PB RST

BACKUP

RDER I FOR ATIO

TOP VIEW

LTC1235

5 6 7

N PACKAGE

16-LEAD PLASTIC DIP

= 110°C, θJA = 130°C/W

JMAX

ORDER PART

NUMBER

RESET

16 15

RESET

WDO

CE IN

CE OUT WDI

PFO

PFI

U G

(Notes 1 and 2)

Output Current .................. Short Circuit Protected

OUT

Power Dissipation............................................. 500mW

Operating Temperature Range

LTC1235C ............................................ 0°C to 70°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec.)................ 300°C

(Note 3)

BATT

GND

BATT ON

LOW LINE

PB RST

BACKUP

CONDITIONS: PCB MOUNT ON FR4 MATERIAL, STILL AIR AT 25°C, COPPER TRACE

1 2

OUT

5 6

16-LEAD PLASTIC SOL

= 110°C, θJA = 130°C/W

JMAX

TOP VIEW

LTC1235

S PACKAGE

16 15

14 13

12 11

PRESET PRESET WDO

CE IN CE OUT WDI PFO

PFI

ORDER PART

NUMBER

LTC1235CSLTC1235CN

U

PRODUCT SELECTIO GUIDE

WATCHDOG BATTERY POWER FAIL RAM WRITE PUSH-BUTTON BATTERY

PINS RESET TIMER BACKUP WARNING PROTECT RESET BACKUP

LTC1235 16 X X X X X X X

LTC690 8 X X X X LTC691 16 X X X X X LTC694 8 X X X X LTC695 16 X X X X X LTC699 8 X X LTC1232 8 X X X

CONDITIONAL

Page 3

LTC1235

LECTRICAL C CHARA TERIST

VCC = Full Operating Range, V

PARAMETER CONDITONS MIN TYP MAX UNITS Battery Backup Switching

Operating Voltage Range

BATT

Output Voltage I

OUT

BACKUP Input Threshold VCC > Reset Voltage Threshold

BACKUP Pullup Current (Note 4) 3 µA V

in Battery Backup Mode (Note 5) I

OUT

in Battery Saving Mode (Note 5) VCC < V

OUT

VCC Supply Current (excluding I

Battery Supply Current in Battery Backup Mode and VCC = 0V, V

Battery Saving Mode (Note 5) ● 0.04 5

Battery Standby Current 5.5 > VCC > V

(+ = Discharge, – = Charge)

Battery Switchover Threshold Power Up 70 mV

VCC – V

BATT

Battery Switchover Hysteresis 20 mV BATT ON Output Voltage (Note 6) I BATT ON Output Short Circuit Current (Note 6) BATT ON = V

Push-Button Reset

PB RST Input Threshold Logic Low 0.8 V

PB RST Input Low Time (Notes 4, 7) ● 40 ms

Reset and Watchdog Timer

Reset Voltage Threshold Reset Threshold Hysteresis 40 mV Reset Active Time V

Watchdog Time-out Period V

Reset Active Time PSRR 1 ms/V Watchdog Time-out Period PSRR 8 ms/V Minimum WDI Input Pulse Width V RESET Output Voltage At VCC = 1V I RESET and LOW LINE Output Voltage I

(Note 6) I

= 2.8V, Backup = No Connection, TA = 25°C, unless otherwise noted.

BATT

OUT

ICS

4.75 5.50 V

2.00 4.25

= 1mA V

OUT

= 50mA VCC – 0.5 VCC – 0.25

OUT

Logic Low 0.8 V Logic High 2.0

= 250µA, VCC < V

OUT

BATT

1MΩ Pulldown on V

≤ 50mA 0.6 1.5 mA

OUT

BATT

Power Down 50

= 3.2mA 0.4 V

SINK

BATT ON = 0V Source Current 0.5 1 25 µA

Logic High 2.0

= 5V 160 200 240 ms

= 5V 1.2 1.6 2.00 sec

= 0.4V, VIH = 3.5V ● 200 ns

SINK

SINK SOURCE

OUT

= 10µA, VCC = 1V 4 200 mV = 1.6mA, VCC = 4.25V 0.4 V

= 1µA, VCC = 5V 3.5

BATT

OUT

= 2.8V 0.04 1 µA

+ 0.2V –0.1 +0.02 µA

BATT

Sink Current 35 mA

● V

● 0.6 2.5

● –1.0 +0.10

● 4.5 4.65 4.75 V

● 140 200 280

● 1.0 1.6 2.25

– 0.05 V

– 0.1 VCC – 0.005

– 0.1 V

BATT

– 0.005 V

– 0.02 V

BATT

Page 4

LTC1235

LECTRICAL C CHARA TERIST

VCC = Full Operating Range, V

PARAMETER CONDITONS MIN TYP MAX UNITS

RESET and WDO Output Voltage I

(Note 6)

RESET, RESET, WDO, LOW LINE Output Source Current 1 3 25 µA

Output Short Circuit Current (Note 6) Output Sink Current 25 mA

WDI Input Threshold Logic Low 0.8 V

WDI Input Current WDI = V

Power Fail Detector

PFI Input Threshold VCC = 5V ● 1.25 1.3 1.35 V PFI Input Threshold PSRR 0.3 mV/V PFI Input Current ±0.01 ±25 nA PFO Output Voltage (Note 6) I

PFO Short Circuit Source Current PFI = HIGH, PFO = 0V 1 3 25 µA

(Note 6) PFI = LOW, PFO = V

PFI Comparator Response Time (falling) ∆V PFI Comparator Response Time (rising) ∆V

(Note 6) with 10kΩ Pullup 8

Chip Enable Gating

CE IN Threshold V

CE IN Pullup Current (Note 4) 3 µA CE OUT Output Voltage I

CE Propagation Delay V

CE OUT Output Short Circuit Current Output Source Current 30 mA

= 2.8V, Backup = No Connection, TA = 25°C, unless otherwise noted.

BATT

ICS

= 1.6mA, VCC = 5V 0.4 V

SINK

= 1µA, VCC = 4.25V 3.5

SOURCE

Logic High 2.0

OUT

WDI = 0V ● –50 –8

= 3.2mA 0.4 V

SINK

= 1µA 3.5

SOURCE

OUT

= –20mV, VOD = 15mV 2 µs

= 20mV, VOD = 15mV 40 µs

= 3.2mA 0.4 V

SINK

= 3.0mA V

SOURCE

= 1µA, VCC = 0V V

SOURCE

= 5V, CL = 20pF 20 35 ns

Output Sink Current 35

● 450µA

30 mA

0.8 V

2.0

– 1.50

OUT

– 0.05

OUT

● 20 45

The ● denotes specifications which apply over the operating temperature range.

Note 1: Absolute maximum ratings are those values beyond which the life of device may be impaired.

Note 2: All voltage values are with respect to GND. Note 3: For military temperature range parts, consult the factory. Note 4: The input pins of PB RST, BACKUP and CE IN, have weak internal

pullups which pull to the supply when the input pins are floating. Note 5: The LTC1235 can be programmed either to provide or not to

provide battery backup power to the V power down condition of V pin which is latched internally when V threshold. If the latched logic level of the BACKUP pin is high, V

is selected by the logic level of the BACKUP

OUT

pin during power failure. The

OUT

falls through the reset voltage

OUT

will be

in Battery Backup Mode and will be switched to V below V be in Battery Saving Mode when V

Note 6: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and RESET have weak internal pullups of typically 3µA. However, external pullup resistors may be used when higher speed is required.

Note 7: The push-button reset input requires an active low signal. Internally, this input signal is debounced and timed for a minimum of 40ms. When this condition is satisfied, the reset outputs go to the active states. The reset outputs will remain in active states for a minimum of 140ms from the moment the push-button reset input is released from logic low level.

. If the latched logic level of the BACKUP pin is low, V

BATT

falls below V

when VCC falls

BATT

OUT

will

Page 5

TEMPERATURE (˚C)

–50

PFI INPUT THRESHOLD (V)

1.304

1.306

1.308

25 75

LTC1235 G03

1.302

1.300

–25 0

50 100 125

1.298

1.296

1.294

VCC = 5V

LPER

TIME (µs)

LTC1235 G09

3 2

1.315V

1.295V

108

PFI

= 20mV STEP

1816

VCC = 5V T

= 25°C

–

PFI

1.3V

PFO

30pF

10k

+5V

PFO OUTPUT VOLTAGE (V)

vs I

OUT

5.00

4.95

4.90

SLOPE = 5Ω

4.85

OUTPUT VOLTAGE (V)

4.80

VCC = 5V V

BATT

= 25°C

ATYPICA

= 2.8V

CCHARA TERIST

vs I

OUT

2.80

2.78

SLOPE = 125Ω

2.76

OUTPUT VOLTAGE (V)

2.74

OUT

ICS

VCC = 0V V

BATT

= 25°C

BACKUP MODE SELECTED

LTC1235

Power Failure Input Threshold vs TemperatureV

= 2.8V

4.75 0

RESET Output Voltage vs Supply Voltage

TA = 25°C EXTERNAL PULLUP = 10µA V

RESET OUTPUT VOLTAGE (V)

Power Fail Comparator Response Time

PFO OUTPUT VOLTAGE (V)

1.305V

1.285V

LOAD CURRENT (mA)

= 0V

BATT

SUPPLY VOLTAGE (V)

PFI

123

PFI

1.3V

= 20mV STEP

TIME (µs)

–

PFO

VCC = 5V T

LTC1235 G01

LTC1235 G04

= 25°C

30pF

LTC1235 G07

2.72

232

224

216

208

200

RESET ACTIVE TIME (ms)

192

184

PFO OUTPUT VOLTAGE (V)

1.315V

1.295V

100

200

LOAD CURRENT (µA)

Reset Active Time vs Temperature

VCC = 5V

–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

Power Fail Comparator Response Time

VCC = 5V

= 25°C

4 3

= 20mV STEP

PFI

TIME (µs)

PFI

1.3V

300

10080

400

500

LTC1235 G02

Reset Voltage Threshold vs Temperature

4.66

4.65

4.64

4.63

4.62

RESET VOLTAGE THRESHOLD (V)

4.61

LTC1235 G05

4.60 –50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

LTC1235 G06

Power Fail Comparator Response Time with Pullup Resistor

PFO

120

140

LTC1235 G08

30pF

180160

–

Page 6

LTC1235

U

PI FU CTIO S

VCC: +5V supply input. The VCC pin should be bypassed with a 0.1µF capacitor.

Backup: Logic input to control the PMOS switch, M2, when VCC is lower than V the reset voltage threshold, the status of the BACKUP pin (logic low or logic high) is latched in Memory Logic and used to turn on or off M2 when VCC is below V latched status of the BACKUP pin is high, the Memory Logic turns on M2 when VCC falls to 50mV greater than V

. If the latched status of the BACKUP pin is low, the

BATT

Memory Logic keeps M2 off even after VCC falls below V

. If the BACKUP pin is left floating it will be pulled high

BATT

by an internal pullup and the LTC1235 will provide battery backup when VCC falls.

: Voltage output for backed up memory. Bypass with

OUT

a capacitor of 0.1µF or greater. During normal operation, V

obtains power from VCC through an NMOS power

OUT

switch, M1, which can deliver up to 50mA and has a typical on resistance of 5Ω. When VCC is lower than V status of the BACKUP pin stored in Memory Logic controls M2. If the status is high, the Memory Logic turns on M2 and V

is internally switched to V

OUT

status is low, the Memory Logic keeps M2 off and V in Battery Saving Mode. If V connect V

: Backup battery input. When VCC falls below V

BATT

OUT

to VCC.

the status of the BACKUP pin stored in the Memory Logic controls M2. If the status is high, auxiliary power, connected to V

is delivered to V

BATT

low, the Memory Logic keeps M2 off and V Saving Mode. If backup battery or auxiliary power is not used, V

should be connected to GND.

BATT

GND: Ground pin. BATT ON: Battery on logic output from comparator C2.

BATT ON goes low when V VCC. The output typically sinks 35mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of V high when VCC falls below V BACKUP pin stored in Memory Logic is high and V switched to V

BATT

. While VCC is falling through

BATT

through M2. If the

BATT

and V

OUT

through M2. If the status is

OUT

is internally connected to

OUT

, if the status of the

BATT

are not used,

BATT

is in Battery

OUT

. BATT ON goes

OUT

. If the

BATT

, the

OUT

BATT

OUT

PFI: Power Failure Input. PFI is the noninverting input to the Power Fail Comparator, C3. The inverting input is internally connected to a 1.3V reference. The Power Failure Output remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. Connect PFI to GND or V

OUT

when

C3 is not used. PFO: Power Failure Output from C3. PFO remains high

when PFI is above 1.3V and goes low when PFI is below

1.3V. When VCC is lower than V

, C3 is shut down and

BATT

PFO is forced low. PB RST: Logic input for direct connection to a push-

button. The push-button reset input requires an active low signal. Internally, this input signal is debounced and timed for a minimum of 40ms. When this condition is satisfied, the reset pulse generator forces RESET to active low. The RESET signal will remain active low for a minimum of 140ms from the moment the push-button reset input is released from logic low level.

RESET: Logic output for µP reset control. The LTC1235 provides three ways to generate µP reset. First, whenever VCC falls below either the reset voltage threshold (4.65V, typically) or V

, RESET goes active low. After V

BATT

returns to 5V, the reset pulse generator forces RESET to remain active low for a minimum of 140ms. Second, when the watchdog timer is enabled but not serviced prior to the time-out period, the reset pulse generator also forces RESET to active low for a minimum of 140ms for every time-out period (see Figure 11). Third, when the PB RST pin stays active low for a minimum of 40ms, RESET is forced low by reset pulse generator. The RESET signal will remain active low for a minimum of 140ms from the moment the push-button reset input is released from logic low level.

RESET: RESET is an active high logic output. It is the inverse of RESET.

LOW LINE: Logic output from comparator C1. LOW LINE indicates a low line condition at the VCC input. When V

falls below the reset voltage threshold (4.65V typically), LOW LINE goes low. As soon as VCC rises above the reset voltage threshold, LOW LINE returns high (see Figure 1). LOW LINE goes low when V

drops below V

BATT

(see

Table 1).

Page 7

LTC1235

U

PI FU CTIO S

WDI: Watchdog Input, WDI, is a three level input. Driving WDI either high or low for longer than the watchdog timeout period, forces both RESET and WDO low. Floating WDI disables the Watchdog Timer. The timer resets itself with each transition of the Watchdog Input (see Figure 11).

WDO: Watchdog logic output. When the watchdog input remains either high or low for longer than the watchdog time-out period, WDO goes low. WDO is set high whenever there is a transition on the WDI pin, or LOW LINE goes low. The watchdog timer can be disabled by floating WDI (see Figure 11).

BLOCK

IDAGRA

BATT

BACKUP

–

CE IN: Logic input to the Chip Enable gating circuit. CE IN can be derived from microprocessor's address line and/or decoder output. See Applications Information Section and Figure 6 for additional information.

CE OUT: Logic output from the Chip Enable gating circuit. When VCC is above the reset voltage threshold, CE OUT is a buffered replica of CE IN. When VCC is below the reset voltage threshold CE OUT is forced high (see Figure 6).

MEMORY

LOGIC

CHARGE

PUMP

OUT

BATT ON

CE IN

PFI

PB RST

WDI

1.3V

GND

LEVEL SENSE

AND

DEBOUNCE

TRANSITION

DETECTOR

LOW LINE

–

OSC

RESET PULSE

GENERATOR

WATCHDOG

TIMER

CE OUT

PFO

RESET

WDO

LTC1235 BD

Page 8

LTC1235

PPLICATI

I FOR ATIO

Power Monitoring

The LTC1235 uses a bandgap voltage reference and a precision voltage comparator C1 to monitor the 5V supply input on VCC (see BLOCK DIAGRAM). When VCC falls below the reset voltage threshold, the reset outputs are forced to active states. The reset voltage threshold accounts for a 5% variation on VCC, so the reset outputs become active when VCC falls below 4.75V (4.65V typical). On power-up, the reset signals are held active states for a minimum of 140ms after the reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. On power-down, the RESET signal remains active low even with VCC as low as 1V. This capability helps hold the microprocessor in stable shutdown condition. Figure 1 shows the timing diagram of the RESET signal.

The precision voltage comparator, C1, typically has 40mV of hysteresis which ensures that glitches at VCC pin do not activate the reset outputs. Response time is typically 10µ s.

To help prevent mistriggering due to transient loads, V

pin should be bypassed with a 0.1µF capacitor with the leads trimmed as short as possible.

LOW LINE is the output of the precision voltage comparator C1. When VCC falls below the reset voltage threshold, LOW LINE goes low. LOW LINE returns high as soon as VCC rises above the reset voltage threshold.

Push-Button Reset

The LTC1235 provides an logic input pin for direct connection to a push-button. The push-button reset input, PB RST, requires an active low signal. Internally, this input signal is debounced and timed for a minimum of 40ms. When this condition is satisfied, the reset pulse generator forces the reset outputs to active states. The reset signals will remain in active states for a minimum of 140ms from the moment the push-button reset input is released from logic low level (Figure 2).

RESET

LOW LINE

V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS

t1 = RESET ACTIVE TIME

LOGIC

HIGH

LOGIC HIGH

LOGIC LOW

LTC1235 F01

= 5V

PB RST

RESET

LOGIC LOW

Figure 1. Reset Active Time

t1 = PUSH-BUTTON RESET LOW TIME t2 = RESET ACTIVE TIME

Figure 2. Push-Button Reset

Page 9

LTC1235

PPLICATI

I FOR ATIO

Voltage Output

During normal operation, the LTC1235 uses a charge pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to V 5Ω. The V

from VCC and has a typical on resistance of

OUT

pin should be bypassed with a capacitor of

OUT

0.1µ F or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads.

When operating currents larger than 50mA are required from V

, or a lower dropout (VCC - V

OUT

voltage differ-

OUT

ential) is desired, the LTC1235 provides BATT ON output to drive the base of external PNP transistor (Figure 3). Another alternative to provide higher current is to connect a high current Schottky diode from the VCC pin to the V

OUT

pin to supply the extra current.

ANY PNP POWER TRANSISTOR

+5V

0.1µF

+3V

Figure 3. Using BATT ON to Drive External PNP Transistor

LTC1235

BATT

BATT ON

GND

OUT

0.1µF

LTC1235 F03

The LTC1235 is protected for safe area operation with short circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for a long period of time, thermal shutdown turns the power switch off until the device cools down. The threshold temperature for thermal shutdown is approximately 155°C with about 10°C of hysteresis which prevents the device from oscillating in and out of shutdown.

The PNP switch was not chosen for the internal power switch because it injects unwanted current into the substrate. This current is collected by the V

pin in com-

BATT

petitive devices and adds to the charging current of the battery which can damage lithium batteries. LTC1235

uses a charge pumped NMOS power switch to eliminate unwanted charging current while achieving low dropout and low supply current. Since no current goes to the substrate, the current collected by V

pin is strictly

BATT

junction leakage.

Conditional Battery Backup

LTC1235 provides an unique feature to either allow V to be switched to V

or to disable the CMOS RAM

BATT

OUT

battery backup function when primary power is lost. Disabling the battery backup function is useful in conserving the backup battery's life when the SRAM doesn't need battery backup during long term storage of a computer system, or delivery of the computer system to the end user.

The BACKUP pin (Pin 8) is used to serve this feature on power-down. When VCC is falling through the reset voltage threshold, the status of the BACKUP pin (logic low or logic high) is stored in the Memory Logic (see BLOCK DIAGRAM). If the stored status is logic high and VCC fall to 50mV greater than V connects the V

BATT

input to V

, a 125Ω PMOS switch, M2,

BATT

and the battery switchover

OUT

comparator, C2, shuts off the NMOS power switch, M1. M2 is designed for very low dropout voltage (input-tooutput differential). This feature is advantageous for low current applications such as battery backup in CMOS RAM and other low power CMOS circuitry. If the stored status is logic low and VCC falls to 50mV greater than V Memory Logic keeps M2 off and C2 shuts off M1. V

BATT

, the

OUT

in Battery Saving Mode (see Figure 4). The supply current in both mode is 1µA maximum.

On power-ups, C2 keeps M1 off before VCC reaches 70mV higher than V

. On the first power-up after the battery

BATT

is replaced (with power off), the status stored in the Memory Logic is undetermined. V

could be either in

OUT

Battery Backup Mode or in Battery Saving Mode. When VCC is 70mV greater than V

, M1 connects V

BATT

OUT

to VCC. C2 has typically 20mV of hysteresis to prevent spurious switching when VCC remains nearly equal to V

BATT

and the

status stored in the Memory Logic is high. The response time of C2 is approximately 20µs.

Page 10

LTC1235

V–V

EXT REQ'D

CC BATT

≥

 



 



PPLICATI

BACKUP

OUT

BACKUP

OUT

I FOR ATIO

IN BATTERY SAVING MODE

OUT

LOGIC LOW

RESET VOLTAGE THRESHOLD

BATT

Hi-Z

IN BATTERY BACKUP MODE

OUT

LOGIC HIGH

RESET VOLTAGE THRESHOLD

BATT

= V

OUT

BATT

LTC1235 F04

Replacing the Backup Battery with Power On

When changing the backup battery with system power on, spurious resets can occur while battery is removed due to battery standby current. Although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the V follows: When V

BATT

pin. The oscillation cycle is as

BATT

reaches within 50mV of VCC, the LTC1235 switches to battery backup or battery saving mode. In either case, the battery supply current pulls V

low and the device goes back to normal operation.

BATT

The leakage current then charges up the V

pin again

BATT

and the cycle repeats. If spurious resets during battery replacement pose no

problems, then no action is required. Otherwise, two methods can be used to eliminate this problem. First, a capacitor from V

to GND will allow time for battery

BATT

replacement by slowing the charge rate. For example, the battery standby current is 1µA maximum over tempera- ture and the external capacitor required to slow the charge rate is:

Figure 4. Conditional Battery Backup Operation

The operating voltage at the V

pin ranges from 2.0V to

BATT

4.25V. High value capacitors, such as electrolytic or faradsize double layer capacitors, can be used for short term memory backup instead of a battery. For capacitor backup, see Typical Applications. The charging resistor for recharging rechargeable batteries should be connected to V

through a diode since this eliminates the discharge

OUT

path that exists when V

collapses and RAM is not backed

up (Figure 5).

– V

BATT

LTC1235

BATT

– V

BACKUP

GND



1N4148

OUT

RAM

0.1µF

I/O LINE

µP

LTC1235 F05

OUT

I =

+5V

0.1µF

+3V

Figure 5. Charging External Battery Through V

where T backup battery. With VCC = 4.5V, V

is the maximum time required to replace the

REQ'D

= 3V and T

BATT

REQ'D

3 sec, the value for external capacitor is 2µF. Second, a resistor from V

to GND will hold the pin low while

BATT

changing the battery. For example, the battery standby current is 1µA maximum over temperature and the external resistor required to hold V

V – 50mV

≤

below VCC is:

BATT

With VCC = 4.5V, a 4.3MΩ resistor will work. With a 3V battery, this resistor will draw only 0.7µA from the battery, which is negligible in most cases.

If the battery connections are made with long wires or PC traces, inductive spikes can be generated during battery replacement. Even if a resistor is used to prevent spurious resets as described above, these spikes can take the V

BATT

pin below GND violating the LTC1235 absolute maximum ratings. A 0.1µF capacitor from V

to GND is recom-

BATT

mended to eliminate these potential spikes when battery replacement is made through long wires.

Page 11

LTC1235

PPLICATI

I FOR ATIO

Table 1 shows the state of each pin during battery backup. If the backup battery is not used, connect V and V

Table 1. Input and Output Status in Battery Backup Mode

SIGNAL STATUS

BACKUP BACKUP is ignored. V

OUT

BATT

BATT ON Logic high. The open circuit output voltage is equal to V PFI Power Failure Input is ignored. PFO Logic low PB RST PB RST is ignored. RESET Logic low RESET Logic high. The open circuit output voltage is equal to V LOW LINE Logic low WDI Watchdog Input is ignored. WDO Logic high. The open circuit output voltage is equal to V CE IN Chip Enable Input is ignored. CE OUT Logic high. The open circuit output voltage is equal to V

to VCC.

OUT

C2 monitors VCC for active switchover.

is connected to V

OUT

The supply current is 1µA maximum.

BATT

through an internal PMOS switch.

BATT

to GND

OUT

IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is +5V, CE OUT follows CE IN with a typical propagation delay of 20ns. When VCC falls below the reset voltage threshold or V

, CE OUT is forced

BATT

high, independent of CE IN. CE OUT is an alternative signal to drive the CE, CS, or Write input of battery-backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 6 shows the timing diagram of CE IN and CE OUT.

CE IN can be derived from the microprocessor’s address decoder output. Figure 7 shows a typical nonvolatile CMOS RAM application.

+5V

0.1µF

+3V

BATT

GND

LTC1235

CE OUT

BACKUP

RESET

OUT

CE IN

10µF

20ns PROPAGATION DELAY

FROM DECODER

TO µP

0.1µF

62512

RAM

GND

LTC1235 F06

Memory Protection

The LTC1235 includes memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when VCC is at invalid level. Two pins, CE

BACKUP = V

CE OUT

CE IN

= V

OUT

BATT

Figure 6. Timing Diagram for CE IN and CE OUT

Figure 7. A Typical Nonvolatile CMOS RAM Application

V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS

= V

OUT

BATT

LTC1235 F06

Page 12

LTC1235

10µF

100µF

OUT

ADJ

LTC1235 F07

0.1µF

TO µP

GND

PFO

LT1086-5

≥ 7.5V

R4 10k

PFI

LTC1235

R1 51k

R2 10k

R3

300k

+ +

+5V

BACKUP

PPLICATI

I FOR ATIO

Power Fail Warning

The LTC1235 generates a Power Failure Output (PFO) for early warning of failure in the microprocessor's power supply. This is accomplished by comparing the Power Failure Input (PFI) with an internal 1.3V reference. PFO goes low when the voltage at PFI pin is less than 1.3V. Typically PFI is driven by an external voltage divider (R1 and R2 in Figures 8 and 9) which senses either an unregulated DC input or a regulated 5V output. The voltage divider ratio can be chosen such that the voltage at PFI pin falls below 1.3V several milliseconds before the +5V supply falls below the maximum reset voltage threshold

4.75V. PFO is normally used to interrupt the microprocessor to execute shut-down procedure between PFO and RESET or RESET.

The power fail comparator, C3, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and lower trip points in the comparator are established as follows:

When PFO output is low, R3 sinks current from the summing junction at the PFI pin.

V5V

HYSTERESIS

850mV

R3 ≈ 5.88 R1

Choose R3 = 300kΩ and R1 = 51kΩ. Also select R4 = 10kΩ which is much smaller than R3.

7.5V =1.3V 1+







51k

(5V –1.3V)51k

ΩΩ

–

1.3V(310k )

 

Ω



R2 = 9.7kΩ, Choose nearest 5% resistor 10k and recalculate VL,



51k

V 1.3V 1







V 1.3V 1

=++





(7.32V – 6.25V)

Ω

10k

Ω

51k

Ω

10k

Ω

10.7ms=

–

(5V –1.3V)51k

1.3V(310k



51k

Ω

300k



Ω





Ω



Ω)



8.151V

7.32V

100mV/ms

HYSTERESIS

= 8.151V – 7.32V = 831mV

When PFO output is high, the series combination of R3 and R4 source current into the PFI summing junction.

Example 1: The circuit in Figure 8 demonstrates the use of the power fail comparator to monitor the unregulated power supply input. Assuming the the rate of decay of the supply input VIN is 100mV/ms and the total time to execute a shut-down procedure is 8ms. Also the noise of VIN is 200mV. With these assumptions in mind, we can reasonably set VL = 7.5V which 1.25V greater than the sum of maximum reset voltage threshold and the dropout voltage of LT1086-5 (4.75V + 1.5V) and V



V =1.3V 1+

V 1.3V 1

R1R2R1











Assuming R4«R3,V 5V







(5V –1.3V)R1

–

1.3V(R3 R4)

HYSTERESIS

 



R1 R3

= 850mV.

Figure 8. Monitoring LTC1235 Power Fail Comparator

LT1086-5

≥ 6.5V

10µF

Figure 9. Monitoring Power Fail Comparator

OUT

ADJ

10µF

Unregulated

R1 27k

R2

8.2k

R5

3.3k

Regulated

DC Supply with the

+5V

R3

2.7M

0.1µF V

R4

10k

DC Supply with the LTC1235

PFO

PFI

LTC1235

BACKUP GND

TO µP

LTC1235 F08

Page 13

LTC1235

PPLICATI

I FOR ATIO

The 10.7ms allows enough time to execute shut-down procedure for microprocessor and 831mV of hysteresis would prevent PFO from going low due to the noise of VIN.

Example 2: The circuit in Figure 9 can be used to measure the regulated 5V supply to provide early warning of power failure. Because of variations in the PFI threshold, this circuit requires adjustment to ensure that the PFI comparator trips before the reset threshold is reached. Adjust R5 such that the PFO output goes low when the VCC supply reaches the desired level (e.g., 4.85V).

Monitoring the Status of the Battery

C3 can also monitor the status of the memory backup battery (Figure 10). If desired, the CE OUT can be used to apply a test load to the battery. Since CE OUT is forced high in battery backup mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered.

watchdog time-out period and reset active time. The watchdog time-out period is restarted as soon as the reset outputs are inactive. When either a high-to-low or low-tohigh transition occurs at the WDI pin prior to time-out, the watchdog time is reset and begins to time out again. To ensure the watchdog time does not time out, either a highto-low or low-to-high transition on the WDI pin must occur at or less than the minimum time-out period. If the input to the WDI pin remains either high or low, reset pulses will be issued every 1.6 seconds typically. The watchdog timer can be deactivated by floating the WDI pin. The timer is also disabled when VCC falls below the reset voltage threshold or V

BATT

The Watchdog Output, WDO, goes low if the watchdog timer is allowed to time out and remains low until set high by the next transition on the WDI pin. WDO is also set high when VCC falls below the reset voltage threshold or V

+5V

BATT

Watchdog Timer

The LTC1235 provides a watchdog timer function to monitor the activity of the microprocessor. If the microprocessor does not toggle the Watchdog Input (WDI) within the time-out period, the reset outputs are forced to active states for a minimum of 140ms. The watchdog time-out period is fixed at 1.0 second minimum on the LTC1235. This time-out period provides adequate time for many systems to service the watchdog timer immediately after a reset. Figure 11 shows the timing diagram of

= 5V

WDI

WDO

BATT

R1 1M

+3V

Figure 10. Backup Battery Monitor with Optional Test Load

t1 = RESET ACTIVE TIME t2 = WATCHDOG TIME-OUT PERIOD

R2 1M

RL 20K

OPTIONAL TEST LOAD

PFI

CE OUT

LTC1235

PFO

BACKUP

CE IN

GND

LOW BATTERY SIGNAL TO µP I/O PIN

TO µP I/O PIN

}

LTC1235 F09

RESET

Figure 11. Watchdog Time-out Period and Reset Active Time

LTC1235 F11

Page 14

LTC1235

10µF

BATT

LTC1235

OUT

GND

LTC1235 TA4

LOW LINE

CE IN

CE OUT

0.1µF

20ns PROPAGA- TION DELAY

62512 RAM

+5V

+3V

0.1µF

62128 RAM

62128

RAM

OPTIONAL CONNECTION FOR ADDITIONAL RAMs

0.1µF

µP

SYSTEM

BACKUP

Capacitor Backup with 74HC4016 Switch Write Protect for Additional RAMs

R1 10k

R2 30k

PPLICATITYPICAL

74HC4016

0.1µF

14121110

100µF

+5V

BATT

LTC1235

LOW LINE

GND

OUT

0.1µF

LTC1235 TA3

Page 15

PACKAGE DESCRIPTIO

U

Dimensions in inches (millimeters) unless otherwise noted.

N Package

16-Lead Plastic DIP

0.770

(19.558)

0.260 ± 0.010

(6.604 ± 0.254)

1314

456

910

LTC1235

0.300 – 0.325

(7.620 – 8.255)

0.009 - 0.015

(0.229 - 0.381)

+0.025

0.325 –0.015

+0.635

8.255

()

–0.381

0.015

(0.381)

MIN

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

SEE NOTE

0.045 ± 0.015

(1.143 ± 0.381)

0.100 ± 0.010

(2.540 ± 0.254)

SO Package

16-Lead SOIC

(10.109 – 10.490)

15 141312

0.045 – 0.065

(1.143 – 1.651)

0.398 – 0.413

0.065

(1.651)

TYP

0.018 ± 0.003

(0.457 ± 0.076)

N16 1291

10 9

0.394 – 0.419

(10.008 – 10.643)

2345678

0.050

(1.270)

TYP

0.014 – 0.019

(0.356 – 0.483)

TYP

0.291 – 0.299

0.005

(0.127)

RAD MIN

0.009 – 0.013

(0.229 – 0.330)

NOTE: PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.

(7.391 – 7.595)

0.010 – 0.029

(0.254 – 0.737)

SEE NOTE

× 45°

0° – 8° TYP

0.016 – 0.050

(0.406 – 1.270)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.

0.093 – 0.104

(2.362 – 2.642)

0.037 – 0.045

(0.940 – 1.143)

0.004 – 0.012

(0.102 – 0.305)

SOL16 12/91

Page 16

LTC1235

U.S. Area Sales Offices

NORTHEAST REGION CENTRAL REGION NORTHWEST REGION Linear Technology Corporation Linear Technology Corporation Linear Technology Corporation

One Oxford Valley Chesapeake Square 782 Sycamore Dr. 2300 E. Lincoln Hwy.,Suite 306 229 Mitchell Court, Suite A-25 Milpitas, CA 95035 Langhorne, PA 19047 Addison, IL 60101 Phone: (408) 244-2050 Phone: (215) 757-8578 Phone: (708) 620-6910 FAX: (408) 432-6331 FAX: (215) 757-5631 FAX: (708) 620-6977

SOUTHEAST REGION SOUTHWEST REGION Linear Technology Corporation Linear Technology Corporation

17060 Dallas Parkway 22141 Ventura Blvd. Suite 208 Suite 206 Dallas, TX 75248 Woodland Hills, CA 91364 Phone: (214) 733-3071 Phone: (818) 703-0835 FAX: (214) 380-5138 FAX: (818) 703-0517

International Sales Offices

FRANCE KOREA UNITED KINGDOM Linear Technology S.A.R.L. Linear Technology Korea Branch Linear Technology (UK) Ltd.

"Le Quartz" Namsong Building, #505 The Coliseum, Riverside Way 58 Chemin de la Justice Itaewon-Dong 260-199 Camberley, Surrey GU15 3YL 92290 Chatenay Mallabry Yongsan-Ku, Seoul United Kingdom France Korea Phone: 011-44-276-677676 Phone: 33-1-46316161 (170) Phone: 82-2-792-1617 FAX: 011-44-276-64851 FAX: 33-1-46314613 FAX: 82-2-792-1619

JAPAN TAIWAN GERMANY Linear Technology KK Linear Technology Corporation Linear Technology GMBH

4F Ichihashi Building Rm. 801, No. 46, Sec. 2 Untere Hauptstr. 9 1-8-4 Kudankita Chiyoda-Ku Chung Shan N. Rd. D-8057 Eching Tokoyo, 102 Japan Taipei, Taiwan, R.O.C. Germany Phone: 81-3-3237-7891 Phone: 886-2-521-7575 Phone: 49-89-3195023 FAX: 81-3-3237-8010 FAX: 886-2-521-7575 Telex: 17-897457

FAX: 49-89-3194821

SINGAPORE Linear Technology PTE. LTD.

101 Boon Keng Road #02-15 Kallang Ind. Estates Singapore 1233 Phone: 65-293-5322 FAX: 65-292-0398

World Headquarters

Linear Technology Corporation

1630 McCarthy Blvd. Milpitas, CA 95035-7487 Phone: (408) 432-1900 FAX: (408) 434-0507

01/21/92

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7487

(408) 432-1900

●

FAX

: (408) 434-0507

●

TELEX

: 499-3977

LT/GP 0192 10K REV 0

 LINEAR TECHNOLOGY CORPORATION 1992

Datasheet LTC1235CS, LTC1235CN Datasheet (Linear Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual