Current Mode Operation for Excellent Line and Load
Transient Response
■
High Efficiency Maintained Over Three Decades of
Output Current
■
Low 160µA Standby Current at Light Loads
■
Logic Controlled Micropower Shutdown: IQ < 20µA
■
Short-Circuit Protection
■
Very Low Dropout Operation: 100% Duty Cycle
■
High Efficiency in a Small Amount of Board Space
■
Output Can Be Externally Held High in Shutdown
■
Available in 8-Pin SO Package
LTC1147-3.3
LTC1147-5/LTC1147L
High Efficiency Step-Down
Switching Regulator Controllers
U
DESCRIPTIO
The LTC®1147 series are step-down switching regulator
controllers featuring automatic Burst ModeTM operation to
maintain high efficiencies at low output currents. These
devices drive an external P-channel power MOSFET at
switching frequencies exceeding 400kHz using a constant
off-time current mode architecture providing constant
ripple current in the inductor.
The operating current level is user-programmable via an
external current sense resistor. Wide input supply range
allows operation from 3.5V* to 14V (16V maximum).
Constant off-time architecture provides low dropout regulation limited by only the R
and resistance of the inductor and current sense resistor.
of the external MOSFET
DS(ON)
U
APPLICATIOS
■
Notebook and Palmtop Computers
■
Portable Instruments
■
Battery-Operated Digital Devices
■
Cellular Telephones
■
DC Power Distribution Systems
■
GPS Systems
A
PPLICATITYPICAL
V
(5.2V TO 14V)
IN
+
1µF
0V = NORMAL
>1.5V = SHUTDOWN
RC
1k
CC
3300pF
CT
470pF
Figure 1. High Efficiency Step-Down Converter
SHDN
I
TH
C
T
V
IN
PDRIVE
LTC1147-5
SENSE
SENSE
GND
+
–
O
U
P-CHANNEL
Si4431DY
1000pF
D1
MBRD330
The LTC1147 series incorporates automatic power saving
Burst Mode operation to reduce switching losses when
load currents drop below the level required for continuous
operation. Standby power is reduced to only 2mW at
VIN = 10V (at I
operation are typically 0mA to 300mA.
For applications where even higher efficiency is required,
refer to the LTC1148 data sheet and Application Note 54.
Burst Mode is a trademark of Linear Technology Corporation.
*LTC1147L and LTC1147L-3.3 only.
+
CIN
100µF
L*
R
**
50µH
*
COILTRONICS CTX50-2-MP
**
KRL SL-1-C1-0R050J
SENSE
0.05Ω
+
= 0). Load currents in Burst Mode
OUT
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTC1147-5 Efficiency
100
95
VIN = 6V
V
OUT
5V/2A
C
OUT
390µF
LT1147 • F01
90
85
EFFICIENCY (%)
80
75
70
0.001
VIN = 10V
0.010.11
LOAD CURRENT (A)
LT1147 • TA01
1
LTC1147-3.3
LTC1147-5/LTC1147L
WW
W
U
ABSOLUTE AXIU RATIGS
Input Supply Voltage (Pin 1)..................... 16V to –0.3V
Continuous Output Current (Pin 8)...................... 50mA
Sense Voltages (Pins 4, 5)
VIN ≥ 12.7V ...........................................13V to –0.3V
VIN < 12.7V............................... (VIN + 0.3V) to –0.3V
UUW
PACKAGE/ORDER IFORA TIO
TOP VIEW
V
1
IN
C
2
T
I
3
TH
–
SENSE
4
N8 PACKAGE
8-LEAD PLASTIC DIP
* ADJUSTABLE OUTPUT VERSION
T
= 125°C, θ
JMAX
= 125°C, θ
T
JMAX
8-LEAD PLASTIC SO
= 110°C/W (N)
JA
= 150°C/W (S)
JA
PDRIVE
8
GND
7
SHDN
6
(V
FB
SENSE
5
S8 PACKAGE
LTC1147CN8-3.3
LTC1147CN8-5
*)
+
LTC1147CS8-3.3
LTC1147CS8-5
LTC1147IS8-3.3
Operating Ambient Temperature Range
LTC1147C................................................0°C to 70°C
LTC1147I.............................................–40°C to 85°C
Extended Commercial
Temperature Range (Note 4) ................. –40°C to 85°C
Junction Temperature (Note 1)............................ 125°C
Storage Temperature Range................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART NUMBERS8 PART MARKING
LTC1147LCS8
LTC1147LCS8-3.3
LTC1147LIS8
11473
11475
1147L
1147L3
1147LI
1147I3
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
V
I
V
∆V
I
6
6
OUT
OUT
Q
Feedback Voltage (LTC1147L)VIN = 9V●1.211.251.29V
Feedback Current (LTC1147L)●0.21µA
Regulated Output VoltageVIN = 9V
LTC1147-3.3, LTC1147L-3.3I
LTC1147-5I
Output Voltage Line RegulationVIN = 7V to 12V, I
Output Voltage Load Regulation
LTC1147-3.3, LTC1147L-3.35mA < I
LTC1147-55mA < I
Burst Mode Output RippleI
Input DC Supply Current (Note 2)(Note 5)
LTC1147 Series
Normal Mode4V < VIN < 12V1.62.1mA
Sleep Mode4V < V
Sleep Mode (LTC1147-5)5V < V
ShutdownV
LTC1147L Series
Normal Mode3.5V < VIN < 12V1.62.1mA
Sleep Mode3.5V < V
Shutdown (LTC1147L-3.3)V
TA = 25°C, VIN = 10V, V
= 700mA●3.233.333.43V
LOAD
= 700mA●4.905.055.20V
LOAD
= 50mA–40040mV
LOAD
< 2A●4065mV
LOAD
< 2A●60100mV
LOAD
= 0A50mV
LOAD
< 12V160230µA
IN
< 12V160230µA
IN
= 2.1V, 4V < VIN < 12V1020µA
SHDN
< 12V160230µA
IN
= 2.1V, 3.5V < VIN < 12V1020µA
SHDN
= 0V, unless otherwise noted.
SHDN
P-P
2
LTC1147-3.3
LTC1147-5/LTC1147L
ELECTRICAL CHARACTERISTICS
TA = 25°C, VIN = 10V, V
= 0V, unless otherwise noted.
SHDN
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
V5 – V
V
6
Current Sense Threshold Voltage (Note 6)
4
LTC1147-3.3, LTC1147L-3.3V
LTC1147–5V
LTC1147LV
SHDN Pin Threshold
SENSE
V
SENSE
SENSE
V
SENSE
SENSE
V
SENSE
–
= V
+ 100mV (Forced)25mV
OUT
–
= V
– 100mV (Forced)130150170mV
OUT
–
= V
+ 100mV (Forced)25mV
OUT
–
= V
– 100mV (Forced)130150170mV
OUT
–
= 5V, V6 = V
–
= 5V, V6 = V
/4 + 25mV (Forced)25mV
OUT
/4 – 25mV (Forced)130150170mV
OUT
LTC1147-3.3/LTC1147-5/LTC1147L-3.30.50.82V
I
6
I
2
t
OFF
tr, t
f
SHDN Pin Input Current
LTC1147-3.3/LTC1147-5/LTC1147L-3.30V < V
CT Pin Discharge CurrentV
The ● denotes specifications which apply over the full specified
temperature range.
Note 1: T
dissipation P
LTC1147CN8-3.3/LTC1147CN8-5: T
LTC1147LIS/LTC1147IS8/LTC1147LCS/
LTC1147CS8-3.3/LTC1147CS8-5: T
Note 2: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Feedback Voltage (LTC1147L)VIN = 9V●1.201.251.30V
Regulated Output VoltageVIN = 9V
LTC1147-3.3/LTC1147L-3.3I
LTC1147-5I
= 700mA●3.173.333.43V
LOAD
= 700mA●4.855.055.20V
LOAD
Input DC Supply Current (Note 2)(Note 5)
LTC1147 Series
Normal Mode4V < V
Sleep Mode4V < V
Sleep Mode (LTC1147-5)5V < V
ShutdownV
< 12V1.62.4mA
IN
< 12V160260µA
IN
< 12V160260µA
IN
= 2.1V, 4V < VIN < 12V1022µA
SHDN
LTC1147L Series
Normal Mode3.5V < VIN < 12V1.62.4mA
Sleep Mode3.5V < V
Shutdown (LTC1147L-3.3)V
Current Sense Threshold Voltage (Note 6)
4
LTC1147-3.3V
LTC1147-5V
LTC1147LV
V
V
V
< 12V160260µA
IN
= 2.1V, 3.5V < VIN < 12V1022µA
SHDN
–
= V
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
+ 100mV (Forced)25mV
OUT
–
= V
– 100mV (Forced)●125150185mV
OUT
–
= V
+ 100mV (Forced)25mV
OUT
–
= V
– 100mV (Forced)●125150185mV
OUT
–
= 5V, 6V = V
–
= 5V, 6V = V
/4 + 25mV (Forced)25mV
OUT
/4 – 25mV (Forced)125150185mV
OUT
SHDN Pin Threshold
LTC1147-3.3/LTC1147-5/LTC1147L-3.30V < V
Off-Time (Note 3)CT = 390pF, I
< 8V, VIN = 16V0.50.82V
SHDN
= 700mA3.856.5µs
LOAD
Note 3: In applications where R
is placed at ground potential, the off-
SENSE
time increases approximately 40%.
is calculated from the ambient temperature TA and power
J
according to the following formulas:
D
= TA + (PD)(110°C/W)
J
Note 4: The LTC1147C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet these
extended temperature limits, but is not tested at –40°C and 85°C. The
LTC1147I is guaranteed to meet the extended temperature limits.
= TA + (PD)(150°C/W)
J
Note 5: The LTC1147L/LTC1147L-3.3 allow operation to V
Note 6: The LTC1147L is tested with external feedback resistors resulting
in a nominal output voltage of 2.5V.
= 3.5V.
IN
3
LTC1147-3.3
LOAD CURRENT (A)
0
–100
∆V
OUT
(mV)
–80
–60
–40
–20
0
20
0.51.01.52.0
LTC1147 • G03
2.5
FIGURE 1 CIRCUIT
R
SENSE
= 0.05Ω
VIN = 6V
VIN = 12V
TEMPERATURE (°C)
0
0
SENSE VOLTAGE (mV)
25
50
75
175
125
20
40
150
100
60
80
100
MAXIMUM
THRESHOLD
MINIMUM
THRESHOLD
LTC1147 • G09
LTC1147-5/LTC1147L
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input VoltageLine RegulationLoad Regulation
100
FIGURE 1 CIRCUIT
98
96
94
92
90
88
EFFICIENCY (%)
86
84
82
80
0
I
LOAD
4
8
INPUT VOLTAGE (V)
I
LOAD
= 100mA
12
= 1A
16
LTC1147 • G01
(mV)
OUT
∆V
–10
–20
–30
–40
40
30
20
10
0
0
FIGURE 1 CIRCUIT
= 1A
I
LOAD
4
INPUT VOLTAGE (V)
812
LTC1147 • G02
16
2.1
1.8
1.5
1.2
0.9
0.6
SUPPLY CURRENT (mA)
0.3
0
14
12
10
8
6
GATE CHARGE CURRENT (mA)
0
DC Supply CurrentSupply Current in Shutdown
NOT INCLUDING
GATE CHARGE CURRENT
ACTIVE MODE
SLEEP MODE
26
0
8 10 12 14 16 18
4
INPUT VOLTAGE (V)
Gate Charge Supply Current
QP = 50nC
4
2
20
OPERATING FREQUENCY (kHz)
80
QP = 29nC
140
200
LTC1147 • G04
260
LTC1147 • G07
20
V
18
(NOT AVAILABLE ON LTC1147L)
16
14
12
10
8
6
SUPPLY CURRENT (µA)
4
2
0
0
= 2V
SHUTDOWN
26
4
INPUT VOLTAGE (V)
Off-Time vs V
80
70
60
50
40
30
OFF-TIME (µs)
20
10
LTC1147-3.3
0
0
1
OUTPUT VOLTAGE (V)
1018
12
8
OUT
V
SENSE
LTC1147-5
23
14
16
LTC1147 • G05
–
= V
4
LTC1147 • G08
OUT
Operating Frequency
vs (VIN – V
1.6
V
= 5V
OUT
1.4
1.2
1.0
0.8
0.6
0.4
NORMALIZED FREQUENCY
0.2
0
0
2
OUT
4
(VIN – V
)
6
) VOLTAGE (V)
OUT
0°C
25°C
8
70°C
1012
LTC1148 • G06
Current Sense Threshold Voltage
5
4
UUU
PI FUCTIOS
V
(Pin 1): Main Supply Pin. Must be closely decoupled
IN
to ground Pin 7.
CT (Pin 2): External capacitor CT from Pin 2 to ground sets
the operating frequency. The actual frequency is also
dependent upon the input voltage.
ITH (Pin 3): Gain Amplifier Decoupling Point. The current
comparator threshold increases with the Pin 3 voltage.
SENSE– (Pin 4): Connects to internal resistive divider
which sets the output voltage. Pin 4 is also the (–) input for
the current comparator.
SENSE+ (Pin 5): The (+) input to the current comparator.
A built-in offset between Pins 4 and 5 in conjunction with
R
sets the current trip threshold.
SENSE
LTC1147-3.3
LTC1147-5/LTC1147L
SHDN/VFB (Pin 6): When grounded, the fixed output
versions of the LTC1147 family operate normally. Pulling
Pin 6 high holds the P-channel MOSFET off and puts the
LTC1147 in micropower shutdown mode. Requires CMOS
logic signal with tr, tf < 1µ s. Do not leave this pin floating.
On the LTC1147L this pin serves as the feedback pin from
an external resistive divider used to set the output voltage.
GND (Pin 7): Two independent ground lines must be
routed separately to: 1) the (–) terminal of C
cathode of the Schottky diode and (–) terminal of CIN.
PDRIVE (Pin 8): High current drive for the P-channel
MOSFET. Voltage swing at this pin is from VIN to ground.
, and 2) the
OUT
UUW
FU CTIO AL DIAGRA
SLEEP
Q
+
S
–
V
V
TH2
2
C
T
TH1
–
+
Pin 6 Connection Shown For LTC1147-3.3 and LTC1147-5; Changes Create LTC1147L.
1
8
7
V
IN
PDRIVE
GND
+
SENSE
5
V
FB
6
–
V
+
SENSE
4
–
–
R
S
T
OFF-TIME
CONTROL
V
IN
SENSE
–
C
I
TH
25mV TO 150mV
+
–
3
+
13k
SHDN
V
–
G
+
6
REFERENCE
OS
1.25V
100k
LTC1147 • FD
5pF
5
LTC1147-3.3
LTC1147-5/LTC1147L
U
OPERATIO
(Refer to Functional Diagram)
The LTC1147 series uses a current mode, constant offtime architecture to switch an external P-channel power
MOSFET. Operating frequency is set by an external capacitor at CT (Pin 2).
The output voltage is sensed by an internal voltage divider
connected to SENSE– (Pin 4). A voltage comparator V, and
a gain block G, compare the divided output voltage with a
reference voltage of 1.25V. To optimize efficiency, the
LTC1147 series automatically switchs between two modes
of operation, burst and continuous. The voltage comparator is the primary control element when the device is in
Burst Mode operation, while the gain block controls the
output voltage in continuous mode.
During the switch “on” cycle in continuous mode, current
comparator C monitors the voltage between Pins 4 and 5
connected across an external shunt in series with the
inductor. When the voltage across the shunt reaches its
threshold value, the PDRIVE output is switched to VIN,
turning off the P-channel MOSFET. The timing capacitor
connected to Pin 2 is now allowed to discharge at a rate
determined by the off-time controller. The discharge current is made proportional to the output voltage (measured
by Pin 4) to model the inductor current, which decays at
a rate which is also proportional to the output voltage.
When the voltage on the timing capacitor has discharged
past V
causes the PDRIVE output to go low turning the P-channel
MOSFET back on. The cycle then repeats.
As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage
, comparator T trips, setting the flip-flop. This
TH1
(Pin 3) to increase the current comparator threshold, thus
tracking the load current.
The sequence of events for Burst Mode operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel MOSFET is held off by comparator V and the timing capacitor
continues to discharge below V
capacitor discharges past V
trips, causing the internal sleep line to go low.
The circuit now enters sleep mode with the power MOSFET turned off. In sleep mode, a majority of the circuitry is
turned off, dropping the quiescent current from 1.6mA to
160µ A. The load current is now being supplied from the
output capacitor. When the output voltage has dropped by
the amount of hysteresis in comparator V, the P-channel
MOSFET is again turned on and this process repeats.
To avoid the operation of the current loop interfering with
Burst Mode operation, a built-in offset VOS is incorporated
in the gain stage. This prevents the current comparator
threshold from increasing until the output voltage has
dropped below a minimum threshold.
Using constant off-time architecture, the operating frequency is a function of the input voltage. To minimize the
frequency variation as dropout is approached, the off-time
controller increases the discharge current as VIN drops
below V
turned on continuously (100% duty cycle), providing low
dropout operation with V
+ 1.5V. In dropout the P-channel MOSFET is
OUT
OUT
TH2
≈ VIN.
. When the timing
TH1
, voltage comparator S
U
WUU
APPLICATIOS IFORA TIO
LTC1147L Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1147L adjustable version is used with an external
resistive divider from V
The regulated voltage is determined by:
V
OUT
= 1.25
1 +
)
to VFB (Pin 6) (see Figure 7).
OUT
R2
)
R1
6
To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1147L.
For Figure 1 applications with V
R
inputs operate near ground. When the current comparator
is operated at less than 2V common mode, the off-time
increases approximately 40%, requiring the use of a
smaller timing capacitor CT.
is moved to ground, the current sense comparator
SENSE
below 2V, or when
OUT
LTC1147-3.3
I
BURST
≈
15mV
R
SENSE
I
SC(PK)
=
150mV
R
SENSE
LTC1147-5/LTC1147L
U
WUU
APPLICATIOS IFORA TIO
The basic LTC1147 application circuit is shown in Figure
1. External component selection is driven by the load
requirement and begins with the selection of R
R
is known, CT and L can be chosen. Next, the power
SENSE
MOSFET and D1 are selected. Finally, CIN and C
selected and the loop is compensated. The circuit shown
in Figure 1 can be configured for operation up to an input
voltage of 16V. If the application requires higher input
voltage, then the synchronous switched LTC1149 should
be used. Consult factory for lower minimum input voltage
version.
R
R
Selection for Output Current
SENSE
is chosen based on the required output current.
SENSE
The LTC1147 series current comparator has a threshold range which extends from a minimum of 25mV/
R
to a maximum of 150mV/R
SENSE
. The current
SENSE
comparator threshold sets the peak of the inductor
ripple current, yielding a maximum output current I
equal to the peak value less half the peak-to-peak ripple
current.
For proper Burst Mode operation, I
must be less than or equal to the minimum current
comparator threshold.
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
I
RIPPLE(P-P)
Operating Frequency). Solving for R
= 25mV/R
(see CT and L Selection for
SENSE
and allowing
SENSE
a margin for variations in the LTC1147 series and
external component values yields:
R
SENSE
A graph for selecting R
100mV
=
I
MAX
versus maximum output
SENSE
current is given in Figure 2.
The load current below in which Burst Mode operation
commences, I
I
I
, both track I
SC(PK)
and I
BURST
SC(PK)
and the peak short-circuit current
BURST
. Once R
MAX
has been chosen,
SENSE
can be predicted from the following:
. Once
SENSE
are
OUT
MAX
RIPPLE(P-P)
0.20
0.15
(Ω)
0.10
SENSE
R
0.05
0
The LTC1147 series automatically extend t
1
0
MAXIMUM OUTPUT CURRENT (A)
Figure 2. Selecting R
2
3
4
5
LTC1147 • F02
SENSE
during a
OFF
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ripple current causes the average short-circuit current
I
SC(AVG)
to be reduced to approximately I
MAX
.
L and CT Selection for Operating Frequency
The LTC1147 series use a constant off-time architecture
with t
determined by an external timing capacitor CT.
OFF
Each time the P-channel MOSFET switch turns on, the
voltage on CT is reset to approximately 3.3V. During the
off-time, CT is discharged by a current which is proportional to V
. The voltage on CT is analogous to the
OUT
current in inductor L, which likewise decays at a rate
proportional to V
. Thus the inductor value must track
OUT
the timing capacitor value.
The value of CT is calculated from the desired continuous
mode operating frequency:
CT =
1
(1.3)(10
4
)(f)
VIN – V
)
V
+ V
IN
OUT
D
)
Where VD is the drop across the Schottky diode.
A graph for selecting CT versus frequency including the
effects of input voltage is given in Figure 3.
As the operating frequency is increased the gate charge
losses will reduce efficiency (see Efficiency Considerations). The complete expression for operating frequency
7
LTC1147-3.3
LTC1147-5/LTC1147L
U
WUU
APPLICATIOS IFORATIO
1000
CAPACITANCE (pF)
is given by:
1
f ≈
t
OFF
where:
t
= (1.3)(104)(CT)
OFF
800
600
400
200
VIN = 7V
0
0
Figure 3. Timing Capacitor Value
1 –
)
V
OUT
V
IN
100
FREQUENCY (kHz)
)
V
)
V
V
SENSE
VIN = 12V
REG
OUT
)
–
200
= V
OUT
VIN = 10V
= 5V
300
LTC1147 • F03
series will delay entering Burst Mode operation and efficiency will be degraded at low currents.
Inductor Core Selection
Once the minimum value for L is known, the type of
inductor must be selected. Highest efficiency will be
obtained using ferrite, Kool Mµ® (from Magnetics, Inc.) or
molypermalloy (MPP) cores. Lower cost powdered iron
cores provide suitable performance but cut efficiency by
3% to 5%. Actual core loss is independent of core size for
a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss, so design goals
can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means
that inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple which can cause Burst Mode operation to be
falsely triggered in the LTC1147. Do not allow the core
to saturate!
V
is the desired output voltage (i.e., 5V, 3.3V). V
REG
the measured output voltage. Thus V
REG/VOUT
is
OUT
= 1 in
regulation.
Note that as VIN decreases, the frequency decreases.
When the input to output voltage differential drops
below 1.5V, the LTC1147 reduces t
by increasing the
OFF
discharge current in CT. This prevents audible operation prior to dropout.
Once the frequency has been set by CT, the inductor L
must be chosen to provide no more than 25mV/R
SENSE
of peak-to-peak inductor ripple current. This results in
a minimum required inductor value of:
L
= (5.1)(105)(R
MIN
SENSE
)(CT)(V
REG
)
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor
are eased at the expense of efficiency. If too small an
inductor is used, the inductor current will become
discontinuous before the LTC1147 series enters Burst
Mode operation.
A consequence of this is that the LTC1147
Kool Mµ is a very good, low loss core material for toroids
with a “soft” saturation characteristic. Molypermalloy is
slightly more efficient at high (>200kHz) switching frequencies but quite a bit more expensive. Toroids are very
space efficient, especially when you can use several
layers of wire. Because they generally lack a bobbin,
mounting is more difficult. However, new designs for
surface mount are available from Coiltronics, Sumida and
Beckman Industrial Corp. which do not increase the
height significantly.
Power MOSFET Selection
An external P-channel power MOSFET must be selected
for use with the LTC1147 series. The main selection
criteria for the power MOSFET are the threshold voltage
V
and “on” resistance R
GS(TH)
DS(ON)
.
The minimum input voltage determines whether a standard threshold or logic-level threshold MOSFET must be
Kool Mµ is a registered trademark of Magnetics, Inc.
8
LTC1147-3.3
CIN Required I
RMS
≈ I
MAX
[V
OUT(VIN – VOUT
)]
1/2
V
IN
LTC1147-5/LTC1147L
U
WUU
APPLICATIOS IFORA TIO
used. For VIN > 8V, a standard threshold MOSFET (V
< 4V) may be used. If VIN is expected to drop below 8V,
a logic-level threshold MOSFET (V
GS(TH)
strongly recommended. When a logic-level MOSFET is
used, the LTC1147 supply voltage must be less than the
absolute maximum VGS ratings for the MOSFET.
The maximum output current I
determines the R
MAX
requirement for the power MOSFET. When the LTC1147
series is operating in continuous mode, the simplifying
assumption can be made that either the MOSFET or
Schottky diode is always conducting the average load
current. The duty cycles for the MOSFET and diode are
given by:
V
P-Ch Duty Cycle =
Schottky Diode Duty Cycle =
From the duty cycle the required R
OUT
V
IN
(V
IN
DS(ON)
– V
OUT
V
IN
for the MOSFET
can be derived:
)(PP)
(V
P-Ch R
DS(ON)
=
(V
OUT
)(I
IN
MAX
2
)(1 + δP)
GS(TH)
< 2.5V) is
DS(ON)
+ VD)
(V
IN
– V
OUT
V
IN
+ VD)
(I
LOAD
)ID1 =
Remember to keep lead lengths short and observe proper
grounding (see Board Layout Checklist) to avoid ringing
and increased dissipation.
The forward voltage drop allowable in the diode is calculated from the maximum short-circuit current as:
P
VF ≈
D
I
SC(PK)
where PD is the allowable power dissipation and will be
determined by efficiency and/or thermal requirements
(see Efficiency Considerations).
CIN and C
Selection
OUT
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle V
OUT/VIN
. To
prevent large voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The
maximum RMS capacitor current is given by:
where PP is the allowable power dissipation and δP is the
temperature dependency of R
. PP will be deter-
DS(ON)
mined by efficiency and/or thermal requirements (see
Efficiency Considerations). (1 + δ) is generally given for a
MOSFET in the form of a normalized R
DS(ON)
vs temperature curve, but δ = 0.007/°C can be used as an approximation for low voltage MOSFETs.
Output Diode Selection (D1)
The Schottky diode D1 shown in Figure 1 only conducts
during the off-time. It is important to adequately specify
the diode peak current and average power dissipation so
as not to exceed the diode ratings.
The most stressful condition for the output diode is under
short circuit (V
must safely handle I
= 0V). Under this condition the diode
OUT
at close to 100% duty cycle.
SC(PK)
Under normal load conditions the average current conducted by the diode is:
This formula has a maximum at VIN = 2V
I
= I
RMS
/2. This simple worst-case condition is com-
OUT
OUT
, where
monly used for design because even significant deviations do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
only 2000 hours of life. This makes it advisable to further
derate the capacitor, or to choose a capacitor rated at a
higher temperature than required. Several capacitors
may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if
there is any question. An additional 0.1µ F to 1µ F ceramic
decoupling capacitor is also required on VIN (Pin 1) for
high frequency decoupling.
The selection of C
series resistance (ESR).
than twice the value of R
is driven by the required effective
OUT
The ESR of C
for proper operation of the
SENSE
must be less
OUT
LTC1147:
C
Required ESR < 2R
OUT
SENSE
9
LTC1147-3.3
LTC1147-5/LTC1147L
U
WUU
APPLICATIOS IFORATIO
Optimum efficiency is obtained by making the ESR equal
to R
efficiency degrades by less than 1%. If the ESR is greater
than 2R
will prematurely trigger Burst Mode operation, resulting in
disruption of continuous mode and an efficiency hit which
can be several percent.
Manufacturers such as Nichicon and United Chemicon
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR/size ratio of any aluminum
electrolytic at a somewhat higher price. Once the ESR
requirement for C
rating generally far exceeds the I
In surface mount applications multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice
is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. For
example, if 200µF/10V is called for in an application
requiring 3mm height, two AVX 100µF/10V (P/N TPSD
107K010) could be used. Consult the manufacturer for
other specific recommendations.
At low supply voltages, a minimum capacitance at C
needed to prevent an abnormal low frequency operating
. As the ESR is increased up to 2R
SENSE
, the voltage ripple on the output capacitor
SENSE
has been met, the RMS current
OUT
RIPPLE(P-P)
1000
800
L = 50µH
R
SENSE
= 0.02Ω
, the
SENSE
requirement.
is
OUT
mode (see Figure 4). When C
is made too small, the
OUT
output ripple at low frequencies will be large enough to trip
the voltage comparator. This causes Burst Mode operation to be activated when the LTC1147 series would
normally be in continuous operation. The effect is most
pronounced with low values of R
and can be im-
SENSE
proved by operating at higher frequencies with lower
values of L. The output remains in regulation at all times.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ∆I
tive series resistance of C
charge or discharge C
(ESR), where ESR is the effec-
LOAD
. ∆I
OUT
until the regulator loop adapts
OUT
LOAD
to the current change and returns V
state value. During this recovery time V
shifts by an
OUT
also begins to
to its steady
OUT
can be
OUT
monitored for overshoot or ringing which would indicate a stability problem. The external components shown
in the Figure 1 circuit will prove adequate compensation
for most applications.
A second, more severe transient is caused by switching
in loads with large (>1µ F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel with C
, causing a rapid drop in V
OUT
. No regulator
OUT
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive so
that the load rise time is limited to approximately
(25)C
. Thus a 10µ F capacitor would require a 250µ s
LOAD
rise time, limiting the charging current to about 200mA.
10
1
(VIN – V
L = 25µH
R
SENSE
R
SENSE
2
) VOLTAGE (V)
OUT
= 0.02Ω
L = 50µH
= 0.05Ω
600
(µF)
OUT
C
400
200
0
0
Figure 4. Minimum Value of C
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
3
4
5
LTC1147 • F04
OUT
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
LTC1147-3.3
LTC1147-5/LTC1147L
U
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APPLICATIOS IFORA TIO
where L1, L2, etc., are the individual losses as a percentage of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power.)
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1147 circuits: 1) LTC1147 DC bias current,
2) MOSFET gate charge current, 3) I2R losses, and 4)
voltage drop of the Schottky diode.
1. The DC supply current is the current which flows into
VIN (Pin 1) less the gate charge current. For VIN = 10V
the LTC1147 series DC supply current is 160µ A for no
load, and increases proportionally with load up to a
constant 1.6mA after the LTC1147 series has entered
continuous mode. Because the DC bias current is
drawn from VIN, the resulting loss increases with
input voltage. For VIN = 10V the DC bias losses are
generally less than 1% for load currents over 30mA.
However, at very low load currents the DC bias current
accounts for nearly all of the loss.
2. MOSFET gate charge current results from switching
the gate capacitance of the power MOSFET. Each time
a MOSFET gate is switched from low to high to low
again, a packet of charge dQ moves from VIN to
ground. The resulting dQ/dt is a current out of V
which is typically much larger than the DC supply
current. In continuous mode, I
GATECHG
= f(QP). The
typical gate charge for a 0.135Ω P-channel power
MOSFET is 40nC. This results in I
GATECHG
= 4mA in
100kHz continuous operation for a 2% to 3% typical
midcurrent loss with VIN = 10V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it argues against using a larger MOSFET than necessary to
control I2R losses, since overkill can cost efficiency as
well as money!
IN
P-channel and Schottky diode. The MOSFET R
DS(ON)
multiplied by the P-channel duty cycle can be summed
with the resistances of L and R
losses. For example, if R
and R
at VIN ≈ 2V
= 0.05Ω, then the total
SENSE
. This results in losses ranging from 3%
OUT
= 0.1Ω, RL = 0.15Ω,
DS(ON)
to obtain I2R
SENSE
resistance is 0.3Ω
to 10% as the output current increases from 0.5A to
2A. I2R losses cause the efficiency to roll off at high
output currents.
4. The Schottky diode is a major source of power loss at
high currents and gets worse at high input voltages.
The diode loss is calculated by multiplying the forward
voltage drop times the Schottky diode duty cycle
multiplied by the load current. For example, assuming
a duty cycle of 50% with a Schottky diode forward
voltage drop of 0.4V, the loss increases from 0.5% to
8% as the load current increases from 0.5A to 2A.
Figure 5 shows how the efficiency losses in a typical
LTC1147 series regulator end up being apportioned.
The gate charge loss is responsible for the majority of
the efficiency lost in the midcurrent region. If Burst
Mode operation was not employed at low currents,
the gate charge loss alone would cause efficiency to
drop to unacceptable levels. With Burst Mode operation, the DC supply current represents the lone (and
unavoidable) loss component which continues to
become a higher percentage as output current is
reduced. As expected, the I2R losses and Schottky
diode loss dominate at high load currents.
100
GATE CHARGE
95
LTC1147 I
Q
90
EFFICIENCY/LOSS (%)
85
SCHOTTKY
I2R
DIODE
3. I2R losses are easily predicted from the DC resistances of the MOSFET, inductor and current shunt. In
continuous mode the average output current flows
through L and R
, but is “chopped” between the
SENSE
80
0.03
0.01
Figure 5. Efficiency Loss
0.1
OUTPUT CURRENT (A)
0.3
1
LTC1147 • F05
3
11
LTC1147-3.3
PD = I
SC(AVG)(VD
)
3.3V
0V
LTC1147 • F06
3.3V
0V
LTC1147-5/LTC1147L
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APPLICATIOS IFORATIO
Other losses including CIN and C
losses, MOSFET switching losses, and inductor core losses,
generally account for less than 2% total additional loss.
Design Example
As a design example, assume VIN = 5V (nominal), V
3.3V, I
= 1A, and f = 130kHz; R
MAX
immediately be calculated:
R
t
= 100mV/1A = 0.1Ω
SENSE
= (1/130kHz)[1 – (3.3/5)] = 2.61µs
OFF
CT = 2.61µs/(1.3)(104) = 220pF
L = (5.1)(105)(0.1Ω)(220pF)(3.3V) = 33µH
Assume that the MOSFET dissipation is to be limited to
PP = 250mW.
If TA = 50°C and the thermal resistance of the MOSFET is
50°C/W, then the junction temperatures will be 63°C and
δP = 0.007(63 – 25) = 0.27. The required R
MOSFET can now be calculated:
P-Ch R
DS(ON)
=
5(0.25)
3.3(1)
2
(1.27)
The P-channel requirement can be met by a Si9430DY.
Note that the most stringent requirement for the Schottky
diode is with V
= 0 (i.e., short circuit). During a
OUT
continuous short circuit, the worst-case Schottky diode
dissipation rises to:
ESR dissipative
OUT
, CT and L can
SENSE
DS(ON)
= 0.3Ω
=
OUT
for the
f
=
MIN
2.61µs
3.3(0.125Ω)(1A)
PP =
1
1 –
)
4.5
3.3
4.5
2
= 102kHz
)
(1.27)
= 116mW
This last step is necessary to assure that the power
dissipation and junction temperature of the P-channel are
not exceeded.
Troubleshooting Hints
Since efficiency is critical to LTC1147 series applications,
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor Pin 2.
In continuous mode (I
pin should be a sawtooth with a 0.9V
LOAD
> I
) the voltage on the C
BURST
P-P
T
swing. This
voltage should never dip below 2V as shown in Figure 6a.
When load currents are low (I
LOAD
< I
) Burst Mode
BURST
operation occurs. The voltage on the CT pin now falls to
ground for periods of time as shown in Figure 6b. During
this time the LTC1147 series are in sleep mode with the
quiescent current reduced to 160µA.
The inductor current should also be monitored. Look to
verify that the peak-to-peak ripple current in continuous
mode operation is approximately the same as in Burst
Mode operation.
With the 0.1Ω sense resistor I
SC(AVG)
= 1A will result,
increasing the 0.4V Schottky diode dissipation to 0.4W.
CIN will require an RMS current rating of at least 0.5A at
temperature, and C
will require an ESR of 0.1Ω for
OUT
optimum efficiency.
Now allow VIN to drop to its minimum value. At lower input
voltages the operating frequency will decrease and the
P-channel will be conducting most of the time, causing the
power dissipation to increase. At V
IN(MIN)
= 4.5V, the
frequency will decrease and the P-channel will be conducting most of the time causing its power dissipation to
increase. At V
12
IN(MIN)
= 4.5V:
Figure 6a. Continuous Mode Operation CT Waveform
Figure 6b. Burst Mode Operation CT Waveform
If Pin 2 is observed falling to ground at high output
currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist.
LTC1147-3.3
LTC1147-5/LTC1147L
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APPLICATIOS IFORA TIO
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1147 series. These items are also illustrated graphically in the layout diagram of Figure 7. Check the following
in your layout:
1. Are the signal and power grounds segregated? The
LTC1147 ground (Pin 7) must return separately to a)
the power and b) signal grounds.
(a) returns to the source anode of the Schottky diode
and (–) plate of CIN, which should have lead lengths
as short as possible. The signal ground (b) connects
to the (–) plate of C
OUT
.
2. Does the LTC1147 SENSE– (Pin 4) connect to a point
close to R
+
V
IN
–
and the (+) plate of C
SENSE
BOLD LINES INDICATE HIGH CURRENT PATHS
The power ground
?
OUT
P-CHLR
+
C
IN
1µF
+
3. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The 1000pF capacitor
between Pins 4 and 5 should be as close as possible to
the LTC1147.
4. Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? This capacitor provides the AC current to the P-channel MOSFET.
5. Is the input decoupling capacitor (0.1µF/1µF) con-
nected closely between VIN (Pin 1) and ground (Pin 7)?
This capacitor carries the MOSFET driver peak currents.
6. On fixed output versions, is the SHDN (Pin 6) actively
pulled to ground during normal operation? The SHDN
pin is high impedance and must not be allowed to float.
SENSE
D1
+
C
OUT
+
V
OUT
–
390pF
3300pF
1k
LTC1147-3.3
LTC1147-5
(LTC1147L)
1
VIN
2
C
T
3
I
TH
4
SENSE
PDRIVE
–
SENSE
GND
SHDN
(V
FB
1000pF
8
7
6
)
5
+
100pF
SHUTDOWN
R1
R2
Figure 7. LTC1147 Layout Diagram (See Board Layout Checklist)
For additional High Efficiency application circuits see Application Note 54.
OUTPUT DIVIDER
REQUIRED WITH
ADJUSTABLE
VERSION ONLY
LTC1147 • F07
13
LTC1147-3.3
LTC1147-5/LTC1147L
U
TYPICAL APPLICATIOS
1
VIN
2
C
T
3
I
CT
120pF
CC
3300pF
R
C
1k
TH
4
SENSE
SUMIDA CDR74B-100LC
*
IRC LRC-LR2010-01-R068-F
**
3.3V Low Dropout High Efficiency Regulator
0.1µF
LTC1147L-3.3
–
PDRIVE
SENSE
GND
SHDN
0.01µF
+
8
7
6
5
SHUTDOWN
Si9433DY
L*
10µH
R
SENSE
0.068Ω
D1
MBRS130LT3
**
V
IN
3.5V TO 12V
+
CIN
47µF
16V
C
OUT
100µF
10V
+
AVX
V
OUT
3.3V/1.25A
LTC1147 • F08
CT
300pF
1
VIN
2
C
3
I
4
SENSE
SUMIDA CDR74-221
*
IRC LRC-LR2010-01-R068-F
**
R
C
1k
CC
3300pF
Precision Constant Current Source
0.1µF
T
TH
LTC1147L
–
SENSE
0.01µF
PDRIVE
GND
SHDN
(V
FB
8
7
6
)
5
+
100pF
Si3455DV
L*
220µH
R
SENSE
0.22Ω
D1
MBRS130LT3
R1
1.2k
R2
**
6.8k
10V TO 14V
+
LTC1147 • F09
V
IN
+
C
OUT
100µF
16V
AVX
V
OUT
CIN
33µF
25V
(A)
OUT
I
1.0
0.8
0.6
0.4
0.2
0
I
VIN = 12.6V
0
OUT
2
vs V
For Figure 9
OUT
6
4
V
(V)
OUT
8
10
LTC1147 F10
14
U
TYPICAL APPLICATIOS
1
VIN
2
C
T
3
I
CT
120pF
R
C
1k
CC
3300pF
TH
4
SENSE
LTC1147L
0.1µF
–
PDRIVE
GND
SHDN
(V
SENSE
0.01µF
2.5V/2A Regulator
8
7
6
)
FB
5
+
I00pF
LTC1147-3.3
LTC1147-5/LTC1147L
V
IN
3.5V TO 12V
+
CIN
C
OUT
220µF
10V × 2
AVX
15µF
25V × 2
Si9433DY
L*
10µH
R
SENSE
0.05Ω
D1
MBRD330
R1
49.9k
1%
R2
49.9k
**
1%
+
COILTRONICS CTX10-4
*
IRC LR2512-01-0R050-G
**
PACKAGE DESCRIPTIO
0.300 – 0.325
(7.620 – 8.255)
0.065
(1.651)
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
–0.015
+0.889
8.255
()
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
TYP
0.100 ± 0.010
(2.540 ± 0.254)
U
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.020
(0.508)
MIN
0.255 ± 0.015*
(6.477 ± 0.381)
2.5V/2A
LTC1147 • F11
0.400*
(10.160)
MAX
876
12
3
5
4
N8 1197
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1147-3.3
LTC1147-5/LTC1147L
U
TYPICAL APPLICATION
CT
220pF
COILTRONICS CTX20-4
*
KRL SP-1/2-A1-OR050
**
R
C
1k
CC
3300pF
PACKAGE DESCRIPTIO
0.010 – 0.020
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
× 45°
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
3.3V/2A Output High Efficiency Regulator
4V TO 14V
Si4431DY
L*
20µH
R
SENSE
0.05Ω
D1
MBRS130LT3
C
220µF
10V
+
AVX
**
LTC1147 • F12
OUT
1
2
3
4
VIN
C
T
LTC1147-3.3
I
TH
SENSE
0.1µF
–
PDRIVE
GND
SHDN
SENSE
0.01µF
+
8
7
6
5
SHUTDOWN
U
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
TYP
0.228 – 0.244
(5.791 – 6.197)
V
IN
+
CIN
22µF
25V × 2
V
OUT
3.3V/2A
0.189 – 0.197*
(4.801 – 5.004)
7
8
1
2
5
6
0.150 – 0.157**
(3.810 – 3.988)
SO8 0996
3
4
RELATED PARTS
PART NUMBERDESCRIPTIONCOMMENTS
LTC1142Dual High Efficiency Synchronous Step-Down Switching RegulatorDual Version of LTC1148
LTC1143Dual High Efficiency Step-Down Switching Regulator ControllerDual Version of LTC1147
LTC1147High Efficiency Step-Down Switching Regulator ControllerNonsynchronous, 8-Lead, VIN ≤ 16V
LTC1148High Efficiency Step-Down Switching Regulator ControllerSynchronous, VIN ≤ 20V
LTC1149High Efficiency Step-Down Switching RegulatorSynchronous, VIN ≤ 48V, for Standard Threshold FETs
LTC1159High Efficiency Step-Down Switching RegulatorSynchronous, VIN ≤ 40V for Logic Level MOSFETS
LTC1174High Efficiency Step-Down and Inverting DC/DC Converter0.5A Switch, VIN ≤ 18.5V, Comparator
LTC1265High Efficiency Step-Down DC/DC Converter1.2A Switch, VIN ≤ 13V, Comparator
LTC1267Dual High Efficiency Synchronous Step-Down Switching RegulatorsDual Version of LTC1159
LTC1435High Efficiency Low Noise Synchronous Step-Down Switching Regulator16-Pin Narrow SO/SSOP; Constant Frequency
1147fd LT/TP 0698 REV D 2K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1993
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
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