Datasheet LTC1142HV Datasheet (LINEAR TECHNOLOGY)

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Page 1

FEATURES

LTC1142/LTC1142L/LTC1142HV

Dual High Efficiency

Synchronous Step-Down

Switching Regulators

DESCRIPTIO

■

Dual Outputs: 3.3V and 5V or User Programmable

■

Ultrahigh Efficiency: Over 95% Possible

■

Current Mode Operation for Excellent Line and Load Transient Response

■

High Efficiency Maintained over 3 Decades of Output Current

■

Low Standby Current at Light Loads: 160µA/Output

■

Independent Micropower Shutdown: I

■

Wide VIN Range: 3.5V to 20V

■

Very Low Dropout Operation: 100% Duty Cycle

■

Synchronous FET Switching for High Efficiency

■

Available in Standard 28-Pin SSOP

< 40µA

APPLICATIO S

■

Notebook and Palmtop Computers

■

Battery-Operated Digital Devices

■

Portable Instruments

■

DC Power Distribution Systems

The LTC®1142/LTC1142L/LTC1142HV are dual synchronous step-down switching regulator controllers featuring automatic Burst ModeTM operation to maintain high efficiencies at low output currents. The devices are composed of two separate regulator blocks, each driving a pair of external complementary power MOSFETs, at switching frequencies up to 250kHz, using a constant off-time current mode architecture providing constant ripple current in the inductor.

The operating current level for both regulators is user programmable via an external current sense resistor. Wide input supply range allows operation from 3.5V* to 18V (20V maximum). Constant off-time architecture provides low dropout regulation limited only by the R

of the external

DS(ON)

MOSFET and resistance of the inductor and current sense resistor.

The LTC1142 series is ideal for applications requiring dual output voltages with high conversion efficiencies over a wide load current range in a small amount of board space.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a trademark of Linear Technology Corporation.

TYPICAL APPLICATIO

IN3

22µF 25V × 2

P-CH Si9430DY

OUT3

3.3V/2A

SENSE3

0.05Ω

50µH

1000pF

MBRS130L

OUT3

220µF 10V × 2

SENSE3, RSENSE5

L1, L2: COILTRONICS CTX50-2-MP PINS 5, 7, 8, 19, 21, 22: NC

NOTE: COMPONENTS OPTIMIZED FOR HIGHEST EFFICIENCY, NOT MINIMUM BOARD SPACE.

N-CH Si9410DY

: DALE WSL-2010-.05

5.2V TO 18V

0.22µF

24 16 10

IN3

PDRIVE 3

SENSE

–

SENSE

NDRIVE 3

PGND3 SGND3 C

4 3 25 27 13 11 17 18

Figure 1. High Efficiency Dual 3.3V, 5V Supply

0V = NORMAL >1.5V = SHDN

SHDN3

LTC1142HV

T3ITH3ITH5

3300pF

560pF

SHDN5

SGND5

3300pF

390pF

IN5

PDRIVE 5

SENSE

NDRIVE 5

PGND5

IN5

0.22µF

P-CH

Si9430DY

–

1000pF

N-CH

Si9410DY

22µF 25V × 2

50µH

D2 MBRS130L

1142 F01

SENSE5

0.05Ω

OUT5

5V/2A

OUT5

220µF 10V × 2

Page 2

LTC1142/LTC1142L/LTC1142HV

TOP VIEW

G PACKAGE

28-LEAD PLASTIC SSOP

SENSE

FB1

SHDN1

SGND1

PGND1

NDRIVE 1

PDRIVE 2

IN2

INTV

CC2

TH2

SENSE–2

SENSE

–

TH1

INTV

CC1

IN1

PDRIVE 1

NDRIVE 2

PGND2

SGND2

SHDN2

FB2

SENSE+2

ABSOLUTE AXI U RATI GS

(Note 1)

Input Supply Voltage (Pins 10, 24)

LTC1142, LTC1142L-ADJ ..................... 16V to – 0.3V

LTC1142HV, LTC1142HV-ADJ ............. 20V to – 0.3V

Continuous Output Current (Pins 6, 9, 20, 23) .... 50mA

Sense Voltages (Pins 1, 14, 15, 28)

VIN > 13V.............................................. 13V to – 0.3V

VIN < 13V.................................. (VIN + 0.3V) to –0.3V

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

SENSE

SHDN3

SGND3

PGND3

NDRIVE 3

PDRIVE 5

IN5

INTV

CC5

TH5

SENSE–5

G PACKAGE

28-LEAD PLASTIC SSOP

= 125°C, θJA = 95°C/W T

JMAX

SENSE

TH3

INTV

CC3

IN3

PDRIVE 3

NDRIVE 5

PGND5

SGND5

SHDN5

SENSE

–

Consult factory for Industrial and Military grade parts.

ORDER PART

NUMBER

LTC1142CG LTC1142HVCG

Operating Ambient Temperature Range ...... 0°C to 70°C

Extended Commercial

Temperature Range ........................... –40°C to 85°C

Junction Temperature (Note 2)............................ 125°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

ORDER PART

NUMBER

LTC1142HVCG-ADJ LTC1142LCG-ADJ

= 125°C, θJA = 95°C/W

JMAX

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. V

= V

= 10V, V

= 0V unless otherwise noted.

SHDN

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V2, V

I2, I

OUT

∆V

OUT

I10, I

Feedback Voltage LTC1142HV-ADJ, LTC1142L-ADJ : V10, V24 = 9V ● 1.21 1.25 1.29 V

Feedback Current LTC1142HV-ADJ, LTC1142L-ADJ ● 0.2 1 µA

Regulated Output Voltage LTC1142, LTC1142HV

3.3V Output I 5V Output I

Output Voltage Line Regulation V

Output Voltage Load Regulation Figure 1 Circuit

3.3V Output 5mA < I 5V Output 5mA < I

Output Ripple (Burst Mode) I

Input DC Supply Current (Note 3) LTC1142

Normal Mode 4V < V Sleep Mode 4V < V24 < 12V, 6V < V Shutdown V

= 700mA, V24 = 9V ● 3.23 3.33 3.43 V

LOAD

= 700mA, V10 = 9V ● 4.90 5.05 5.20 V

LOAD

= 7V to 12V, I

10, V24

< 2A ● 40 65 mV

LOAD

< 2A ● 60 100 mV

LOAD

= 0A 50 mV

LOAD

, V

< 12V 1.6 2.1 mA

= V

SD1

= 2.1V, 4V < V10, V

SD2

= 50mA – 40 0 40 mV

LOAD

< 12V 160 230 µA

< 12V 10 20 µA

P-P

Page 3

LTC1142/LTC1142L/LTC1142HV

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. V

= V

= 10V, V

= 0V unless otherwise noted.

SHDN

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input DC Supply Current (Note 3) LTC1142HV, LTC1142HV-ADJ

Normal Mode 4V < V Sleep Mode 4V < V24 < 18V, 6V < V Shutdown V

SD1

, V

< 18V 1.6 2.3 mA

= V

= 2.1V, 4V < V10, V

SD2

< 18V 160 250 µA

< 18V 10 22 µA

Input DC Supply Current (Note 3) LTC1142L-ADJ (Note 6)

V1 – V V

– V

Normal Mode 3.5V < V Sleep Mode 3.5V < V Shutdown V

Current Sense Threshold Voltage LTC1142HV-ADJ, LTC1142L-ADJ

SD1

, V24 < 12V 1.6 2.1 mA

, V

< 12V 160 230 µA

= V

= 2.1V, 3.5V < V10, V

SD2

= V28 = V = V28 = V

OUT OUT

+ 100mV, V2 = V16 = V – 100mV, V2 = V16 = V

< 12V 10 20 µA

+ 25mV 25 mV

REF

– 25mV ● 130 150 170 mV

REF

LTC1142, LTC1142HV

V28 = V V

+ 100mV (Forced) 25 mV

OUT

= V

– 100mV (Forced) ● 130 150 170 mV

OUT

LTC1142, LTC1142HV

= V

+ 100mV (Forced) 25 mV

OUT

= V

– 100mV (Forced) ● 130 150 170 mV

OUT

< 8V, V10, V

SHDN

LOAD

= 16V 1.2 5 µA

–

SENSE

= V

OUT

50 70 90 µA

= 700mA 4 5 6 µs

SHDN

I11, I

OFF

tr, t

Shutdown Pin Threshold 0.5 0.8 2 V

Shutdown Pin Input Current 0V < V

CT Pin Discharge Current V

in Regulation, V

OUT

= 0V 2 10 µA

OUT

Off-Time (Note 4) CT = 390pF, I

Driver Output Transition Times CL = 3000pF (Pins 6, 9, 20, 23), V10, V24 = 6V 100 200 ns

–40°C ≤ TA ≤ 85°C (Note 5), V

= V

= 10V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V2, V

I2, I

OUT

I10, I

Feedback Voltage LTC1142HV-ADJ Only: V10, V24 = 9V 1.21 1.25 1.29 V

Feedback Current LTC1142HV-ADJ Only 0.2 1 µA

Regulated Output Voltage LTC1142, LTC1142HV

3.3V Output I 5V Output I

= 700mA, V24 = 9V 3.17 3.33 3.43 V

LOAD

= 700mA, V10 = 9V 4.85 5.05 5.20 V

LOAD

Input DC Supply Current (Note 3) LTC1142

Normal Mode 4V < V10, V Sleep Mode 4V < V Shutdown V

SHDN

< 12V 1.6 2.4 mA

< 12V, 6V < V

= 2.1V, 4V < V10, V

< 12V 160 260 µA

< 12V 10 22 µA

Input DC Supply Current (Note 3) LTC1142HV-ADJ, LTC1142HV

Normal Mode 4V < V10, V Sleep Mode 4V < V Shutdown V

SHDN

< 18V 1.6 2.6 mA

< 18V, 6V < V

= 2.1V, 4V < V10, V

< 18V 160 280 µA

< 12V 10 24 µA

Input DC Supply Current (Note 3) LTC1142L-ADJ (Note 6)

, V24 < 12V 1.6 2.4 mA

, V

< 12V 160 260 µA

= V

= 2.1V, 3.5V < V10, V

SD2

= V28 = V = V28 = V

OUT OUT

+ 100mV, V2 = V16 = V – 100mV, V2 = V16 = V

< 12V 10 22 µA

+ 25mV 25 mV

REF

– 25mV 125 150 175 mV

REF

V1 – V V

– V

Normal Mode 3.5V < V Sleep Mode 3.5V < V Shutdown V

Current Sense Threshold Voltage LTC1142HV-ADJ, LTC1142L-ADJ

SD1

LTC1142, LTC1142HV

= V

V28 = V

+ 100mV (Forced) 25 mV

OUT

– 100mV (Forced) 125 150 175 mV

OUT

Page 4

LTC1142/LTC1142L/LTC1142HV

ELECTRICAL CHARACTERISTICS

–40°C ≤ TA ≤ 85°C (Note 5), V

= V

= 10V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LTC1142, LTC1142HV

= V

OFF

SHDN

Shutdown Pin Threshold 0.55 0.8 2 V

Off-Time (Note 4) CT = 390pF, I

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.

Note 2: T dissipation P

is calculated from the ambient temperature TA and power

according to the following formula:

LTC1142CG: T

= TA + (P

× 95°C/W)

Note 3: This current is for one regulator block. Total supply current is the sum of Pins 10 and 24 currents. Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See the

+ 100mV (Forced) 25 mV

OUT

= V

– 100mV (Forced) 125 150 175 mV

OUT

= 700mA 3.8 5 6 µs

LOAD

Note 4: In applications where R

is placed at ground potential, the off-

SENSE

time increases approximately 40%. Note 5: The LTC1142/LTC1142L/LTC1142HV are guaranteed to meet

specified performance from 0°C to 70°C and are designed, characterized

and expected to meet these extended temperature limits, but are not tested

at –40°C and 85°C. Guaranteed I-grade parts are available, consult the

factory. Note 6: The LTC1142L-ADJ allows operation down to V

= 3.5V.

Applications Information section.

TYPICAL PERFOR A CE CHARACTERISTICS

5V Output Efficiency 3.3V Output Efficiency 5V Efficiency vs Input Voltage

100

EFFICIENCY (%)

0.01

VIN = 6V

VIN = 10V

0.1 1

LOAD CURRENT (A)

1142 G01

100

EFFICIENCY (%)

0.01

VIN = 5V

VIN = 10V

0.1 1

LOAD CURRENT (A)

1142 G02

100

EFFICIENCY (%)

= 100mA

LOAD

INPUT VOLTAGE (V)

FIGURE 1 CIRCUIT V

= 5V

OUT

= 1A

LOAD

1142 G03

3.3V Efficiency vs Input Voltage Load RegulationLine Regulation

(mV)

OUT

∆V

–10

–20

–30

–40

100

EFFICIENCY (%)

= 100mA

LOAD

INPUT VOLTAGE (V)

FIGURE 1 CIRCUIT V

OUT

LOAD

= 3.3V

= 1A

1142 G04

FIGURE 1 CIRCUIT

= 1A

LOAD

INPUT VOLTAGE (V)

–20

(mV)

–40

OUT

∆V

–60

–80

1142 G05

–100

VIN = 6V

OUT

0.5 LOAD CURRENT (A)

VIN = 6V

= 5V = 3.3V

1.0

FIGURE 1 CIRCUIT

= 0.05Ω

SENSE

VIN = 12V

1.5

2.0

2.5

1142 G06

Page 5

LTC1142/LTC1142L/LTC1142HV

TYPICAL PERFOR A CE CHARACTERISTICS

DC Supply Current

2.1

1.8

1.5

1.2 PER REGULATOR BLOCK

NOT INCLUDING

0.9

GATE CHARGE CURRENT PINS 10, 24

0.6

SUPPLY CURRENT (mA)

0.3

INPUT VOLTAGE (V)

ACTIVE MODE

SLEEP MODE

12 16

1142 G07

Supply Current in Shutdown

PER REGULATOR BLOCK

PINS 10, 24 V

SUPPLY CURRENT (µA)

SHUTDOWN

= 2V

INPUT VOLTAGE (V)

12 16

1142 G08

1.6

1.4

1.2

1.0

0.8

0.6

0.4

NORMALIZED FREQUENCY

0.2

Operating Frequency vs VIN – V

OUT

= 5V

OUT

0°C

25°C

VIN – V

VOLTAGE (V)

OUT

70°C

1142 G09

Gate Charge Supply Current

GATE CHARGE CURRENT (mA)

QN + QP = 100nC

QN + QP = 50nC

80 260200

OPERATING FREQUENCY (kHz)

140

1142 G10

Off-Time vs Output Voltage

OFF-TIME (µs)

= 3.3V

OUT

OUTPUT VOLTAGE (V)

UUU

PI FU CTIO S

LTC1142/LTC1142HV

SENSE+3 (Pin 1): The (+) Input to the 3.3V Section

Current Comparator. A built-in offset between Pins 1 and 28 in conjunction with R threshold for the 3.3V section.

SHDN3 (Pin 2): When grounded, the 3.3V section operates normally. Pulling Pin 2 high holds both MOSFETs off and puts the 3.3V section in micropower shutdown mode. Requires CMOS logic-level signal with tr, t “float” Pin 2.

sets the current trip

SENSE3

< 1µs. Do not

Current Sense Threshold Voltage

= V

SENSE

OUT

= 5V

OUT

1142 G11

175

150

125

100

SENSE VOLTAGE (mV)

TEMPERATURE (°C)

MAXIMUM

THRESHOLD

MINIMUM

THRESHOLD

100

1142 G12

SGND3 (Pin 3): The 3.3V section small-signal ground must be routed separately from other grounds to the (–) terminal of the 3.3V section output capacitor.

PGND3 (Pin 4): The 3.3V section driver power ground connects to source of N-channel MOSFET and the (–) terminal of the 3.3V section input capacitor.

NC (Pin 5): No Connection.

NDRIVE 3 (Pin 6): High Current Drive for Bottom N-Channel

MOSFET, 3.3V Section. Voltage swing at Pin 6 is from ground to V

IN3

Page 6

LTC1142/LTC1142L/LTC1142HV

UUU

PI FU CTIO S

NC (Pins 7, 8): No Connection.

PDRIVE 5 (Pin 9): High Current Drive for Top P-Channel

MOSFET, 5V Section. Voltage swing at this pin is from V to ground.

(Pin 10): Supply pin, 5V section, must be closely

IN5

decoupled to 5V power ground Pin 18.

CT5 (Pin 11): External capacitor CT5 from Pin 11 to ground sets the operating frequency for the 5V section. (The actual frequency is also dependent upon the input voltage.)

INTV

section, nominally 3.3V, can be decoupled to signal ground, Pin 17. Do not externally load this pin.

TH5

tion. The 5V section current comparator threshold increases with the Pin 13 voltage.

SENSE–5 (Pin 14): Connects to internal resistive divider which sets the output voltage for the 5V section. Pin 14 is also the (–) input for the current comparator on the 5V section.

(Pin 12) : Internal supply voltage for the 5V

CC5

(Pin 13): Gain Amplifier Decoupling Point, 5V Sec-

IN5

NC (Pins 21, 22): No Connection.

PDRIVE 3 (Pin 23): High Current Drive for Top P-Channel

MOSFET, 3.3V Section. Voltage swing at this pin is from V

to ground.

IN3

(Pin 24): Supply pin, 3.3V section, must be closely

IN3

decoupled to 3.3V power ground, Pin 4.

(Pin 25): External capacitor CT3 from Pin 25 to ground

sets the operating frequency for the 3.3V section. (The actual frequency is also dependent upon the input voltage.)

INTV

section, nominally 3.3V, can be decoupled to signal ground, Pin 3. Do not externally load this pin.

TH3

Section. The 3.3V section current comparator threshold increases with the Pin 27 voltage.

SENSE–3 (Pin 28): Connects to internal resistive divider which sets the output voltage for the 3.3V section. Pin 28 is also the (–) input for the current comparator on the

3.3V section.

(Pin 26): Internal supply voltage for the 3.3V

CC3

(Pin 27): Gain Amplifier Decoupling Point, 3.3V

SENSE+5 (Pin 15): The (+) Input to the 5V Section Current

Comparator. A built-in offset between Pins 15 and 14 in conjunction with R for the 5V section.

SHDN5 (Pin 16): When grounded, the 5V section operates normally. Pulling Pin 16 high holds both MOSFETs off and puts the 5V section in micropower shutdown mode. Requires CMOS logic signal with tr, t Pin 16.

SGND5 (Pin 17): The 5V section small-signal ground must be routed separately from other grounds to the (–) terminal of the 5V section output capacitor.

PGND5 (Pin 18): The 5V section driver power ground connects to source of N-channel MOSFET and the (–) terminal of the 5V section input capacitor.

NC (Pin 19): No Connection.

NDRIVE 5 (Pin 20): High Current Drive for Bottom

N-Channel MOSFET, 5V Section. Voltage swing at Pin 20 is from ground to V

sets the current trip threshold

SENSE5

< 1µs. Do not “float”

IN5

LTC1142HV-ADJ/LTC1142L-ADJ

SENSE+1 (Pin 1): The (+) Input to the Section 1 Current

Comparator. A built-in offset between Pins 1 and 28 in conjunction with R for this section.

(Pin 2): This pin serves as the feedback pin from an

FB1

external resistive divider used to set the output voltage for section 1.

SHDN1 (Pin 3): When grounded, the section 1 regulator operates normally. Pulling Pin 3 high holds both MOSFETs off and puts this section in micropower shutdown mode. Requires CMOS logic signal with tr, t Pin 3.

SGND1 (Pin 4): The section 1 small-signal ground must be routed separately from other grounds to the (–) terminal of the section 1 output capacitor.

PGND1 (Pin 5): The section 1 driver power ground connects to source of N-channel MOSFET and the (–) terminal of the section 1 input capacitor.

sets the current trip threshold

SENSE1

< 1µs. Do not “float”

Page 7

PI FU CTIO S

LTC1142/LTC1142L/LTC1142HV

UUU

NDRIVE 1 (Pin 6): High Current Drive for Bottom N-Channel MOSFET, Section 1. Voltage swing at Pin 6 is from ground to V

NC (Pins 7, 8): No Connection.

PDRIVE 2 (Pin 9): High Current Drive for Top P-Channel

MOSFET, Section 2. Voltage swing at this pin is from V to ground.

decoupled to section 2 power ground, Pin 19.

CT2 (Pin 11): External capacitor CT2 from Pin 11 to ground sets the operating frequency for the section 2. (The actual frequency is also dependent upon the input voltage.)

INTV

nominally 3.3V, can be decoupled to signal ground, Pin

18. Do not externally load this pin.

The section 2 current comparator threshold increases with the Pin 13 voltage.

IN1

(Pin 10): Supply pin, section 2, must be closely

IN2

(Pin 12) : Internal supply voltage for section 2,

CC2

(Pin 13): Gain Amplifier Decoupling Point, Section 2.

TH2

IN2

SGND2 (Pin 18): The section 2 small-signal ground must be routed separately from other grounds to the (–) terminal of the section 2 output capacitor.

PGND2 (Pin 19): The section 2 driver power ground connects to source of the N-channel MOSFET and the (– terminal of the section 2 input capacitor.

NDRIVE 2 (Pin 20): High Current Drive for Bottom N-Channel MOSFET, Section 2. Voltage swing at Pin 20 is from ground to V

NC (Pins 21, 22): No Connection.

PDRIVE 1 (Pin 23): High Current Drive for Top P-Channel

MOSFET, Section 1. Voltage swing at this pin is from V to ground.

(Pin 24): Supply Pin, Section 1. Must be closely

IN1

decoupled to section 1 power ground Pin 5.

(Pin 25): External capacitor CT1 from Pin 25 to ground

sets the operating frequency for section 1. (The actual frequency is also dependent upon the input voltage.)

IN2

)

IN1

SENSE–2 (Pin 14): Connects (–) input for the current comparator on section 2.

SENSE+2 (Pin 15): The (+) Input to the Section 2 Current Comparator. A built-in offset between Pins 15 and 14 in conjunction with R for this section.

(Pin 16): This pin serves as the feedback pin from an

FB2

external resistive divider used to set the output voltage for section 2.

SHDN2 (Pin 17): When grounded, the section 2 regulator operates normally. Pulling Pin 17 high holds both MOSFETs off and puts section 2 in micropower shutdown mode. Requires CMOS logic signal with tr, t Pin 17.

sets the current trip threshold

SENSE2

< 1µs. Do not “float”

INTV

nominally 3.3V, can be decoupled to signal ground, Pin 4. Do not externally load this pin.

TH1

The section 1 current comparator threshold increases with the Pin 27 voltage.

SENSE–1 (Pin 28): Connects to the (–) input for the current comparator on section 1.

(Pin 26): Internal supply voltage for section 1,

CC1

(Pin 27): Gain Amplifier Decoupling Point, Section 1.

Page 8

LTC1142/LTC1142L/LTC1142HV

FU CTIO AL DIAGRA

Only one regulator block shown. Pin numbers are for 3.3V (5V) sections for LTC1142/LTC1142HV, and V

OUT1

) for LTC1142L-ADJ/LTC1142HV-ADJ.

OUT2

2(16)

LTC1142-ADJ

3(17)

PIN NUMBERS FOR LTC1142, LTC1142HV

PIN NUMBERS FOR LTC1142L-ADJ LTC1142HV-ADJ

SLEEP

–

TH2

25(11)

TH1

–

OFF-TIME CONTROL

SGND

24(10)

23(9)

PDRIVE

NDRIVE

6(20)

PGND

4(18)

LTC1142L-ADJ, LTC1142HV-ADJ: 5(19)

–

SENSE

25mV TO 150mV

27(13)

SHDN

LTC1142L-ADJ

LTC1142HV-ADJ

3(17)

–

13k

3(17)

LTC1142L-ADJ

LTC1142HV-ADJ

–

REFERENCE

4(18)

SENSE

1(15)

LTC1142L-ADJ

LTC1142HV-ADJ

1.25V

2(16)

NC/ADJ

INTV

26(12)2(16)

SENSE

28(14)

–

5pF

100k

1142 BD

OPERATIO

The LTC1142 series consists of two individual regulator blocks, each using current mode, constant off-time architectures to synchronously switch an external pair of complementary power MOSFETs. The two regulators are internally set to provide output voltages of 3.3V and 5V for the LTC1142. The LTC1142HV-ADJ/LTC1142L-ADJ are configured to provide two user selectable output voltages, each set by external resistor dividers. Operating frequency is individually set on each section by the external capacitors at CT, Pins 11 and 25.

The output voltage is sensed by an internal voltage divider connected to Sense–, Pin 28 (14) (LTC1142) or external divider returned to VFB, Pin 2 (16) (LTC1142-ADJ). A voltage comparator V and a gain block G compare the divided output voltage with a reference voltage of 1.25V. To optimize efficiency, the LTC1142 series automatically switches between two modes of operation, Burst Mode and continuous mode. The voltage comparator is the primary control element when the device is in Burst Mode operation, while the gain block controls the output voltage in continuous mode.

Refer to Functional Diagram

During the switch “ON” cycle in continuous mode, current comparator C monitors the voltage between Pins 1 (15) and 28 (14) connected across an external shunt in series with the inductor. When the voltage across the shunt reaches its threshold value, the PDrive output is switched to VIN, turning off the P-channel MOSFET. The timing capacitor connected to Pin 25 (11) is now allowed to discharge at a rate determined by the off-time controller. The discharge current is made proportional to the output voltage [measured by Pin 28 (14)] to model the inductor current, which decays at a rate that is also proportional to the output voltage. While the timing capacitor is discharging, the NDrive output goes to VIN, turning on the N-channel MOSFET.

When the voltage on the timing capacitor has discharged past V

, comparator T trips, setting the flip-flop. This

TH1

causes the NDrive output to go low (turning off the N-channel MOSFET) and the PDrive output to also go low (turning the P-channel MOSFET back on). The cycle then repeats.

Page 9

OPERATIO

LTC1142/LTC1142L/LTC1142HV

Refer to Functional Diagram

As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage [Pin 27(13)] to increase the current comparator threshold, thus tracking the load current.

The sequence of events for Burst Mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. When the output voltage is at or above the desired regulated value, the P-channel MOSFET is held off by comparator V and the timing capacitor continues to discharge below V timing capacitor discharges past V tor S trips, causing the internal sleep line to go low and the N-channel MOSFET to turn off.

The circuit now enters sleep mode with both power MOSFETs turned off. In sleep mode a majority of the circuitry is turned off, dropping the quiescent current

from 1.6mA to 160µA (for one regulator block). The load

current is now being supplied from the output capacitor. When the output voltage has dropped by the amount of

, voltage compara-

TH2

. When the

TH1

hysteresis in comparator V, the P-channel MOSFET is again turned on and this process repeats.

To avoid the operation of the current loop interfering with Burst Mode operation, a built-in offset VOS is incorporated in the gain stage. This prevents the current comparator threshold from increasing until the output voltage has dropped below a minimum threshold.

To prevent both the external MOSFETs from ever being turned on at the same time, feedback is incorporated to sense the state of the driver output pins. Before the NDrive output can go high, the PDrive output must also be high. Likewise, the PDrive output is prevented from going low while the NDrive output is high.

Using constant off-time architecture, the operating frequency is a function of the input voltage. To minimize the frequency variation as dropout is approached, the off-time controller increases the discharge current as VIN drops below V turned on continuously (100% duty cycle) providing low dropout operation with V

+ 1.5V. In dropout the P-channel MOSFET is

OUT

~ VIN.

OUT

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APPLICATIO S I FOR ATIO

he basic LTC1142 application circuit is shown in Figure␣ 1. External component selection is driven by the load requirement and begins with the selection of R Once R power MOSFETs and D1 are selected. Finally, CIN and C

are selected and the loop is compensated. Since the

OUT

3.3V and 5V sections in the LTC1142 are identical and similarly section 1 and section 2 in the LTC1142HV-ADJ/ LTC1142L-ADJ are identical, the process of component selection is the same for both sections. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 20V.

SENSE

The LTC1142 current comparators have a threshold range which extends from a minimum of 25mV/R maximum of 150mV/R threshold sets the peak of the inductor ripple current,

is known, CT and L can be chosen. Next, the

SENSE

Selection for Output Current

is chosen based on the required output current.

SENSE

. The current comparator

SENSE

to a

yielding a maximum output current I value less half the peak-to-peak ripple current.

Burst Mode operation, I

RIPPLE(P-P)

equal to the peak

MAX

For proper

must be less than or

equal to the minimum current comparator threshold.

Since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., I

RIPPLE(P-P)

Operating Frequency section). Solving for R allowing a margin for variations in the LTC1142 and external component values yields:

SENSE

A graph for Selecting R is given in Figure 2.

The load current below which Burst Mode operation commences, I

= 25mV/R

100mV

MAX

, and the peak short-circuit current I

BURST

(see CT and L Selection for

SENSE

vs Maximum Output Current

SENSE

SC(PK)

and

Page 10

LTC1142/LTC1142L/LTC1142HV

FREQUENCY (kHz)

CAPACITANCE (pF)

100

150 200

1142 F03

250

1000

800

600

400

200

300

VIN = 12V

VIN = 10V

VIN = 7V

SENSE

= V

OUT

= 5V

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APPLICATIO S I FOR ATIO

both track I I

can be predicted from the following:

SC(PK)

BURST

SC(PK)

The LTC1142 automatically extends t circuit to allow sufficient time for the inductor current to decay between switch cycles. The resulting ripple current causes the average short-circuit current I reduced to approximately I

. Once R

MAX

15mV

≈

SENSE

150mV R

SENSE

0.20

0.15

(Ω)

0.10

SENSE

0.05

MAXIMUM OUTPUT CURRENT (A)

Figure 2. Selecting R

has been chosen, I

SENSE

MAX

during a short

OFF

SC(AVG)

1142 F02

SENSE

BURST

to be

and

A graph for selecting CT versus frequency including the effects of input voltage is given in Figure 3.

As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations section). The complete expression for operating frequency of the circuit in Figure 1 is given by:

=−

OFF







OUT

 



where:

=•••

13 10

OFF T

is the desired output voltage (i.e., 5V, 3.3V). V

REG

 



is the measured output voltage. Thus V

REG

OUT

 



OUT

REG/VOUT

= 1 in

regulation.

Note that as VIN decreases, the frequency decreases. When the input-to-output voltage differential drops below

1.5V for a particular section, the LTC1142 reduces t

OFF

in that section by increasing the discharge current in CT. This prevents audible operation prior to dropout.

L and CT Selection for Operating Frequency

Each regulator section of the LTC1142 uses a constant offtime architecture with t timing capacitor CT. Each time the P-channel MOSFET switch turns on, the voltage on CT is reset to approximately

3.3V. During the off-time, CT is discharged by a current which is proportional to V analogous to the current in inductor L, which likewise decays at a rate proportional to V value must track the timing capacitor value.

The value of CT is calculated from the desired continuous mode operating frequency:

Assumes VIN = 2V

26 10

••

OUT

determined by an external

OFF

. The voltage on CT is

OUT

, Figure 1 circuit.

. Thus the inductor

Figure 3. Timing Capacitor Value

Once the frequency has been set by CT, the inductor L must be chosen to provide no more than 25mV/R

SENSE

of peakto-peak inductor ripple current. This results in a minimum required inductor value of:

= 5.1 • 105 • R

MIN

SENSE

• CT • V

REG

As the inductor value is increased from the minimum value, the ESR requirements for the output capacitor are

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APPLICATIO S I FOR ATIO

eased at the expense of efficiency. If too small an inductor is used, the inductor current will decrease past zero and change polarity. A consequence of this is that the LTC1142 may not enter Burst Mode operation and efficiency will be severely degraded at low currents.

Inductor Core Selection

Once the minimum value for L is known, the type of inductor must be selected. The highest efficiency will be

obtained using ferrite, molypermalloy (MPP), or Kool Mµ

cores. Lower cost powdered iron cores provide suitable performance, but cut efficiency by 3% to 7%. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase.

Ferrite designs have very low core loss, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple which can cause Burst Mode operation to be falsely triggered. Do not allow the core to saturate!

Kool Mµ

(from Magnetics, Inc.) is a very good, low loss core material for toroids with a “soft” saturation characteristic. Molypermalloy is slightly more efficient at high (>200kHz) switching frequencies, but it is quite a bit more expensive. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, new designs for surface mount are available from Coiltronics and Beckman Industrial Corporation which do not increase the height significantly.

Power MOSFET and D1, D2 Selection

Two external power MOSFETs must be selected for use with each section of the LTC1142: a P-channel MOSFET for the main switch, and an N-channel MOSFET for the synchronous switch. The main selection criteria for the power MOSFETs are the threshold voltage V

Kool Mµ

is a registered trademark of Magnetics, Inc.

and on- resistance R

GS(TH)

DS(ON)

The minimum input voltage determines whether standard threshold or logic-level threshold MOSFETs must be used. For VIN > 8V, standard threshold MOSFETs (

below 8V, logic-level threshold MOSFETs (V

< 4V) may be used. If VIN is expected to drop

GS(TH)

2.5V) are strongly recommended. When logic-level MOSFETs are used, the LTC1142 supply voltage must be less than the absolute maximum VGS ratings for the MOSFETs.

The maximum output current I

determines the R

MAX

DS(ON)

requirement for the two MOSFETs. When the LTC1142 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. The duty cycles for the two MOSFETs are given by:

P-Ch Duty Cycle =

N-Ch Duty Cycle =

From the duty cycles the required R

OUT

−

IN OUT

DS(ON)

for each

MOSFET can be derived:

•

P-Ch R =

N-Ch R =

DS(ON)

••+

VV I

()

OUT

−

IN OUT MAX N

MAX P

()

•

••+

()

where PP and PN are the allowable power dissipations and

δP and δ

are the temperature dependencies of R

DS(ON)

PP and PN will be determined by efficiency and/or thermal

requirements (see Efficiency Considerations). (1 + δ) is

generally given for a MOSFET in the form of a normalized R

vs Temperature curve, but δ = 0.007/°C can be

DS(ON)

used as an approximation for low voltage MOSFETs.

The Schottky diodes D1 and D2 shown in Figure 1 only conduct during the dead-time between the conduction of the respective power MOSFETs. The sole purpose of D1 and D2 is to prevent the body diode of the N-channel MOSFET from turning on and storing charge during the

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APPLICATIO S I FOR ATIO

dead-time, which could cost as much as 1% in efficiency (although there are no other harmful effects if D1 and D2 are omitted). Therefore, D1 and D2 should be selected for a forward voltage of less than 0.6V when conducting I

CIN and C

Selection

OUT

In continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle V

OUT/VIN

prevent large voltage transients, a low ESR input capacitor sized for the

maximum RMS current must be used. The

maximum RMS capacitor current is given by:

VVV

OUT IN OUT

Required I

IN MAX

RMS

≈

[]

This formula has a maximum at VIN = 2V I

RMS

= I

/2. This simple worst case conditon is com-

OUT

−

()

, where

OUT

monly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any

question. An additional 0.1µF to 1µF ceramic capacitor is

also required on each VIN line (Pins 10 and 24) for high frequency decoupling.

The selection of C Series Resistance (ESR).

than twice the value of R

is driven by the required Effective

OUT

The ESR of C

for proper operation of the

SENSE

must be less

OUT

LTC1142:

Required ESR < 2R

OUT

SENSE

Optimum efficiency is obtained by making the ESR equal to R

. As the ESR is increased up to 2R

SENSE

efficiency degrades by less than 1%. If the ESR is greater than 2R

, the voltage ripple on the output capacitor

SENSE

will prematurely trigger Burst Mode operation, resulting in disruption of continuous mode and an efficiency hit which can be several percent.

Manufacturers such as Nichicon and United Chemicon should be considered for high performance capacitors. The OS-CON semiconductor dielectric capacitor available

12/

MAX

. To

, the

from Sanyo has the lowest ESR/size ratio of any aluminum electrolytic at a somewhat higher price. Once the ESR requirement for C rating generally far exceeds the I

has been met, the RMS current

OUT

RIPPLE(P-P)

requirement.

In surface mount applications multiple capacitors may have to be parallel to meet the capacitance, ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums,

avail-

able in case heights ranging from 2mm to 4mm. For

example, if 200µF/10V is called for in an application requiring 3mm height, two AVX 100µF/10V (P/N TPSD

107K010) could be used. Consult the manufacturer for other specific recommendations.

At low supply voltages, a minimum capacitance at C

OUT

is needed to prevent an abnormal low frequency operating mode (see Figure 4). When C

is made too small, the

OUT

output ripple at low frequencies will be large enough to trip the voltage comparator. This causes Burst Mode operation to be activated when the LTC1142 would normally be in continuous operation. The output remains in regulation at all times.

1000

L = 50µH R

= 0.02Ω

SENSE

= 0.02Ω

L = 50µH

= 0.05Ω

VOLTAGE (V)

OUT

1142 F04

OUT

800

L = 25µH

600

400

OUTPUT CAPACITANCE (µF)

200

Figure 4. Minimum Value of C

VIN – V

Checking Transient Response

The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load

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APPLICATIO S I FOR ATIO

current. When a load step occurs, V

amount equal to ∆I

series resistance of C or discharge C current change and returns V value. During this recovery time V for overshoot or ringing which would indicate a stability problem. The Pin 27 (13) external components shown in the Figure 1 circuit will prove adequate compensation for most applications.

A second, more severe transient is caused by switching in

loads with large (>1µF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel with C

OUT

deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately 25 • C

Thus a 10µF capacitor would require a 250µs rise time,

limiting the charging current to about 200mA.

Efficiency Considerations

OUT

, causing a rapid drop in V

• ESR, where ESR is the effective

LOAD

. ∆I

OUT

until the regulator loop adapts to the

also begins to charge

LOAD

to its steady- state

OUT

shifts by an

OUT

can be monitored

. No regulator can

LOAD

section) less the gate charge current. For VIN = 10V the

LTC1142 DC supply current for each section is 160µA

with no load, and increases proportionally with load up to a constant 1.6mA after the LTC1142 has entered continuous mode. Because the DC bias current is drawn from VIN, the resulting loss increases with input voltage. For VIN = 10V the DC bias losses are generally less than 1% for load currents over 30mA. However, at very low load currents the DC bias current accounts for nearly all of the loss.

2. MOSFET gate charge current results from switching

the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN which is typically much larger than the DC supply current. In continuous mode, I

gate charge for a 0.1Ω N-channel power MOSFET is

25nC, and for a P-channel about twice that value. This results in I operation, for a 2% to 3% typical mid-current loss with VIN = 10V.

GATE(CHG)

= 7.5mA in 100kHz continuous

= f (QN + QP). The typical

The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc., are the individual losses as a percentage of input power. (For high efficiency circuits only small errors are incurred by expressing losses as a percentage of output power.)

Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LTC1142 circuits:

1. LTC1142 DC bias current

2. MOSFET gate charge current

3. I2R losses

1. The DC supply current is the current which flows into VIN (pin 24 for the 3.3V section, Pin 10 for the 5V

Note that the gate charge loss increases directly with both input voltage and operating frequency. This is the principal reason why the highest efficiency circuits operate at moderate frequencies. Furthermore, it argues against using larger MOSFETs than necessary to control I2R losses, since overkill can cost efficiency as well as money!

3. I2R losses are easily predicted from the DC resistances of the MOSFET, inductor, and current shunt. In continuous mode the average output current flows through L and R and N-channel MOSFETs. If the two MOSFETs have approximately the same R one MOSFET can simply be summed with the resistances of L and R example, if each R R

SENSE

results in losses ranging from 3% to 12% as the output current increases from 0.5A to 2A. I2R losses cause the efficiency to roll off at high output currents.

, but is “chopped” between the P-channel

SENSE

, then the resistance of

DS(ON)

to obtain I2R losses. For

SENSE

= 0.1Ω, RL = 0.15Ω, and

DS(ON)

= 0.05Ω, then the total resistance is 0.3Ω. This

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APPLICATIO S I FOR ATIO

Figure 5 shows how the efficiency losses in one section of a typical LTC1142 regulator end up being apportioned. The gate charge loss is responsible for the majority of the efficiency lost in the mid-current region. If Burst Mode operation was not employed at low currents, the gate charge loss alone would cause efficiency to drop to unacceptable levels. With Burst Mode operation, the DC supply current represents the lone (and unavoidable) loss component which continues to become a higher percentage as output current is reduced. As expected, the I2R losses dominate at high load currents.

Other losses including CIN and C losses, MOSFET switching losses, Schottky conduction losses during dead-time and inductor core losses, generally account for less than 2% total additional loss.

100

GATE CHARGE

1/2 LTC1142 I

EFFICIENCY/LOSS (%)

0.01

Figure 5. Efficiency Loss

0.03

0.1

OUTPUT CURRENT (A)

0.3

Design Example

As a design example, assume VIN = 12V (nominal), 5V section, I

= 2A and f = 200kHz; R

MAX

immediately be calculated:

ESR dissipative

OUT

I2R

1142 F05

, CT and L can

SENSE

and δP = δ

= 0.007(63 – 25) = 0.27. The required R

DS(ON)

for each MOSFET can now be calculated:

12 0 25

PCh- R

N-Ch R

DS(ON)

(. )

52 127

()(. )

12 0 25

(. )

52 127

()(. )

012

0 085

Ω

The P-channel requirement can be met by a Si9430DY, while the N-channel requirement is exceeded by a Si9410DY. Note that the most stringent requirement for the N-channel MOSFET is with V

= 0 (i.e., short circuit).

OUT

During a continuous short circuit, the worst case N-channel dissipation rises to:

PN = I

SC(AVG)

With the 0.05Ω sense resistor, I

• R

DS(ON)

• (1 + δ

SC(AVG)

)

= 2A will result,

increasing the 0.085Ω N-channel dissipation to 450mW at a die temperature of 73°C.

CIN will require an RMS current rating of at least 1A at temperature, and C

will require an ESR of 0.05Ω for

OUT

optimum efficiency.

Now allow VIN to drop to its minimum value. At lower input voltages the operating frequency will decrease and the P-channel will be conducting most of the time, causing its power dissipation to increase. At V

= (1/2.92µs)[1 – (5V/ 7V)] = 98kHz

MIN

(. )( )(. )Ω

5 0 12 2 1 27

435

IN(MIN)

= 7V:

A similar calculation for the 3.3V section results in the component values shown in Figure 14.

R t C L2

= 100mV/2 = 0.05Ω

SENSE

= (1/200kHz) • [1 – (5/12)] = 2.92µs

OFF

= 2.92µs/(1.3 • 10

= 5.1 • 10

MIN

) = 220pF

• 0.05Ω • 220pF • 5V = 28µH

Assume that the MOSFET dissipations are to be limited to PN = PP = 250mW.

If T

= 50°C and the thermal resistance of each MOSFET

is 50°C/W, then the junction temperatures will be 63°C

LTC1142HV-ADJ/LTC1142L-ADJ Adjustable Applications

When an output voltage other than 3.3V or 5V is required, the LTC1142 adjustable version is used with an external resistive divider from V

to VFB, Pin 2 (16). The regu-

OUT

lated output voltage is determined by:

125 1

OUT

 









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APPLICATIO S I FOR ATIO

To prevent stray pickup a 100pF capacitor is suggested across R1 located close to the LTC1142HV-ADJ/LTC1142LADJ as in Figure 6. The external divider network must be placed across C to signal ground. Refer to the Board Layout Checklist.

[PIN 2(16)]

SGND

[PIN 4(18)]

Figure 6. LTC1142-ADJ External Feedback Network

Board Layout Checklist

When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1142. These items are also illustrated graphically in

with the negative plate of C

OUT

100pF

returned

OUT

SENSE

OUT

1142 F06

the layout diagram of Figure 7. In general each block should be self-contained with little cross coupling for best performance. Check the following in your layout:

1. Are the signal and power grounds segregated? The LTC1142 signal ground [Pin 3 (17) for the LTC1142, Pin 4 (18) for LTC1142-ADJ] must return to the (–) plate C

. The power ground returns to the source of the

OUT

N-channel MOSFET, anode of the Schottky diode, and (–) plate of CIN, which should have as short lead lengths as possible.

2. Does the LTC1142 Sense– , Pin 28 (14) connect to a point close to R

and the (+) plate of C

SENSE

OUT

3. Are the Sense– and Sense+ leads routed together with minimum PC trace spacing? The 1000pF capacitor between Pins 1 (15) and 28 (14) should be as close as possible to the LTC1142. Ensure accurate current sens-

SENSE3

OUT3

–

IN3

OUT3

N-CH

IN3

BOLD LINES INDICATE HIGH CURRENT PATHS

SHDN (3.3V OUTPUT)

P-CH

1µF

IN5

3300pF

SENSE+3

SHDN3

SGND3

PGND3

NDRIVE 3

PDRIVE 5

IN5

INTV

CC5

TH5

SENSE–5

1000pF

LTC1142

1000pF

SENSE

TH3

INTV

CC3

IN3

PDRIVE 3

NDRIVE 5

PGND5

SGND5

SHDN5

SENSE

–

3300pF

IN3

1µF

SHDN (5V OUTPUT)

SENSE RESISTOR PCB PATTERN

SENSE

OUT5

P-CH

N-CH

SENSE

IN5

–

SENSE5

–

1142 F07

OUT5

IN5

Figure 7. LTC1142 Layout Diagram (see Board Layout Checklist)

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APPLICATIO S I FOR ATIO

ing with Kelvin connections. Be sure to use a PCB pattern similar to that shown in Figure 7 for the current sense resistors.

4. Does the (+) plate of CIN connect to the source of the P-channel MOSFET as closely as possible? This capacitor provides the AC current to the P-channel MOSFET.

5. Is the input decoupling capacitor (1µF/0.22µF) con-

nected closely between Pin 24 (10) and power ground [Pin 4 (18) for the LTC1142, Pin 5 (19) for the LTC1142ADJ]? This capacitor carries the MOSFET driver peak currents.

6. Are the shutdown Pins 2 and 16 for the LTC1142 (Pins 3 and 17 for the LTC1142-ADJ) actively pulled to ground during normal operation? Both Shutdown pins are high impedance and must not be allowed to float. Both pins can be driven by the same external signal if needed.

7. For the LTC1142-ADJ adjustable applications, the resistive divider R1, R2 must be connected between the (+) plate of C

and signal ground.

OUT

FROM CROWBAR

DETECT CIRCUIT

(ACTIVE WHEN V

OFF WHEN V

Figure 8. Output Crowbar Interface

GATE

= V

= GND)

PIN 26(12)

VN2222LL

PIN 25(11)

INT V

LTC1142

1142 F08

Troubleshooting Hints

Since efficiency is critical to LTC1142 applications, it is very important to verify that the circuit is functioning correctly in both continuous and Burst Mode operation. The waveform to monitor is the voltage on the CT, Pins 25 and 11.

In continuous mode (I pin should be a sawtooth with a 0.9V

LOAD

> I

) the voltage on the C

BURST

P-P

swing. This

voltage should never dip below 2V as shown in Figure 9a.

When load currents are low (I

LOAD

< I

) Burst Mode

BURST

operation occurs. The voltage on the CT pin now falls to ground for periods of time as shown in Figure 9b.

3.3V

Output Crowbar

An added feature to using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. Pulling the CT , Pin 25 (11) above

1.5V when the output voltage is greater than the desired

regulated value will turn “on” the N-channel MOSFET for that regulator section.

A fault condition which causes the output voltage to go above a maximum allowable value can be detected by external circuitry. Turning on the N-channel MOSFET when this fault is detected will cause large currents to flow and blow the system fuse.

The N-channel MOSFET needs to be sized so it will safely handle this overcurrent condition. The typical delay from pulling the CT pin high and the NDrive Pin 6 (20) going high is 250ns. Note: Under shutdown conditions, the N-channel is held OFF and pulling the CT pin high will not cause the N-channel MOSFET to crowbar the output.

A simple N-channel FET can be used as an interface between the overvoltage detect circuitry and the LTC1142 as shown in Figure 8.

(a) CONTINUOUS MODE OPERATION

(b) Burst Mode

Figure 9. CT Waveforms

OPERATION

3.3V

1142 F09

Inductor current should also be monitored. Look to verify that the peak-to-peak ripple current in continuous mode operation is approximately the same as in Burst Mode operation.

If Pin 25 or Pin 11 is observed falling to ground at high output currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist.

Auxiliary Windings––Suppressing Burst Mode Operation

The LTC1142 synchronous switch removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. With synchronous switching, auxiliary outputs

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APPLICATIO S I FOR ATIO

may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation.

Burst Mode operation can be suppressed at low output currents with a simple external network which cancels the 25mV minimum current comparator threshold. This technique is also useful for eliminating audible noise from certain types of inductors in high current (I applications when they are lightly loaded.

An external offset is put in series with the Sense– pin to subtract from the built-in 25mV offset. An example of this

technique is shown in Figure 10. Two 100Ω resistors are

inserted in series with the sense leads from the sense resistor.

SENSE

[PIN 1(15)]

SENSE

[PIN 28(14)]

–

1000pF

100Ω

SENSE

OUT

1142 F10

OUT

> 5A)

With the addition of R3 a current is generated through R1 causing an offset of:

OFFSET OUT

If V

OFFSET

=•

> 25mV, the built-in offset will be cancelled and

 









Burst Mode operation is prevented from occurring. Since V

is constant, the maximum load current is also

OFFSET

decreased by the same offset. Thus, to get back to the same I

, the value of the sense resistor must be lower:

MAX

≈

SENSE

MAX

To prevent noise spikes from erroneously tripping the current comparator, a 1000pF capacitor is needed across Pins 1 (15) and Pins 28 (14).

Figure 10. Suppression of Burst Mode Operation

TYPICAL APPLICATIO S

IN1

OUT1

3.6V/2A

OUT1

220µF

10V

× 2

SENSE1

0.05Ω

100k

52.3k

22µF 35V × 2

27µH

MBRS130T3

100pF

SENSE1, RSENSE2

L1: SUMIDA CDRH125-270 L2: SUMIDA CDRH125-330

0.22µF

P-CH Si9430DY

1000pF

N-CH Si9410DY

: DALE WSL-2010-.05

(For additional high efficiency circuits, see Application Note 54)

5.2V TO 18V

0V = NORMAL >1.5V = SHDN

24 17

IN1

PDRIVE 1

SENSE

–

SENSE

FB1

NDRIVE 1

PGND1 SGND1 C

5 4 25 27 13 11 18 19

SHDN1

LTC1142HV-ADJ

T1ITH1ITH2

270pF

3300pF

SHDN2

3300pF

270pF

SGND2

PDRIVE 2

SENSE+2

SENSE

NDRIVE 2

PGND2

0.22µF

P-CH

Si9430DY

1000pF

N-CH

Si9410DY

IN2

–

FB2

33µH

D2 MBRS130T3

100pF

IN2

22µF 35V × 2

SENSE2

0.05Ω

R4 150k 1%

49.9k 1%

OUT2

5V/2A

OUT2

220µF 10V × 2

1142 F11

Figure 11. LTC1142HV-ADJ Dual Regulator with 3.6V/2A and 5V/2A Outputs

Page 18

LTC1142/LTC1142L/LTC1142HV

TYPICAL APPLICATIO S

IN1

OUT1

2.5V/1.5A

OUT1

220µF

10V

× 2

SENSE1

0.075Ω

49.9k 1%

22µF 35V × 2

33µH

MBRS130T3

100pF

: IRC L1206-01-R075-J

SENSE1

: IRC L1206-01-R050-J

SENSE2

0.22µF

P-CH Si9430DY

1000pF

N-CH Si9410DY

24 17

IN1

PDRIVE 1

SENSE

SENSE–1

FB1

NDRIVE 1

PGND1 SGND1 C

5 4 25 27 13 11 18 19

L1: COILTRONICS CTX33-4 L2: COILTRONICS CTX25-4

SHDN1

T1ITH1ITH2

330pF

4.5V TO 18V

0V = NORMAL

>1.5V = SHDN

LTC1142HV-ADJ

3300pF

SHDN2

330pF

SGND2

IN2

PDRIVE 2

SENSE+2

SENSE

FB2

NDRIVE 2

PGND2

IN2

0.22µF

P-CH

Si9430DY

–

1000pF

N-CH

Si9410DY

25µH

D2 MBRS130T3

100pF

22µF 35V × 2

SENSE2

0.05Ω

84.5k 1%

R3 51k 1%

OUT2

3.3V/2A

OUT2

220µF 10V × 2

1142 F12

OUT3

3.3V/3A

SENSE3

0.033Ω

100µF 10V × 3

Figure 12. LTC1142HV-ADJ High Efficiency Regulator with 3.3V/2A and 2.5V/1.5A Outputs

5.2V TO 18V

IN3

MBRS130T3

OUT3

22µF

25V

10µH

× 2

0.22µF

P-CH Si9433DY

1000pF

N-CH Si9410DY

0V = NORMAL >1.5V = SHDN

24 16 10

IN3

PDRIVE 3

SENSE

–

SENSE

NDRIVE 3

PGND3 SGND3 C

4 3 25 27 13 11 17 18

SHDN3

LTC1142HV

T3ITH3ITH5

3300pF

200pF

510Ω

3300pF

SHDN5

C 150pF

SGND5

IN5

PDRIVE 5

SENSE

NDRIVE 5

PGND5

0.22µF

P-CH

Si9430DY

–

1000pF

N-CH

Si9410DY

IN5

22µF 25V × 2

22µH

D2 MBRS130T3

SENSE5

0.05Ω

OUT5

5V/2A

OUT5

220µF 10V × 2

: IRC L1206-01-R033-J

SENSE3

: IRC L1206-01-R050-J

SENSE5

L1: COILCRAFT D03316P-103 L2: COILCRAFT D03316P-223

Figure 13. LTC1142HV High Efficiency Regulator with 3.3V/3A and 5V/2A Outputs

1142 F13

Page 19

TYPICAL APPLICATIO S

6.5V TO 14V

3.3V/2A

SENSE3

0.05Ω

OUT3

100µF 10V × 2

: KRL SL-C1-1/2-0R050J

SENSE3

: KRL SL-C1-1/2-0R040J

SENSE5

L1: COILTRONICS CTX33-4 T1: DALE LPE-6562-A026 PRIMARY: SECONDARY = 1:1.8

22µF

33µH

MBRS140T3

12V ENABLE

0V = 12V OFF

>3V = 12V ON

25V

× 2

(6V MAX)

P-CH Si9430DY

0.01µF

N-CH Si9410DY

12V/150mA

1µF

22µF

25V

PDRIVE 3

SENSE

NDRIVE 3

PGND3 SGND3 C

LTC1142/LTC1142L/LTC1142HV

0V = NORMAL >1.5V = SHDN

24 16 10

IN3

–

4 3 25 27 13 11 17 18

SHDN3

T3ITH3ITH5

390pF

20pF

649k 1%

R4 294k 1%

LTC1142

510Ω

3300pF

ADJ

510Ω

3300pF

SHDN5

OUT

LT1121

GND

SGND5

200pF

SHUTDOWN

IN5

PDRIVE 5

SENSE

NDRIVE 5

PGND5

1µF

Si9430DY

1000pF

Si9410DY

D3 MBRS140T3

–

P-CH

N-CH

D2 MBRS140T3

22Ω

1000pF

22µF 25V × 2

30µH

100Ω

SENSE5

0.04Ω

R1,100Ω

R5 18k

220µF

10V

× 2

VN2222LL

22µF

35V

OUT5

5V/2A

1142 F14

FROM WALL ADAPTER

D3 MBRS340T3

SENSE1

0.1Ω

OUT1

220µF

10V

SENSE1

SENSE2

L1: COILTRONICS CTX50-4 L2: COILTRONICS CTX25-4

274k

49.9k 1%

: KRL SL-C1-1/2-1R100J : KRL SL-C1-1/2-1R050J

8V TO 18V

50µH

MBRS140T3

100pF

IN1

22µF 35V × 2

P-CH Si9430DY

1000pF

N-CH Si9410DY

“1” FOR TRICKLE CHARGE

Figure 14. LTC1142 Triple Output Regulator with Switched 12V Output

0.22µF

0V = CHARGE ON

>1.5V = CHARGE OFF

24 17

IN1

PDRIVE 1

SENSE

–

SENSE

FB1

NDRIVE 1

PGND1

5 4 25 27 13 11 18 19

VN2222LL

SGND1

SHDN1

T1ITH1

C 200pF

LTC1142HV-ADJ

3300pF

51Ω

0V = OUTPUT ON

>1.5V = 3.3V OUTPUT OFF

TH2

R 1k

3300pF

SHDN2

SGND2

330pF

0.22µF

P-CH

Si9433DY

1000pF

N-CH

Si9410DY

IN2

PDRIVE 2

SENSE+2

–

SENSE

FB2

NDRIVE 2

PGND2

FAST CHARGE = 130mV/R TRICKLE CHARGE = 130mV/R

SENSE1

25µH

D2 MBRS140T3

100pF

= 1.3A

= 100mA

SENSE1

IN2

22µF 25V × 2

SENSE2

0.05Ω

84.5k 1%

R3 51k 1%

BATT

4 CELLS NiCAD

OUT2

3.3V/2A

OUT2

220µF 10V × 2

1142 F15

Figure 15. LTC1142HV-ADJ High Efficiency Power Supply Providing 3.3V/2A with Built-In Battery Charger

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Page 20

LTC1142/LTC1142L/LTC1142HV

TYPICAL APPLICATIO S

1400

1200

1000

800

600

400

OUTPUT CURRENT (mA)

200

Figure 16. LTC1142HV-ADJ Output Current vs Trickle Charge Set Resistance

) for the Circuit in Figure 15 Using a 0.1Ω Current Sense Resistor R

PACKAGE DESCRIPTIO

5.20 – 5.38** (0.205 – 0.212)

° – 8°

0.13 – 0.22

(0.005 – 0.009)

NOTE: DIMENSIONS ARE IN MILLIMETERS

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

0.55 – 0.95

(0.022 – 0.037)

12 4

SET RESISTANCE (kΩ)

1142 F16

Dimensions in inches (millimeters) unless otherwise noted.

G Package

28-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

0.65

(0.0256)

BSC

0.25 – 0.38

(0.010 – 0.015)

1.73 – 1.99

(0.068 – 0.078)

0.05 – 0.21

(0.002 – 0.008)

2526 22 21 20 19 181716 1523242728

12345678 9 10 11 12 1413

SENSE1

10.07 – 10.33*

(0.397 – 0.407)

7.65 – 7.90

(0.301 – 0.311)

G28 SSOP 1098

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SENSE

Up to 40A

OUT

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear-tech.com

Required

SENSE

, 16-Lead SSOP Package

SENSE

Up to 42A

OUT

1142fd LT/TP 0600 2K REV D • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1995