Datasheet LTC1094ACN, LTC1093ACN, LTC1093, LTC1092CN8, LTC1092ACN8 Datasheet (Linear Technology)

LTC1091/LTC1092

LTC1093/LTC1094

1-, 2-, 6- and 8-Channel, 10-Bit

Serial I/O Data Acquisition Systems

FEATURES

■

Programmable Features – Unipolar/Bipolar Conversions –

Differential/Single-Ended Multiplexer Configurations

■

Sample-and-Holds

■

Single Supply 5V, 10V or ±5V Operation

■

Direct 3- or 4-Wire Interface to Most MPU Serial Ports and All MPU Parallel I/O Ports

■

Analog Inputs Common Mode to Supply Rails

■

Resolution: 10 Bits

■

Total Unadjusted Error (A Grade): ±1LSB Over Temp

■

Fast Conversion Time: 20µs

■

Low Supply Current

LTC1091: 3.5mA Max, 1.5mA Typ LTC1092/LTC1093/LTC1094: 2.5mA Max, 1mA Typ

U

DESCRIPTIO

The LTC®1091/LTC1092/LTC1093/LTC1094 10-bit data acquisition systems are designed to provide complete function, excellent accuracy and ease of use when digitizing analog data from a wide variety of signal sources and transducers. Built around a 10-bit, switched capacitor, successive approximation A/D core, these devices include software configurable analog multiplexers and bipolar and unipolar conversion modes as well as on-chip sample-

and-holds. On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers. These circuits can provide a complete data acquisition system in ratiometric applications or can be used with an external reference in others.

The high impedance analog inputs and the ability to operate with reduced spans (below 1V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages.

An efficient serial port communicates without external hardware to most MPU serial ports and all MPU parallel I/O ports allowing eight channels of data to be transmitted over as few as three wires. This, coupled with low power consumption, makes remote location possible and facilitates transmitting data through isolation barriers.

Temperature drift of offset, linearity and full-scale error are all extremely low (1ppm/°C typically) allowing all grades to be specified with offset and linearity errors of ±0.5LSB maximum over temperature. In addition, the A grade devices are specified with full-scale error and total unadjusted error (including the effects of offset, linearity and full-scale errors) of ±1LSB maximum over temperature. The lower grade has a full-scale specification of ±2LSB for applications where full scale is adjustable or less critical.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATION

5V

8

V

CC

(V

)

REF

7

CLK

6

D

OUT

5

D

IN

ANALOG INPUT #1

0V TO 5V RANGE

ANALOG INPUT #2

0V TO 5V RANGE

1

CS

2

CH0

LTC1091

3

CH1

4

GND

U

4.7µF

SERIAL DATA LINK

MPU

(e.g., 8051)

P1.4 P1.3 P1.2

FOR 8051 CODE SEE

APPLICATIONS INFORMATION

SECTION

1091 TA01

1.25

1024

1.00

0.75

0.50

0.25

0

VCC = 5V

0

1

2

REFERENCE VOLTAGE (V)

)

REF

1

LINEARITY ERROR (LSB = • V

3

4

5

1091 TA02

1

LTC1091/LTC1092

1 2 3 4 5 6 7 8 9

10

TOP VIEW

N PACKAGE

20-LEAD PDIP

20 19 18 17 16 15 14 13 12 11

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

COM

DGND

DV

CC

AV

CC

CLK CS D

OUT

D

IN

REF

+

REF

–

AGND V

–

LTC1093/LTC1094

A

W

O

LUTEXI TIS

S

A

WUW

U

ARB

G

(Notes 1, 2)

Supply Voltage (VCC) to GND or V–........................ 12V

Negative Supply Voltage (V–).................... –6V to GND

Voltage

Analog Reference and LTC1091/2 CS

Inputs ................................. (V–) –0.3V to (V

+ 0.3V)

CC

Digital Inputs (except LTC1091/2 CS) .. –0.3V to 12V

Digital Outputs ........................ –0.3V to (V

+ 0.3V)

CC

WU

/

PACKAGE

1

CS

2

CH0

3

CH1

4

GND

T

= 110°C, θJA = 150°C/W (N)

JMAX

O

TOP VIEW

N8 PACKAGE 8-LEAD PDIP

RDER I FOR ATIO

ORDER PART

(V

)

V

8

CC

REF

CLK

7

D

6

OUT

D

5

IN

NUMBER

LTC1091ACN8 LTC1091CN8

Power Dissipation............................................. 500mW

Operating Temperature Range

LTC1091/2/3/4AC, LTC1091/2/3/4C..... –40°C to 85°C

Storage Temperature Range................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec.)................ 300°C

U

TOP VIEW

1

CS

2

+IN

3

–IN

4

GND

N8 PACKAGE 8-LEAD PDIP

T

= 110°C, θJA = 150°C/W (N)

JMAX

V

8

CC

CLK

7

D

6

OUT

V

5

REF

ORDER PART

NUMBER

LTC1092ACN8 LTC1092CN8

TOP VIEW

1

CH0

2

CH1

3

CH2

4

CH3

5

CH4

6

CH5

7

COM

8

DGND

N PACKAGE

16-LEAD PDIP

T

JMAX

16-LEAD PLASTIC SO WIDE

= 110°C, θJA = 150°C/W (N)

JMAX

= 110°C, θJA = 130°C/W (SW)

16 15 14 13 12 11 10

9

SW PACKAGE

V

CC

CLK CS D

OUT

D

IN

V

REF

AGND

–

V

LTC1093ACN LTC1093CN LTC1093CSW

T

= 110°C, θJA = 150°C/W (N)

JMAX

LTC1094ACN LTC1094CN

Consult factory for Industrial and Military grade parts.

PRODUCT GUIDE

PART NUMBER #CHANNELS UNIPOLAR BIPOLAR (SEPARATE V

LTC1091 2 ● Pin-for-Pin 10-Bit Upgrade of ADC0832 LTC1092 1 ●●Pin-for-Pin 10-Bit Upgrade of ADC0831 LTC1093 6 ●● ● ● LTC1094 8 ●● ● ●

2

CONVERSION MODES

REDUCED SPAN

CAPABILITY

REF

±

5V

) CAPABILITY

LTC1091/LTC1092

LTC1093/LTC1094

UUUUWW

RECO E DED OPERATI G CO DITIO S

LTC1091A/LTC1092A/LTC1093A/LTC1094A

SYMBOL PARAMETER CONDITIONS MIN MAX UNITS

V

CC –

V f

CLK

t

CYC

t

hDI

t

suCS

t

suDI

t

WHCLK

t

WLCLK

t

WHCS

t

WLCS

Supply Voltage 4.5 10 V Negative Supply Voltage LTC1093/LTC1094, VCC = 5V –5.5 0 V Clock Frequency VCC = 5V 0.01 0.5 MHz Total Cycle Time LTC1091 15 CLK Cycles

Hold Time, DIN Alter SCLK↑ VCC = 5V 150 ns Setup Time CS↓ Before CLK↑ VCC = 5V 1 µs Setup Time DIN Stable Before CLK↑ VCC = 5V 400 ns CLK High Time VCC = 5V 0.8 µs CLK Low Time VCC = 5V 1 µs CS High Time Between Data Transfer Cycles VCC = 5V 2 µs CS Low Time During Data Transfer LTC1091 15 CLK Cycles

LTC1091/LTC1092/LTC1093/LTC1094

+ 2µs

LTC1092 12 CLK Cycles

+ 2µs

LTC1093/LTC1094 18 CLK Cycles

+ 2µs

LTC1092 12 CLK Cycles LTC1093/LTC1094 18 CLK Cycles

UW

U

CONVERTER AND MULTIPLEXER CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 3)

LTC1091A/LTC1092A LTC1091/LTC1092

LTC1093A/LTC1094A LTC1093/LTC1094

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Offset Error (Note 4) ● ±0.5 ±0.5 LSB Linearity Error (Notes 4, 5) ● ±0.5 ±0.5 LSB Full-Scale Error (Note 4) ● ±1.0 ±2.0 LSB Total Unadjusted Error V Reference Input Resistance LTC1092/LTC1093/LTC1094 ● 510 510 kΩ

Analog and REF Input Range (Note 7) (V–) –0.05V to VCC + 0.05V V On-Channel Leakage Current On-Channel = 5V ● 11µA

(Note 8) Off-Channel = 0V

Off-Channel Leakage Current On-Channel = 5V ● –1 –1 µA (Note 8) Off-Channel = 0V

= 5.000V (Notes 4, 6) ● ±1.0 LSB

REF

V

= 5V

REF

On-Channel = 0V ● –1 –1 µA Off-Channel = 5V

On-Channel = 0V ● 11µA Off-Channel = 5V

3

LTC1091/LTC1092 LTC1093/LTC1094

AC CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 3)

LTC1091A/LTC1092A/LTC1093A/LTC1094A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t

SMPL

t

CONV

t

dDO

t

dis

t

en

t

hDO

t

f

t

r

C

IN

Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles Conversion Time See Operating Sequence 10 CLK Cycles Delay Time, CLK↓ to D Delay Time, CS↑ to D Delay Time, CLK↓ to D Time Output Data Remains Valid After SCLK↓ 150 ns D

Fall Time See Test Circuits ● 90 300 ns

OUT

D

Rise Time See Test Circuits ● 60 300 ns

OUT

Input Capacitance Analog Inputs On-Channel 65 pF

Data Valid See Test Circuits ● 400 850 ns

OUT

Hi-Z See Test Circuits ● 180 450 ns

OUT

Enabled See Test Circuits ● 160 450 ns

OUT

LTC1091/LTC1092/LTC1093/LTC1094

Analog Inputs Off-Channel 5 pF Digital Inputs 5 pF

U

DIGITAL

A

DC

D

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IH

I

IL

V

OH

V

OL

I

OZ

I

SOURCE

I

SINK

I

CC

I

REF

–

I Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND,

GND and REF connected to the AGND pin on the LTC1093. DGND, AGND, REF are internally connected to the GND pin on the LTC1091/LTC1092.

Note 3: V –5V for bipolar mode, CLK = 0.5MHz unless otherwise specified.

Note 4: These specs apply for both unipolar (LTC1091/LTC1092/LTC1093/ LTC1094) and bipolar (LTC1093/LTC1094 only) modes. In bipolar mode, one LSB is equal to the bipolar input span (2V example, when V

Note 5: Linearity error is specified between the actual end points of the A/D transfer curve.

High Level Input Voltage VCC = 5.25V ● 2.0 V Low Level Input Voltage VCC = 4.75V ● 0.8 V High Level Input Current VIN = V Low Level Input Current VIN = 0V ● –2.5 µA High Level Output Voltage VCC = 4.75V, I

Low Level Output Voltage VCC = 4.75V, I Hi-Z Output Leakage V

Output Source Current V Output Sink Current V Positive Supply Current LTC1091, CS High ● 1.5 3.5 mA

Reference Current LTC1092/LTC1093/LTC1094, V Negative Supply Current LTC1093/LTC1094, CS High, V– = –5V ● 150µA

–

wired together (unless otherwise noted). REF– is internally

= 5V, V

CC

+

= 5V, V

REF

= 5V, 1LSB (bipolar) = 2(5V)/1024 = 9.77mV.

REF

LECTRICAL C CHARA TER ST

E

CC

= 10µA 4.7 V

= 4.75V, I

V

CC

= VCC, CS High ● 3 µA

OUT

V

= 0V, CS High ● –3 µA

OUT

= 0V –10 mA

OUT

= V

OUT

LTC1092/LTC1093/LTC1094, CS High, REF+ Open ● 1.0 2.5 mA

–

= 0V, V– = 0V for unipolar mode and

REF

OUT

= 360µA ● 2.4 4.0 V

OUT

= 1.6mA ● 0.4 V

OUT

CC

–

and V

) divided by 1024. For

= 5V ● 0.5 1.0 mA

REF

Note 6: Total unadjusted error includes offset, full scale, linearity, multiplexer and hold step errors.

Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop

–

below V VCC levels (4.5V), as high level reference or analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for inputs near full scale. This spec allows 50mV forward bias of either diode. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over initial tolerance, temperature variations and loading.

Note 8: Channel leakage current is measured after the channel selection.

or one diode drop above VCC. Be careful during testing at low

ICS

I

LTC1091A/LTC1092A/LTC1093A/LTC1094A LTC1091/LTC1092/LTC1093/LTC1094

● 2.5 µA

10 mA

4

LPER

LTC1091/LTC1092

LTC1093/LTC1094

UW

R

F

O

ATYPICA

CCHARA TERIST

E

C

ICS

Change in Offset Error vs Temperature

0.6 VCC (V

) = 5V

REF

= 500kHz

f

CLK

0.5

0.4

0.3

0.2

0.1

MAGNITUDE OF OFFSET CHANGE (LSB)

0

–50

–25

25

0

AMBIENT TEMPERATURE (°C)

50

Digital Input Logic Threshold vs Supply Voltage

4

TA = 25°C

3

2

LOGIC THRESHOLD (V)

1

0

4

678

5

SUPPLY VOLTAGE (V)

Maximum Clock Rate vs Temperature

3.0 VCC = 5V

2.5

75

1091/2/3/4 G01

1091/2/3/4 G04

125100

910

Change in Linearity Error vs Temperature

0.6 VCC (V

) = 5V

REF

= 500kHz

f

CLK

0.5

0.4

0.3

0.2

0.1

MAGNITUDE OF LINEARITY CHANGE (LSB)

DELAY TIME FROM SCLK↓ (ns)

OUT

D

600

500

400

300

200

100

0

–50

–25

D

Delay Time vs Temperature

OUT

VCC = 5V

MSB-FIRST DATA

LSB-FIRST DATA

–25

25

50

0

AMBIENT TEMPERATURE (°C)

25

0

AMBIENT TEMPERATURE (°C)

75

50

75

Maximum Clock Rate vs Supply Voltage

3.0 TA = 25°C

2.5

1091/2/3/4 G02

1091/2/3/4 G05

Change in Full-Scale Error vs Temperature

0.6 VCC (V

) = 5V

REF

= 500kHz

f

CLK

0.5

0.4

0.3

0.2

0.1

MAGNITUDE OF FULL-SCALE CHANGE (LSB)

125100

0

–50

–25

D

Delay Time vs

OUT

25

50

0

AMBIENT TEMPERATURE (°C)

75

125100

1091/2/3/4 G03

Supply Voltage

600

TA = 25°C

500

400

300

200

DELAY TIME FROM SCLK↓ (ns)

100

OUT

D

125100

0

4

MSB-FIRST DATA

LSB-FIRST DATA

678

5

SUPPLY VOLTAGE (V)

910

1091/2/3/4 G06

Minimum Clock Rate vs Temperature

0.3 VCC = 5V

0.25

2.0

1.5

1.0

0.5

MAXIMUM CLK FREQUENCY* (MHz)

0

–50

–25

*MAXIMUM CLK FREQUENCY REPRESENTS THE HIGHEST FREQUENCY AT WHICH CLK CAN

BE OPERATED (WITH 50% DUTY CYCLE) WHILE STILL PROVIDING 100ns SETUP TIME FOR THE DEVICE RECEIVING THE D

25

50

OUT

75

DATA.

0

AMBIENT TEMPERATURE (°C)

125100

1091/2/3/4 G07

2.0

1.5

1.0

0.5

MAXIMUM CLK FREQUENCY* (MHz)

0

4

678

5

SUPPLY VOLTAGE (V)

0.20

0.15

0.10

0.05

MINIMUM CLK FREQUENCY** (MHz)

910

1091/2/3/4 G08

**AS THE CLK FREQUENCY IS DECREASED FROM 500kHz, MINIMUM CLK FREQUENCY

(∆ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST DETECTED.

0

–50

0

–25

AMBIENT TEMPERATURE (°C)

25

50

75

1091/2/3/4 G09

5

125100

LTC1091/LTC1092

R

SOURCE

+

(Ω)

100 1k 10k

1091/2/3/4 G12

0.1

S & H ACQUISITION TIME TO 0.1% (µs)

1

10

+ –

V

IN

R

SOURCE

+

VCC = 5V T

A

= 25°C

0V TO 5V INPUT STEP

SUPPLY VOLTAGE (V)

4

LINEARITY ERROR [LSB = • V

CC

(V

REF

)]

1.25

1.00

0.75

0.5

0.25

0

5

678

1091/2/3/4 G15

910

f

CLK

= 500kHz

T

A

= 25°C

1

1024

LTC1093/LTC1094

LPER

R

F

O

ATYPICA

UW

CCHARA TERIST

E

C

ICS

LTC1091/LTC1092/LTC1093/LTC1094 Maximum Clock Rate vs Source Resistance

1.25

1.00

(MHz)

†

0.75

0.50

R

SOURCE

“+” OR “–” INPUT

V

0.25

MAXIMUM CLK FREQUENCY

0

IN

10

100 1k 10k

R

SOURCE

VCC = 5V T

(Ω)

LTC1091/LTC1092 Input Channel Leakage Current vs Temperature

100

ON-CHANNEL OR OFF-CHANNEL

80

60

= 25°C

A

1091/2/3/4 G10

LTC1091/LTC1092/LTC1093/LTC1094 Maximum Filter Resistor vs Cycle Time

100k

10k

(Ω)

††

FILTER

1k

100

MAXIMUM R

10

R

FILTER

V

C

FILTER

IN

≥1µF

+

–

10 1000 10000

100

CYCLE TIME (µs)

LTC1091 Offset Error vs Supply Voltage

1.25

)]

f

= 500kHz

CLK

= 25°C

T

REF

A

(V

1

CC

1024

1.00

0.75

OS

= 0.85mV AT VCC (V

V

REF

) = 5V

LTC1091/LTC1092/LTC1093/LTC1094 Sample-and-Hold Acquisition Time vs Source Resistance

1091/2/3/4 G11

LTC1091 Linearity Error vs Supply Voltage

40

20

INPUT CHANNEL LEAKAGE CURRENT (nA)

0

–50

–25

25

0

AMBIENT TEMPERATURE (°C)

LTC1091 Change in Full-Scale Error vs Supply Voltage

0.50 f

= 500kHz

CLK

= 25°C

T

A

0.25

)]

REF

(V

0

CC

1

–0.25

1024

[LSB = • V

–0.50

CHANGE IN FULL-SCALE ERROR

–0.75

4

†

AS THE CLK FREQUENCY AND SOURCE RESISTANCE ARE INCREASED, MAXIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 500kHz, 0Ω VALUE IS FIRST DETECTED.

6

678

5

SUPPLY VOLTAGE (V)

50

0.5

0.25

OFFSET ERROR [LSB = • V

75

125100

1091/2/3/4 G13

910

1091/2/3/4 G16

0

4

678

5

SUPPLY VOLTAGE (V)

LTC1091 Supply Current vs Supply Voltage

7

f

= 500kHz

CLK

CS = V

(V

6

T

= 25°C

A

5

4

3

2

SUPPLY CURRENT (mA)

1

0

4

5

)

CC

REF

678910

SUPPLY VOLTAGE (V)

††

MAXIMUM R CHANGE IN FULL-SCALE ERROR FROM ITS VALUE AT R

910

1091/2/3/4 G14

LTC1091 Supply Current vs Temperature

1.8

1.6

1.4

1.2

1.0

SUPPLY CURRENT (mA)

0.8

0.6 –50

1092/2/3/4 G17

REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB

FILTER

0

–25

AMBIENT TEMPERATURE (°C)

FILTER

f

CLK

V CS = 5V

25

50

= 0 IS FIRST DETECTED.

= 500kHz

(V

CC

75

) = 5V

REF

1091/2/3/4 G18

125100

LPER

LTC1091/LTC1092

LTC1093/LTC1094

UW

R

F

O

ATYPICA

CCHARA TERIST

E

C

ICS

LTC1092/LTC1093/LTC1094 Unadjusted Offset Error vs Reference Voltage

10

VCC = 5V

9

)

REF

8 7

1

1024

6 5 4 3 2

OFFSET ERROR (LSB = • V

1 0

0.1 0.2 1 5 10

VOS = 1mV

VOS = 0.5mV

REFERENCE VOLTAGE (V)

LTC1092/LTC1093/LTC1094 Noise Error vs Reference Voltage

2.00 NOISE = 200µV

1.75

1.50

1.25

1.00

0.75

0.50

PEAK-TO-PEAK NOISE ERROR (LSB)

0.25

0

0.1 0.2 1 5 10

P-P

REFERENCE VOLTAGE (V)

LTC1092/LTC1093/LTC1094 Change in Full-Scale Error vs Supply Voltage

0.50 V

= 4V

REF

= 500kHz

f

CLK

0.25

0

–0.25

–0.50

CHANGE IN FULL-SCALE ERROR (LSB)

–0.75

4

678

5

SUPPLY VOLTAGE (V)

1091/2/3/4 G19

1091/2/3/4 G22

910

1091/2/3/4 G25

LTC1092/LTC1093/LTC1094 Linearity Error vs Reference Voltage

1.25

1.00

1024

0.75

0.50

0.25

0

VCC = 5V

0

1

2

REFERENCE VOLTAGE (V)

)

REF

1

LINEARITY ERROR (LSB = • V

LTC1092/LTC1093/LTC1094 Offset Error vs Supply Voltage

1.25 V

= 4V

REF

= 500kHz

f

CLK

= 1.25mV AT VCC = 5V

V

OS

1.00

0.75

0.50

OFFSET ERROR (LSB)

0.25

0

4

678

5

SUPPLY VOLTAGE (V)

LTC1092/LTC1093/LTC1094 Supply Current vs Supply Voltage

6

V

OPEN

REF

= 500kHz

f

CLK

5

CS = V

CC

TA = 25°C

4

3

2

SUPPLY CURRENT (mA)

1

0

4

678

5

SUPPLY VOLTAGE (V)

3

4

5

1092/2/3/4 G20

910

1091/2/3/4 G23

910

1091/2/3/4 G26

LTC1092/LTC1093/LTC1094 Change in Full-Scale Error vs Reference Voltage

)

1.25

REF

1

CHANGE IN FULL-SCALE ERROR (LSB = • V

1024

1.00

0.75

0.50

0.25

0

VCC = 5V

1

REFERENCE VOLTAGE (V)

3

2

LTC1092/LTC1093/LTC1094 Linearity Error vs Supply Voltage

1.25 V

= 4V

REF

= 500kHz

f

CLK

1.00

0.75

0.50

LINEARITY ERROR (LSB)

0.25

0

4

678

5

SUPPLY VOLTAGE (V)

LTC1092/LTC1093/LTC1094 Supply Current vs Temperature

1.4

1.2

1.0

0.8

0.6

SUPPLY CURRENT (mA)

0.4

0.2 –50

0

–25

AMBIENT TEMPERATURE (°C)

25

V

REF

f

CLK

CS = 5V V

CC

50

75

4

1092/2/3/4 G21

910

1091/2/3/4 G24

OPEN

= 500kHz

= 5V

1091/2/3/4 G27

5

125100

7

LTC1091/LTC1092 LTC1093/LTC1094

LPER

R

F

O

ATYPICA

UW

CCHARA TERIST

E

C

ICS

LTC1092/LTC1093/LTC1094 Reference Current vs Temperature

0.6

0.5

0.4

0.3

0.2

REFERENCE CURRENT (mA)

0.1

0

–50

U

25

0

–25

AMBIENT TEMPERATURE (°C)

UU

V

= 5V

REF

50

75

125100

1091/2/3/4 G28

PI FU CTIO S

LTC1091/LTC1092

CS (Pin 1): Chip Select Input. A logic low on this input

enables the LTC1091/LTC1092. CH0, CH1/+ IN, – IN (Pins 2, 3): Analog Inputs. These

inputs must be free of noise with respect to GND.

LTC1093/LTC1094 Input Channel Leakage Current vs Temperature

1000

900 800 700 600 500 400 300 200 100

INPUT CHANNEL LEAKAGE CURRENT (nA)

0

–50

0

–25

AMBIENT TEMPERATURE (°C)

GUARANTEED

ON-CHANNEL

OFF-CHANNEL

75

50 125

25

100

1091/2/3/4 G29

VCC (Pin 8 )(LTC1092): Positive Supply Voltage. This pin provides power to the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane.

GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane.

DIN (Pin 5)(LTC1091): Digital Data Input. The multiplexer address is shifted into this input.

V

(Pin 5)(LTC1092): Reference Input. The reference

REF

input defines

the span of the A/D converter and must be

kept free of noise with respect to AGND.

D

(Pin 6): Digital Data Output. The A/D conversion

OUT

result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial

data transfer.

VCC(V

)(Pin 8)(LTC1091): Positive Supply and Refer-

REF

ence Voltage. This pin provides power and defines the span of the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane.

LTC1093/LTC1094

CH0 to CH5/CH0 to CH7 (Pins 1 to 6/Pins 1 to 8): Analog

Inputs. The analog inputs must be free of noise with respect to AGND.

COM (Pin 7/Pin 9): Common. The common pin defines the zero reference point for all single-ended inputs. It must be free of noise and is usually tied to the analog ground plane.

DGND (Pin 8/Pin 10): Digital Ground. This is the ground for the internal logic. Tie to the ground plane.

V– (Pin 9/Pin 11): Negative Supply. Tie V– to most negative potential in the circuit. (Ground in single supply applications.)

AGND (Pin 10/Pin 12): Analog Ground. AGND should be tied directly to the analog ground plane.

8

LTC1091/LTC1092

LTC1093/LTC1094

U

UU

PI FU CTIO S

V

(Pin 11)(LTC1093): Reference Input. The reference

REF

input must be kept free of noise with respect to AGND. REF+, REF– (Pins 13, 14 )(LTC1094): Reference Input.

The reference input must be kept free of noise with respect to AGND.

DIN (Pin 12/Pin 15): Data Input. The A/D configuration word is shifted into this input.

D

(Pin 13/Pin 16): Digital Data Output. The A/D con-

OUT

version result is shifted out of this output. CS (Pin 14/Pin 17): Chip Select Input. A logic low on this

input enables the LTC1093/LTC1094.

W

BLOCK DIAGRA

(Pin numbers refer to LTC1094)

CLK (Pin 15/Pin 18): Shift Clock. This clock synchronizes

the serial data transfer. VCC (Pin 16)(LTC1093): Positive Supply. This supply

must be kept free of noise and ripple by bypassing directly to the analog ground plane.

AVCC, DVCC (Pins 19, 20)(LTC1094): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. AVCC and DVCC should be tied together on the LTC1094.

AV

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

COM

DV

CC

19

18

16

17

1091/2/3/4 BD

CLK

D

CS

OUT

20

CC

INPUT

REGISTER

ANALOG

INPUT MUX

10

DGND

SHIFT

SAMPLE-

AND-HOLD

11 12 13 14

–

V

AGND

COMP

CAPACITIVE

–

REF

10-BIT

DAC

REF

+

15

D

IN

1 2 3 4 5 6 7 8 9

OUTPUT

SHIFT

REGISTER

10-BIT

SAR

CONTROL

AND

TIMING

9

LTC1091/LTC1092

D

OUT

WAVEFORM 1

(SEE NOTE 1)

2.0V

t

dis

90%

10%

D

OUT

WAVEFORM 2

(SEE NOTE 2)

CS

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL

1091/2/3/4 TC06

LTC1093/LTC1094

TEST CIRCUITS

On- and Off-Channel Leakage Current

5V

POLARITY

Voltage Waveforms for D

D

CLK

OUT

0.8V t

dDO

Load Circuit for t

I

ON

A

I

OFF

A

ON-CHANNEL

OFFCHANNELS

1091/2/3/4 TC01

D

OUT

Voltage Waveforms for D

Delay Time, t

OUT

dDO

2.4V

D

OUT

t

r

1.4V

OUT

Voltage Waveforms for t

0.4V

1091/2/3/4 TC03

, tr, t

dDO

3k

100pF

f

TEST POINT

1091/2/3/4 TC02

Rise and Fall Times, tr, t

2.4V

0.4V

t

f

1091/2/3/4 TC04

dis

f

Load Circuit for t

TEST POINT

D

CLK

OUT

3k

100pF

CS

IN

LTC1091

D

OUT

dis

, t

5V t

START

en

WAVEFORM 2, t

dis

t

WAVEFORM 1

dis

1

en

1091/2/3/4 TC05

Voltage Waveforms for t

2

34

en

B9

0.4V

t

en

1091/2/3/4 TC07

10

TEST CIRCUITS

LTC1091/LTC1092

LTC1093/LTC1094

CS

D

IN

CLK

D

OUT

START

Voltage Waveforms for t

LTC1092

CS

CLK

D

OUT

1

2

4

en

1

0.4V

t

en

563

B9

1091/2/3/4 TC08

7

B9

0.4V

t

en

1091/2/3/4 TC09

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

The LTC1091/LTC1092/LTC1093/LTC1094 are data acquisiton components that contain the following functional blocks:

1. 10-Bit Successive Approximation A/D Converter

2. Analog Multiplexer (MUX)

3. Sample-and-Hold (S/H)

4. Synchronous, Half-Duplex Serial Interface

5. Control and Timing Logic

DIGITAL CONSIDERATIONS

1. Serial Interface

The LTC1091/LTC1093/LTC1094 communicate with microprocessors and other external circuitry via a synchronous, half-duplex, 4-wire serial interface while the LTC1092 uses a 3-wire interface (see Operating Sequence). The clock (CLK) synchronizes the data transfer with each bit being transmitted on the falling CLK edge and captured on the rising CLK edge in both transmitting and receiving

systems. The LTC1091/LTC1093/LTC1094 first receive input data and then transmit back the A/D conversion result (half-duplex). Because of the half-duplex operation, DIN and D over just three wires: CS, CLK and DATA (DIN/D

may be tied together allowing transmission

OUT

).

Data transfer is initiated by a falling chip select (CS) signal. After CS falls, the LTC1091/LTC1093/LTC1094 looks for a start bit. After the start bit is received, a 3-bit input word (6 bits for the LTC1093/LTC1094) is shifted into the D

IN

input which configures the LTC1091/LTC1093/LTC1094 and starts the conversion. After one null bit, the result of the conversion is output on the D

line. At the end of the

OUT

data exchange, CS should be brought high. This resets the LTC1091/LTC1093/LTC1094 in preparation for the next data exchange.

The LTC1092 does not require a configuration input word and has no DIN pin. A falling CS initiates data transfer as shown in the LTC1092 Operating Sequence. After CS falls,

11

LTC1091/LTC1092 LTC1093/LTC1094

U

O

PPLICATI

A

CS

DIN 1 DIN 2

SHIFT MUX

ADDRESS IN

1 NULL BIT

the first CLK pulse enables D

S

I FOR ATIO

D

1

OUT

SHIFT A/D CONVERSION RESULT OUT

. After one null bit, the A/D

OUT

conversion result is output on the D

WU

D

2

OUT

line. Bringing CS

OUT

U

1091/2/3/4 AI01

high resets the LTC1092 for the next data exchange.

2. Input Data Word

The LTC1092 requires no DIN word. It is permanently configured to have a single differential input and to operate in unipolar mode. The conversion result is output on the D

line in MSB-first sequence, followed by LSB-first

OUT

sequence, providing easy interface to MSB- or LSB-first serial ports. The following disussion applies to the configuration of the LTC1091/LTC1093/LTC1094.

The LTC1091/LTC1093/LTC1094 clock data into the D

IN

input on the rising edge of the clock. The input data words are defined as follows:

LTC1091 DATA INPUT (D

START

LTC1093/LTC1094 DATA INPUT (D

START

SGL/

DIFF

MUX ADDRESS

SGL/

DIFF

) WORD:

IN

ODD/ SIGN

MSB-FIRST/

LSB-FIRST

IN

SELECT

ODD/ SIGN

MUX ADDRESS

MSBF

)WORD:

1

SELECT

0

UNIPOLAR/

BIPOLAR

UNI

MSBF

1091/2/3/4 AI02

MSB-FIRST/

LSB-FIRST

MSB-First Data (MSBF = 1)

CS

CLK

SGL/

DIFF

ODD/SIGN

MSBF

t

SMPL

D

IN

D

OUT

START

Hi-Z

LSB-First Data (MSBF = 0)

CS

CLK

START

Hi-Z

ODD/SIGN

SGL/

DIFF

MSBF

t

SMPL

D

IN

D

OUT

LTC1091 Operating Sequence

Example: Differential Inputs (CH1+, CH0–)

t

CYC

DON’T CARE

B1B9 B0

FILLED WITH ZEROS

t

CONV

t

CYC

DON’T CARE

B1B9 B0 B1 B9

t

CONV

FILLED WITH

ZEROS

Hi-Z

1091/2/3/4 AI03

Hi-Z

1091/2/3/4 AI04

12

LTC1091/LTC1092

LTC1093/LTC1094

U

O

PPLICATI

A

CS

CLK

Hi-Z

D

OUT

t

SMPL

S

B9 B9

MSB-First Data (MSBF = 1)

CS

WU

I FOR ATIO

B1

t

CONV

LTC1093/LTC1094 Operating Sequence

Example: Differential Inputs (CH4+, CH5–), Unipolar Mode

U

LTC1092 Operating Sequence

t

CYC

B0 B1

t

CYC

SMPL

1091/2/3/4 AI05

CLK

ODD/ SIGN

SEL1

D

IN

D

OUT

START

Hi-Z

SGL/ DIFF

LSB-First Data (MSBF = 0)

CS

CLK

SEL1

ODD/ SIGN

D

OUT

START

IN

SGL/

Hi-Z

DIFF

Hi-Z

SEL0

UNI

MSBF

t

SMPL

MSBF

t

SMPL

t

CONV

t

CONV

t

CYC

DON’T CARE

B1B9 B0

DON’T CARE

B1B9 B0

FILLED WITH ZEROS

B9B1

FILLED WITH

ZEROS

Hi-Z

1091/2/3/4 AI06

Hi-Z

1091/2/3/4 AI07

13

LTC1091/LTC1092 LTC1093/LTC1094

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

Start Bit

The first “logical one” clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer. The LTC1091/LTC1093/LTC1094 will ignore all leading zeros which precede this logical one. After the start bit is received, the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle.

Multiplexer (MUX) Address

The bits of the input word following the START bit assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the

LTC1093 Channel Selection

MUX ADDRESS

SGL/

DIFF

0 0 0 0 0 0 0 0

ODD/ SIGN

0 0 0 0 1 1 1 1

SELECT 1

0 0 1 1 0 0 1 1

DIFFERENTIAL CHANNEL SELECTION

0

1

2

0

+

0 1 0 1 0 1 0 1

–

+

3

+

–

NOT USED

–

+

NOT USED

4

5

+

–

+

voltage between the two channels indicated by the + and – signs in the selected row of the following tables. In single-ended mode, all input channels are measured with respect to GND on the LTC1091 and COM on the LTC1093/LTC1094.

LTC1091 Channel Selection

MUX ADDRESS CHANNEL # GND SGL/

DIFF

SINGLE-ENDED

MUX MODE

DIFFERENTIAL

MUX MODE

LTC1094 Channel Selection

MUX ADDRESS

ODD/ SIGN

0 0 0 0 1 1 1 1

SELECT

1

0 0 1 1 0 0 1 1

0

0 1 0 1 0 1 0 1

SGL/ DIFF

0 0 0 0 0 0 0 0

ODD/

1

SIGN

1 1 0 0

0 1 0 1

DIFFERENTIAL CHANNEL SELECTION

0

1

+

–

+

0

+

+ –

+

–

2

3

4

+

–

+

–

+

–

5

–

+

– –

1091-4 AI08

6

+

–

7

–

+

MUX ADDRESS

SGL/

DIFF

1 1 1 1 1 1 1 1

14

ODD/ SIGN

0 0 0 0 1 1 1 1

SELECT

1

0 0 1 1 0 0 1 1

SINGLE-ENDED CHANNEL SELECTION

0

0 1 0 1 0 1 0 1

0+1+2

3+4+5

+

NOT USED

MUX ADDRESS

ODD/ SIGN

0 0 0 0 1 1 1 1

SELECT

1

0 0 1 1 0 0 1 1

SGL/

COM

– – –

+

1091-4 AI09

DIFF

1 1 1 1 1 1 1 1

SINGLE-ENDED CHANNEL SELECTION

0

0 1 0 1 0 1 0 1

0+1+2

3+4+5+6+7

+

COM

– – – – – – – –

+

1091-4 AI0

LTC1091/LTC1092

LTC1093/LTC1094

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

MSB-First/LSB-First (MSBF)

The output data of the LTC1091/LTC1093/LTC1094 is programmed for MSB-first or LSB-first sequence using the MSBF bit. When the MSBF bit is a logical one, data will appear on the D

line in MSB-first format. Logical zeros

OUT

will be filled in indefinitely following the last data bit to accommodate longer word lengths required by some microprocessors. When the MSBF bit is a logical zero, LSB-first data will follow the normal MSB-first data on the D

line. (See operating sequence).

OUT

Unipolar/Bipolar (UNI)

The UNI bit of the LTC1093/LTC1094 determines whether the conversion will be unipolar or bipolar. When UNI is a logical one, a unipolar conversion will be performed on the selected input voltage. When UNI is a logical zero, a bipolar conversion will result. The input span and code assignment for each conversion type are shown in the figures below.

The LTC1091/LTC1092 are permanently configured for unipolar mode.

Unipolar Transfer Curve (UNI = 1)

Unipolar Output Code (UNI = 1)

INPUT VOLTAGE

(V

OUTPUT CODE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

•

• 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

INPUT VOLTAGE

V

– 1LSB

REF

V

– 2LSB

REF

•

1LSB

0V

= 5V)

REF

4.9951V

4.9902V

•

0.0049V 0V

1091-4AI13

Bipolar Output Code (UNI = 0) LTC1093/LTC1094 Only

OUTPUT CODE

0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0

•

• 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

•

• 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

INPUT VOLTAGE

V

– 1LSB

REF

V

– 2LSB

REF

•

1LSB

0V –1LSB –2LSB

•

–(V

) + 1LSB

REF

–(V

)

REF

INPUT VOLTAGE

(V

= 5V)

REF

4.9902V

4.9805V

•

0.0098V 0V

–0.0098V –0.0195V

•

–4.9902V

–5.000V

1091-4AI14

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

V

1LSB

0V

REF

– 2LSB

V

REF

– 1LSB

V

REF

V

1091-4 AI11

IN

Bipolar Transfer Curve (UNI = 0) LTC1093/LTC1094 Only

0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0

–V

+ 1LSB

REF

–V

REF

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

–1LSB

–2LSB

1LSB

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

V

– 2LSB

REF

V

REF

– 1LSB

V

REF

IN

1091-4 AI12

15

LTC1091/LTC1092 LTC1093/LTC1094

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

3. Accommodating Microprocessors with Different Word Lengths

The LTC1091/LTC1093/LTC1094 will fill zeros indefinitely after the transmitted data until CS is brought high. At that time the D

line is disabled. This makes interfacing easy

OUT

to MPU serial ports with different transfer increments including 4 bits (e.g., COP400) and 8 bits (e.g., SPI and MICROWIRE/PLUSTM). Any word length can be accommodated by the correct positioning of the start bit in the LTC1091 input word.

Figure 1 shows examples of LTC1091 input and output words for 4-bit and 8-bit processors. A complete data exchange can be implemented with two 4-bit MPU outputs and three inputs in 4-bit systems and one 8-bit output and two inputs in 8-bit systems. The resulting data winds up left justified in the MPU with zeros automatically filled in the unused low order bits by the LTC1091. In section 5 another example is given using the MC68HC05C4 which

eliminates one 8-bit transfer and positions data right justified inside the MPU.

4. Operation with DIN and D

Tied Together

OUT

The LTC1091/LTC1093/LTC1094 can be operated with DIN and D

tied together. This eliminates one of the lines

OUT

required to communicate to the MPU. Data is transmitted in both directions on a single wire. The processor pin connected to this data line should be configurable as either an input or an output. The LTC1091, for example, will take control of the data line and drive it low on the 4th falling CLK edge after the start bit is received (see Figure 2). Therefore, the processor port line must be switched to an input before this happens, to avoid a conflict.

In the next section, an example is made of interfacing the LTC1091 with DIN and D

tied together to the Intel

OUT

8051 MPU.

4-BIT

TRANSFERS

8-BIT

TRANSFERS

CS

CLK

START

SGL/ DIFF

ODD/ SIGN

MSBF

MSBF X

• • •

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0

D

OUT

MPU SENDS

2 D

WORDS

IN

MPU READS BACK

3 D

WORDS

OUT

MPU SENDS

1 D

WORD

IN

MPU READS BACK

2 D

WORDS

OUT

D

IN

START

0 0 0 1

START

0 0 0 1

Hi-Z

BIT

Figure 1. LTC1091 Input and Output Word Arrangements for 4-Bit and 8-Bit Serial Port Microprocessors

FILL ZEROS

X = DON’T CARE

1091/2/3/4 F01

MICROWIRE/PLUS is a trademark of National Semiconductor Corp.

16

LTC1091/LTC1092

LTC1093/LTC1094

PPLICATI

A

DATA (DIN/D

CLK

OUT

U

O

S

I FOR ATIO

CS

)

WU

12

START

MPU CONTROLS

DATA LINE AND SENDS

MUX ADDRESS TO LTC1091

RISING CLK AND BEFORE

U

34

SGL/ DIFF

ODD/ SIGN

PROCESSOR

MUST RELEASE

DATA LINE AFTER 4TH THE 4TH FALLING CLK

MSBF

LATCHED

BY LTC1091

MSBF B9 B8 • • •

Figure 2. LTC1091 Operation with DIN and D

LTC1091 CONTROLS

DATA LINE AND SENDS

A/D RESULT BACK TO MPU

LTC1091 TAKES CONTROL OF DATA LINE ON 4TH FALLING CLK

Tied Together

OUT

1091/2/3/4 F02

5. Microprocessor Interfaces

The LTC1091/LTC1092/LTC1093/LTC1094 can interface directly (without external hardware) to most popular microprocessor (MPU) synchronous serial formats (see Table 1). If an MPU without a dedicated serial port is used, then three or four of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1091/ LTC1092/LTC1093/LTC1094. Included here are one serial interface example and one example showing a parallel port programmed to form the serial interface.

Table 1. Microprocessors with Hardware Serial Interfaces Compatible with the LTC1091/LTC1092/LTC1093/LTC1094

PART NUMBER TYPE OF INTERFACE

Motorola

MC6805S2, S3 SPI MC68HC11 SPI MC68HC05 SPI

RCA

CDP68HC05 SPI

Hitachi

HD6305 SCI Synchronous HD63705 SCI Synchronous HD6301 SCI Synchronous HD63701 SCI Synchronous HD6303 SCI Synchronous HD64180 CSI/O

National Semiconductor

COP400 Family MICROWIRE COP800 Family MICROWIRE/PLUS NS8050U MICROWIRE/PLUS HPC16000 Family MICROWIRE/PLUS

Texas Instruments

TMS7002 Serial Port TMS7042 Serial Port TMS70C02 Serial Port TMS70C42 Serial Port TMS32011* Serial Port TMS32020 Serial Port

*Requires external hardware

MICROWIRE is a trademark of National Semiconductor Corp.

TM

17

LTC1091/LTC1092 LTC1093/LTC1094

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

Motorola SPI (MC68HC05C4, MC68HC11)

The MC68HC05C4 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSB first and in 8-bit increments. With two 8-bit transfers, the A/D result is read into the MPU. The first 8-bit transfer sends the DIN word to the LTC1091 and clocks B9 and B8 of the A/D conversion result into the processor. The

Data Exchange Between LTC1091 and MC68HC05C4

START

MPU TRANSMIT

WORD

D

BIT

START

SGL/ DIFF

0 1

CS

IN

BYTE 1

ODD/

MSBF X X X

SIGN

ODD/

MSBF

SIGN

second 8-bit transfer clocks the remaining bits, B7 through B0, into the MPU.

ANDing the first MPU received byte with 03 Hex clears the six most significant bits. Notice how the position of the start bit in the first MPU transmit word is used to position the A/D result right justified in two memory locations.

BYTE 2 (DUMMY)

X X

X X X X X X

X = DON’T CARE

DON’T CARE

ANALOG

INPUTS

LOCATION A + 1

CLK

D

OUT

BYTE 1

MPU RECEIVED

WORD

? ?

? ? ? 0 B9 B8

1ST TRANSFER

Hardware and Software Interface to

Motorola MC68HC05C4 Processor

CS

LTC1091

D

from LTC1091 Stored in MC68HC05C4 RAM

OUT

LOCATION A

CLK

D

IN

D

OUT

0 0 0 0 0 0 B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

CO SCK MOSI MISO

MSB

MC68HC05C4

1091-4 AI16

BYTE 1

LSB

BYTE 2

B9

B8 B7 B6 B5 B4 B3 B2 B1 B0

BYTE 2

B7 B6

LABEL MNEMONIC COMMENTS

START BCLRn Bit 0 Port C Goes Low (CS Goes Low)

B5 B4 B3 B2 B1 B0

2ND TRANSFER

LDA Load LTC1090 D STA Load LTC1090 D

Transfer Begins TST Test Status of SPIF BPL Loop to Previous Instruction If Not Done

with Transfer LDA Load contents of SPI Data Register into

Acc (D STA Start Next SPI Cycle AND Clear 6 MSBs of First D STA Store in Memory Location A (MSBs) TST Test Status of SPIF BPL Loop to Previous Instruction If Not Done

with Transfer BSETn Set B0 of Port C (CS Goes High) LDA Load contents of SPI Data Register into

Acc (D STA Store in Memory location A + 1 (LSBs)

OUT

Word into Acc

IN

Word into SPI from Acc

IN

MSBs)

OUT

LSBs)

1091/2/3/4 AI15

Word

18

LTC1091/LTC1092

LTC1093/LTC1094

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

Interfacing to the Parallel Port of the Intel 8051 Family

The Intel 8051 has been chosen to demonstrate the interface between the LTC1091 and parallel port microprocessors. Normally, the CS, SCLK and DIN signals would be generated on three port lines and the D

OUT

signal read on a 4th port line. This works very well. However, we will demonstrate here an interface with the DIN and D

OUT

of the LTC1091 tied together as described in section 4. This saves one wire.

The 8051 first sends the start bit and MUX address to the LTC1091 over the data line connected to P1.2. Then P1.2 is reconfigured as an input (by writing to it a one) and the 8051 reads back the 10-bit A/D result over the same data line.

P1.4 P1.3 P1.2

8051

1091-4 AI17

ANALOG

INPUTS

CS

CLK

D

OUT

D

MUX ADDRESS

IN

A/D RESULT

from LTC1091 Stored in 8051 RAM

MSB

B9 B8 B7 B6 B5 B4 B3 B2

LSB

B1 B0 0 0 0 0 0 0

D

LTC1091

OUT

R2

R3

LABEL MNEMONIC OPERAND COMMENTS

MOV A, #FFH DIN Word for LTC1091 SETB P1.4 Make Sure CS Is High CLR P1.4 CS Goes Low MOV R4, #04 Load Counter

LOOP 1 RLC A Rotate DIN Bit into Carry

CLR P1.3 SCLK Goes Low MOV P1.2, C Output D SETB P1.3 SCLK Goes High DJNZ R4, LOOP 1 Next Bit MOV P1, #04 Bit 2 Becomes an Input CLR P1.3 SCLK Goes Low MOV R4, #09 Load Counter

LOOP MOV C, P1.2 Read Data Bit into Carry

RLC A Rotate Data Bit into Acc SETB P1.3 SCLK Goes High CLR P1.3 SCLK Goes Low DJNZ R4, LOOP Next Bit MOV R2, A Store MSBs in R2 MOV C, P1.2 Read Data Bit into Carry SETB P1.3 SCLK Goes High CLR P1.3 SCLK Goes Low CLR A Clear Acc RLC A Rotate Data Bit from Carry to Acc MOV C, P1.2 Read Data Bit into Carry RRC A Rotate Right into Acc RRC A Rotate Right into Acc MOV R3, A Store LSBs in R3 SETB P1.4 CS Goes High

Bit to LTC1091

IN

DATA (DIN/D

CS

CLK

)

OUT

START

8051 P1.2 OUTPUTS

DATA TO LTC1091

8051 P1.2 RECONFIGURED AS AN

INPUT AFTER THE 4TH RISING CLK

AND BEFORE THE 4TH FALLING CLK

12

SGL/

ODD/

DIFF

SIGN

MSBF BIT LATCHED

INTO LTC1091

3

4

MSBF

B9

B8 B7

LTC1091 TAKES CONTROL OF DATA LINE ON 4TH FALLING CLK

B6

LTC1091 SENDS A/D RESULT

BACK TO 8051 P1.2

B5 B4 B3

B2

B1 B0

1091/2/3/4 AI18

19

LTC1091/LTC1092 LTC1093/LTC1094

PPLICATI

A

U

O

S

I FOR ATIO

OUTPUT PORT

Figure 3. Several LTC1094s Sharing One 3-Wire Serial Interface

WU

2

10

SERIAL DATA

MPU

U

3

CS

LTC1094

8 CHANNELS

Sharing the Serial Interface

The LTC1094 can share the same 2- or 3-wire serial interface with other peripheral components or other LTC1094s (see Figure 3). In this case, the CS signals decide which LTC1094 is being addressed by the MPU.

ANALOG CONSIDERATIONS

1. Grounding

The LTC1091/LTC1092/LTC1093/LTC1094 should be used with an analog ground plane and single point grounding techniques.

The AGND pin (GND on the LTC1091/LTC1092) should be tied directly to this ground plane.

The DGND pin of the LTC1093/LTC1094 can also be tied directly to this ground plane because minimal digital noise is generated within the chip itself.

3-WIRE SERIAL

33

LTC1094

8 CHANNELS 8 CHANNELS

3

CS

LTC1094

INTERFACE TO OTHER PERIPHERALS OR LTC1094s

CS

LTC1091-4 F03

Figure 4 shows an example of an ideal LTC1091 ground plane design for a 2-sided board. Of course, this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible.

2. Bypassing

For good performance, VCC must be free of noise and ripple. Any changes in the VCC voltage with respect to analog ground during a conversion cycle can induce errors or noise in the output code. Because the VCC (V

REF

pin of the LTC1091 defines the voltage span of the A/D converter, its bypassing is especially important. VCC noise and ripple can be kept below 1mV by bypassing the VCC pin directly to the analog ground plane with a 4.7µF tantalum with leads as short as possible. AVCC and DVCC should be tied together on the LTC1094. Figures 5 and 6 show the effects of good and poor VCC bypassing.

)

The V

pin should be bypassed to the ground plane with

CC

a 4.7µF tantalum with leads as short as possible. AVCC and DVCC should be tied together on the LTC1094. The V– pin (LTC1093/LTC1094) should be bypassed with a 0.1µF ceramic disk. For single supply applications, V– can be tied to the ground plane.

It is also recommended that the REF– pin and the COM pin be tied directly to the ground plane. All analog inputs should be referenced directly to the single point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry.

20

4.7µF

V

TANTALUM

1 2 3 4

Figure 4. Example Ground Plane for the LTC1091

CC

S

8 7 6 5

LTC1091-4 F04

LTC1091/LTC1092

LTC1093/LTC1094

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

3. Analog Inputs

Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1091/ LTC1092/LTC1093/LTC1094 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. However, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to ensure that the transients caused by the current spikes settle completely before the conversion begins.

Source Resistance

The analog inputs of the LTC1091/LTC1092/LTC1093/ LTC1094 look like a 60pF capacitor (CIN) in series with a 500Ω resistor (RON) as shown in Figure 7.

CIN gets switched between the selected “+” and “–” inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of

the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within the allowed time.

0.5mV/DIV

10µs/DIV

1091-4 F05

Figure 5. Poor VCC Bypassing. Noise and Ripple Can Cause A/D Errors

0.5mV/DIV

“+” Input Settling

This input capacitor is switched onto the “+” input during the sample phase (t

, see Figure 8). The sample phase

SMPL

is the 1 1/2 CLK cycles before the conversion starts. The voltage on the “+” input must settle completely within this sample time. Minimizing R

SOURCE

+

and C1 will improve the input settling time. If large “+” input source resistance must be used, the sample time can be increased by using a slower CLK frequency. With the minimum possible sample time of 3µs, R

SOURCE

+

< 2k and C1 < 20pF will

provide adequate settling.

10µs/DIV

Figure 6. Good VCC Bypassing Keeps Noise and Ripple on VCC Below 1mV

“+”

INPUT

+

R

SOURCE

+

V

IN

C1

“–”

INPUT

–

R

SOURCE

–

V

IN

C2

Figure 7. Analog Input Equivalent Circuit

3RD CLK↑

R

ON

4TH CLK↓

= 500Ω

1091-4 F06

LTC1091

C

IN

60pF

LTC091-4 F07

=

21

LTC1091/LTC1092 LTC1093/LTC1094

PPLICATI

A

“–” Input Settling

U

O

S

I FOR ATIO

WU

U

At the end of the sample phase the input capacitor switches to the “–” input and the conversion starts (see Figure 8). During the conversion, the “+” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. However, it is critical that the “–” input voltage settle completely during the first CLK cycle of the conversion time and be free of noise. Minimizing R

SOURCE

–

and C2 will improve settling time. If large “–” input source resistance must be used, the time allowed for settling can be extended by using a slower CLK frequency. At the maximum CLK rate of 500kHz, R

SOURCE

–

< 1kΩ and

C2 < 20pF will provide adequate settling.

CS

Input Op Amps

When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figure 8). Again, the “+” and “–” input sampling times can be extended as previously described to accommodate slower op amps. Most op amps, including the LT1006 and LT1013 single supply op amps, can be made to settle well even with the minimum settling windows of 3µs (“+” input) and 2µs (“–” input) which occur at the maximum clock rate of 500kHz. Figures 9 and 10 show examples of adequate and poor op amp settling.

SAMPLE HOLD

“+” INPUT MUST SETTLE DURING

THIS TIME

t

SMPL

t

CONV

CLK

D

OUT

“+” INPUT

“–” INPUT

IN

Figure 8. “+” and “–” Input Settling Windows

SGL/DIFFSTART MSBF

1ST BIT TEST “–” INPUT MUST

SETTLE DURING THIS TIME

DON‘T CARE

B9

1091-4 F08

22

LTC1091/LTC1092

LTC1093/LTC1094

U

O

PPLICATI

A

5mV/DIV

Figure 9. Adequate Settling of Op Amp Driving Analog Input

5mV/DIV

Figure 10. Poor Op Amp Settling Can Cause A/D Errors

S

I FOR ATIO

1µs/DIV

20µs/DIV

WU

1091-4 F09

1091-4 F10

U

resistor must be used, errors can be eliminated by increasing the cycle time as shown in the typical curve of Maximum Filter Resistor vs Cycle Time.

Input Leakage Current

Input leakage currents can also create errors if the source resistance gets too large. For instance, the maximum input leakage specification of 1µA (at 125°C) flowing through a source resistance of 1kΩ will cause a voltage drop of 1mV or 0.2LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see the typical curve of Input Channel Leakage Current vs Temperature).

4. Sample-and-Hold

Single-Ended Inputs

The LTC1091/LTC1093/LTC1094 provide a built-in sampleand-hold (S&H) function for all signals acquired in the singleended mode. This sample-and-hold allows conversion of rapidly varying signals (see typical curve of S&H Acquisition Time vs Source Resistance). The input voltage is sampled during the t

time as shown in Figure 8. The sampling

SMPL

interval begins as the bit preceding the MSBF bit is shifted in and continues until the falling CLK edge after the MSBF bit is received. On this falling edge, the S&H goes into hold mode and the conversion begins.

RC Input Filtering

It is possible to filter the inputs with an RC network as shown in Figure 11. For large values of CF (e.g., 1µF), the capacitive input switching currents are averaged into a net DC current. Therefore, a filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = (60pF)(VIN/t

) and is roughly proportional to VIN.

CYC

When running at the minimum cycle time of 32µs, the input current equals 9µA at VIN = 5V. In this case, a filter resistor of 50Ω will cause 0.1LSB of full-scale error. If a larger filter

I

FILTER

DC

“+”

C

FILTER

“–”

R

V

IN

Figure 11. RC Input Filtering

LTC1091

1091-4 F11

23

LTC1091/LTC1092 LTC1093/LTC1094

PPLICATI

A

Differential Inputs

U

O

S

I FOR ATIO

WU

U

With differential inputs, the A/D no longer converts just a single voltage but rather the difference between two voltages. In this case, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. However, the voltage on the selected “–” input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the differencing operation may not be performed accurately. The conversion time is 10 CLK cycles. Therefore, a change in the “–” input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the “–” input this error would be:

V

ERROR(MAX)

= (V

)(2π) • f(“–”)(10/f

PEAK

CLK

)

Where f(“–”) is the frequency of the “–” input voltage, V

is its peak amplitude and f

PEAK

CLK. In most cases V

will not be significant. For a

ERROR

is the frequency of the

CLK

60Hz signal on the “–” input to generate a 0.25LSB error (1.25mV) with the converter running at CLK = 500kHz, its peak value would have to be 150mV.

5. Reference Inputs

2. Transients on the reference inputs caused by the capacitive switching currents must settle completely during each bit test (each CLK cycle). Figures 13 and 14 show examples of both adequate and poor settling. Using a slower CLK will allow more time for the reference to settle. However, even at the maximum CLK rate of 500kHz most references and op amps can be made to settle within the 2µs bit time.

3. It is recommended that the REF– input of the LTC1094 be tied directly to the analog ground plane. If REF– is biased at a voltage other than ground, the voltage must not change during a conversion cycle. This voltage must also be free of noise and ripple with respect to analog ground.

+

REF

14

R

OUT

V

REF

13

(AGND)

10k TYP

LTC1091/2/3/4

EVERY CLK CYCLE

R

ON

5pF TO 30pF

1091-4 F12

The voltage between the reference inputs of the LTC1091/LTC1092/LTC1093/LTC1094 defines the voltage span of the A/D converter. The reference inputs look primarily like a 10k resistor but will have transient capacitive switching currents due to the switched capacitor conversion technique (see Figure 12). During each bit test of the conversion (every CLK cycle), a capacitive current spike will be generated on the reference pins by the A/D. These current spikes settle quickly and do not cause a problem. However, if slow settling circuitry is used to drive the reference inputs, care must be taken to ensure that transients caused by these current spikes settle completely during each bit test of the conversion.

When driving the reference inputs, three things should be kept in mind:

1. The source resistance (R

) driving the reference

OUT

inputs should be low (less than 1Ω) to prevent DC drops caused by the 1mA maximum reference current (I

).

REF

Figure 12. Reference Input Equivalent Circuit

0.5mV/DIV

1µs/DIV

1091-4 F13

Figure 13. Adequate Reference Settling

24

LTC1091/LTC1092

LTC1093/LTC1094

U

O

PPLICATI

A

0.5mV/DIV

Figure 14. Poor Reference Settling Can Cause A/D Errors

6. Reduced Reference Operation

The minimum reference voltage of the LTC1091 is limited to 4.5V because the VCC supply and reference are internally tied together. However, the LTC1092/LTC1093/LTC1094 can operate with reference voltages below 1V.

The effective resolution of the LTC1092/LTC1093/LTC1094 can be increased by reducing the input span of the converter. The parts exhibit good linearity and gain over a wide range of reference voltages (see typical curves of Linearity and Full-Scale Error vs Reference Voltage). However, care must be taken when operating at low values of V because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converter. The following factors must be considered when operating at low V

1. Offset

2. Noise

3. Conversion speed (CLK frequency)

Offset with Reduced V

The offset of the LTC1092/ effect on the output code when the A/D is operated with reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Unadjusted Offset Error vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 0.5mV which is 0.1LSB with a

REF

values:

S

I FOR ATIO

1µs/DIV

REF

LTC1093/LTC109

WU

1091-4 F14

4 has a larger

U

REF

5V reference becomes 0.5LSB with a 1V reference and

2.5LSBs with a 0.2V reference. If this offset is unaccept-

able, it can be corrected digitally by the receiving system or by offsetting the “–” input to the LTC1092/ LTC109

Noise with Reduced V

The total input-referred noise of the LTC1092/ LTC109 peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Noise Error vs Reference Voltage shows the LSB contribution of this 200µV of noise.

For operation with a 5V reference, the 200µV noise is only

0.04LSB peak-to-peak. In this case, the LTC1092/

LTC109 the output code. However, for reduced references, the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 1V reference, this same 200µV noise is 0.2LSB peak-to-peak. This will reduce the range of input voltages over which a stable output code can be achieved by

0.2LSB. If the reference is further reduced to 200mV, the

200µV noise becomes equal to one LSB and a stable code may be difficult to achieve. In this case averaging readings may be necessary.

This noise data was taken in a very clean setup. Any setupinduced noise (noise or ripple on VCC, V add to the internal noise. The lower the reference voltage to be used, the more critical it becomes to have a clean, noise-free setup.

Conversion Speed with Reduced V

With reduced reference voltages, the LSB step size is reduced and the LTC1092/ comparator overdrive is reduced. Therefore, it may be necessary to reduce the maximum CLK frequency when low values of V

4.

REF

4 can be reduced to approximately 200µV peak-to-

4 noise will contribute virtually no uncertainty to

REF

LTC1093/LTC109

are used.

REF

LTC109

, VIN or V–) will

4 internal

3/

25

LTC1091/LTC1092 LTC1093/LTC1094

PPLICATITYPICAL

0°C to 500°C Furnace Exhaust Gas Temperature Monitor with Low Supply Detection

8

–

J TYPE

+

1µF

J

LT1025A

GND

4

O

2

V

IN

COMMON

0.1µF

U SA

5

3

2

+

LTC1052

–

1

9V

V

2

IN

0.1µF

20k

7

6

8

4

0.1µF

47Ω

1µF

10k

LT1021-5

1N4148

LTC1091A CS CH0 CH1 GND

56k

4

V

CLK

D

OUT

V

6

OUT

+

10µF

CC

D

IN

TO MCU

1091 TA03

1k

0.1%

3.4k 1%

0.33µF

178k

0.1%

26

LTC1091/LTC1092

LTC1093/LTC1094

U

O

PPLICATITYPICAL

SA

0°C to 100°C 0.25°C Accurate Thermistor Based

Temperature Measurement System

YSI 44201

0°C TO

100°C

5k AT

25°C

20°C TO

–40°C

YSI 44201

*

5000Ω

*YSI 44007, 44034 OR EQUIVALENT

2954Ω

4562Ω

10k

±10%

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM DGND

2N3904

LTC1094

1491Ω

DV AV

CLK

D

OUT

D REF REF

AGND

15k

±10%

CC CC

CS

IN

+ –

–

V

5V 4.7µF

TO MCU

+

LT1006

–

1091-4 TA04

226Ω

–55°C to 125°C Thermometer Using

Current Output Silicon Sensors

9V

LM134 OR OTHER 1µA/°K SENSOR

LTC1092

11.5k

CS

+ –

GND

V SCLK D

OUT

V

REF

CC

5V4.7µF

LT1019-2.5

10µF

V

OUT

3Ω

TO MCU

1091 TA05

27

LTC1091/LTC1092 LTC1093/LTC1094

PACKAGE DESCRIPTIO

U

Dimensions in inches (millimeters) unless otherwise noted.

N8 Package

8-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

0.400*

(10.160)

MAX

876

0.255 ± 0.015* (6.477 ± 0.381)

5

12

0.300 – 0.325

(7.620 – 8.255)

0.065

(1.651)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015 +0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

TYP

0.045 – 0.065

(1.143 – 1.651)

0.100

(2.54)

BSC

3

4

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

0.020

(0.508)

MIN

N8 1098

28

PACKAGE DESCRIPTIO

LTC1091/LTC1092

LTC1093/LTC1094

U

Dimensions in inches (millimeters) unless otherwise noted.

N Package

16-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

0.770* (19.558)

MAX

12

13

4

11

6

5

7

0.255 ± 0.015* (6.477 ± 0.381)

14

15

16

2

1

3

910

8

0.300 – 0.325

(7.620 – 8.255)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015

+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.020

(0.508)

MIN

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

0.100 (2.54)

BSC

0.045 – 0.065

(1.143 – 1.651)

0.065

(1.651)

TYP

0.018 ± 0.003

(0.457 ± 0.076)

N16 1098

29

LTC1091/LTC1092 LTC1093/LTC1094

PACKAGE DESCRIPTIO

U

Dimensions in inches (millimeters) unless otherwise noted.

N Package

20-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

1.040*

(26.416)

MAX

0.255 ± 0.015* (6.477 ± 0.381)

19 1112

20

18

1517

131416

1234

0.300 – 0.325

(7.620 – 8.255)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015 +0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.020

(0.508)

MIN

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

0.005

(0.127)

MIN

0.045 – 0.065

(1.143 – 1.651)

0.100

(2.54)

BSC

5

7

6

8

910

0.065

(1.651)

TYP

0.018 ± 0.003

(0.457 ± 0.076)

N20 1098

30

PACKAGE DESCRIPTIO

LTC1091/LTC1092

LTC1093/LTC1094

U

Dimensions in inches (millimeters) unless otherwise noted.

SW Package

16-Lead Plastic Small Outline (Wide 0.300)

(LTC DWG # 05-08-1620)

0.398 – 0.413*

(10.109 – 10.490)

15 14

16

12

13

10 9

11

NOTE 1

2345

0.050

(1.270)

BSC

1

0.014 – 0.019

(0.356 – 0.482)

TYP

0.291 – 0.299** (7.391 – 7.595)

0.010 – 0.029

(0.254 – 0.737)

0.009 – 0.013

(0.229 – 0.330)

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

*

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

**

NOTE 1

× 45°

0.016 – 0.050

(0.406 – 1.270)

° – 8° TYP

0

0.093 – 0.104

(2.362 – 2.642)

6

78

0.037 – 0.045

(0.940 – 1.143)

0.394 – 0.419

(10.007 – 10.643)

0.004 – 0.012

(0.102 – 0.305)

S16 (WIDE) 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.

31

LTC1091/LTC1092 LTC1093/LTC1094

TYPICAL APPLICATION

Micropower, 500V Optoisolated, Multichannel, 10-Bit Data

U

Acquisition System Is Accessed Once Every Two Seconds

LT1021-5

+

LTC1094 CH0 CH1

8 ANALOG

INPUTS

0V TO 5V

RANGE

*SOLID TANTALUM **MC68HC05 CODE AVAILABLE FROM LINEAR TECHNOLOGY

CH2 CH3 CH4 CH5 CH6 CH7 COM DGND

10µF*

DV AV

CLK

CS

D

OUT

D REF REF

AGND

10k

9V

5.1k × 3

10k

51k

300Ω

2N3904

2N3906

1Ω

CC CC

IN

+ –

–

V

TO ADDITIONAL

LTC1094s

4N28

4N28s

4N28

ISOLATION

BARRIER

51k

5V

2N3906

150Ω

5V

5.1k

10k

C1

SCK

C0

MOSI

MISO

LT1091-4 TA06

TO 68HC05**

NC

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1090 10-Bit, 8-Channel ADC Serial I/O, 1.5mA Supply Current LTC1291/LTC1292 12-BIT, 2-Channel and Differential ADCs Pin Compatible Upgrades to LTC1091/LTC1092 LTC1293/LTC1294 12-Bit, 6- and 8-Channel ADCs Pin Compatible Upgrades to LTC1093/LTC1094

1091fa LT/TP 1099 2K REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1988

32

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear-tech.com