Datasheet LT3431 Datasheet (LINEAR TECHNOLOGY)

FEATURES

■

Wide Input Range: 5.5V to 60V

■

3A Peak Switch Current

■

Small Thermally Enhanced 16-Pin TSSOP Package

■

Constant 500kHz Switching Frequency

■

Saturating Switch Design: 0.1Ω

■

Peak Switch Current Maintained Over
Full Duty Cycle Range

■

Effective Supply Current: 2.5mA

■

Shutdown Current: 30µA

■

1.2V Feedback Reference Voltage

■

Easily Synchronizable

■

Cycle-by-Cycle Current Limiting

U

APPLICATIO S

■

Industrial and Automotive Power Supplies

■

Portable Computers

■

Battery Chargers

■

Distributed Power Systems

LT3431

High Voltage, 3A,

500kHz Step-Down

Switching Regulator

U

DESCRIPTIO

The LT®3431 is a 500kHz monolithic buck switching regu­lator that accepts input voltages up to 60V. A high efficiency
3A, 0.1Ω switch is included on the die along with all the nec­essary oscillator, control and logic circuitry. A current mode
architecture provides fast transient response and good loop
stability.

Special design techniques and a new high voltage process
achieve high efficiency over a wide input range. Efficiency
is maintained over a wide output current range by using the
output to bias the circuitry and by utilizing a supply boost
capacitor to saturate the power switch. Patented circuitry
maintains peak switch current over the full duty cycle range.
A shutdown pin reduces supply current to 30µA and the de-
vice can be externally synchronized from 580kHz to 700kHz
with logic level inputs.

The LT3431 is available in a thermally enhanced 16-pin
TSSOP package.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

5V, 2A Buck Converter

V

12V

(TRANSIENTS

TO 60V)

IN

2.2µF†
100V
CERAMIC

**

INCREASE INDUCTOR VALUE FOR LOAD CURRENTS ABOVE 2A
(SEE APPLICATIONS INFORMATION—MAXIMUM OUTPUT LOAD CURRENT)

†

UNITED CHEMI-CON THCS50EZA225ZT

3, 4

1, 8, 9, 16

BOOST

V

IN

LT3431

15

SHDN

14

SYNC

GND

1.5k

15nF

U

MMSD914TI

6

SW

BIAS

FB

V

C

11

220pF

2, 5

10

12

0.22µF

30BQ060

10µH**

15.4k

4.99k

V

OUT

5V
2A

47µF
CERAMIC

3431 TA01

Efficiency vs Load Current

100

= 12V

V

IN

L = 15µH

90

80

70

EFFICIENCY (%)

60

50

0

0.5

1.0

LOAD CURRENT (A)

V

= 5V

OUT

V

= 3.3V

OUT

1.5

2.0

2.5

3431 TA02

sn3431 3431fs

1

LT3431

WWWU

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

UU

W

(Note 1)

Input Voltage (VIN) ................................................. 60V

BOOST Pin Above SW ............................................ 35V

BOOST Pin Voltage ................................................. 68V

SYNC Voltage ........................................................... 7V

SHDN Voltage ........................................................... 6V

BIAS Pin Voltage .................................................... 30V

FB Pin Voltage/Current .................................. 3.5V/2mA

Operating Junction Temperature Range

LT3431EFE (Notes 8, 10) ................. –40°C to 125°C

LT3431IFE (Notes 8, 10) ................. –40°C to 125°C

Storage Temperature Range ................ –65°C to 150°C

TOP VIEW

1

GND

2

SW

3

V

IN

4

V

IN

5

SW

6

BOOST

7

NC

8

GND

FE PACKAGE

16-LEAD PLASTIC TSSOP

T

= 125°C, θJA = 45°C/W, θJC (PAD) = 10°C/W

JMAX

EXPOSED PAD MUST BE SOLDERED

TO GROUND PLANE

16
15
14
13
12
11
10

9

GND
SHDN
SYNC
NC
FB
V

C

BIAS
GND

ORDER PART

NUMBER

LT3431EFE
LT3431IFE

FE PART MARKING

3431EFE
3431IFE

Lead Temperature (Soldering, 10 sec)................. 300°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Reference Voltage (V

FB Input Bias Current ● –0.2 –1.5 µA
Error Amp Voltage Gain (Note 2) 200 475 V/V
Error Amp g

VC to Switch g

m

m

EA Source Current FB = 1V or V
EA Sink Current FB = 1.4V or V
VC Switching Threshold Duty Cycle = 0 0.8 V
VC High Clamp SHDN = 1V 2.1 V
Switch Current Limit VC Open, BOOST = VIN + 5V, FB = 1V or V

Switch On Resistance ISW = 2.5A, BOOST = VIN + 5V (Note 7) 0.1 0.14 Ω

Maximum Switch Duty Cycle FB = 1V or V

Switch Frequency VC Set to Give DC = 50% 460 500 540 kHz

fSW Line Regulation 5.5V ≤ VIN ≤ 60V ● 0.05 0.15 %/V
fSW Shifting Threshold Df = 10kHz 0.8 V

) 5.5V ≤ VIN ≤ 60V 1.204 1.219 1.234 V

REF

+ 0.2 ≤ VC ≤ VOH – 0.2 ● 1.195 1.243 V

V

OL

dl (VC) = ±10µA 1650 2200 3300 µMho

● 1000 4200 µMho

3.4 A/V

= 4.1V ● 125 275 450 µA

SENSE

= 5.7V ● 100 275 500 µA

SENSE

= 4.1V –40°C␣ ≤ Tj ≤ 25°C 3.0 5 6.5 A

SENSE

(Note 9) Tj = 125°C 2.5 4 5.5 A

● 0.18 Ω

= 4.1V 88 92 %

SENSE

● 80 %

● 430 500 570 kHz

2

sn3431 3431fs

LT3431

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Minimum Input Voltage (Note 3) ● 4.6 5.5 V
Minimum Boost Voltage (Note 4) ISW ≤ 2.5A ● 1.8 3 V
Boost Current (Note 5) BOOST = VIN + 5V, ISW = 0.75A ● 25 50 mA

BOOST = VIN + 5V, ISW = 2.5A ● 75 120 mA
Input Supply Current (I
Bias Supply Current (I
Shutdown Supply Current SHDN = 0V, VIN ≤ 60V, SW = 0V, VC Open 30 100 µA

Lockout Threshold VC Open, ● 2.30 2.42 2.53 V
Shutdown Thresholds VC Open, Shutting Down ● 0.15 0.37 0.58 V

Minimum SYNC Amplitude ● 1.5 2.2 V
SYNC Frequency Range 580 700 kHz
SYNC Input Resistance 20 kΩ

) (Note 6) V

VIN

) (Note 6) V

BIAS

V

= 5V 1.5 2.2 mA

BIAS

= 5V 3.1 4.2 mA

BIAS

● 200 µA

Open, Starting Up ● 0.25 0.42 0.6 V

C

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: Gain is measured with a VC swing equal to 200mV above the low
clamp level to 200mV below the upper clamp level.

Note 3: Minimum input voltage is not measured directly, but is guaranteed
by other tests. It is defined as the voltage where internal bias lines are still
regulated so that the reference voltage and oscillator remain constant.
Actual minimum input voltage to maintain a regulated output will depend
upon output voltage and load current. See Applications Information.

Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.

Note 5: Boost current is the current flowing into the BOOST pin with the
pin held 5V above input voltage. It flows only during switch on time.

Note 6: Input supply current is the quiescent current drawn by the input
pin when the BIAS pin is held at 5V with switching disabled. Bias supply
current is the current drawn by the BIAS pin when the BIAS pin is held at
5V. Total input referred supply current is calculated by summing input
supply current (I

= I

I

TOTAL

= 15V, V

With V

IN

) with a fraction of bias supply current (I

VIN

+ (I

VIN

OUT

)(V

BIAS

= 5V, I

OUT/VIN

= 1.5mA, I

VIN

)

= 3.1mA, I

BIAS

BIAS

TOTAL

):

= 2.5mA.

Note 7: Switch on resistance is calculated by dividing VIN to SW voltage by
the forced current (3A). See Typical Performance Characteristics for the
graph of switch voltage at other currents.

Note 8: The LT3431EFE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3431IFE is guaranteed over the full –40°C to 125°C operating junction
temperature range.

Note 9: See Typical Performance Graph of Peak Switch Current Limit vs
Junction Temperature.

Note 10. This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.

sn3431 3431fs

3

LT3431

JUNCTION TEMPERATURE (°C)

–50

250

200

150

100

12

6

0

25 75

3431 G03

–25 0

50 100 125

CURRENT (µA)

CURRENT REQUIRED TO FORCE SHUTDOWN

(FLOWS OUT OF PIN). AFTER SHUTDOWN,

CURRENT DROPS TO A FEW µA

AT 2.38V STANDBY THRESHOLD

(CURRENT FLOWS OUT OF PIN)

SHUTDOWN VOLTAGE (V)

0

0

INPUT SUPPLY CURRENT (µA)

50

100

150

200

250

300

0.1 0.2 0.3 0.4

3431 G06

0.5

VIN = 60V

V

IN

= 15V

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Switch Peak Current Limit

6

Tj = 25°C

5

TYPICAL

4

3

SWITCH PEAK CURRENT (A)

2

GUARANTEED MINIMUM

20 40

DUTY CYCLE (%)

Lockout and Shutdown
Thresholds

2.4

2.0

1.6

1.2

0.8

SHDN PIN VOLTAGE (V)

0.4

0

–25 125

–50

JUNCTION TEMPERATURE (°C)

LOCKOUT

START-UP

SHUTDOWN

0

25 75

60 80

50 100

3431 G01

3431 G04

1.234

1.229

1.224

1.219

1.214

FEEDBACK VOLTAGE (V)

1.209

1.204

1000

FB Pin Voltage and Current SHDN Pin Bias Current

2.0

1.5

CURRENT (µA)

VOLTAGE

1.0

CURRENT

0.5

–50

–25 0

JUNCTION TEMPERATURE (°C)

50 100 125

25 75

0

3431 G02

Shutdown Supply Current Shutdown Supply Current

40

V

= 0V

SHDN

35

30

25

20

15

10

INPUT SUPPLY CURRENT (µA)

5

0

0

10 20 30 40 50 60

INPUT VOLTAGE (V)

3431 G05

Error Amplifier Transconductance

2500

2000

1500

1000

500

TRANSCONDUCTANCE (µmho)

0

–50

4

0

JUNCTION TEMPERATURE (°C)

50 100

25 75–25 125

3431 G07

Error Amplifier Transconductance

3000

2500

2000

1500

V

GAIN (µMho)

1000

500

2 • 10

FB

ERROR AMPLIFIER EQUIVALENT CIRCUIT

R

LOAD

100 10k 100k 10M

PHASE

GAIN

R

–3

)(

= 50Ω

1k 1M

FREQUENCY (Hz)

OUT

200k

C

OUT

12pF

V

C

3431 G08

200

150

100

50

0

–50

625

500

PHASE (DEG)

375

250

OR FB CURRENT (µA)

125

SWITICHING FREQUENCY (kHz)

0

0 0.2

Frequency Foldback

0.4

0.6

VFB (V)

SWITCHING
FREQUENCY

FB PIN

CURRENT

0.8

1.0

sn3431 3431fs

1.2

3431 G09

SWITCH CURRENT (A)

0123

BOOST PIN CURRENT (mA)

3431 G12

90

80

70

60

50

40

30

20

10

0

UW

JUNCTION TEMPERATURE (°C)

–50

SWITCH MINIMUM ON TIME (ns)

400

500

600

25 75

3431 G15

300

200

–25 0

50 100 125

100

0

TYPICAL PERFOR A CE CHARACTERISTICS

Minimum Input Voltage

Switching Frequency BOOST Pin Current

575

with 5V Output

7.5

LT3431

550

525

500

475

FREQUENCY (kHz)

450

425

–50

0

–25 125

JUNCTION TEMPERATURE (°C)

25 75

VC Pin Shutdown Threshold

2.1

1.9

1.7

1.5

1.3

1.1

THRESHOLD VOLTAGE (V)

0.9

0.7
–50

–25 0

JUNCTION TEMPERATURE (°C)

25 75

50 100

3431 G10

50 100 125

3431 G13

7.0

6.5

6.0

INPUT VOLTAGE (V)

5.5

5.0
0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

MINIMUM INPUT
VOLTAGE TO START

MINIMUM INPUT
VOLTAGE TO RUN

LOAD CURRENT (A)

3431 G11

Switch Voltage Drop

450

400

350

300

250

200

150

SWITCH VOLTAGE (mV)

100

50

0

0123

TJ = 25°C

SWITCH CURRENT (A)

TJ = 125°C

TJ = –40°C

3431 G14

Switch Minimum ON Time
vs Temperature

Switch Peak Current Limit

6.00

5.50

5.00

4.50

4.00

3.50

3.00

SWITCH PEAK CURRENT LIMIT (A)

2.50
–50

0

–25 125

JUNCTION TEMPERATURE (°C)

25 75

50 100

3431 G16

sn3431 3431fs

5

LT3431

U

UU

PI FU CTIO S

GND (Pins 1, 8, 9, 16): The GND pin connections act as
the reference for the regulated output, so load regulation
will suffer if the “ground” end of the load is not at the same
voltage as the GND pins of the IC. This condition will occur
when load current or other currents flow through metal
paths between the GND pins and the load ground. Keep the
paths between the GND pins and the load ground short
and use a ground plane when possible. The FE package has
an exposed pad that is fused to the GND pins. The pad
should be soldered to the copper ground plane under the
device to reduce thermal resistance. (See Applications
Information—Layout Considerations.)

SW (Pins 2, 5): The switch pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
switch pin voltage negative during switch off time. Nega­tive voltage is clamped with the external catch diode.
Maximum negative switch voltage allowed is –0.8V.

VIN (Pins 3, 4): This is the collector of the on-chip power
NPN switch. VIN powers the internal control circuitry when
a voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance in this path creates voltage spikes at switch off,
adding to the VCE voltage across the internal NPN.

BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal bipo­lar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The ad­ditional BOOST voltage allows the switch to saturate and
voltage loss approximates that of a 0.1Ω FET structure.

NC (Pins 7, 13): No Connection.

supply. This architecture increases efficiency especially
when the input voltage is much higher than the output.
Minimum output voltage setting for this mode of operation
is 3V.

VC (Pin 11) The VC pin is the output of the error amplifier
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. VC sits
at about 0.9V for light loads and 2.1V at maximum load. It
can be driven to ground to shut off the regulator, but if
driven high, current must be limited to 4mA.

FB (Pin 12): The feedback pin is used to set the output
voltage using an external voltage divider that generates

1.22V at the pin for the desired output voltage. Three
additional functions are performed by the FB pin. When the
pin voltage drops below 0.6V, switch current limit is
reduced and the external SYNC function is disabled. Below

0.8V, switching frequency is also reduced. See Feedback
Pin Functions in Applications Information for details.

SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between
10% and 90% duty cycle. The synchronizing range is
equal to initial operating frequency up to 700kHz. See
Synchronizing in Applications Information for details.

SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input drain current to a few
microamperes. This pin has two thresholds: one at 2.38V
to disable switching and a second at 0.4V to force com­plete micropower shutdown. The 2.38V threshold func­tions as an accurate undervoltage lockout (UVLO); some­times used to prevent the regulator from delivering power
until the input voltage has reached a predetermined level.

B

IAS (Pin 10): The BIAS pin is used to improve efficiency

when operating at higher input voltages and light load
current. Connecting this pin to the regulated output volt­age forces most of the internal circuitry to draw its oper­ating current from the output voltage rather than the input

6

If the SHDN pin functions are not required, the pin can
either be left open (to allow an internal bias current to lift
the pin to a default high state) or be forced high to a level
not to exceed 6V.

sn3431 3431fs

BLOCK DIAGRA

LT3431

W

The LT3431 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
two feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscilla­tor pulse which sets the RS flip-flop to turn the switch on.
When switch current reaches a level set by the inverting
input of the comparator, the flip-flop is reset and the
switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip point. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes

V

IN

3, 4

BIAS

SYNC

10

14

SHUTDOWN

COMPARATOR

2.9V BIAS

REGULATOR

+

0.4V

–

INTERNAL
V

CC

SLOPE COMP

ANTISLOPE COMP

500kHz

OSCILLATOR

Σ

it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.

Most of the circuitry of the LT3431 operates from an
internal 2.9V bias line. The bias regulator normally draws
power from the regulator input pin, but if the BIAS pin is
connected to an external voltage equal to or higher than
3V, bias power will be drawn from the external source
(typically the regulated output voltage). This will improve
efficiency if the BIAS pin voltage is lower than regulator
input voltage.

High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external
capacitor and diode. Two comparators are connected to
the shutdown pin. One has a 2.38V threshold for under­voltage lockout and the second has a 0.4V threshold for
complete shutdown.

R

LIMIT

–

+

CURRENT
COMPARATOR

BOOST

6

S

R

R

S

FLIP-FLOP

DRIVER

CIRCUITRY

R

SENSE

Q1
POWER
SWITCH

SHDN

5.5µA

2.38V

+

–

LOCKOUT

COMPARATOR

V

C(MAX)

CLAMP

FREQUENCY

FOLDBACK

×1

Q2

FOLDBACK

Q3

CURRENT

LIMIT

CLAMP

11

V

C

AMPLIFIER

g

= 2000µMho

m

ERROR

–

+

15

1.22V

2, 5

12

3431 F01

SW

FB

GND
1, 8, 9, 16

Figure 1. LT3431 Block Diagram

sn3431 3431fs

7

LT3431

WUUU

APPLICATIO S I FOR ATIO

FEEDBACK PIN FUNCTIONS

The feedback (FB) pin on the LT3431 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the second part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design.

The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following if divider resistors are increased
above the suggested values.

RV

2122

()

=

R

1

Table 1

OUTPUT R1 % ERROR AT OUTPUT

VOLTAGE R2 (NEAREST 1%) DUE TO DISCREET 1%

(V) (k

3 4.99 7.32 +0.32

3.3 4.99 8.45 –0.43
5 4.99 15.4 –0.30
6 4.75 18.7 +0.40
8 4.47 24.9 +0.20

10 4.32 30.9 – 0.54
12 4.12 36.5 + 0.24
15 4.12 46.4 – 0.27

−

OUT

.

122

.

Ω

)(k

Ω

) RESISTOR STEPS

More Than Just Voltage Feedback

The feedback pin is used for more than just output voltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency
Foldback graph in Typical Performance Characteristics).
This is done to control power dissipation in both the IC and
in the external diode and inductor during short-circuit
conditions. A shorted output requires the switching regu­lator to operate at very low duty cycles, and the average
current through the diode and inductor is equal to the

short-circuit current limit of the switch (typically 4A for the
LT3431, folding back to less than 2A). Minimum switch on
time limitations would prevent the switcher from attaining
a sufficiently low duty cycle if switching frequency were
maintained at 500kHz, so frequency is reduced by about
5:1 when the feedback pin voltage drops below 0.8V (see
Frequency Foldback graph). This does not affect operation
with normal load conditions; one simply sees a gear shift
in switching frequency during start-up as the output
voltage rises.

In addition to lower switching frequency, the LT3431 also
operates at lower switch current limit when the feedback
pin voltage drops below 0.6V. Q2 in Figure 2 performs this
function by clamping the VC pin to a voltage less than its
normal 2.1V upper clamp level. This

foldback current limit

greatly reduces power dissipation in the IC, diode and in­ductor during short-circuit conditions. External synchro­nization is also disabled to prevent interference with fold­back operation. Again, it is nearly transparent to the user
under normal load conditions. The only loads that may be
affected are current source loads which maintain full load
current with output voltage less than 50% of final value. In
these rare situations the feedback pin can be clamped above

0.6V with an external diode to defeat foldback current limit.

Caution:

clamping the feedback pin means that frequency
shifting will also be defeated, so a combination of high in­put voltage and dead shorted output may cause the LT3431
to lose control of current limit.

The internal circuitry which forces reduced switching
frequency also causes current to flow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 0.8V, Q1 begins to
conduct current and reduces frequency at the rate of
approximately 3.5kHz/µA. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance must be low enough
to pull 115µA out of the FB pin with 0.44V on the pin (R
≤ 3.8k).

The net result is that reductions in frequency and

DIV

current limit are affected by output voltage divider imped­ance. Although divider impedance is not critical, caution
should be used if resistors are increased beyond the
suggested values and short-circuit conditions can possi­bly occur with high input voltage.

High frequency pickup

sn3431 3431fs

8

WUUU

APPLICATIO S I FOR ATIO

LT3431

LT3431

TO FREQUENCY

ERROR

AMPLIFIER

SHIFTING

1.4V

+

1.2V
R3

1k

Q1

R4
2k

–

BUFFER

Q2

TO SYNC CIRCUIT

GND

V

C

Figure 2. Frequency and Current Limit Foldback

will increase and the protection accorded by frequency
and current foldback will decrease.

CHOOSING THE INDUCTOR

For most applications, the output inductor will fall into the
range of 5µH to 33µH. Lower values are chosen to reduce
physical size of the inductor. Higher values allow more
output current because they reduce peak current seen by
the LT3431 switch, which has a 3A limit. Higher values
also reduce output ripple voltage.

When choosing an inductor you will need to consider
output ripple voltage, maximum load current, peak induc­tor current and fault current in the inductor. In addition,
other factors such as core and copper losses, allowable
component height, EMI, saturation and cost should also
be considered. The following procedure is suggested as a
way of handling these somewhat complicated and con­flicting requirements.

Output Ripple Voltage

Figure 3 shows a comparison of output ripple voltage for
the LT3431 using either a tantalum or ceramic output
capacitor. It can be seen from Figure 3 that output ripple
voltage can be significantly reduced by using the ceramic
output capacitor; the significant decrease in output ripple
voltage is due to the very low ESR of ceramic capacitors.

V

SW

10mV/DIV

L1

R1

FB

R2

= 12V 3431 F03

V

IN

V

= 5V

OUT

L = 10µH

+

1µs/DIV

C1

3431 F02

OUTPUT
5V

V

USING

OUT

47µF CERAMIC
OUTPUT
CAPACITOR

USING

V

OUT

100µF, 0.08Ω
TANTALUM
OUTPUT
CAPACITOR

Figure 3. LT3431 Output Ripple Voltage Waveforms.
Ceramic vs Tantalum Output Capacitors

Output ripple voltage is determined by ripple current
(I

) through the inductor and the high frequency

LP-P

impedance of the output capacitor. At high frequencies,
the impedance of the tantalum capacitor is dominated by
its effective series resistance (ESR).

Tantalum Output Capacitor

The typical method for reducing output ripple voltage
when using a tantalum output capacitor is to increase the
inductor value (to reduce the ripple current in the induc­tor). The following equations will help in choosing the
required inductor value to achieve a desirable output
ripple voltage level. If output ripple voltage is of less

sn3431 3431fs

9

LT3431

II

I

I

VVV

VfL

PEAK OUT

LP P

OUT

OUT IN OUT

IN

=+ =+

()( )

()( )()()

()

–

-

2

2

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APPLICATIO S I FOR ATIO

importance, the subsequent suggestions in Peak Induc­tor and Fault Current and EMI will additionally help in the
selection of the inductor value.

Peak-to-peak output ripple voltage is the sum of a triwave
(created by peak-to-peak ripple current (I
and a square wave (created by parasitic inductance (ESL)
and ripple current slew rate). Capacitive reactance is
assumed to be small compared to ESR or ESL.

V I ESR ESL

RIPPLE LP P

where:

ESR = equivalent series resistance of the output
capacitor

ESL = equivalent series inductance of the output
capacitor

dI/dt = slew rate of inductor ripple current = VIN/L

Peak-to-peak ripple current (I
and into the output capacitor is typically chosen to be
between 20% and 40% of the maximum load current. It is
approximated by:

=

-

()()

+

()

LP-P

dI

Σ

dt

) through the inductor

) times ESR)

LP-P

physically larger inductor with the possibility of increased
component height and cost.

Ceramic Output Capacitor

An alternative way to further reduce output ripple voltage
is to reduce the ESR of the output capacitor by using a
ceramic capacitor. Although this reduction of ESR re­moves a useful zero in the overall loop response, this zero
can be replaced by inserting a resistor (RC) in series with
the VC pin and the compensation capacitor CC. (See
Ceramic Capacitors in Applications Information.)

Peak Inductor Current and Fault Current

To ensure that the inductor will not saturate, the peak
inductor current should be calculated knowing the maxi­mum load current. An appropriate inductor should then
be chosen. In addition, a decision should be made whether
or not the inductor must withstand continuous fault
conditions.

If maximum load current is 1A, for instance, a 1A inductor
may not survive a continuous 4A overload condition. Dead
shorts will actually be more gentle on the inductor because
the LT3431 has frequency and current limit foldback.

Peak inductor and switch current can be significantly

VVV

OUT IN OUT

I

LP P

()( )

=

-

()()()

Example: with VIN = 12V, V

0.080Ω and ESL = 10nH, output ripple voltage can be
approximated as follows:

IA

=

P-P

12 10 10 500 10

()

()()

dI

Σ

dt

VA

RIPPLE

=+=

..

0 046 0 012 58

To reduce output ripple voltage further requires an in­crease in the inductor value with the trade-off being a

12

==

•

10 10

=

.. • .

0 58 0 08 10 10 10 1 2

()()

–

VfL

IN

= 5V, L = 10µH, ESR =

OUT

−

512 5

()

()

−

63

••

6

•.

10 1 2

−

6

+

()()

mV

P-P

=

−

.

058

96

()

higher than output current, especially with smaller induc­tors and lighter loads, so don’t omit this step. Powdered
iron cores are forgiving because they saturate softly,
whereas ferrite cores saturate abruptly. Other core mate­rials fall somewhere in between. The following formula
assumes continuous mode of operation, but errs only
slightly on the high side for discontinuous mode, so it can
be used for all conditions.

EMI

Decide if the design can tolerate an “open” core geometry
like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid to
prevent EMI problems. This is a tough decision because
the rods or barrels are temptingly cheap and small and

sn3431 3431fs

10

WUUU

I–

I

2

=I

P

LP-P

P

−

+

()

−

()

()()( )

VVVVV

LfV

OUT F IN OUT F

IN

–

2

APPLICATIO S I FOR ATIO

LT3431

there are no helpful guidelines to calculate when the
magnetic field radiation will be a problem.

Table 2

VENDOR/ VALUE I

µ

PART NUMBER (
Sumida

CDRH8D28-4R7 4.7 3.4 0.019 3
CDRH8D28-7R3 7.3 2.8 0.030 3
CDRH8D43-100 10 4 0.029 4.5
CDRH8D43-150 15 2.9 0.042 4.5
CEI122-100 10 3.4 0.029 3
CEI122(H)-150 15 3.6 0.071 3
CDRH104R-150 15 3.6 0.037 4
CDRH104R-220 22 2.9 0.054 4
CDRH124-330 33 2.9 0.066 4.5

Coiltronics

UP2B-6R8 6.8 3.6 0.020 6
UP2B-100 10 3.3 0.027 6
UP3B-220 22 3.7 0.049 6.8
UP3B-330 33 3.0 0.069 6.8

Coilcraft

DO1813P-472 4.7 2.6 0.054 5
DS3316P-472 4.7 3.2 0.054 5.08
DS3316P-682 6.8 2.8 0.075 5.08
DO3316P-103 10 3.8 0.038 5.21
DO3316P-153 15 3.0 0.046 5.21

Additional Considerations

After making an initial choice, consider additional factors
such as core losses and second sourcing, etc. Use the
experts in Linear Technology’s Applications department if
you feel uncertain about the final choice. They have
experience with a wide range of inductor types and can tell
you about the latest developments in low profile, surface
mounting, etc.

Maximum Output Load Current

Maximum load current for a buck converter is limited by
the maximum switch current rating (IP). The current rating
for the LT3431 is 3A. Unlike most current mode convert­ers, the LT3431 maximum switch current limit does not

H) (Amps) (Ohms) (mm)MAX

DC

DCR HEIGHT

fall off at high duty cycles. Most current mode converters
suffer a drop off of peak switch current for duty cycles
above 50%. This is due to the effects of slope compensa­tion required to prevent subharmonic oscillations in cur­rent mode converters. (For detailed analysis, see Applica­tion Note 19.)

The LT3431 is able to maintain peak switch current limit
over the full duty cycle range by using patented circuitry to
cancel the effects of slope compensation on peak switch
current without affecting the frequency compensation it
provides.

Maximum load current would be equal to maximum
switch current
finite inductor size, maximum load current is reduced by
one-half peak-to-peak inductor current (I
ing formula assumes continuous mode operation, imply­ing that the term on the right is less than one-half of IP.

I

OUT(MAX)

Continuous Mode

For V

OUT

and L = 10µH:

I

OUT MAX

()

Note that there is less load current available at the higher
input voltage because inductor ripple current increases. At
VIN = 24V, duty cycle is 23% and for the same set of
conditions:

I

OUT MAX()

for an infinitely large inductor

=

= 5V, VIN = 12V, V

5 0 52 12 5 0 52

+

()

3

=−

2 15 10 500 10 12

••

()()

=− =

30327

..

5 0 52 24 5 0 52

+

()

3

=−

2 15 10 500 10 24

••

()()

=− =

3 0 43 2 57

..

= 0.52V, f = 500kHz

F(D1)

.–.

()

−

63

A

.–.

()

−

63

A

, but with

). The follow-

LP-P

−

()

−

()

sn3431 3431fs

11

LT3431

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APPLICATIO S I FOR ATIO

To calculate actual peak switch current with a given set of
conditions, use:

I

P

II

SW PEAK

()

Reduced Inductor Value and Discontinuous Mode

If the smallest inductor value is of most importance to a
converter design, in order to reduce inductor size/cost,
discontinuous mode may yield the smallest inductor solu­tion. The maximum output load current in discontinuous
mode, however, must be calculated and is defined later in
this section.

Discontinuous mode is entered when the output load
current is less than one-half of the inductor ripple
current (I
zero before the next switch turn on (see Figure 8). Buck
converters will be in discontinuous mode for output
load current given by:

I

OUT

Discontinuous Mode

The inductor value in a buck converter is usually chosen
large enough to keep inductor ripple current (I
this is done to minimize output ripple voltage and maxi­mize output load current. In the case of large inductor
values, as seen in the equation above, discontinuous
mode will be associated with “light loads.”

When choosing small inductor values, however, discon­tinuous mode will occur at much higher output load
currents. The limit to the smallest inductor value that can
be chosen is set by the LT3431 peak switch current (IP)
and the maximum output load current required, given by:

I

OUT(MAX)

Discontinuous Mode

=+

OUT

I

=+

OUT

). In this mode, inductor current falls to

LP-P

L-P

2

VVVVV

+−

() –

OUT F IN OUT F

<

=

22()( )

=

VVVVV

()(––)

()

LfV

2

()()( )

+()(––)

VVVVV

OUT F IN OUT F

2

I

P

I

LP-P

IfLV

PIN

+

OUT F IN OUT F

IN

()( )()()

VfL

2

IN

) low;

LP-P

2

••

()

Example: For VIN = 12V, V
and L = 2.2µH.

I

OUT(MAX)

Discontinuous
Mode

I

OUT(MAX)

Discontinuous Mode

What has been shown here is that if high inductor ripple
current and discontinuous mode operation can be toler­ated, small inductor values can be used. If a higher output
load current is required, the inductor value must be
increased. If I
mode criteria, use the I
mode; the LT3431 is designed to operate well in both
modes of operation, allowing a large range of inductor
values to be used.

Short-Circuit Considerations

For a ground short-circuit fault on the regulated output,
the maximum input voltage for the LT3431 is typically
limited to 21V. If a greater input voltage is required,
increasing the resistance in series with the inductor may
suffice (see short-circuit calculations at the end of this
section). Alternatively, the LT3430 can be used since it is
identical to the LT3431 but runs at a lower frequency of
200kHz, allowing higher sustained input voltage capability
during output short-circuit.

The LT3431 is a current mode controller. It uses the V
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
peak current is reached. The internal clamp on the V
node, nominally 2V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit.

A potential controllability problem could occur under
short-circuit conditions. If the power supply output is
short circuited, the feedback amplifier responds to the low
output voltage by raising the control voltage, VC, to its
peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
the value indicated by VC. However, there is finite response

=

OUT(MAX)

= 5V, VF = 0.52V, f = 500kHz

OUT

236

•(•)(.• )()

3 500 10 4 7 10 12

(.)(––.)

+

25052125052

= 1.66A

no longer meets the discontinuous

OUT(MAX)

equation for continuous

–

C

C

sn3431 3431fs

12

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APPLICATIO S I FOR ATIO

LT3431

time involved in both the current comparator and turnoff
of the output switch. These result in a minimum on time
t

ON(MIN)

. When combined with the large ratio of VIN to
(VF + I • R), the diode forward voltage plus inductor I • R
voltage drop, the potential exists for a loss of control.
Expressed mathematically the requirement to maintain
control is:

VIR

•≤+

ft

•

ON

F

V

IN

where:
f = switching frequency
tON = switch minimum on time
VF = diode forward voltage
VIN = Input voltage
I • R = inductor I • R voltage drop

If this condition is not observed, the current will not be
limited at IPK, but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT3431 clock frequency
of 500KHz, a VIN of 12V and a (VF + I • R) of say 0.6V, the
maximum tON to maintain control would be approximately
100ns, an unacceptably short time.

The solution to this dilemma is to slow down the oscilla­tor when the FB pin voltage is abnormally low thereby
indicating some sort of short-circuit condition. Oscillator
fre

quency is unaffected until FB voltage drops to about 2/3
of its normal value. Below this point the oscillator fre­quency decreases roughly linearly down to a limit of about
100kHz. This lower oscillator frequency during short­circuit conditions can then maintain control with the
effective minimum on time. Even with frequency foldback,
however, the LT3431 will not survive a permanent output
short at the absolute maximum voltage rating of VIN = 60V;
this is defined solely by internal semiconductor junction
breakdown effects.

For the maximum input voltage allowed during an output
short to ground, the previous equation defining minimum
on-time can be used. Assuming VF (D1 catch diode) =

0.52V at 2.5A (short-circuit current is folded back to
typical switch current limit • 0.5), I (inductor) • DCR = 2.5A

• 0.027 = 0.068V (L = UP2B-100), typical f = 100kHz
(folded back) and typical minimum on-time = 275ns, the

maximum allowable input voltage during an output short
to ground is typically:

VIN = (0.52V + 0.068V)/(100kHz • 275ns)
V

IN(MAX)

= 21V

Increasing the DCR of the inductor will increase the
maximum VIN allowed during an output short to ground
but will also drop overall efficiency during normal opera­tion.

It is recommended that for [VIN/(V

+ VF)] ratios > 4, a

OUT

soft-start circuit should be used to control the output
capacitor charge rate during start-up or during recovery
from an output short circuit, thereby adding additional
control over peak inductor current. See Buck Converter
with Adjustable Soft-Start later in this data sheet.

OUTPUT CAPACITOR

The LT3431 will operate with either ceramic or tantalum
output capacitors. The output capacitor is normally cho­sen by its effective series resistance (ESR), because this
is what determines output ripple voltage. The ESR range
for typical LT3431 applications using a tantalum output
capacitor is 0.05Ω to 0.2Ω. A typical output capacitor is an
AVX type TPS, 100µF at 10V, with a guaranteed ESR less
than 0.1Ω. This is a “D” size surface mount solid tantalum
capacitor. TPS capacitors are specially constructed and
tested for low ESR, so they give the lowest ESR for a given
volume. The value in microfarads is not particularly criti­cal, and values from 22µF to greater than 500µF work well,
but you cannot cheat mother nature on ESR. If you find a
tiny 22µF solid tantalum capacitor, it will have high ESR,
and output ripple voltage will be terrible. Table 3 shows
some typical solid tantalum surface mount capacitors.

Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current

ESR (Max., Ω) Ripple Current (A)

E Case Size

AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1

D Case Size

AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1

C Case Size

AVX TPS 0.2 (typ) 0.5 (typ)

sn3431 3431fs

13

LT3431

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APPLICATIO S I FOR ATIO

Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true, and type TPS capacitors are
specially tested for surge capability, but surge ruggedness
is not a critical issue with the
tantalum capacitors fail during very high
which do not occur at the output of regulators. High

discharge

dead shorted, do not harm the capacitors.
Unlike the input capacitor, RMS ripple current in the

output capacitor is normally low enough that ripple cur­rent rating is not an issue. The current waveform is
triangular with a typical value of 250mA
to calculate this is:

Output capacitor ripple current (RMS):

I

surges, such as when the regulator output is

VVV

029.

OUT IN OUT

()

RIPPLE RMS

()

=

()()( )

Ceramic Capacitors

Ceramic capacitors are generally chosen for their good
high frequency operation, small size and very low ESR
(effective series resistance). Their low ESR reduces out­put ripple voltage but also removes a useful zero in the
loop frequency response, common to tantalum capaci­tors. To compensate for this, a resistor RC can be placed
in series with the VC compensation capacitor CC. Care
must be taken however, since this resistor sets the high
frequency gain of the error amplifier, including the gain at
the switching frequency. If the gain of the error amplifier
is high enough at the switching frequency, output ripple
voltage (although smaller for a ceramic output capacitor)
may still affect the proper operation of the regulator. A
filter capacitor CF in parallel with the RC/CC network is
suggested to control possible ripple at the VC pin. An “All
Ceramic” solution is possible for the LT3431 by choosing
the correct compensation components for the given
application.

Example: For VIN = 8V to 20V, V
can be stabilized, provide good transient response and
maintain very low output ripple voltage using the follow­ing component values: (refer to the first page of this data

output

capacitor. Solid

turn-on

RMS

−

()

LfV

IN

= 5V at 2A, the LT3431

OUT

surges,

. The formula

sheet for component references) C3 = 2.2µF, RC = 1.5k,
CC = 15nF, CF = 220pF and C1 = 47µF. See Application
Note 19 for further detail on techniques for proper loop
compensation.

INPUT CAPACITOR

Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage
ripple this causes at the input of LT3431 and force the
switching current into a tight local loop, thereby minimiz­ing EMI. The RMS ripple current can be calculated from:

IIVVVV

RIPPLE RMS

Ceramic capacitors are ideal for input bypassing. At 500kHz
switching frequency, the energy storage requirement of
the input capacitor suggests that values in the range of

2.2µF to 10µF are suitable for most applications. If opera-
tion is required close to the minimum input required by the
output of the LT3431, a larger value may be required. This
is to prevent excessive ripple causing dips below the
minimum operating voltage resulting in erratic operation.

Depending on how the LT3431 circuit is powered up you
may need to check for input voltage transients.

The input voltage transients may be caused by input
voltage steps or by connecting the LT3431 converter to an
already powered up source such as a wall adapter. The
sudden application of input voltage will cause a large
surge of current in the input leads that will store energy in
the parasitic inductance of the leads. This energy will
cause the input voltage to swing above the DC level of input
power source and it may exceed the maximum voltage
rating of input capacitor and LT3431.

The easiest way to suppress input voltage transients is to
add a small aluminum electrolytic capacitor in parallel with
the low ESR input capacitor. The selected capacitor needs
to have the right amount of ESR in order to critically
dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESR will fall in the range of 0.5Ω to 2Ω and capacitance will
fall in the range of 5µF to 50µF.

=

()

OUT OUT IN OUT IN

–/

()

2

sn3431 3431fs

14

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APPLICATIO S I FOR ATIO

LT3431

If tantalum capacitors are used, values in the 22µF to
470µF range are generally needed to minimize ESR and
meet ripple current and surge ratings. Care should be
taken to ensure the ripple and surge ratings are not
exceeded. The AVX TPS and Kemet T495 series are surge
rated. AVX recommends derating capacitor operating
voltage by 2:1 for high surge applications.

CATCH DIODE

Highest efficiency operation requires the use of a Schottky
type diode. DC switching losses are minimized due to its
low forward voltage drop, and AC behavior is benign due
to its lack of a significant reverse recovery time. Schottky
diodes are generally available with reverse voltage ratings
of up to 60V and even 100V, and are price competitive with
other types.

The use of so-called “ultrafast” recovery diodes is gener­ally not recommended. When operating in continuous
mode, the reverse recovery time exhibited by “ultrafast”
diodes will result in a slingshot type effect. The power
internal switch will ramp up VIN current into the diode in an
attempt to get it to recover. Then, when the diode has
finally turned off, some tens of nanoseconds later, the V
node voltage ramps up at an extremely high dV/dt, per­haps 5 to even 10V/ns! With real world lead inductances,
the VSW node can easily overshoot the VIN rail. This can
result in poor RFI behavior and if the overshoot is severe
enough, damage the IC itself.

SW

BOOST␣ PIN␣

For most applications, the boost components are a 0.22µF
capacitor and a MMSD914TI diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately V
stage. However, the output stage discharges the boost
capacitor during the on time of the switch. The output
driver requires at least 3V of headroom throughout this
period to keep the switch fully saturated. If the output
voltage is less than 3.3V, it is recommended that an
alternate boost supply is used. The boost diode can be
connected to the input, although, care must be taken to
prevent the 2× VIN boost voltage from exceeding the
BOOST pin absolute maximum rating. The additional
voltage across the switch driver also increases power
loss, reducing efficiency. If available, an independent
supply can be used with a local bypass capacitor.

A 0.22µF boost capacitor is recommended for most appli-
cations. Almost any type of film or ceramic capacitor is
suitable, but the ESR should be <1Ω to ensure it can be
fully recharged during the off time of the switch. The
capacitor value is derived from worst-case conditions of
1840ns on time, 75mA boost current and 0.7V discharge
ripple. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve
circuit operation or efficiency. Under low input voltage and
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start-up operation.

above VIN to drive the output

OUT

The suggested catch diode (D1) is an International Recti­fier 30BQ060 Schottky. It is rated at 3A average forward
current and 60V reverse voltage. Typical forward voltage
is 0.52V at 3A. The diode conducts current only during
switch off time. Peak reverse voltage is equal to regulator
input voltage. Average forward current in normal opera­tion can be calculated from:

IVV

I

D AVG

()

This formula will not yield values higher than 3A with
maximum load current of 3A.

OUT IN OUT

=

–

()

V

IN

SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT

Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT3431. Typically, UVLO is used in situations where
the input supply is
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.

current limited

, or has a relatively high

sn3431 3431fs

15

LT3431

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APPLICATIO S I FOR ATIO

R

FB

LT3431

INPUT

IN

R

HI

SHDN

R

C2

LO

Figure 4. Undervoltage Lockout

2.38V

5.5µA

0.4V

Threshold voltage for lockout is about 2.38V. A 5.5µA bias
current flows

out

of the pin at this threshold. The internally
generated current is used to force a default high state on
the shutdown pin if the pin is left open. When low shut­down current is not an issue, the error due to this current
can be minimized by making R

10k or less. If shutdown

LO

current is an issue, RLO can be raised to 100k, but the error
due to initial bias current and changes with temperature
should be considered.

+

STANDBY

–

+

–

GND

TOTAL
SHUTDOWN

25k suggested for R

L1

V

SW

LO

OUTPUT

+

C1

3431 F04

VIN = Input voltage at which switching stops as input
voltage descends to trip level
∆V = Hysteresis in input voltage level

Example: output voltage is 5V, switching is to stop if input
voltage drops below 12V and should not restart unless
input rises back to 13.5V. ∆V is therefore 1.5V and
VIN␣ =␣ 12V. Let RLO = 25k.

Rk

=

10

LO

R

HI

to 100k 25k suggested

RV V

LO IN

()

()

−

238

.

=

VR A

−

238 55

..µ

LO

()

VIN = Minimum input voltage

Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capaci­tance to the switching nodes are minimized. If high
resistor values are used, the shutdown pin should be
bypassed with a 1000pF capacitor to prevent coupling
problems from the switch node. If hysteresis is desired in
the undervoltage lockout point, a resistor RFB can be
added to the output node. Resistor values can be calcu­lated from:

RV VV V

LO IN OUT

R

=

HI

=

RRVV

FB HI OUT

()( )

−+

238 1

./

∆∆

[]

238 55

()

−

RA

..

LO

()

/

∆

+

µ

k

25 12 238155 1 15

R

=

HI

25 10 41

=

Rk k

=

116 5 1 5 387

FB

−+

../ .

[]

238 25 55

.– .

k

.

()

224

.

/.

()

()

kA

()

k

=

116

=

+

µ

SYNCHRONIZING

The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The synchronizing range is equal
to

initial

operating frequency up to 700kHz. This means

that

minimum

worst-case

practical sync frequency is equal to the

high

self-oscillating frequency (570kHz), not
the typical operating frequency of 500kHz. Caution should
be used when synchronizing above 662kHz because at
higher sync frequencies the amplitude of the internal slope
compensation used to prevent subharmonic switching is

16

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LT3431

reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa­tion. Application Note 19 has more details on the theory
of slope compensation.

At power-up, when VC is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows the
frequency foldback to operate in the shorted output con­dition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches

0.6V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.

LAYOUT CONSIDERATIONS

As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal elec­trical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the

nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is imple­mented in the suggested layout of Figure 6. Shortening
this path will also reduce the parasitic trace inductance of
approximately 25nH/inch. At switch off, this parasitic in­ductance produces a flyback spike across the LT3431
switch. When operating at higher currents and input volt­ages, with poor layout, this spike can generate voltages
across the LT3431 that may exceed its absolute maximum
rating. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling and over­all noise.

LT3431

HIGH

V

IN

FREQUENCY

CIRCULATING

PATH

Figure 5. High Speed Switching Path

L1

D1C3 C1

5V

LOAD

3431 F05

GND1

2

SW
V

3

IN

V

4

IN

LT3431

SW

5
6 BOOST

PINS 3 AND 4

V

IN

ARE SHORTED TOGETHER.

SW PINS 2 AND 5 ARE ALSO

SHORTED TOGETHER (USING
AVAILABLE SPACE UNDERNEATH
THE DEVICE BETWEEN PINS AND

GND PLANE)

MINIMIZE LT3430

C3-D1 LOOP

GND

V

IN

L1

D2

D1

C3

PLACE FEEDTHROUGH AROUND

GROUND PINS (4 CORNERS) FOR

GOOD THERMAL CONDUCTIVITY

C2

GND GND1

2

SW
V

3

IN

V

4

IN

LT3431

SW

5

BOOST

6
7
8

GND

BIAS

GND

Figure 6. Suggested Layout

CONNECT TO

GROUND PLANE

GND

SOLDER THE EXPOSED PAD

C1

V

16

SHDN

15
14

SYNC

13

FB

12

V

11

R2

C

10

9

CFB

F

R1

C

RCC

C

KELVIN SENSE

V

TO THE ENTIRE COPPER
GROUND PLANE UNDERNEATH
THE DEVICE. NOTE: THE BOOST
AND BIAS COPPER TRACES ARE

OUT

ON A SEPARATE LAYER FROM
THE GROUND PLANE

OUT

KEEP FB AND VC COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS

3431 F06

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The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT3431
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.

Board layout also has a significant effect on thermal
resistance. Pins 1, 8, 9 and 16, GND, are a continuous
copper plate that runs under the LT3431 die. This is an
exposed pad and is the best thermal path for heat out of the
package. Soldering the exposed pad to the copper ground
plane under the device will reduce die temperature and
increase the power capability of the LT3431. Adding
multiple solder filled feedthroughs under and around the
four corner pins to the ground plane will also help. Similar
treatment to the catch diode and coil terminations will
reduce any additional heating effects.

PARASITIC RESONANCE

Resonance or “ringing” may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schot­tky diodes have very high “Q” junction capacitance that
can ring for many cycles when excited at high frequency.
If total lead length for the input capacitor, diode and
switch path is 1 inch, the inductance will be approximately
25nH. At switch off, this will produce a spike across the
NPN output device in addition to the input voltage. At
higher currents this spike can be in the order of 10V to 20V
or higher with a poor layout, potentially exceeding the

abso

lute max switch voltage. The path around switch,
catch diode and input capacitor must be kept as short as
possible to ensure reliable operation. When looking at this,
a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
switch off spike will also cause the SW node to go below
ground. The LT3431 has special circuitry inside which
mitigates this problem, but negative voltages over 0.8V
lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.

A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor current to fall to zero during part of the switch off
time (see Figure 8). Switch and diode capacitance reso­nate with the inductor to form damped ringing at 1MHz to
10MHz. This ringing is not harmful to the regulator and it
has not been shown to contribute significantly to EMI. Any
attempt to damp it with a resistive snubber will degrade
efficiency.

0.2A/DIV

5V/DIV

= 12V 500ns/DIV 3431 F08

V

IN

V

= 5V

OUT

L = 10µH

Figure 8. Discontinuous Mode Ringing

INDUCTOR
CURRENT AT
I

= 0.1A

OUT

SWITCH NODE
VOLTAGE

18

SW RISE SW FALL

2V/DIV

50ns/DIV

Figure 7. Switch Node Resonance

3431 F07

THERMAL CALCULATIONS

Power dissipation in the LT3431 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu­las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.

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LT3431

Switch loss:

RI V

P

=

SW

2

SW OUT OUT

()( )

+

V

IN

tIVf

12(/ )

EFF OUT IN

()()()

When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power:

P

DIODE

=

Boost current loss:

VF = Forward voltage of diode (assume 0.52V at 2A)

2

VI

P

BOOST

OUT OUT

=

Quiescent current loss:

PV V

=

Q IN OUT

0 0015 0 003..

()

RSW = Switch resistance (≈0.15) hot
t

= Effective switch current/voltage overlap time

EFF

= (tr + tf + tIr + tIf)
tr = (VIN/1.2)ns

36/

()

V

IN

+

()

PW

==

DIODE

Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
lower VF diode can improve efficiency by several percent.

P

INDUCTOR

R

= Inductor DC resistance (assume 0.1Ω)

IND

P

INDUCTOR

tf = (VIN/1.1)ns
tIr = tIf = (I

OUT

/0.05)ns

f = Switch frequency

Typical thermal resistance of the board is 5°C/W. Taking
the catch diode and inductor power dissipation into ac­count and using the example calculations for LT3431

Example: with VIN = 12V, V

015 2 5

P

PW

PW

(. )()()

=+

SW

025 061 086

=+=

...

BOOST

Q

==

12 0 0015 5 0 003 0 033

(. ) (. ) .

=+=

2

12

2

5236

()( / )

12

101 10 12 2 12 500 10

( • )( / )( )( )( • )

Total power dissipation in the IC is given by:

P

= PSW + P

TOT

BOOST

= 0.86W + 0.12W + 0.03W = 1.01W

Thermal resistance for the LT3431 package is influenced
by the presence of internal or backside planes.

TSSOP (Exposed Pad) Package: With a full plane under the
TSSOP package, thermal resistance (θJA) will be about
45°C/W.

OUT

W

012

.

+ P

= 5V and I

OUT

= 2A

dissipation, the LT3431 die temperature will be estimated
as:

93

−

TJ = TA + (θJA • P

With the TSSOP package (θJA = 45°C/W), at an ambient
temperature of 50°C:

TJ = 50 + (45 • 1.01) + (5 • 1.01) = 101°C

Die temperature can peak for certain combinations of VIN,
V

and load current. While higher VIN gives greater

OUT

switch AC losses, quiescent and catch diode losses, a
lower VIN may generate greater losses due to switch DC

Q

losses. In general, the maximum and minimum VIN levels
should be checked with maximum typical load current for
calculation of the LT3431 die temperature. If a more
accurate die temperature is required, a measurement of
the SYNC pin resistance (to GND) can be used. The SYNC
pin resistance can be measured by forcing a voltage no
greater than 0.5V at the pin and monitoring the pin current
over temperature in an oven. This should be done with

To calculate die temperature, use the proper thermal
resistance number for the desired package and add in
worst-case ambient temperature:

TJ = TA + (θJA • P

TOT

)

minimal device power (low VIN and no switching
(VC = 0V)) in order to calibrate SYNC pin resistance with
ambient (oven) temperature.

VV V I

( )( – )( )

F IN OUT LOAD

V

IN

(. )( – )()

052 12 5 2

.

061

12

= (I

LOAD

)2(R

IND

)

(2)2(0.1) = 0.4W

) + [5 • (P

TOT

DIODE

+ P

INDUCTOR

sn3431 3431fs

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APPLICATIO S I FOR ATIO

Note: Some of the internal power dissipation in the IC, due
to BOOST pin voltage, can be transferred outside of the IC
to reduce junction temperature, by increasing the voltage
drop in the path of the boost diode D2. (see Figure␣ 9). This
reduction of junction temperature inside the IC will allow
higher ambient temperature operation for a given set of
conditions. BOOST pin circuitry dissipates power given
by:

P

DISS BOOST

()

•( / )•

OUT SW C

=

36

V

IN

2

VI V

Typically VC2 (the boost voltage across the capacitor C2)
equals V

. This is because diodes D1 and D2 can be

OUT

considered almost equal, where:

VC2 = V

OUT

– V

FD2

– (–V

FD1

) = V

OUT

.

Hence the equation used for boost circuitry power dissipa­tion given in the previous Thermal Calculations section is
stated as:

Example : The BOOST pin power dissipation for a 20V input
to 12V output conversion at 2A is given by :

12 2 36 12

PW

BOOST

•( / )•

==

04

.

20

If a 7V zener D4 is placed in series with D2, then power
dissipation becomes :

12 2 36 5

PW

BOOST

•( / )•

==

0 167

.

20

For an FE package with thermal resistance of 45°C/W,
ambient temperature savings would be, T

(AMBIENT)

sav-

ings = 0.233W • 45°C/W = 11°C. The 7V zener should be
sized for excess of 0.233W operaton. The tolerances of the
zener should be considered to ensure minimum VC2 ex­ceeds 3.3V + V

DROOP

.

D2 D4

D2

P

DISS BOOST

()

•( / )•

VI V

OUT SW OUT

=

36

V

IN

Here it can be seen that Boost power dissipation increases
as the square of Vout. It is possible, however, to reduce
VC2 below Vout to save power dissipation by increasing
the voltage drop in the path of D2. Care should be taken
that VC2 does not fall below the minimum 3.3V Boost
voltage required for full saturation of the internal power
switch. For output voltages of 5V, VC2 is approximately 5V.
During switch turn on, VC2 will fall as the boost capacitor
C2 is dicharged by the boost pin. In a previous BOOST Pin
section, the value of C2 was designed for a 0.7V droop in
VC2 = V

. Hence, an output voltage as low as 4V

DROOP

would still allow the minimum 3.3V for the boost function
using the C2 capacitor calculated. If a target output voltage
of 12V is required, however, an excess of 8V is placed
across the boost capacitor which is not required for the
boost function, but still dissipates additional power. What
is required is a voltage drop in the path of D2 to achieve
minimal power dissipation while still maintaining mini­mum boost voltage across C2. A zener, D4, placed in
series with D2 (see Figure 9), drops voltage to C2.

SW

BIAS

V

C2

FB

C

C

F

L1

R1

+

D1

R2

C1

3431 F09

BOOST

V

IN

V

LT3431

IN

C3

SHDN
SYNC

GND

R

C

C

C

Figure 9. BOOST Pin, Diode Selection

Input Voltage vs Operating Frequency Considerations

The absolute maximum input supply voltage for the LT3431
is specified at 60V. This is based on internal semiconduc­tor junction breakdown effects. The practical maximum
input supply voltage for the LT3431 may be less than 60V
due to internal power dissipation or switch minimum on
time considerations.

For the extreme case of an output short-circuit fault to
ground, see the section Short-Circuit Considerations.

20

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LT3431

A detailed theoretical basis for estimating internal power
dissipation is given in the Thermal Calculations section.
This will allow a first pass check of whether an application’s
maximum input voltage requirement is suitable for the
LT3431. Be aware that these calculations are for DC input
voltages and that input voltage transients as high as 60V
are possible if the resulting increase in internal power
dissipation is of insufficient time duration to raise die
temperature significantly. For the FE package, this means
high voltage transients on the order of hundreds of milli­seconds are possible. If LT3431 thermal calculations
show power dissipation is not suitable for the given
application, the LT3430 is a recommended alternative
since it is identical to the LT3431 but runs cooler at
200kHz.

Switch minimum on time is the other factor that may limit
the maximum operational input voltage for the LT3431 if
pulse-skipping behavior is not allowed. For the LT3431,
pulse-skipping may occur for VIN/(V

+ VF) ratios > 4.

OUT

(VF = Schottky diode D1 forward voltage drop, Figure 5.)
If the LT3430 is used, the ratio increases to 10. Pulse­skipping is the regulator’s way of missing switch pulses to
maintain output voltage regulation. Although an increase
in output ripple voltage can occur during pulse-skipping,
a ceramic output capacitor can be used to keep ripple
voltage to a minimum (see output ripple voltage compari­son for tantalum vs ceramic output capacitors, Figure 3).

FREQUENCY COMPENSATION

Before starting on the theoretical analysis of frequency
response, the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/
or catch diode, and connecting the VC compensation to a
ground track carrying significant switch current. In addi-

tion, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with produc­tion layout and components.

The LT3431 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 10.
The LT3431 can be considered as two gm blocks, the error
amplifier and the power stage.

LT3431

CURRENT MODE

POWER STAGE

= 2mho

g

m

V

GND

C

R

C

ERROR

AMPLIFIER

=

g

m

2000µmho

R

O

200k

C

C

F

C

Figure 10. Model for Loop Response

SW

C

R1

FB

–

+

1.22V

FB

R

LOAD

R2

+

3431 F10

OUTPUT

CERAMIC

ESR

C1

TANTALUM

ESL

C1

Figure 11 shows the overall loop response. At the VC pin,
the frequency compensation components used are:
RC = 3.3k, CC = 0.022µF and CF = 220pF. The output
capacitor used is a 100µF, 10V tantalum capacitor with
typical ESR of 100mΩ.

The ESR of the tantalum output capacitor provides a
useful zero in the loop frequency response for maintain­ing stability.

This ESR, however, contributes significantly to the ripple
voltage at the output (see Output Ripple Voltage in the
Applications Information section). It is possible to reduce
capacitor size and output ripple voltage by replacing the

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21

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APPLICATIO S I FOR ATIO

tantalum output capacitor with a ceramic output capacitor
because of its very low ESR. The zero provided by the
tantalum output capacitor must now be reinserted back
into the loop. Alternatively there may be cases where, even
with the tantalum output capacitor, an additional zero is
required in the loop to increase phase margin for improved
transient response.

A zero can be added into the loop by placing a resistor, R
at the VC pin in series with the compensation capacitor, C

C,

C

or by placing a capacitor, CFB, between the output and the
FB pin.

80

60

40

20

GAIN (dB)

0

–20

–40

PHASE

10

= 12V

V

IN

= 5V

V

OUT

= 1A

I

LOAD

= 100µF, 10V, 0.1Ω

C

OUT

GAIN

1k 10k 1M100 100k

FREQUENCY (Hz)

RC = 3.3k

= 22nF

C

C

= 220pF

C

F

Figure 11. Overall Loop Response

3431 F11

180

150

120

90

60

30

0

PHASE (DEG)

When using RC, the maximum value has two limitations.
First, the combination of output capacitor ESR and RC may
stop the loop rolling off altogether. Second, if the loop gain
is not rolled sufficiently at the switching frequency, output
ripple will perturb the VC pin enough to cause unstable
duty cycle switching similar to subharmonic oscillation. If
needed, an additional capacitor (CF) can be added across
the RC/CC network from VC pin to ground to further
suppress VC ripple voltage.

With a tantalum output capacitor, the LT3431 already
includes a resistor, RC and filter capacitor, CF, at the VC pin
(see Figures 10 and 11) to compensate the loop over the
entire VIN range (to allow for stable pulse skipping for high
VIN-to-V

ratios ≥4). A ceramic output capacitor can still

OUT

be used with a simple adjustment to the resistor RC for
stable operation. (See Ceramic Capacitors section for
stabilizing LT3431). If additional phase margin is required,

a capacitor, CFB, can be inserted between the output and
FB pin but care must be taken for high output voltage
applications. Sudden shorts to the output can create
unacceptably large negative transients on the FB pin.

For VIN-to-V

ratios <4, higher loop bandwidths are

OUT

possible by readjusting the frequency compensation com­ponents at the VC pin.

When checking loop stability, the circuit should be oper­ated over the application’s full voltage, current and
temperature range. Proper loop compensation may be
obtained by empirical methods as described in detail in
Application Notes 19 and 76.

CONVERTER WITH BACKUP OUTPUT REGULATOR

In systems with a primary and backup supply, for ex­ample, a battery powered device with a wall adapter input,
the output of the LT3431 can be held up by the backup
supply with the LT3431 input disconnected. In this condi­tion, the SW pin will source current into the VIN pin. If the
SHDN pin is held at ground, only the shut down current of
30µA will be pulled via the SW pin from the second supply.
With the SHDN pin floating, the LT3431 will consume its
quiescent operating current of 1.5mA. The VIN pin will also
source current to any other components connected to the
input line. If this load is greater than 10mA or the input
could be shorted to ground, a series Schottky diode must
be added, as shown in Figure 12. With these safeguards,
the output can be held at voltages up to the VIN absolute
maximum rating.

D2

MMSD914TI

D3

REMOVABLE

INPUT

30BQ060

54k

25k

C3

4.7µF

V

IN

SHDN
SYNC

GND

0.022µF

BOOST
LT3431

R

C

3.3k
C

C

BIAS

V

SW

FB

C

C
220pF

Figure 12. Dual Source Supply with 25µA Reverse Leakage

C2

0.22µF
10µH

5V, 2A

ALTERNATE

R1

15.4k

D1
30BQ060

F

R2

4.99k

SUPPLY

+

C1
100µF
10V

3431 F12

22

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LT3431

BUCK CONVERTER WITH ADJUSTABLE SOFT-START

Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 13 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
configuration with the addition of R3, R4, CSS and Q1.
As the output starts to rise, Q1 turns on, regulating switch
current via the VC pin to maintain a constant dv/dt at the
output. Output rise time is controlled by the current
through CSS defined by R4 and Q1’s VBE. Once the output
is in regulation, Q1 turns off and the circuit operates
normally. R3 is transient protection for the base of Q1.

RC V

4

Rise Time

()( )( )

=

SS OUT

V

BE

Using the values shown in Figure 10,

Rise Time ms=

39

••

47 10 15 10 5

()( )

07

–

()

=

5

.

The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can be
used for sequencing multiple regulator outputs.

D2

MMSD914TI

C2

INPUT

12V

C3

4.7µF
25V
CER

BOOST BIAS

V

IN

LT3431

SHDN

SYNC

GND

R

C

3.3k

C

C

0.022µF

0.22µF

SW

FB

V

C

C

F

220pF

D1
30BQ060
OR B250A

Q1

L1

15µH

+

C1

100µF

10V

C

SS

R3

15nF

2k

R4
47k

L1: CDRH104R-220M

R1

15.4k

R2

4.99k

3431 F13

OUTPUT
5V
2A

Dual Polarity Output Converter

The circuit in Figure 14a generates both positive and
negative 5V outputs with all components under 3mm
height. The topology for the 5V output is a standard buck
converter. The –5V output uses a second inductor L2,
diode D3, and output capacitor C6. The capacitor C4
couples energy to L2 and ensures equal voltages across
L2 and L1 during steady state. Instead of using a trans­former for L1 and L2, uncoupled inductors were used
because they require less height than a single transformer,
can be placed separately in the circuit layout for optimized
space savings and reduce overall cost. This is true even
when the uncoupled inductors are sized (twice the value of
inductance of the transformer) in order to keep ripple
current comparable to the transformer solution. If a single
transformer becomes available to provide a better height
/cost solution, refer to the Dual Output SEPIC circuit
description in Design Note 100 for correct transformer
connection.

During switch on-time, in steady state, the voltage across
both L1 and L2 is positive and equal ; with energy (and
current) ramping up in each inductor. The current in L2 is
provided by the coupling capacitor C4. During switch off­time, current ramps downward in each inductor. The
current in L2 and C4 flows via the catch diode D3, charging
the negative output capacitor C6. If the negative output is
not loaded enough it can go severely unregulated (become
more negative). Figure 14b shows the maximum allow­able –5V output load current (vs load current on the 5V
output) that will maintain the –5V output within 3%
tolerance. Figure 14c shows the –5V output voltage regu­lation versus its own load current when plotted for three
separate load currents on the 5V output. The efficiency of
the dual polarity output converter circuit shown in Figure
14a is given in Figure 14d.

Figure 13. Buck Converter with Adjustable Soft-Start

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23

LT3431

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APPLICATIO S I FOR ATIO

V

IN

9V TO 16V

36V TRANSIENT

C3

2.2µF

50V

CER

V

IN

SHDN

LT3431EFE

SYNC

GND V

BOOST

SW

BIAS

C

D2

MMSD914T1

C2

0.22µF

V

OUT1

R2

15.4k

F

B

R3

4.99k

C4
10µF

6.3V
0805
X5R
CER

L1

CDRH6D28-100

10µH

V

OUT1

5V AT

1.5A*

C5
22µF

6.3V
X5R CER

1200

1000

800

600

LOAD CURRENT (mA)

400

OUT2

V

200

0

0

500

V

OUT1

Figure 14a. Dual Polarity Output Converter with all Components Under 3mm Height

VIN = 16V

VIN = 12V

1000

LOAD CURRENT (mA)

1500

R

1.5k

†

FOR LOAD CURRENT LESS THAN 25mA,
A PRELOAD OF 200Ω SHOULD BE USED

TO IMPROVE LOAD REGULATION.

*SEE FIGURE 14c FOR V

LOAD CURRENT RELATIONSHIP

VIN = 9V

2000

3431F14b

5.30

5.25

5.20

5.15

5.10

5.05

| (V)

5.00

OUT2

4.95

|V

4.90

4.85

4.80
4/75

4.70

OUT1

, V

OUT2

V

AT 500mA

OUT1

200

0

C

C

F

220pF

C

C

10nF

V

400

V

LOAD CURRENT (mA)

OUT2

OUT1

600

V

OUT1

AT 1A

D1
B140A

L2
CDRH6D28-100
10µH

B140A

VIN = 12V

AT 1.5A

800

1000

3431 F14c

C6
22µF

6.3V
X5R CER

†

V

OUT2

D3

–5V AT 0.9A*

3431 F14a

100

95

90

85

80

75

EFFICIENCY ( %)

70

65

60

0 200

V

OUT1

V

OUT1

AT 500mA

400

V

LOAD CURRENT (mA)

OUT2

VIN = 12V

AT 1A

V

AT 1.5A

OUT1

600 800 1000

3431 F14d

Figure 14b. V

OUT2

Allowable Load Current vs V
(5V) Load Current

24

(–5V) Maximum

OUT1

Figure 14c. V

OUT2

(–5V)

Output Voltage vs Load Current

Figure 14d. Dual Polarity
Output Converter Efficiency

sn3431 3431fs

WUUU

APPLICATIO S I FOR ATIO

LT3431

POSITIVE-TO-NEGATIVE CONVERTER

The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback signal
because the LT3431 accepts only positive feedback sig­nals. The ground pin must be tied to the regulated negative
output. A resistor divider to the FB pin then provides the
proper feedback voltage for the chip.

The following equation can be used to calculate maximum
load current for the positive-to-negative converter:

I

MAX



I



P



=

VV

()( )

–

IN OUT

VVfL

2

(–.)()

+

()()()

OUT IN

VV VV

++

OUT IN OUT F



VV

()(–.)



OUT IN



015

015

IP = Maximum rated switch current
VIN = Minimum input voltage
V

= Output voltage

OUT

VF = Catch diode forward voltage

0.15 = Switch voltage drop at 3A

Example: with V
VF = 0.52V, IP = 3A: I

INPUT

12V

C3

2.2µF

25V

CER

* INCREASE L1 FOR HIGHER CURRENT APPLICATIONS.

SEE APPLICATIONS INFORMATION

** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE

AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION

V

IN

GND

Figure 15. Positive-to-Negative Converter

IN(MIN)

MAX

BOOST

LT3431

C

F

= 5.5V, V

= 0.6A.

SW

FB

V

C

C

C

R

C

= 12V, L = 3.9µH,

OUT

†

D2

MMSD914TI

C2

L1*

0.22µF

3.9µH

R1

36.5k

D1
30BQ060

R2

4.12k

+

C1
100µF
16V TANT

OUTPUT**
–12V, 0.5A

3431 F15

Inductor Value

The criteria for choosing the inductor is typically based on
ensuring that peak switch current rating is not exceeded.
This gives the lowest value of inductance that can be used,
but in some cases (lower output load currents) it may give
a value that creates unnecessarily high output ripple
voltage.

The difficulty in calculating the minimum inductor size
needed is that you must first decide whether the switcher
will be in continuous or discontinuous mode at the critical
point where switch current reaches 3A. The first step is to
use the following formula to calculate the load current
above which the switcher must use continuous mode. If
your load current is less than this, use the discontinuous
mode formula to calculate minimum inductor needed. If
load current is higher, use the continuous mode formula.

Output current where continuous mode is needed:

22

VI

()()

I

CONT

>

4

VV VV V

()( )

IN OUT IN OUT F

IN P

+++

Minimum inductor discontinuous mode:

VI

2

()()

=

OUT OUT

2

fI

()( )

P

L

MIN

Minimum inductor continuous mode:

()( )

VV

IN OUT









()

VV

+

OUT F





V

IN















L

=

MIN

()( ) –

21

fV V I I

++

IN OUT P OUT

For a 12V to –12V converter using the LT3431 with peak
switch current of 3A and a catch diode of 0.52V:

22

()()

IA

=

CONT

()( .)

412121212052

12 3

+++

=

0 742

.

sn3431 3431fs

25

LT3431

WUUU

APPLICATIO S I FOR ATIO

For a load current of 0.5A, this says that discontinuous
mode can be used and the minimum inductor needed is
found from:

212 05

LH

MIN

()(.)

==µ

500 10 3

(•)()

32

27

.

In practice, the inductor should be increased by about
30% over the calculated minimum to handle losses and
variations in value. This suggests a minimum inductor of

3.5µH for this application.

Ripple Current in the Input and Output Capacitors

Positive-to-negative converters have high ripple current in
the input capacitor. For long capacitor lifetime, the RMS
value of this current must be less than the high frequency
ripple current rating of the capacitor. The following for­mula will give an
rent.

This formula assumes continuous mode and large

inductor value

approximate

value for RMS ripple cur-

. Small inductors will give somewhat higher
ripple current, especially in discontinuous mode. The
exact formulas are very complex and appear in Application
Note 44, pages 29 and 30. For our purposes here I have
simply added a fudge factor (ff). The value for ff is about

1.2 for higher load currents and L ≥15µH. It increases to
about 2.0 for smaller inductors at lower load currents.

reduces the size required for the output capacitor (versus
placing the input capacitor between VIN and ground).

The peak-to-peak ripple current in both the inductor and
output capacitor (assuming continuous mode) is:

•

DC V

I

=

P-P

==

DC Duty Cycle

I RMS

COUT

IN

•

fL

()

I

=

+

VV

OUT F

++

VVV

OUT IN F

P-P

12

The output ripple voltage for this configuration is as low as
the typical buck regulator based predominantly on the
inductor’s triangular peak-to-peak ripple current and the
ESR of the chosen capacitor (see Output Ripple Voltage in
Applications Information).

Diode Current

Average

diode current is equal to load current.

Peak

diode

current will be considerably higher.
Peak diode current:

Continuous Mode

=

V

Capacitor I ff I

= ()( )

RMS OUT

OUT

V

IN

ff = 1.2 to 2.0
The output capacitor ripple current for the positive-to-

negative converter is similar to that for a typical buck
regulator—it is a triangular waveform with peak-to-peak
value equal to the peak-to-peak triangular waveform of the
inductor. The low output ripple design in Figure 15 places
the input capacitor between VIN and the regulated negative
output. This placement of the input capacitor significantly

26

VV

+

()()()

IN OUT

I

OUT

V

IN

Discontinuous Mode

VV

+

IN OUT

LfV V

()()( )

2

=

+

IN OUT

IV

()( )

2

OUT OUT

()()

Lf

Keep in mind that during start-up and output overloads,
average diode current may be much higher than with
normal loads. Care should be used if diodes rated less than
1A are used, especially if continuous overload conditions
must be tolerated.

sn3431 3431fs

PACKAGE DESCRIPTIO

(.141)

3.58

U

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663,

Exposed Pad Variation BB)

4.90 – 5.10*
(.193 – .201)

3.58

(.141)

16 1514 13 12 11

LT3431

10 9

6.60 ±0.10

4.50 ±0.10

RECOMMENDED SOLDER PAD LAYOUT

0.09 – 0.20

(.0036 – .0079)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

0.65 BSC

4.30 – 4.50*
(.169 – .177)

0.45 – 0.75

(.018 – .030)

MILLIMETERS

(INCHES)

(.116)

0.45 ±0.05

2.94

1.05 ±0.10

1345678

2

° – 8°

0

0.65

(.0256)

BSC

0.195 – 0.30

(.0077 – .0118)

4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE

2.94

(.116)

1.10

(.0433)

MAX

0.05 – 0.15

(.002 – .006)

FE16 (BB) TSSOP 0203

6.40
BSC

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

sn3431 3431fs

27

LT3431

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1074/LT1074HV 4.4A (I

Step-Down DC/DC Converter DD-5/7, TO220-5/7 Packages

LT1076/LT1076HV 1.6A (I

Step-Down DC/DC Converter DD-5/7, TO220-5/7 Packages

LT1616 25V, 500mA (I

Step-Down DC/DC Converter ThinSOT Package

LT1676 60V, 440mA (I

Step-Down DC/DC Converter S8 Package

LTC1701/LTC1701B 700mA (I

Step-Down DC/DC Converter ThinSOT Package

LT1765 25V, 2.75A (I

Step-Down DC/DC Converter S8, TSSOP16E Packages

LT1766 60V, 1.2A (I

Step-Down DC/DC Converter TSSOP16/E Package

LT1767 25V, 1.2A (I

Step-Down DC/DC Converter MS8/E Packages

LT1776 40V, 550mA (I

Step-Down DC/DC Converter N8, S8 Packages

LTC1875 1.5A (I

Step-Down DC/DC Converter TSSOP16 Package

LTC1877 600mA (I

Step-Down DC/DC Converter MS8 Package

LTC1879 1.2A (I

Step-Down DC/DC Converter TSSOP16 Package

LT1956 60V, 1.2A (I

Step-Down DC/DC Converter TSSOP16/E Package

LTC3404 600mA (I

Step-Down DC/DC Converter MS8 Package

LTC3405/LTC3405A 300mA (I

Step-Down DC/DC Converter ThinSOT Package

LTC3406/LTC3406B 600mA (I

Step-Down DC/DC Converter ThinSOT Package

LTC3411 1.25A (I

Step-Down DC/DC Converter MS Package

LTC3412 2.5A (I

Step-Down DC/DC Converter TSSOP16E Package

LT3430 60V, 2.75A (I

Step-Down DC/DC Converter TSSOP16E Package

ThinSOT is a trademark of Linear Technology Corporation.

), 100kHz, High Efficiency VIN = 7.3V to 45/64V, V

OUT

), 100kHz, High Efficiency VIN = 7.3V to 45/64V, V

OUT

), 1.4MHz, High Efficiency VIN = 3.6V to 25V, V

OUT

), 100kHz, High Efficiency VIN = 7.4V to 60V, V

OUT

), 1MHz, High Efficiency VIN = 2.5V to 5V, V

OUT

), 1.25MHz, High Efficiency VIN = 3V to 25V, V

OUT

), 200kHz, High Efficiency VIN = 5.5V to 60V, V

OUT

), 1.25MHz, High Efficiency VIN = 3V to 25V; V

OUT

), 200kHz, High Efficiency VIN = 7.4V to 40V; V

OUT

), 550kHz, Synchronous VIN = 2.7V to 6V; V

OUT

), 550kHz, Synchronous VIN = 2.7V to 10V; V

OUT

), 550kHz, Synchronous VIN = 2.7V to 10V; V

OUT

), 500kHz, High Efficiency V

OUT

), 1.4MHz, Synchronous VIN = 2.7V to 6V, V

OUT

), 1.5MHz, Synchronous VIN = 2.7V to 6V, V

OUT

), 1.5MHz, Synchronous VIN = 2.5V to 5.5V, V

OUT

), 4MHz, Synchronous VIN = 2.5V to 5.5V, V

OUT

), 4MHz, Synchronous VIN = 2.5V to 5.5V, V

OUT

), 200kHz, High Efficiency VIN = 5.5V to 60V, V

OUT

= 5.5V to 60V, V

IN

= 2.21V, IQ = 8.5mA, I

OUT

= 2.21V, IQ = 8.5mA, I

OUT

= 1.25V, IQ = 1.9mA, I

OUT

= 1.24V, IQ = 3.2mA, I

OUT

= 1.25V, IQ = 135µA, I

OUT

= 1.2V, IQ = 1mA, I

OUT

= 1.2V, IQ = 2.5mA, I

OUT

= 1.2V, IQ = 1mA, I

OUT

= 1.24V, IQ = 3.2mA, I

OUT

= 0.8V, IQ = 15µA, I

OUT

= 0.8V, IQ = 10µA, I

OUT

= 0.8V, IQ = 15µA, I

OUT

= 1.2V, IQ = 2.5mA, I

OUT

= 0.8V, IQ = 10µA, I

OUT

= 0.8V, IQ = 20µA, I

OUT

= 0.6V, IQ = 20µA, I

OUT

= 0.8V, IQ = 60µA, I

OUT

= 0.8V, IQ = 60µA, I

OUT

= 1.2V, IQ = 2.5mA, I

OUT

SD

SD

SD

SD

SD

SD

SD

SD

= 15µA,

SD

= 6µA,

SD

= <1µA,

= <1µA,

SD

= <1µA,

SD

= 25µA,

SD

= <1µA,

= <1µA,

= <1µA,

SD

= <1µA,

SD

= <1µA,

SD

SD

= 10µA,

SD

= 10µA,

SD

= <1µA,

= 2.5µA,

= <1µA,

= 25µA,

= 30µA,

= 30µA,

28

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

sn3431 3431fs

LT/TP 0303 2K • PRINTED IN USA

 LINEAR TECHNOLOGY CORP ORATION 2003