Page 1
FEATURES
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
50
75
1
1
1977 TA02
25
0
0.001
0.01
0.01
0.1
0.1
10
10
100
POWER LOSS (W)
0.001
VIN = 12V
V
OUT
= 5V
V
OUT
= 3.3V
TYPICAL
POWER LOSS
LT1977
High Voltage 1.5A, 500kHz
Step-Down Switching Regulator
with 100µA Quiescent Current
U
DESCRIPTIO
■
Wide Input Range: 3.3V to 60V
■
1.5A Peak Switch Current
■
Burst Mode® Operation: 100µA Quiescent Current**
■
Low Shutdown Current: IQ < 1µA
■
Power Good Flag with Programmable Threshold
■
Load Dump Protection to 60V
■
500kHz Switching Frequency
■
Saturating Switch Design: 0.2Ω On-Resistance
■
Peak Switch Current Maintained Over
Full Duty Cycle Range*
■
1.25V Feedback Reference Voltage
■
Easily Synchronizable
■
Soft-Start Capability
■
Small 16-Pin Thermally Enhanced TSSOP Package
U
APPLICATIO S
■
High Voltage Power Conversion
■
14V and 42V Automotive Systems
■
Industrial Power Systems
■
Distributed Power Systems
■
Battery-Powered Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
*Protected by U.S. Patents including 6498466, 6531909.
**See Burst Mode Operation section for conditions
The LT®1977 is a 500kHz monolithic buck switching
regulator that accepts input voltages up to 60V. A high
efficiency 1.5A, 0.2Ω switch is included on the die along
with all the necessary oscillator, control and logic circuitry. Current mode topology is used for fast transient
response and good loop stability.
Innovative design techniques along with a new high voltage process achieve high efficiency over a wide input
range. Efficiency is maintained over a wide output current
range by employing Burst Mode operation at low currents,
utilizing the output to bias the internal circuitry, and by
using a supply boost capacitor to fully saturate the power
switch. Patented circuitry maintains peak switch current
over the full duty cycle range.* Shutdown reduces input
supply current to less than 1µA. External synchronization
can be implemented by driving the SYNC pin with logic-level
inputs. A single capacitor from the C
pin to the output
SS
provides a controlled output voltage ramp (soft-start). The
device also has a power good flag with a programmable
threshold and time-out and thermal shutdown protection.
The LT1977 is available in a 16-pin TSSOP package with
exposed pad leadframe for low thermal resistance. The
LT1976, a 200kHz reduced switch frequency version of the
LT1977, is also available. See the Applications Information
section for selection criteria between the LT1976 and
LT1977.
TYPICAL APPLICATIO
14V to 3.3V Step-Down Converter with
100µA No Load Quiescent Current
1500pF
26k
V
IN
1µF
2.2µF
100V
CER
330pF
V
SHDN
V
C
SYNC
GND
IN
C
T
LT1977
BOOST
SW
C
SS
V
BIAS
FB
PGFB
PG
0.1µF
0.1µF
10pF
10µH
10MQ100N
U
1N4148
165k
1%
100k
1%
Efficiency and Power Loss
Supply Current vs Input Voltage
150
125
V
OUT
3.3V
1A
100µF
+
6.3V
TANT
1977 TA01
100
75
50
SUPPLY CURRENT (µA)
25
0
10
0
20
INPUT VOLTAGE (V)
30 40
V
= 3.3V
OUT
= 25°C
T
A
50
60
1977 F05
vs Load Current
1977fa
1
Page 2
LT1977
WW
W
U
ABSOLUTE AXI U RATI GS
(Note 1)
VIN, SHDN, BIAS, SW, PG....................................... 60V
BOOST Pin Above SW ............................................ 35V
BOOST Pin Voltage ................................................. 68V
SYNC, C
Operating JunctionTemperature Range
LT1977EFE (Note 2) ........................ – 40°C to 125°C
LT1977IFE (Note 2) ......................... – 40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
, PGFB, FB................................................ 6V
SS
UUW
PACKAGE/ORDER I FOR ATIO
TOP VIEW
1
NC
2
SW
3
NC
4
V
IN
NC
BOOST
C
T
GND
16-LEAD PLASTIC TSSOP
T
= 125°C, θJA = 45°C/W, θ
JMAX
EXPOSED PAD IS GND (PIN 17)
MUST BE SOLDERED TO GND (PIN 8)
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
5
6
7
8
17
FE PACKAGE
16
15
14
13
12
11
10
JC(PAD)
PG
SHDN
SYNC
PGFB
FB
V
BIAS
C
9
= 10°C/W
C
SS
ORDER PART
NUMBER
LT1977EFE
LT1977IFE
FE PART
MARKING
1977EFE
1977IFE
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V, CSS/SYNC = 0V
J
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
SHDN
I
SHDN
I
VINS
I
VIN
I
BIASS
I
BIAS
V
REF
I
FB
I
PK
SHDN Threshold 1.15 1.3 1.45 V
SHDN Input Current SHDN = 12V
Minimum Input Voltage (Note 3)
Supply Shutdown Current SHDN = 0V, BOOST = 0V, FB/PGFB = 0V 0.1 2 µA
Supply Sleep Current (Note 4) BIAS = 0V, FB = 1.35V
FB = 1.35V
Supply Quiescent Current BIAS = 0V, FB = 1.15V 4.10 mA
BIAS = 5V, FB = 1.15V 3.25 mA
Minimum BIAS Voltage (Note 5) FB = 1.15V
BIAS Sleep Current (Note 4)
BIAS Quiescent Current SYNC = 3.3V 700 900 µA
Minimum Boost Voltage (Note 6) ISW = 1.5A 1.8 V
Input Boost Current (Note 7) ISW = 1.5A 40 mA
Reference Voltage (V
FB Input Bias Current 75 200 nA
EA Voltage Gain (Note 8) 900 V/V
EA Voltage g
EA Source Current FB = 1.15V 20 40 55 µA
EA Sink Current FB = 1.35V 15 30 40 µA
VC to SW g
VC High Clamp 2.1 2.2 2.4 V
SW Current Limit
m
m
) 3.3V < V
REF
dI(VC)= ±10µA 450 650 900 µMho
VIN
< 60V
●
●
●
●
●
●
●
1.225 1.25 1.275 V
●
1.5 2.4 3.5 A
520 µA
2.4 3 V
170 250 µA
45 75 µA
2.7 3 V
110 180 µA
3A/V
1977fa
2
Page 3
LT1977
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V, CSS/SYNC = 0V
J
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Switch On Resistance (Note 9)
Switching Frequency
Maximum Duty Cycle 86 92 %
Minimum SYNC Amplitude 1.5 2.0 V
SYNC Frequency Range 575 700 kHz
SYNC Input Impedance 85 kΩ
I
CSS
I
PGFB
V
PGFB
I
CT
V
CT
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1977EFE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT1977IFE is guaranteed and tested over the full –40°C to 125°C
operating junction temperature range.
Note 3: Minimum input voltage is defined as the voltage where switching
starts. Actual minimum input voltage to maintain a regulated output will
depend upon output voltage and load current. See Applications
Information.
Note 4: Supply input current is the quiescent current drawn by the input
pin. Its typical value depends on the voltage on the BIAS pin and operating
state of the LT1977. With the BIAS pin at 0V, all of the quiescent current
required to operate the LT1977 will be provided by the V
BIAS voltage above its minimum input voltage, a portion of the total
quiescent current will be supplied by the BIAS pin. Supply sleep current is
defined as the quiescent current during the “sleep” portion of Burst Mode
operation. See Applications Information for determining application supply
currents.
CSS Current Threshold (Note 10) FB = 0V 7 13 20 µA
PGFB Input Current 25 100 nA
PGFB Voltage Threshold (Note 11)
CT Source Current (Note 11) 2 3.6 5.5 µA
CT Sink Current (Note 11) 1 2 mA
CT Voltage Threshold (Note 11) 1.16 1.2 1.26 V
PG Leakage (Note 11) VPG = 12V 0.1 1 µA
PG Sink Current (Note 11) PGFB = 1V, PG = 400mV 100 200 µA
pin. With the
IN
Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when I
sourced into the pin.
Note 6: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 7: Boost current is the current flowing into the BOOST pin with the pin
held 3.3V above input voltage. It flows only during switch on time.
Note 8: Gain is measured with a V
Note 9: Switch on resistance is calculated by dividing V
forced current (1.5A). See Typical Performance Characteristics for the graph
of switch voltage at other currents.
Note 10: The C
C
pin which results in an increase in sink current from the VC pin. See the
SS
Soft-Start section in Applications Information.
Note 11: The PGFB threshold is defined as the percentage of V
which causes the current source output of the C
sinking (below threshold) to sourcing current (above threshold). When
sourcing current, the voltage on the C
internally. When the clamp is activated, the output of the PG pin will be set
to a high impedance state. When the C
be set active low with a current sink capability of 200µA.
threshold is defined as the value of current sourced into the
SS
●
●
425 500 575 kHz
●
88 90 92 %
swing from 1.15V to 750mV.
C
pin rises until it is clamped
T
T
0.2 0.4 Ω
to SW voltage by the
IN
pin to change from
T
clamp is inactive the PG pin will
REF
BIAS
voltage
is
1977fa
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LT1977
UW
TYPICAL PERFOR A CE CHARACTERISTICS
FB Voltage Oscillator Frequency SHDN Threshold
1.30
1.29
1.28
1.27
1.26
1.25
1.24
VOLTAGE (V)
1.23
1.22
1.21
1.20
–50 0
–25
SHDN Pin Current
5.5
TJ = 25°C
5.0
4.5
4.0
3.5
3.0
2.5
CURRENT (µA)
2.0
1.5
1.0
0
10
0
50
25
TEMPERATURE (°C)
30 40
20
SHDN VOLTAGE (V)
550
540
530
520
510
500
490
FREQUENCY (kHz)
480
470
460
450
100
125
1977 G01
75
–50
–25
0
TEMPERATURE (°C)
50
25
75
100
125
1977 G02
Shutdown Supply Current Sleep Mode Supply Current
25
20
15
10
CURRENT (µA)
5
0
50
60
1977 G04
–50 0
VIN = 42V VIN = 12V
–25
TEMPERATURE (°C)
VIN = 60V
50
25
75
100
125
1977 G05
1.40
1.35
1.30
1.25
1.20
VOLTAGE (V)
0.15
1.10
1.05
1.00
–50 0
200
180
160
140
120
100
80
CURRENT (µA)
60
40
20
0
–50 0
–25
–25
50
25
TEMPERATURE (°C)
V
= 0V
BIAS
V
= 5V
BIAS
50
25
TEMPERATURE (°C)
100
100
125
1977 G03
125
1977 G06
75
75
Bias Sleep Current
200
180
160
140
120
100
80
CURRENT (µA)
60
40
20
0
–50 0
–25
4
50
25
TEMPERATURE (°C)
PGFB Threshold
1.20
1.18
1.16
1.14
1.12
1.10
1.08
VOLTAGE (V)
1.06
1.04
1.02
1.00
100
125
1977 G07
75
–50 0
–25
TEMPERATURE (°C)
50
25
75
100
125
1977 G08
PG Sink Current
250
200
150
100
CURRENT (µA)
50
0
–50 0
–25
50
25
TEMPERATURE (°C)
100
125
1977 G09
1977fa
75
Page 5
UW
SWITCH CURRENT (A)
0
0
BOOST CURRENT (mA)
5
15
20
25
1
45
1977 G22
10
0.5
0.25
1.25
0.75 1.5
30
35
40
TYPICAL PERFOR A CE CHARACTERISTICS
Soft-Start Current Threshold
Switch Peak Current Limit
3.5
3.0
2.5
2.0
PEAK SWITCH CURRENT (A)
1.5
–50
–25 –0 25 50
TEMPERATURE (°C)
75 100 125
1977 G10
vs FB Voltage
50
TJ = 25°C
45
40
35
30
25
20
CURRENT (µA)
15
10
5
0
0
0.2
0.6 0.8
0.4
FB VOLTAGE (V)
SOFT-START
DEFEATED
1.0
1977 G11
1.2
LT1977
Frequency Foldback Percentage
100
90
80
70
60
50
40
30
FOLDBACK PERCENTAGE (%)
20
10
0
0.25
0
FB PIN VOLTAGE (V)
0.5
0.75
1
1.25
1977 G12
500
450
400
350
300
250
200
VOLTAGE (mV)
150
100
50
0
–0.1
500
450
400
350
300
250
200
150
LOAD CURRENT (mA)
100
50
0
Switch On Voltage (V
TJ = 125°C
0.1 0.5
0.3
0.7
LOAD CURRENT (A)
CESAT
TJ = 25°C
TJ = –50°C
0.9
1.1
)
1.3
1977 G13
Burst Mode Threshold
vs Input Voltage
V
= 3.3V
OUT
L = 10µH
= 100µF
C
OUT
Burst Mode EXIT
(INCREASING LOAD)
Burst Mode ENTER
(DECREASING LOAD)
8
7
614
5
12
11
13
10
9
INPUT VOLTAGE (V)
16 17 18 19
15
1977 G20
1.5
20
Supply Current vs Input Voltage Minimum Input Voltage
150
125
100
75
50
SUPPLY CURRENT (µA)
25
0
10
0
30 40
20
INPUT VOLTAGE (V)
V
= 3.3V
OUT
= 25°C
T
A
50
60
1977 F05
7.5
7.0
6.5
6.0
5V START
5.5
5.0
4.5
3.3V START
INPUT VOLTAGE (V)
4.0
3.5
3.0
0
3.3V RUNNING
0.40.2 0.8 10.6 1.2 1.4
5V RUNNING
LOAD CURRENT (A)
Minimum On Time Boost Current vs Switch Current
500
450
400
350
LOAD CURRENT = 0.5A
300
250
LOAD CURRENT = 1A
200
ON TIME (ns)
150
100
50
0
–50
0
–25
TEMPERATURE (°C)
50
25
75
100
125
1977 G21
1.6
1977 G19
1977fa
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Page 6
LT1977
UW
TYPICAL PERFOR A CE CHARACTERISTICS
4.0
3.5
3.0
2.5
2.0
1.5
OUTPUT VOLTAGE (V)
1.0
0.5
0
V
OUT
20mV/DIV
I
SW
500mA/DIV
Dropout Operation Dropout Operation
V
= 3.3V
OUT
BOOST DIODE = DIODES INC B1100
LOAD CURRENT = 250mA
LOAD CURRENT = 1.25A
2.5 3 4
2
INPUT VOLTAGE (V)
3.5
Burst Mode Operation
4.5
1977 G23
6
5
4
3
2
OUTPUT VOLTAGE (V)
1
0
2
No Load 1A Step Response
V
OUT
50mV/DIV
I
OUT
500mA/DIV
V
= 5V
OUT
BOOST DIODE = DIODES INC B1100
LOAD CURRENT = 250mA
LOAD CURRENT = 1.25mA
2.5 3.5
3
4
INPUT VOLTAGE (V)
5.5
4.5 6.5
6
5
1977 G24
V
OUT
20mV/DIV
I
SW
500mA/DIV
V
OUT
50mV/DIV
I
OUT
500mA/DIV
Burst Mode Operation
V
= 12V
IN
V
OUT
= 100µA
I
Q
= 3.3V
5ms/DIV
Step Response
1977 G14
U
V
= 12V
IN
V
OUT
= 100µA
I
Q
= 3.3V
2µs/DIV
1977 G15
UU
V
V
C
I
IN
OUT
OUT
DC
= 12V
= 3.3V
= 100µF
= 0mA
PI FU CTIO S
NC (Pins 1, 3, 5): No Connection.
SW (Pin 2): The SW pin is the emitter of the on-chip power
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the SW pin
negative during switch off time. Negative voltage is clamped
with the external catch diode. Maximum negative switch
voltage allowed is –0.8V.
V
(Pin 4): This is the collector of the on-chip power NPN
IN
switch. V
voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the VCE voltage across the internal NPN.
powers the internal control circuitry when a
IN
500µs/DIV
1977 G17
= 12V
V
IN
V
OUT
C
OUT
= 350mA
I
DC
= 3.3V
500µs/DIV
= 100µF
1977 G18
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.2Ω FET
structure.
C
(Pin 7): A capacitor on the CT pin determines the amount
T
of delay time between the PGFB pin exceeding its threshold (V
When the PGFB pin rises above V
from the C
) and the PG pin set to a high impedance state.
PGFB
, current is sourced
PGFB
pin into the external capacitor. When the volt-
T
age on the external capacitor reaches an internal clamp
), the PG pin becomes a high impedance node. The
(V
CT
resultant PG delay time is given by t = C
• VCT/ICT. If the
CT
1977fa
6
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LT1977
U
UU
PI FU CTIO S
voltage on the PGFB pin drops below V
discharged rapidly to 0V and PG will be active low with a
200µA sink capability. If the C
pin is clamped (Power Good
T
condition) during normal operation and SHDN is taken low,
pin will be discharged and a delay period will occur
the C
T
when SHDN is returned high. See the Power Good section
in Applications Information for details.
GND (Pins 8, 17): The GND pin connection acts as the
reference for the regulated output, so load regulation will
suffer if the “ground” end of the load is not at the same
voltage as the GND pin of the IC. This condition will occur
when load current or other currents flow through metal
paths between the GND pin and the load ground. Keep the
path between the GND pin and the load ground short and
use a ground plane when possible. The GND pin also acts
as a heat sink and should be soldered (along with the
exposed leadframe) to the copper ground plane to reduce
thermal resistance (see Applications Information).
CSS (Pin 9): A capacitor from the CSS pin to the regulated
output voltage determines the output voltage ramp rate
during start-up. When the current through the C
tor exceeds the C
threshold (I
SS
the output is limited. The C
SS
), the voltage ramp of
CSS
threshold is proportional to
the FB voltage (see Typical Performance Characteristics)
and is defeated for FB voltage greater than 0.9V (typical).
See Soft-Start section in Applications Information for
details.
BIAS (Pin 10): The BIAS pin is used to improve efficiency
when operating at higher input voltages and light load
current. Connecting this pin to the regulated output voltage forces most of the internal circuitry to draw its
operating current from the output voltage rather than the
input supply. This architecture increases efficiency especially when the input voltage is much higher than the
output. Minimum output voltage setting for this mode of
operation is 3V.
(Pin 11): The VC pin is the output of the error amplifier
V
C
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. VC sits
at about 0.45V for light loads and 2.2V at maximum load.
, CCT will be
PGFB
capaci-
SS
During the sleep portion of Burst Mode operation, the V
C
pin is held at a voltage slightly below the burst threshold
for better transient response. Driving the V
pin to ground
C
will disable switching and place the IC into sleep mode.
FB (Pin 12): The feedback pin is used to determine the
output voltage using an external voltage divider from the
output that generates 1.25V at the FB pin . When the FB pin
drops below 0.9V, switching frequency is reduced, the
SYNC function is disabled and output ramp rate control is
enabled via the C
pin. See the Feedback section in
SS
Applications Information for details.
PGFB (PIN 13): The PGFB pin is the positive input to a
comparator whose negative input is set at V
PGFB is taken above V
the C
pin starting the PG delay period. When the voltage
T
on the PGFB pin drops below V
, current (I
PGFB
) is sourced into
CSS
, the CT pin is rapidly
PGFB
PGFB
. When
discharged resetting the PG delay period. The PGFB voltage is typically generated by a resistive divider from the
regulated output or input supply. See Power Good section
in Applications Information for details.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between
30% and 70% duty cycle. The synchronizing range is
equal to maximum initial operating frequency up to 700kHz.
When the voltage on the FB pin is below 0.9V the SYNC
function is disabled. See the Synchronizing section in
Applications Information for details.
SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input current to less than 1µA. The
SHDN pin requires a voltage above 1.3V with a typical
source current of 5µA to take the IC out of the shutdown
state.
PG (Pin 16): The PG pin is functional only when the SHDN
pin is above its threshold, and is active low when the
internal clamp on the C
pin is below its clamp level and
T
high impedance when the clamp is active. The PG pin has
a typical sink capability of 200µA. See the Power Good
section in Applications Information for details.
1977fa
7
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LT1977
BLOCK DIAGRA
V
IN
4
BIAS
10
SYNC
14
SHDN
15
+
SHDN
COMP
–
1.3V
W
INTERNAL REF
UNDERVOLTAGE
LOCKOUT
THERMAL
SHUTDOWN
2.4V
SLOPE
COMP
500kHz
OSCILLATOR
ANTISLOPE
COMP
Σ
CURRENT
COMP
R
S
+
–
SWITCH
LATCH
Q
DRIVER
CIRCUITRY
BOOST
SW
6
2
C
SS
9
FB
12
1.25V
V
C
11
PGFB
13
1.12V
C
T
7
SOFT-START
FOLDBACK
DETECT
–
ERROR
AMP
+
+
PG
COMP
–
BURST MODE
DETECT
V
C
CLAMP
1.2V C
CLAMP
Figure 1. LT1977 Block Diagram
The LT1977 is a constant frequency, current mode buck
converter. This means that there is an internal clock and two
feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS latch to turn the switch on. When
switch current reaches a level set by the current comparator the latch is reset and the switch turns off. Output voltage control is obtained by using the output of the error
amplifier to set the switch current trip point. This technique
means that the error amplifier commands current to be
PG
16
T
GND
17
PGND
8
1977 BD
delivered to the output rather than voltage. A voltage fed
system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt
180° shift will occur. The current fed system will have 90°
phase shift at a much lower frequency, but will not have the
additional 90° shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response.
Most of the circuitry of the LT1977 operates from an
internal 2.4V bias line. The bias regulator normally draws
8
1977fa
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BLOCK DIAGRA
LT1977
W
power from the VIN pin, but if the BIAS pin is connected to
an external voltage higher than 3V bias power will be
drawn from the external source (typically the regulated
output voltage). This improves efficiency.
High switch efficiency is achieved by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external capacitor and diode.
WUUU
APPLICATIO S I FOR ATIO
CHOOSING THE LT1976 OR LT1977
The LT1976 and LT1977 are both high voltage 1.5A stepdown Burst Mode switching regulators with a typical
quiescent current of 100µA. The difference between the
two is that the fixed switching frequency of the LT1976 is
200kHz versus 500kHz for the LT1977. The switching
frequency affects: inductor size, input voltage range in
continuous mode operation, efficiency, thermal loss and
EMI.
OUTPUT RIPPLE AND INDUCTOR SIZE
Output ripple current is determined by the input to output
voltage ratio, inductor value and switch frequency. Since
the switch frequency of the LT1977 is 2.5 times greater
than that of the LT1976, the inductance used in the LT1977
application can be 2.5 times lower than the LT1976 while
maintaining the same output ripple current. The lower
value used in the LT1977 application allows the use of a
physically smaller inductor.
INPUT VOLTAGE RANGE
The LT1976 and LT1977 minimum on and off times are
equivalent. This results in a narrower range of continuous
mode operation for the LT1977. Typical minimum and
maximum duty cycles are 6% to 95% for the LT1976 and
15% to 90% for the LT1977. Both parts will regulate up to
an input voltage of 60V but the LT1977 will transistion into
pulse skipping/Burst Mode operation when the input
voltage is above 30V for a 5V output. At outputs above 10V
To further optimize efficiency, the LT1977 automatically
switches to Burst Mode operation in light load situations.
In Burst Mode operation, all circuitry associated with
controlling the output switch is shut down reducing the
input supply current to 45µA.
The LT1977 contains a power good flag with a programmable threshold and delay time. A logic-level low on the
SHDN pin disables the IC and reduces input suppy current
to less than 1µA.
the LT1977’s input range will be similar to the LT1976.
Lowering the input voltage below the maximum duty cycle
limitation will cause a dropout in regulation.
Table 1. LT1976/LT1977 Comparison
PARAMETER ADVANTAGE
Minimum Duty Cycle LT1976
Maximum Duty Cycle LT1976
Inductor Size LT1977
Output Capacitor Size LT1977
Efficiency LT1976
EMI LT1976
Input Range LT1976
Output Ripple LT1977
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT1977 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
frequency foldback and soft-start features. Please read
both parts before committing to a final design.
Referring to Figure 2, the output voltage is determined by
a voltage divider from V
1.25V at the FB pin. Since the output divider is a load on the
output care must be taken when choosing the resistor
divider values. For light load applications the resistor
values should be as large as possible to achieve peak
efficiency in Burst Mode operation. Extremely large values
for resistor R1 will cause an output voltage error due to the
to ground which generates
OUT
1977fa
9
Page 10
LT1977
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APPLICATIO S I FOR ATIO
V
LT1977
SOFT-START
500kHz
OSCILLATOR
Figure 2. Feedback Network
Table 2
OUTPUT R1 OUTPUT
VOLTAGE R2 NEAREST (1%) ERROR
(V) (kΩ, 1%) (kΩ) (%)
2.5 100 100 0
3 100 140 0
3.3 100 165 0.38
5 100 300 0
6 100 383 0.63
8 100 536 – 0.63
10 100 698 – 0.25
12 100 866 0.63
FOLDBACK
DETECT
ERROR
AMP
SW
2
C
–
+
1.25V
C1
SS
9
FB
12
V
C
11
1977 F02
50nA FB pin input current. The suggested value for the
output divider resistor (see Figure 2) from FB to ground
(R2) is 100k or less. A formula for R1 is shown below. A
table of standard 1% values is shown in Table 2 for
common output voltages.
RR
12
=+•
V
125 2 50
.•
125
–.
OUT
RnA
More Than Just Voltage Feedback
The FB pin is used for more than just output voltage
sensing. It also reduces switching frequency and controls the soft-start voltage ramp rate when output voltage
is below the regulated level (see the Frequency Foldback
OUT
R1
R2
and Soft-Start Current graphs in Typical Performance
Characteristics).
Frequency foldback is used to control power dissipation in
both the IC and in the external diode and inductor during
short-circuit conditions. A shorted output requires the
switching regulator to operate at very low duty cycles. As
a result the average current through the diode and inductor is equal to the short-circuit current limit of the switch
(typically 2A for the LT1977). Minimum switch on time
limitations would prevent the switcher from operating at a
sufficiently low duty cycle if switching frequency were
maintained at 500kHz, so frequency is reduced by about
4:1 when the FB pin voltage drops below 0.4V (see
Frequency Foldback graph). In addition, if the current in
the switch exceeds 1.5 times the current limitations specified by the VC pin, due to minimum switch on time, the
LT1977 will skip the next switch cycle. As the feedback
voltage rises, the switching frequency increases to 500kHz
with 0.95V on the FB pin. During frequency foldback,
external synchronization is disabled to prevent interference with foldback operation. Frequency foldback does
not affect operation during normal load conditions.
In addition to lowering switching frequency the soft-start
ramp rate is also affected by the feedback voltage. Large
capacitive loads or high input voltages can cause a high
input current surge during start-up. The soft-start function reduces input current surge by regulating switch
current via the VC pin to maintain a constant voltage ramp
rate (dV/dt) at the output. A capacitor (C1 in Figure 2) from
the C
dV/dt. When the feedback voltage is below 0.4V, the V
pin to the output determines the maximum output
SS
C
pin
will rise, resulting in an increase in switch current and
output voltage. If the dV/dt of the output causes the current
through the CSS capacitor to exceed I
the VC voltage is
CSS
reduced resulting in a constant dV/dt at the output. As the
feedback voltage increases I
increases, resulting in an
CSS
increased dV/dt until the soft-start function is defeated
with 0.9V present at the FB pin. The soft-start function
does not affect operation during normal load conditions.
However, if a momentary short (brown out condition) is
present at the output which causes the FB voltage to drop
below 0.9V, the soft-start circuitry will become active.
10
1977fa
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APPLICATIO S I FOR ATIO
LT1977
INPUT CAPACITOR
Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage
ripple this causes at the input of LT1977 and force the
switching current into a tight local loop, thereby minimizing EMI. The RMS ripple current can be calculated from:
I
I
RIPPLE RMS
OUT
VVV
V
OUT IN OUT()
IN
–=
()
Ceramic capacitors are ideal for input bypassing. At 500kHz
switching frequency input capacitor values in the range of
4.7µF to 20µF are suitable for most applications. If opera-
tion is required close to the minimum input required by the
LT1977 a larger value may be required. This is to prevent
excessive ripple causing dips below the minimum operating voltage resulting in erratic operation.
Input voltage transients caused by input voltage steps or
by hot plugging the LT1977 to a pre-powered source such
as a wall adapter can exceed maximum V
ratings. The
IN
sudden application of input voltage will cause a large
surge of current in the input leads that will store energy in
the parasitic inductance of the leads. This energy will
cause the input voltage to swing above the DC level of input
power source and it may exceed the maximum voltage
rating of the input capacitor and LT1977. All input voltage
transient sequences should be observed at the V
pin of
IN
the LT1977 to ensure that absolute maximum voltage
ratings are not violated.
exceeded. The AVX TPS and Kemet T495 series are surge
rated. AVX recommends derating capacitor operating
voltage by 2:1 for high surge applications.
OUTPUT CAPACITOR
The output capacitor is normally chosen by its effective
series resistance (ESR) because this is what determines
output ripple voltage. To get low ESR takes volume, so
physically smaller capacitors have higher ESR. The ESR
range for typical LT1977 applications is 0.05Ω to 0.2Ω. A
typical output capacitor is an AVX type TPS, 100µF at 10V,
with a guaranteed ESR less than 0.1Ω. This is a “D” size
surface mount solid tantalum capacitor. TPS capacitors
are specially constructed and tested for low ESR, so they
give the lowest ESR for a given volume. The value in
microfarads is not particularly critical and values from
22µF to greater than 500µF work well, but you cannot
cheat Mother Nature on ESR. If you find a tiny 22µF solid
tantalum capacitor, it will have high ESR and output ripple
voltage could be unacceptable. Table 3 shows some
typical solid tantalum surface mount capacitors.
Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E CASE SIZE ESR MAX (Ω) RIPPLE CURRENT (A)
AVX TPS 0.1 to 0.3 0.7 to 1.1
D CASE SIZE
AVX TPS 0.1 to 0.3 0.7 to 1.1
C CASE SIZE
AVX TPS 0.2 0.5
The easiest way to suppress input voltage transients is to
add a small aluminum electrolytic capacitor in parallel with
the low ESR input capacitor. The selected capacitor needs
to have the right amount of ESR to critically damp the
resonant circuit formed by the input lead inductance and
the input capacitor. The typical values of ESR will fall in the
range of 0.5Ω to 2Ω and capacitance will fall in the range
of 5µF to 50µF.
If tantalum capacitors are used, values in the 22µF to
470µF range are generally needed to minimize ESR and
meet ripple current and surge ratings. Care should be
taken to ensure the ripple and surge ratings are not
Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true and type TPS capacitors are
specially tested for surge capability but surge ruggedness
is not a critical issue with the output capacitor. Solid
tantalum capacitors fail during very high turn-on surges
which do not occur at the output of regulators. High
discharge surges, such as when the regulator output is
dead shorted, do not harm the capacitors.
Unlike the input capacitor RMS, ripple current in the
output capacitor is normally low enough that ripple current rating is not an issue. The current waveform is
1977fa
11
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LT1977
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APPLICATIO S I FOR ATIO
triangular with a typical value of 200mA
. The formula
RMS
to calculate this is:
Output capacitor ripple current (RMS)
I
()
RIPPLE RMS
()( )
=
OUT IN OUT
LfV
()()( )
IN
I
P-P
=
12
.–
VVV
029
CERAMIC CAPACITORS
Higher value, lower cost ceramic capacitors are now
becoming available. They are generally chosen for their
good high frequency operation, small size and very low
ESR (effective series resistance). Low ESR reduces output
ripple voltage but also removes a useful zero in the loop
frequency response, common to tantalum capacitors. To
compensate for this a resistor RC can be placed in series
with the V
compensation capacitor CC (Figure 10). Care
C
must be taken however since this resistor sets the high
frequency gain of the error amplifier including the gain at
the switching frequency. If the gain of the error amplifier
is high enough at the switching frequency output ripple
voltage (although smaller for a ceramic output capacitor)
may still affect the proper operation of the regulator. A
filter capacitor C
with a small feedforward capacitor C
control possible ripple at the V
stabilized using a 100µF ceramic output capacitor and V
in parallel with the RC/CC network, along
F
, is suggested to
FB
pin. The LT1977 can be
C
C
component values of CC = 1500pF, RC = 10k, CF = 330pF
and C
= 10pF.
FB
V
OUT
10mV/DIV
100µF
75mΩ
TANTALUM
V
OUT
10mV/DIV
100µF
CERAMIC
V
SW
10V/DIV
V
= 12V
IN
= 3.3V
V
OUT
= 1A
I
L
Figure 3. LT1977 Ripple Voltage Waveform
500ns/DIV
1977 F03
Peak-to-peak output ripple voltage is the sum of a triwave
created by peak-to-peak ripple current times ESR and a
square wave created by parasitic inductance (ESL) and
ripple current slew rate. Capacitive reactance is assumed
to be small compared to ESR or ESL.
V I ESR ESL
RIPPLE
Example: with V
=
()( )+()
P-P
= 12V, V
IN
di
dt
= 3.3V, L = 15µH, ESR =
OUT
0.08Ω, ESL = 10nH:
.–.
33 12 33
I
P-P
di
dt e
()( )
=
12 15 6 500 3
()
==
15 6
ee
()()
12
–
−
e
08 6
.
=
0 319
.
A
OUTPUT RIPPLE VOLTAGE
Figure 3 shows a typical output ripple voltage waveform
for the LT1977. Ripple voltage is determined by the
impedance of the output capacitor and ripple current
through the inductor. Peak-to-peak ripple current through
the inductor into the output capacitor is:
I
VVV
OUT IN OUT
=
P-P
–
()
VLf
()()()
IN
For high frequency switchers the ripple current slew rate
is also relevant and can be calculated from:
didtV
IN
=
L
12
V
= 0.026 + 0.008 = 34mV
= (0.319A)(0.08) + (10e – 9)(0.8e6)
RIPPLE
P-P
MAXIMUM OUTPUT LOAD CURRENT
Maximum load current for a buck converter is limited by
the maximum switch current rating (I
). The minimum
PK
specified current rating for the LT1977 is 1.5A. Unlike
most current mode converters, the LT1977 maximum
switch current limit does not fall off at high duty cycles.
Most current mode converters suffer a drop off of peak
switch current for duty cycles above 50%. This is due to
the effects of slope compensation required to prevent
subharmonic oscillations in current mode converters.
(For detailed analysis, see Application Note 19.)
1977fa
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APPLICATIO S I FOR ATIO
LT1977
The LT1977 is able to maintain peak switch current limit
over the full duty cycle range by using patented circuitry to
cancel the effects of slope compensation on peak switch
current without affecting the frequency compensation it
provides.
Maximum load current would be equal to maximum
switch current for an infinitely large inductor, but with
finite inductor size, maximum load current is reduced by
one-half peak-to-peak inductor current. The following
formula assumes continuous mode operation, implying
that the term on the right (I
VVV
()( )
II
()
OUT MAX PK
Discontinuous operation occurs when:
VVV
I
()
OUT DIS
For V
OUT
I
OUT MAX()
Note that there is less load current available at the higher
input voltage because inductor ripple current increases. At
V
= 15V, duty cycle is 33% and for the same set of
IN
conditions:
I
OUT MAX()
To calculate actual peak switch current in continuous
mode with a given set of conditions, use:
II
()
SW PK OUT
If a small inductor is chosen which results in discontinous
mode operation over the entire load range, the maximum
load current is equal to:
OUT IN OUT
≤
= 5V, V
15
=
==
.–. .
1 5 0 125 1 375
.–
=
15
.–. .
==
15 022 128
=+
OUT IN OUT
–
()
2
()()( )
LfV
= 8V and L = 15µH:
IN
.–
2 15 6 500 3 8
()()()
2 15 6 500 3 15
()()()
VVV
OUT IN OUT
/2) is less than I
P-P
–
2
LfV
()()( )
–
IN
()( )
ee
()( )
ee
()
2
LfV
()()( )
IN
–
58 5
–
–
515 5
–
A
–
IN
=
A
.
OUT
I
-P
P
–=
I
PK
2
2
2
IfLV
()( )( )
I
()
OUT MAX
CHOOSING THE INDUCTOR
For most applications the output inductor will fall in the
range of 5µH to 33µH. Lower values are chosen to reduce
physical size of the inductor. Higher values allow more
output current because they reduce peak current seen by
the LT1977 switch, which has a 1.5A limit. Higher values
also reduce output ripple voltage and reduce core loss.
When choosing an inductor you might have to consider
maximum load current, core and copper losses, allowable component height, output voltage ripple, EMI, fault
current in the inductor, saturation and of course cost.
The following procedure is suggested as a way of handling these somewhat complicated and conflicting
requirements.
1. Choose a value in microhenries such that the maximum
load current plus half the ripple current is less than the
minimum peak switch current (I
inductor with lighter loads may result in discontinuous
mode of operation, but the LT1977 is designed to work
well in either mode.
Assume that the average inductor current is equal to
load current and decide whether or not the inductor
must withstand continuous fault conditions. If maximum load current is 0.5A, for instance, a 0.5A inductor
may not survive a continuous 2A overload condition.
For applications with a duty cycle above 50%, the
inductor value should be chosen to obtain an inductor
ripple current of less than 40% of the peak switch
current.
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
can be significantly higher than output current, especially
with smaller inductors and lighter loads, so don’t omit
this step. Powdered iron cores are forgiving because they
saturate softly, whereas ferrite cores saturate abruptly.
Other core materials fall somewhere in between. The
following formula assumes continuous mode of operation, but it errs only slightly on the high side for discontinuous mode, so it can be used for all conditions.
PK IN
=
2
VVV
()( )
OUT IN OUT
–
PK
). Choosing a small
1977fa
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LT1977
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APPLICATIO S I FOR ATIO
Table 4. Inductor Selection Criteria
VENDOR/ VALUE I
PART NO. (
Coiltronics
UP1B-100 10 1.9 0.111 5.0
UP1B-220 22 1.2 0.254 5.0
UP2B-220 22 2.0 0.062 6.0
UP2B-330 33 1.7 0.092 6.0
UP1B-150 15 1.5 0.175 5.0
Coilcraft
D01813P-153HC 15 1.5 0.170 5.0
D01813P-103HC 10 1.9 0.111 5.0
D53316P-223 22 1.6 0.207 5.1
D53316P-333 33 1.4 0.334 5.1
LP025060B-682 6.8 1.3 0.165 1.65
Sumida
CDRH4D28-4R7 4.7 1.32 0.072 3.0
CDRH5D28-100 10 1.30 0.065 3.0
CDRH6D28-150 15 1.40 0.084 3.0
CDRH6D28-180 18 1.32 0.095 3.0
CDRH6D28-220 22 1.20 0.128 3.0
CDRH6D38-220 22 1.30 0.096 4.0
II
=+
PEAK OUT
µ
H) (Amps) (Ohms) (mm)
VVV
OUT IN OUT
DC(MAX)
–
()
2
fLV
()( )( )
IN
DCR HEIGHT
VIN = maximum input voltage
f = switching frequency, 500kHz
3. Decide if the design can tolerate an “open” core geometry like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid
to prevent EMI problems. This is a tough decision
because the rods or barrels are temptingly cheap and
small and there are no helpful guidelines to calculate
when the magnetic field radiation will be a problem.
4. After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the Linear Technology’s applications
department if you feel uncertain about the final choice.
They have experience with a wide range of inductor
types and can tell you about the latest developments in
low profile, surface mounting, etc.
Short-Circuit Considerations
The LT1977 is a current mode controller. It uses the V
C
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the V
C
node, nominally 2.2V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the maximum specified switch current
limit.
A potential control problem could occur under shortcircuit conditions. If the power supply output is short
circuited, the feedback amplifier responds to the low
output voltage by raising the control voltage, V
, to its
C
peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
the value indicated by VC. However, there is finite response
time involved in both the current comparator and turn-off
of the output switch. These result in a typical minimum on
time of 300ns (see Typical Performance Characteristics)
.
When combined with the large ratio of VIN to (VF + I • R),
the diode forward voltage plus inductor I • R voltage drop,
the potential exists for a loss of control. Expressed mathematically the requirement to maintain control is:
VIR
•≤+
ft
•
ON
F
V
IN
where:
f = switching frequency
t
= switch on time
ON
VF = diode forward voltage
VIN = Input voltage
I • R = inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at IPK but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT1977 clock frequency
of 500kHz, a V
of 12V and a (VF + I • R) of say 0.7V, the
IN
maximum tON to maintain control would be approximately
116ns, an unacceptably short time.
The solution to this dilemma is to slow down the oscillator
to allow the current in the inductor to drop to a sufficiently
1977fa
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APPLICATIO S I FOR ATIO
low value such that the current doesn’t continue to ratchet
higher. When the FB pin voltage is abnormally low thereby
indicating some sort of short-circuit condition, the oscillator frequency will be reduced. Oscillator frequency is
reduced by a factor of 4 when the FB pin voltage is below
0.4V and increases linearly to its typical value of 500kHz at
a FB voltage of 0.95V (see Typical Performance Characteristics). In addition, if the current in the switch exceeds 1.5
• I
current demanded by the VC pin, the LT1977 will skip
PK
the next on cycle effectively reducing the oscillator frequency by a factor of 2. These oscillator frequency reductions during short-circuit conditions allow the LT1977 to
maintain current control.
SOFT-START
For applications where [V
large input surge currents can’t be tolerated, the LT1977
soft-start feature should be used to control the output
capacitor charge rate during start-up, or during recovery
from an output short circuit thereby adding additional
control over peak inductor current. The soft-start function
limits the switch current via the VC pin to maintain a
constant voltage ramp rate (dV/dt) at the output capacitor.
A capacitor (C1 in Figure 2) from the C
regulated output voltage determines the output voltage
ramp rate. When the current through the C
exceeds the C
threshold (I
SS
output capacitor is limited by reducing the V
The C
threshold is proportional to the FB voltage (see
SS
Typical Performance Characteristics) and is defeated for
FB voltages greater than 0.9V (typical). The output dV/dt
can be approximated by:
dVdtI
CSS
=
C
SS
but actual values will vary due to start-up load conditions,
compensation values and output capacitor selection.
Burst Mode OPERATION
T
o enhance efficiency at light loads, the LT1977 automatically switches to Burst Mode operation (see Typical
Performance Characteristics) which keeps the output
/(V
IN
+ VF)] ratios > 10 or
OUT
pin to the
SS
SS
), the voltage ramp of the
CSS
pin voltage.
C
capacitor
LT1977
C
= 1000pF
CSS
V
OUT
1V/DIV
capacitor charged to the proper voltage while minimizing
the input quiescent current. During Burst Mode operation, the LT1977 delivers short bursts of current to the
output capacitor followed by sleep periods where the
output power is delivered to the load by the output
capacitor. In addition, V
are reduced to typically 45µA and 110µA respectively
during the sleep time. As the load current decreases
towards a no load condition, the percentage of time that
the LT1977 operates in sleep mode increases and the
average input current is greatly reduced resulting in
higher efficiency.
The minimum average input current depends on the VIN to
V
ratio, VC frequency compensation, feedback divider
OUT
network and Schottky diode leakage. It can be approximated by the following equation:
III
IN AVG VINS SHDN
()
where:
I
= input pin current in sleep mode
VINS
V
= output voltage
OUT
V
input voltage
IN =
I
BIASS
IFB = feedback network current
IS = catch diode reverse leakage at V
η = low current efficiency (non Burst Mode operation)
C
= 0.01µF
CSS
V
= 12V
IN
= 3.3V
V
OUT
Figure 4. V
≅ ++
C
= 0.1µF
CSS
1ms/DIV
dV/dt
OUT
and BIAS quiescent currents
IN
⎛
V
⎜
⎝
V
III
⎞
()
OUT
BIASS FB S
⎟
⎠
IN
= BIAS pin current in sleep mode
OUT
1977 F04
++
η
()
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APPLICATIO S I FOR ATIO
Example: For V
IAA
IN AVG()
=µ+µ+
45 5
=µ+µ+µ=µ
45 5 44 99
150
125
100
75
50
SUPPLY CURRENT (µA)
25
0
During the sleep portion of the Burst Mode cycle, the V
= 3.3V, VIN = 12V
OUT
µ+ µ+ µ
125 12 5 0 5
AAA
()
.
33
⎛
⎞
⎜
⎟
⎝
⎠
12
AA A A
V
= 3.3V
OUT
= 25°C
T
A
10
0
30 40
20
INPUT VOLTAGE (V)
Figure 5. IQ vs V
50
IN
..
.
08
()
60
1977 F05
C
pin voltage is held just below the level needed for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and transient response waveforms.
If a no load condition can be anticipated, the supply current
can be further reduced by cycling the SHDN pin at a rate
higher than the natural no load burst frequency. Figure 6
shows Burst Mode operation with the SHDN pin. V
OUT
burst ripple is maintained while the average supply current
drops to 15µA. The PG pin will be active low during the
“on” portion of the SHDN waveform due to the C
capaci-
T
tor discharge when SHDN is taken low. See the Power
Good section for further information.
CATCH DIODE
The catch diode carries load current during the SW off
time. The average diode current is therefore dependent on
the switch duty cycle. At high input to output voltage ratios
the diode conducts most of the time. As the ratio approaches unity the diode conducts only a small fraction of
the time. The most stressful condition for the diode is
when the output is short circuited. Under this condition the
diode must safely handle I
at maximum duty cycle.
PEAK
V
OUT
50mV/DIV
V
SHDN
2V/DIV
I
SW
500mA/DIV
= 12V TIME (50ms/DIV)
V
IN
V
= 3.3V
OUT
= 15µA
I
Q
1977 G16
Figure 6. Burst Mode with Shutdown Pin
To maximize high and low load current efficiency a fast
switching diode with low forward drop and low reverse
leakage should be used. Low reverse leakage is critical to
maximize low current efficiency since its value over temperature can potentially exceed the magnitude of the
LT1977 supply current. Low forward drop is critical for
high current efficiency since the loss is proportional to
forward drop.
These requirements result in the use of a Schottky type
diode. DC switching losses are minimized due to its low
forward voltage drop and AC behavior is benign due to its
lack of a significant reverse recovery time. Schottky diodes
are generally available with reverse voltage ratings of 60V
and even 100V and are price competitive with other types.
The effect of reverse leakage and forward drop on efficiency for various Schottky diodes is shown in Table 5. As
can be seen these are conflicting parameters and the user
Table 5. Catch Diode Selection Criteria
IQ at 125°C EFFICIENCY
LEAKAGE V
= 3.3V VF AT 1A V
V
OUT
DIODE 25°C 125°C25°CI
IR 10BQ100 0.0µA59µA 0.72V 125µA 76.1%
Diodes Inc. 0.1µA 242µA 0.48V 215µA 80.4%
B260SMA
Diodes Inc. 0.2µA 440µA 0.45V 270µA 80.8%
B360SMB
IR 1µA 1.81mA 0.42V 821µA 81.4%
MBRS360TR
IR 30BQ100 0.5µA 225µA 0.59V 206µA 78.8%
=12V VIN =12V
IN
= 3.3 V
OUT
= 0A IL = 1A
L
OUT
= 3.3V
1977fa
16
Page 17
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APPLICATIO S I FOR ATIO
LT1977
must weigh the importance of each specification in choosing the best diode for the application.
The use of so-called “ultrafast” recovery diodes is generally not recommended. When operating in continuous
mode, the reverse recovery time exhibited by “ultrafast”
diodes will result in a slingshot type effect. The power
internal switch will ramp up VIN current into the diode in an
attempt to get it to recover. Then, when the diode has
finally turned off, some tens of nanoseconds later, the V
SW
node voltage ramps up at an extremely high dV/dt, perhaps 5V to even 10V/ns! With real world lead inductances
the V
node can easily overshoot the VIN rail. This can
SW
result in poor RFI behavior and, if the overshoot is severe
enough, damage the IC itself.
BOOST PIN
For most applications the boost components are a 0.1µF
capacitor and a MMSD914 diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately V
above VIN to drive the output
OUT
stage (Figure 7a). However, the output stage discharges
the boost capacitor during the on time of the switch. The
output driver requires at least 2.5V of headroom throughout this period to keep the switch fully saturated. If the
output voltage is less than 3.3V it is recommended that an
alternate boost supply is used. The boost diode can be
connected to the input (Figure 7b) but care must be taken
to prevent the boost voltage (V
= VIN • 2) from
BOOST
exceeding the BOOST pin absolute maximum rating. The
additional voltage across the switch driver also increases
power loss and reduces efficiency. If available, an independent supply can be used to generate the required
BOOST voltage (Figure 7c). Tying BOOST to V
or an
IN
independent supply may reduce efficiency but it will reduce the minimum V
required to start-up with light
IN
loads. If the generated BOOST voltage dissipates too
much power at maximum load, the BOOST voltage the
LT1977 sees can be reduced by placing a Zener diode in
series with the BOOST diode (Figure 7a option).
A 0.1µF boost capacitor is recommended for most appli-
cations. Almost any type of film or ceramic capacitor is
suitable but the ESR should be <1Ω to ensure it can be fully
recharged during the off time of the switch. The capacitor
OPTIONAL
BOOST
V
IN
V
V
BOOST
V
BOOST(MAX)
IN
LT1977
– VSW = V
= VIN + V
SWGND
OUT
OUT
V
OUT
(7a)
BOOST
V
IN
V
IN
LT1977
V
BOOST
V
BOOST(MAX)
SWGND
– VSW = V
= 2V
V
OUT
IN
IN
(7b)
BOOST
V
IN
V
V
BOOST
V
BOOST(MAX)
IN
LT1977
– VSW = V
= VDC + V
SWGND
D
SS
DC
IN
1977 F07
V
DC
V
OUT
(7c)
Figure 7. BOOST Pin Configurations
value is derived from worst-case conditions of 1800ns on
time, 40mA boost current and 0.7V discharge ripple. The
boost capacitor value could be reduced under less demanding conditions but this will not improve circuit operation or efficiency. Under low input voltage and low load
conditions a higher value capacitor will reduce discharge
ripple and improve start-up operation.
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
The SHDN pin on the LT1977 controls the operation of the
IC. When the voltage on the SHDN pin is below the 1.2V
shutdown threshold the LT1977 is placed in a “zero”
supply current state. Driving the SHDN pin above the
shutdown threshold enables normal operation. The SHDN
pin has an internal sink current of 3µA.
1977fa
17
Page 18
LT1977
WUUU
APPLICATIO S I FOR ATIO
In addition to the shutdown feature, the LT1977 has an
undervoltage lockout function. When the input voltage is
below 2.4V, switching will be disabled. The undervoltage
lockout threshold doesn’t have any hysteresis and is
mainly used to insure that all internal voltages are at the
correct level before switching is enabled. If an undervoltage lockout function with hysteresis is needed to limit
input current at low V
IN
to V
ratios refer to Figure 8 and
OUT
the following:
V
⎛
VR
=++
UVLO
V
=
HYST
SHDN SHDN
1
⎜
R
⎝
VR
()
OUT
R
3
V
IV
32
R
SHDN SHDN
1
⎞
+
⎟
⎠
R1 should be chosen to minimize quiescent current during
normal operation by the following equation:
–
VV
2
R
1
=
IN
.
I
15
()
()
()
SHDN MAX
Example:
12 2
R
1
=
R
3
–
155
=
A
.
µ
()
M
513
Ω
.
()
M
= Ω
13
.
= ΩΩ
65
.
M
(Nearest 1% 6.49M )
1
R2 =
7 – 1.3
1.3M
=
408
k
1.3
13
649
.
.
M
Ω
A
µ
1
––
Ω
(Nearest 1% 412k)
See the Typical Performance Characteristics section for
graphs of SHDN and VIN currents versus input voltage.
SYNCHRONIZING
Oscillator synchronization to an external input is achieved
by connecting a TTL logic-compatible square wave with a
30%
and
70%
duty cycle between
to the LT1977 SYNC
pin. The synchronizing range is equal to initial operating
frequency up to
700kHz
. This means that minimum
practical sync frequency is equal to the worst-case high
LT1977
V
IN
4
R1
R3
V
OUT
SHDN
15
R2
3µA
Figure 8. Undervoltage Lockout
self-oscillating frequency (
ating frequency of
500kHz
synchronizing above
+
V
IN
COMP
–
2.4V
+
SHDN
COMP
–
1.3V
575kHz
), not the typical oper-
. Caution should be used when
575kHz
because at higher sync
ENABLE
1977 F08
frequencies the amplitude of the internal slope compensation used to prevent subharmonic switching is reduced. This type of subharmonic switching only occurs at
input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensation. Application Note 19 has more details on the theory
of slope compensation.
If the FB pin voltage is below 0.9V (power-up or output
short-circuit conditions) the sync function is disabled.
This allows the frequency foldback to operate to avoid any
hazardous conditions for the SW pin.
If the synchronization signal is present during Burst Mode
operation, synchronization will occur during the burst
portion of the output waveform. Synchronization the
LT1977 during Burst Mode operation may alter the natural
burst frequency which can lead to jitter and increased
ripple in the burst waveform.
If no synchronization is required this pin should be connected to ground.
POWER GOOD
The LT1977 contains a power good block which consists
of a comparator, delay timer and active low flag that allows
1977fa
18
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WUUU
APPLICATIO S I FOR ATIO
LT1977
the user to generate a delayed signal after the power good
threshold is exceeded.
Referring to Figure 2, the PGFB pin is the positive input to
a comparator whose negative input is set at V
PGFB is taken above V
the C
pin starting the delay period. When the voltage on
T
the PGFB pin drops below V
V
OUT
500mV/DIV
PG
100k TO V
IN
V
CT
500mV/DIV
V
SHDN
2V/DIV
, current (I
PGFB
PGFB
TIME (10ms/DIV)
Figure 9. Power Good
) is sourced into
CSS
the CT pin is rapidly
1977 F09
PGFB
. When
discharged resetting the delay period. The PGFB voltage is
typically generated by a resistive divider from the regulated output or input supply.
The capacitor on the CT pin determines the amount of
delay time between the PGFB pin exceeding its threshold
(V
When the PGFB pin rises above V
(I
) and the PG pin set to a high impedance state.
PGFB
current is sourced
PGFB
) from the CT pin into the external capacitor. When the
CT
voltage on the external capacitor reaches an internal clamp
(V
), the PG pin becomes a high impedance node. The
CT
resultant PG delay time is given by t = C
the voltage on the PGFB pin drops below its V
•(VCT)/(ICT). If
CT
, CCT will
PGFB
be discharged rapidly and PG will be active low with a
200µA sink capability. If the SHDN pin is taken below its
threshold during normal operation, the C
pin will be
T
discharged and PG inactive, resulting in a non Power Good
cycle when SHDN is taken above its threshold. Figure 9
shows the power good operation with PGFB connected to
FB and the capacitance on C
= 0.1µF. The PGOOD pin has
T
PG at 80% V
V
IN
PG
LT1977
PGFB
FB
C
T
V
Disconnect at 80% V
OUT
with 100ms Delay
V
IN
PG
LT1977
PGFB
FB
C
T
with 100ms Delay
OUT
200k
153k
12k
100k
0.27µF
200k
153k
12k
100k
0.27µF
OUT
PG at VIN > 4V with 100ms Delay
V
IN
V
= 3.3V
OUT
C
OUT
V
OUT
PG
LT1977
PGFB
FB
C
T
Disconnect 3.3V Logic Signal
511k
200k
0.27µF
200k
165k
100k
V
= 3.3V
OUT
C
OUT
with 100µs Delay
V
IN
PG
V
= 3.3V
OUT
C
OUT
LT1977
PGFB
FB
C
200k
V
= 12V
C
OUT
866k
T
100k
270pF
1977 F10
OUT
Figure 10. Power Good Circuits
1977fa
19
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LT1977
WUUU
APPLICATIO S I FOR ATIO
a limited amount of drive capability and is susceptible to
noise during start-up and Burst Mode operation. If erratic
operation occurs during these conditions a small filter
capacitor from the PGOOD pin to ground will ensure
proper operation. Figure 10 shows several different configurations for the LT1977 Power Good circuitry.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path, shown
in Figure 11, must be kept as short as possible. This is
GND
LT1977
V
42
IN
SW
V
IN
+
C2 C1
HIGH
FREQUENCY
CIRCULATION
PATH
Figure 11. High Speed Switching Path
C2 D2
V
OUT
C1
MINIMIZE
D1-C3
LOOP
C3
V
IN
CONNECT PIN 8 GND TO THE
PIN 17 EXPOSED PAD GND
L1
PLACE VIA's UNDER EXPOSED
PAD TO A BOTTOM PLANE TO
D1
C4
ENHANCE THERMAL
NC
1
SW
2
LT1977
NC
3
V
4
IN
NC
5
BOOST
6
TCAP
7
GND
8
CONDUCTIVITY
PGOOD
SHDN
SYNC
PGFB
BIAS
C
L1
D1
16
15
14
13
FB
12
11
V
C
10
9
SS
V
OUT
LOAD
1977 F11
KELVIN SENSE
FEEDBACK
TRACE AND
KEEP SEPARATE
FROM BIAS TRACE
R3
R1
R2
C2
C5
implemented in the suggested layout of Figure 12. Shortening this path will also reduce the parasitic trace inductance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a flyback spike across the
LT1977 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT1977 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The V
and FB components should be kept as far away as
C
possible from the switch and boost nodes. The LT1977
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
Board layout also has a significant effect on thermal
resistance. Pin 8 and the exposed die pad, Pin 17, are a
continuous copper plate that runs under the LT1977 die.
This is the best thermal path for heat out of the package.
Reducing the thermal resistance from Pin 8 and exposed
pad onto the board will reduce die temperature and increase the power capability of the LT1977. This is achieved
by providing as much copper area as possible around the
exposed pad. Adding multiple solder filled feedthroughs
under and around this pad to an internal ground plane will
also help. Similar treatment to the catch diode and coil
terminations will reduce any additional heating effects.
THERMAL CALCULATIONS
Power dissipation in the LT1977 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formulas show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
20
GND
Figure 12. Suggested Layout
1977 F12
Switch loss:
RI V
P
=
SW
2
()( )
SW OUT OUT
V
IN
tIVf
+
12/
()()()
()
EFF OUT IN
1977fa
Page 21
WUUU
APPLICATIO S I FOR ATIO
LT1977
Boost current loss:
2
VI
P
BOOST
()
=
()
OUT OUT
V
IN
Quiescent current loss:
32/
Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the LT1977
is specified at 60V. This is based solely on internal semiconductor junction breakdown effects. Due to internal
power dissipation the actual maximum V
particular application may be less than this.
= VIN (0.0015) + V
P
Q
OUT
(0.003)
A detailed theoretical basis for estimating internal power
= switch resistance (≈0.3 when hot )
R
SW
t
= effective switch current/voltage overlap time
EFF
(tr + tf + tIR + tIF)
tr = (VIN/1.1)ns
tf = (VIN/1.8)ns
loss is given in the section Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switching loss is also proportional to the square of input voltage.
For example, while the combination of V
5V at 1A and f
tIR = tIF = (I
f = switch frequency
Example: with V
Pee
=
SW
+= + =
....
0 04 0 125 0 172 0 297
PW
BOOST
=
PW
Q
Total power dissipation is:
P
= 0.297 + 0.065 + 0.033 = 0.40W
TOT
Thermal resistance for the LT1977 package is influenced
by the presence of internal or backside planes. With a full
plane under the FE16 package, thermal resistance will be
about 45°C/W. No plane will increase resistance to about
150°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
T
= TA + QJA (P
J
With the FE16 package (Q
temperature of 70°C:
= 70 + 45(0.40) = 98°C
T
J
/0.05)ns
OUT
= 12V, V
IN
03 1 5
()()()
2
.
+
12
= 5V and I
OUT
9
−
./
57 6 1 2 1 12 500 3
()
()
TBD W
2
/
5132
()
=
()
=
0 002
.
12
...
12 0 0015 5 0 003 0 033
()
+
()
)
TOT
=
= 45°C/W) at an ambient
JA
= 1A:
OUT
()( )( )
multaneously raising V
possible. Nevertheless, input voltage transients up to 60V
can usually be accommodated, assuming the resulting
increase in internal dissipation is of insufficient time duration to raise die temperature significantly.
A second consideration is control. A potential limitation
occurs with a high step-down ratio of VIN to V
requires a correspondingly narrow minimum switch on
time. An approximate expression for this (assuming continuous mode operation) is given as follows:
t
ON(MIN)
= V
where:
= input voltage
V
IN
V
= output voltage
OUT
VF = Schottky diode forward drop
f
= switching frequency
OSC
A potential control problem arises if the LT1977 is called
upon to produce an on time shorter than it is able to
produce. Feedback loop action will lower then reduce the
control voltage to the point where some sort of cycle-
V
C
skipping or Burst Mode behavior is exhibited.
In summary:
1. Be aware that the simultaneous requirements of high
, high I
V
IN
practice due to internal dissipation. The Thermal Considerations section offers a basis to estimate internal
achievable in a
IN
= 40V, V
IN
= 500kHz may be easily achievable, si-
OSC
+ VF/VIN(f
OUT
and high f
OUT
to 60V and f
IN
OSC
may not be achievable in
OSC
)
to 700kHz is not
OSC
OUT
OUT
, as this
=
1977fa
21
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LT1977
WUUU
APPLICATIO S I FOR ATIO
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high V
high f
can result in an unacceptably short minimum
OSC
, low V
IN
OUT
and
switch on time. Cycle skipping and/or Burst Mode behavior will result causing an increase in output voltage
ripple while maintaining the correct output voltage.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits. Read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/or
catch diode and connecting the V
compensation to a
C
ground track carrying significant switch current. In addition the theoretical analysis considers only first order nonideal component behavior. For these reasons, it is important
that a final stability check is made with production layout
and components.
The LT1977 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 12.
The LT1977 can be considered as two gm blocks, the error
amplifier and the power stage.
Figure 13 shows the overall loop response with a 330pF V
C
capacitor and a typical 100µF tantalum output capacitor.
LT1977
CURRENT MODE
POWER STAGE
Ω
= 3
g
m
V
C
11
C
C
F
C
C
gm = 650µ
1.5MR
Ω
ERROR
AMP
Figure 13. Model for Loop Response
SW
2
R1
–
FB
12
+
R2
1.25V
C
FB
1977 F13
OUTPUT
ESR
C
OUT
The response is set by the following terms:
Error amplifier: DC gain is set by g
and RO:
m
Ω
EA Gain = 650µ • 1.5M = 975
The pole set by CF and RL:
EA Pole = 1/(2π • 1.5M • 330pF) = 322Hz
Unity gain frequency is set by C
and gm:
F
Ω
EA Unity Gain Frequency = 650µ /(2π • 330pF)
= 313kHz
Powerstage: DC gain is set by g
and RL (assume 10Ω):
m
PS DC Gain = 3 • 10 = 30
Pole set by C
OUT
and RL:
PS Pole = 1/(2π • 100µF • 10) = 159Hz
Unity gain set by C
OUT
and gm:
PS Unity Gain Freq = 3/(2π • 100µF) = 4.7kHz.
Tantalum output capacitor zero is set by C
OUT
and C
OUT
ESR
Output Capacitor Zero = 1/(2π • 100µF • 0.1) = 159kHz
The zero produced by the ESR of the tantalum output capacitor is very useful in maintaining stability. If better
transient response is required, a zero can be added to the
loop using a resistor (R
capacitor(s). As the value of R
) in series with a compensation
C
is increased, transient re-
C
sponse will generally improve but two effects limit its value.
1977 F14
1M10
100
135
PHASE (DEG)
90
45
0
1977fa
100
50
GAIN (dB)
0
–50
100 1k 10k 100k
V
OUT
C
OUT
= 330pF
C
F
R
C/CC
I
LOAD
FREQUENCY (Hz)
= 3.3V
= 100µF, 0.1Ω
= NC
= 350mA
Figure 14. Overall Loop Response
22
Page 23
WUUU
APPLICATIO S I FOR ATIO
LT1977
First, the combination of output capacitor ESR and a large
may stop loop gain rolling off altogether. Second, if the
R
C
loop gain is not rolled off sufficiently at the switching frequency output ripple will perturb the V
pin enough to cause
C
unstable duty cycle switching similar to subharmonic
oscillation. This may not be apparent at the output. Smallsignal analysis will not show this since a continuous time
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
3.58
(.141)
6.60 ±0.10
4.50 ±0.10
SEE NOTE 4
2.94
(.116)
0.45 ±0.05
system is assumed. If needed, an additional capacitor (C
)
F
can be added to form a pole at below the switching frequency
(if R
= 26k, CC = 1500pF, CF = 330pF).
C
When checking loop stability the circuit should be operated over the application’s full voltage, current and temperature range. Any transient loads should be applied and
the output voltage monitored for a well-damped behavior.
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
16 1514 13 12 11
10 9
2.94
(.116)
6.40
(.252)
BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.50 – 0.75
(.020 – .030)
MILLIMETERS
(INCHES)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1345678
2
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
FE16 (BC) TSSOP 0204
1977fa
23
Page 24
LT1977
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1074/LT1074HV 4.4A (I
LT1076/LT1076HV 1.6A (I
LT1676 60V, 700mA (ISW), 100kHz, High Efficiency Step-Down DC/DC VIN: 7.4V to 60V, V
Converter I
LT1765 25V, 3A (ISW), 1.25MHz, High Efficiency Step-Down DC/DC VIN: 3V to 25V, V
Converter SO-8, TSSOP16/E
LT1766 60V, 1.5A (ISW), 200kHz, High Efficiency Step-Down DC/DC VIN: 5.5V to 60V, V
Converter I
LT1767 25V, 1.5A (ISW), 1.25MHz, High Efficiency Step-Down DC/DC VIN: 3V to 25V, V
Converter MS8E
LT1776 40V, 700mA (ISW), 200kHz, High Efficiency Step-Down DC/DC VIN: 7.4V to 40V, V
Converter I
LT1940 Dual 1.4A (I
Converter
LT1956 60V, 1.5A (ISW), 500kHz, High Efficiency Step-Down DC/DC VIN: 5.5V to 60V, V
Converter I
LT1976 60V, 1.5A (ISW), 200kHz High Efficiency Micropower VIN: 3.3V to 60V, IQ = 100µA, ISD < 1µA, TSSOP16E
Step-Down DC/DC Converter
LT3010 80V, 50mA, Low Noise Linear Regulator VIN: 1.5V to 80V, V
LTC3412 2.5A (I
LTC3414 4A (I
LT3430 60V, 2.5A (I
Converter I
LT3431 60V, 2.5A (I
Converter I
LT3433 60V, 400mA (I
LT3434/LT3435 60V, 3A (ISW), 200kHz/500kHz High Efficiency Micropower VIN: 3.3V to 60V, IQ = 100µA, ISD < 1µA, TSSOP16E,
Step-Down DC/DC Converter
LT3437 80V, 500mA (ISW), 200kHz High Efficiency Micropower VIN: 3.3V to 60V, IQ = 100µA, ISD < 1µA, TSSOP16E,
Step-Down DC/DC Converter 3 × 3 DFN-10
LTC3727/LTC3727-1 36V, 500kHz, High Efficiency Step-Down DC/DC Controllers VIN: 4V to 36V, V
), 100kHz, High Efficiency Step-Down DC/DC Converters VIN: 7.3V to 45V/64V, V
OUT
), 100kHz, High Efficiency Step-Down DC/DC Converters VIN: 7.3V to 45V/64V, V
OUT
), 1.1MHz, High Efficiency Step-Down DC/DC VIN: 3V to 25V, V
OUT
< 10µA, DD5/7, TO220-5/7
I
SD
< 10µA, DD5/7, TO220-5/7
I
SD
< 2.5µA, S8
SD
< 25µA, TSSOP16E
SD
< 30µA, N8, S8
SD
< 25µA, TSSOP16E
SD
MS8E
), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, V
OUT
TSSOP16E
), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.25V to 5.5V, V
OUT
TSSOP20E
), 200kHz, High Efficiency Step-Down DC/DC VIN: 5.5V to 60V, V
OUT
), 500kHz, High Efficiency Step-Down DC/DC VIN: 5.5V to 60V, V
OUT
), 200kHz, Buck-Boost DC/DC Converter VIN: 5V to 60V, V
OUT
< 30µA, TSSOP16E
SD
< 30µA, TSSOP16E
SD
QFN-32, SSOP-28
= 2.21V, IQ = 8.5mA,
OUT(MIN)
= 2.21V, IQ = 8.5mA,
OUT(MIN)
= 1.24V, IQ = 3.2mA,
OUT(MIN)
= 1.20V, IQ = 1mA, I
OUT(MIN)
= 1.20V, IQ = 2.5mA,
OUT(MIN)
= 1.20V, IQ = 1mA, I
OUT(MIN)
= 1.24V, IQ = 3.2mA,
OUT(MIN)
= 1.2V, IQ = 3.8mA, MS10
OUT(MIN)
= 1.20V, IQ = 2.5mA,
OUT(MIN)
= 1.28V, IQ = 30µA, ISD < 1µA,
OUT(MIN)
= 0.8V, IQ = 60µA, ISD < 1µA,
OUT(MIN)
= 0.8V, IQ = 64µA, ISD < 1µA,
OUT(MIN)
= 1.20V, IQ = 2.5mA,
OUT(MIN)
= 1.20V, IQ = 2.5mA,
OUT(MIN)
: 3.3V to 20V, IQ = 100µA, TSSOP16E
OUT
= 0.8V, IQ = 670µA, ISD < 20µA,
OUT(MIN)
SD
SD
< 15µA,
< 6µA,
24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
1977fa
LT/LT 0805 REV A • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2004
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