Datasheet LT1725 Datasheet (LINEAR TECHNOLOGY)

FEATURES

I

LOAD

(A)

0

V

OUT

(V)

5.00

1725 F10b

4.75

0.5

1.0

1.5

2.0

5.25

VIN = 36V

VIN = 72V

VIN = 48V

LT1725

General Purpose

Isolated Flyback Controller

U

DESCRIPTIO

■

Drives External Power MOSFET with External

Resistor

I

SENSE

■

Application Input Voltage Limited Only by
External Power Components

■

Senses Output Voltage Directly from Primary Side
Winding—No Optoisolator Required

■

Accurate Regulation Without User Trims

■

Regulation Maintained Well into Discontinuous Mode

■

Switching Frequency from 50kHz to 250kHz with
External Capacitor

■

Optional Load Compensation

■

Optional Undervoltage Lockout

■

Available in 16-Pin SO and SSOP Packages

U

APPLICATIO S

■

Telecom Isolated Converters

■

Offline Isolated Power Supplies

■

Instrumentation Power Supplies

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

The LT®1725 is a monolithic switching regulator control­ler specifically designed for the isolated flyback topology.
It drives the gate of an external MOSFET and is generally
powered from a third transformer winding. These features
allow for an application input voltage limited only by
external power path components. The third transformer
winding also provides output voltage feedback informa­tion, such that an optoisolator is not required. Its gate
drive capability coupled with a suitable external MOSFET
can deliver load power up to tens of watts.

The LT1725 has a number of features not found on most
other switching regulator ICs. By utilizing current mode
switching techniques, it provides excellent AC and DC line
regulation. Its unique control circuitry can maintain regu­lation well into discontinuous mode in most applications.
Optional load compensation circuitry allows for improved
load regulation. An optional undervoltage lockout pin
halts operation when the application input voltage is too
low. An optional external capacitor implements a soft­start function. A 3V output is available at up to several mA
for powering primary side application circuitry.

TYPICAL APPLICATIO

35.7k
1%

3.01k
1%

1nF

47pF

51k

51k

51k

2.7k

0.1µF

3V

OUT

FB

SFST

VC

OSCAP

t

ON

ENDLY

MENAB

R

OCMP

R

CMPC

SGND PGND

LT1725

UVLO

I

SENSE

U

48V to Isolated 5V Converter

V

36V TO 72V

V

GATE

BAS16

22Ω

CC

+

15µF

100pF

47k

820k

33k

IN

1µF

1.5µF

68Ω

150pF

CTX02-14989

6

1

2

4

IRF620

0.18Ω

1725 TA01a

9

11

10

12

18Ω

12CWQ06

150µF

470pF

+

51Ω
1W

V

OUT

I

OUT

= 5V

= 0 to 2A

Output Load Regulation

1725fa

1

LT1725

PACKAGE/ORDER I FOR ATIO

UU

W

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

VCC Supply Voltage ................................................. 22V

UVLO Pin Voltage .................................................... V

I

Pin Voltage .................................................... 2V

SENSE

FB Pin Current ..................................................... ± 2mA

Operating Junction
Temperature Range

LT1725C .............................................. 0°C to 100°C

LT1725I ........................................... –40°C TO 125°C

Storage Temperature Range ................ – 65°C to 150°C

Lead Temperature (Soldering, 10 sec)................ 300°C

CC

TOP VIEW

1

PGND

2

I

SENSE

3

SFST

4

R

OCMP

5

R

CMPC

6

OSCAP

7

V

C

8

FB

GN PACKAGE

16-LEAD PLASTIC SSOP

T

= 125°C, θJA = 110°C/W (GN)

JMAX

= 125°C, θJA = 100°C/W (SO)

T

JMAX

16

GATE

15

V

CC

14

t

ON

13

ENDLY

12

MINENAB

11

SGND

10

UVLO

9

3V

OUT

S PACKAGE

16-LEAD PLASTIC SO

ORDER PART NUMBER

LT1725CGN
LT1725IGN

GN PART MARKING

1725

1725I
LT1725CS
LT1725IS

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply

V

CC

I

CC

Feedback Amplifier

V

FB

I

FB

g

m

I

, I

SRC

V

CL

VCC Turn-On Voltage
V

Turn-Off Voltage

CC

Hysteresis (Note 3) (V

V

CC

Supply Current VC = Open
Start-Up Current

Feedback Voltage 1.230 1.245 1.260 V

Feedback Pin Input Current 500 nA
Feedback Amplifier Transconductance ∆lC = ±10µA

Feedback Amplifier Source or Sink Current

SNK

Feedback Amplifier Clamp Voltage 2.5 V
Reference Voltage/Current Line Regulation 12V ≤ VIN ≤ 18V

Voltage Gain VC = 1V to 2V 2000 V/V

Soft-Start Charging Current V

Soft-Start Discharge Current V

The ● denotes specifications which apply over the full operating

= 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.

A

●

14.0 15.1 16.0 V

●

8 9.7 11 V

– V

TURN-ON

= 0V 25 40 50 µA

SFST

= 1.5V, V

SFST

)

TURN-OFF

= 0V 0.8 1.5 mA

UVLO

●

4.0 5.4 6.5 V

●

61015mA

●

●

1.220 1.270 V

●

400 1000 1800 µmho

●

30 50 80 µA

●

120 280 µA

0.01 0.05 %/V

2

1725fa

LT1725

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Gate Output

V

GATE

I

GATE

t

r

t

f

Output High Level I

Output Low Level I

Output Sink Current in Shutdown, V

UVLO

= 0V V

GATE

I

GATE

GATE

I

GATE

GATE

= 100mA
= 500mA

= 100mA
= 500mA

= 2V

●

11.5 12.1 V

●

11.0 11.8 V

●

●

●

1.2 2.5 mA

0.3 0.45 V

0.6 1.0 V

Rise Time CL = 1000pF 30 ns

Fall Time CL = 1000pF 30 ns

Current Amplifier

V

C

V

ISENSE

Control Pin Threshold Duty Cycle = Min 0.90 1.12 1.25 V

●

0.80 1.35 V

Switch Current Limit Duty Cycle ≤ 30% 220 250 270 mV

●

Duty Cycle ≤ 30%

200 280 mV

Duty Cycle = 80% 220 mV

∆V

ISENSE

/∆V

C

0.30 mV

Timing

f Switching Frequency C

C

OSCAP

t

ON

t

ED

t

EN

R

t

Oscillator Capacitor Value (Note 2) 33 200 pF

Minimum Switch On Time R

Flyback Enable Delay Time R

Minimum Flyback Enable Time R
Timing Resistor Value (Note 2) 24 200 kΩ

Maximum Switch Duty Cycle

= 100pF 90 100 115 kHz

OSCAP

= 50k 200 ns

tON

= 50k 200 ns

ENDLY

= 50k 200 ns

MENAB

●

80 125 kHz

●

85 90 %

Load Compensation

Sense Offset Voltage 25mV

Current Gain Factor 0.80 0.95 1.05 mV

UVLO Function

V

UVLO

I

UVLO

UVLO Pin Threshold

UVLO Pin Bias Current V

●

1.21 1.25 1.29 V

= 1.2V –0.25 + 0.1 +0.25 µA

UVLO

V

= 1.3V –4.50 – 3.5 –2.50 µA

UVLO

3V Output Function

V

REF

Reference Output Voltage I

LOAD

= 1mA

●

2.8 3.0 3.2 V

Output Impedance 10 Ω

Current Limit

●

815 mA

Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.

Note 2: Component value range guaranteed by design.
Note 3: The V

turn-on/turn-off voltages and hysteresis voltage are

CC

proportional in magnitude to each other-guaranteed by design.

1725fa

3

LT1725

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Hysteresis Voltage vs

VCC Turn-On Voltage vs
Temperature

16.00

V

CC

Temperature Start-Up Current vs Temperature

6.50

250

15.75

15.50

15.25

15.00

TURN-ON VOLTAGE (V)

14.75

CC

V

14.50

14.25
–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

Supply Current vs Temperature

13

12

11

10

SUPPLY CURRENT (mA)

9

1725 G01

6.25

6.00

5.75

5.50

5.25

HYSTERESIS VOLTAGE (V)

CC

V

5.00

4.75
–50

–25 0

25 75

TEMPERATURE (°C)

UVLO Pin Input Current vs
Temperature

1

V

0

–1

–2

–3

–4

UVLO PIN INPUT CURRENT (µA)

–5

UVLO

V

UVLO

50 100 125

= 1.2V

= 1.3V

1725 G02

200

150

100

START-UP CURRENT (µA)

50

0

–50

–25

25

0

TEMPERATURE (°C)

Oscillator Frequency vs
Temperature

115

110

105

100

95

OSCILLATOR FREQUENCY (kHz)

90

50

75

100

125

1725 G03

(V)

V

4

1.0

0.8

0.6

GATE

0.4

0.2

8

–50

0

–25

TEMPERATURE (°C)

50

25

75

100

125

1725 G04

–6

–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

1725 G05

85

–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

1725 G06

VC Clamp Voltage, Switching

–0.5

–1.0

(V)

GATE

–1.5

-V
CC

V

–2.0

–2.5

–3.0

VCC-V

0

1

V

vs I

GATE

0

1

SINK

TA = 125°C

TA = 25°C

TA = –55°C

10 100 1000

I

(mA)

SINK

1725 G07

GATE

TA = –55°C

vs I

SOURCE

TA = 125°C

TA = 25°C

10 100 1000

I

(mA)

SOURCE

1725 G08

Threshold vs Temperature

3.0

2.5

2.0

1.5

1.0
SWITCHING THRESHOLD

0.5

CLAMP VOLTAGE, SWITCHING THRESHOLD (V)

C

0

V

–50

–25 0

TEMPERATURE (°C)

CLAMP VOLTAGE

50 100 125

25 75

1725 G09

1725fa

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LT1725

Minimum Switch-On Time vs
Temperature

275

R

= 50k

TON

250

225

200

175

150

MINIMUM SWITCH-ON TIME (ns)

125

–50

–25 0

25 75

TEMPERATURE (°C)

Feedback Amplifier Output Current
vs FB Pin Voltage

80

60

40

TA = 25°C

20

0

–20

–40

–60

FEEDBACK AMPLIFIER OUTPUT CURRENT (µA)

–80

1.05

Minimum Enable Time vs
Temperature

275

R

MINENAB

250

225

200

175

MINIMUM ENABLE TIME (ns)

150

50 100 125

1725 G10

TA = –55°C

1.15 1.25

1.10 1.20 1.30 1.40
FB PIN VOLTAGE (V)

125

–50

TA = 125°C

1.35

1725 G13

= 50k

–25 0

50 100 125

25 75

TEMPERATURE (°C)

Enable Delay Time vs
Temperature

275

250

225

200

175

ENABLE DELAY TIME (ns)

150

125

–50

–25 0

1725 G11

Feedback Amplifier
Transconductance vs Temperature

1600

1400

1200

1000

800

600

400

200

FEEDBACK AMPLIFIER TRANSCONDUCTANCE (µmho)

–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

50 100 125

25 75

TEMPERATURE (°C)

1725 G14

1725 G12

Soft-Start Charging Current vs
Temperature

60

50

40

30

20

10

SOFT-START CHARGING CURRENT (µA)

0

–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

V(SFST) = 0V

1725 G15

Soft-Start Sink Current vs
Temperature

2.5

2.0

1.5

1.0

0.5

SOFT-START SINK CURRENT (mA)

0

–50

–25

25

0

TEMPERATURE (°C)

V(SFST) = 1.5V

50

75

100

125

1725 G16

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5

LT1725

U

UU

PI FU CTIO S

PGND (Pin 1): The power ground pin carries the GATE
node discharge current. This is typically a current spike of
several hundred mA with a duration of tens of nanosec­onds. It should be connected directly to a good quality
ground plane.

I

(Pin 2): Pin to measure switch current with exter-

SENSE

nal sense resistor. The sense resistor should be of a
noninductive construction as high speed performance is
essential. Proper grounding technique is also required to
avoid distortion of the high speed current waveform. A
preset internal limit of nominally 250mV at this pin effects
a switch current limit.

SFST (Pin 3): Pin for optional external capacitor to effect
soft-start function. See Applications Information for details.

(Pin 4): Input pin for optional external load compen-

R

OCMP

sation resistor. Use of this pin allows nominal compensa­tion for nonzero output impedance in the power transformer
secondary circuit, including secondary winding impedance,
output Schottky diode impedance and output capacitor
ESR. In less demanding applications, this resistor is not
needed. See Applications Information for more details.

R

(Pin 5): Pin for external filter capacitor for optional

CMPC

load compensation function. A common 0.1µF ceramic
capacitor will suffice for most applications. See Applica­tions Information for further details.

OSCAP (Pin 6): Pin for external timing capacitor to set
oscillator switching frequency. See Applications Informa­tion for details.

VC (pin 7): This is the control voltage pin which is the
output of the feedback amplifier and the input of the
current comparator. Frequency compensation of the
overall loop is effected in most cases by placing a capaci­tor between this node and ground.

FB (Pin 8): Input pin for external “feedback” resistor
divider. The ratio of this divider, times the internal
bandgap (V

) reference, times the effective output-to-

BG

third winding transformer turns ratio is the primary deter­minant of the output voltage. The Thevenin equivalent
resistance of the feedback divider should be roughly 3k.
See Applications Information for more details.

3V

(Pin 9): Output pin for nominal 3V reference. This

OUT

facilitates various user applications. This node is internally
current limited for protection and is intended to drive
either moderate capacitive loads of several hundred pF or
less, or, very large capacitive loads of 0.1µF or more. See
Applications Information for more details.

UVLO (Pin 10): This pin allows the use of an optional
external resistor divider to set an undervoltage lockout
based upon V
sufficient to allow the part to start up, but the UVLO pin is
held below its threshold, output switching action will be
disabled, but the part will draw its normal quiescent
current from V
oscillation action on the V
“trickle-charge” bootstrapped configuration.)

The bias current on this pin is a function of the state of the
UVLO comparator; as the threshold is exceeded, the bias
current increases. This creates a hysteresis band equal to
the change in bias current times the Thevenin impedance
of the user’s resistive divider. The user may thereby adjust
the impedance of the UVLO divider to achieve a desired
degree of hysteresis. A 100pF capacitor to ground is
recommended on this pin. See Applications Information
for details.

SGND (Pin 11): The signal ground pin is a clean ground.
The internal reference, oscillator and feedback amplifier
are referred to it. Keep the ground path connection to the
FB pin, OSCAP capacitor and the VC compensation capaci­tor free of large ground currents.

MINENAB (Pin 12): Pin for external programming resistor
to set minimum enable time. See Applications Information
for details.

(not VCC) level. (Note: If the VCC voltage is

IN

. This typically causes a benign relaxation

CC

pin in the conventional

CC

6

1725fa

LT1725

U

UU

PI FU CTIO S

ENDLY (Pin 13): Pin for external programming resistor to
set enable delay time. See Applications Information for
details.

tON (Pin 14): Pin for external programming resistor to set
switch minimum on time. See Applications Information
for details.

W

BLOCK DIAGRA

V

CC

3V

UVLO

BIAS

OUT

3V REG
(INTERNAL)

VCC (Pin 15): Supply voltage for the LT1725. Bypass this
pin to ground with 1µF or more.

GATE (Pin 16): This is the gate drive to the external power
MOSFET switch and has large dynamic currents flowing
through it. Keep the trace to the MOSFET as short as
possible to minimize electromagnetic radiation and volt­age spikes. A series resistance of 5Ω or more may help to
dampen ringing in less than ideal layouts.

OSCAP

FB

OSC

FDBK

MINENABt

ON

LOGIC

V

C

ENDLY

MOSFET

DRIVER

PGND

COMP

SOFT-START

SFST R

COMPENSATION

R

OCMP

LOAD

I

AMP

CMPC

1725 BD

GATE

I

SENSE

SGND

1725fa

7

LT1725

UWW

TI I G DIAGRA

V

SW

VOLTAGE

V

IN

GND

SWITCH

STATE

OFF ON

MINIMUM t

ON

FLYBACK AMP

STATE

ENABLE DELAY

MINIMUM ENABLE TIME

V

FLBK

OFF ON

ENABLEDDISABLED DISABLED

0.80×
V

FLBK

COLLAPSE
DETECT

1725 TD

W

FLYBACK ERROR A PLIFIER

V

IN

M1

R1

FB

Q1 Q2

R2

I

T1

•

D1

+

+

C1

•

ISOLATED

V

OUT

–

•

I

M

V

BG

I

FXD

V

C

ENAB

C2

I

M

1725 EA

8

1725fa

OPERATIO

LT1725

U

The LT1725 is a current mode switcher controller IC
designed specifically for the isolated flyback topology. The
Block Diagram shows an overall view of the system. Many
of the blocks are similar to those found in traditional
designs, including: Internal Bias Regulator, Oscillator,
Logic, Current Amplifier and Comparator, Driver and Out­put Switch. The novel sections include a special Flyback
Error Amplifier and a Load Compensation mechanism.
Also, due to the special dynamic requirements of flyback
control, the Logic system contains additional functionality
not found in conventional designs.

The LT1725 operates much the same as traditional current
mode switchers, the major difference being a different
type of error amplifier that derives its feedback informa­tion from the flyback pulse. Due to space constraints, this
discussion will not reiterate the basics of current mode
switcher/controllers and isolated flyback converters. A
good source of information on these topics is Application
Note AN19.

ERROR AMPLIFIER—PSEUDO DC THEORY

Please refer to the simplified diagram of the Flyback Error
Amplifier. Operation is as follows: when MOSFET output
switch M1 turns off, its drain voltage rises above the V
rail. The amplitude of this flyback pulse as seen on the third
winding is given as:

V

FLBK

V V I ESR

++

()

OUT F SEC

=

N

•

ST

IN

The relatively high gain in the overall loop will then cause
the voltage at the FB pin to be nearly equal to the bandgap
reference V
may then be expressed as:

V

FLBK BG

Combination with the previous V
expression for V
programming resistors, transformer turns ratio and diode
forward voltage drop:

VV

OUT BG ST F SEC

Additionally, it includes the effect of nonzero secondary
output impedance, which is discussed below in further
detail, see Load Compensation Theory. The practical as­pects of applying this equation for V
Applications Information section.

So far, this has been a pseudo-DC treatment of flyback
error amplifier operation. But the flyback signal is a pulse,
not a DC level. Provision must be made to enable the
flyback amplifier only when the flyback pulse is present.
This is accomplished by the dotted line connections to the
block labeled “ENAB”. Timing signals are then required to
enable and disable the flyback amplifier.

ERROR AMPLIFIER—DYNAMIC THEORY

. The relationship between V

BG

RR

+

12

()

=

R

=

V

2

FLBK

in terms of the internal reference,

OUT

12

RR

+

()

2

R

–– •

NVIESR

()

expression yields an

are found in the

OUT

FLBK

and V

BG

VF = D1 forward voltage
I

= transformer secondary current

SEC

ESR = total impedance of secondary circuit
NST = transformer effective secondary-to-third

winding turns ratio

The flyback voltage is then scaled by external resistor
divider R1/R2 and presented at the FB pin. This is then
compared to the internal bandgap reference by the differ­ential transistor pair Q1/Q2. The collector current from Q1
is mirrored around and subtracted from fixed current
source I
this net current to provide the control voltage to set the
current mode trip point.

at the VC pin. An external capacitor integrates

FXD

There are several timing signals which are required for
proper LT1725 operation. Please refer to the Timing
Diagram.

Minimum Output Switch On Time

The LT1725 affects output voltage regulation via flyback
pulse action. If the output switch is not turned on at all,
there will be no flyback pulse and output voltage informa­tion is no longer available. This would cause irregular loop
response and start-up/latchup problems. The solution cho­sen is to require the output switch to be on for an absolute
minimum time per each oscillator cycle. This in turn estab­lishes a minimum load requirement to maintain regula­tion. See Applications Information for further details.

1725fa

9

LT1725

OPERATIO

U

Enable Delay

When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans­former primary side voltage waveform approximately rep­resents the output voltage. This is partly due to rise time
on the MOSFET drain node, but more importantly, due to
transformer leakage inductance. The latter causes a volt­age spike on the primary side not directly related to output
voltage. (Some time is also required for internal settling of
the feedback amplifier circuitry.)

In order to maintain immunity to these phenomena, a
fixed delay is introduced between the switch turnoff
command and the enabling of the feedback amplifier. This
is termed “enable delay”. In certain cases where the
leakage spike is not sufficiently settled by the end of the
enable delay period, regulation error may result. See
Applications Information for further details.

Collapse Detect

Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
voltage (FB referred) to a fixed reference, nominally 80%
of V

. When the flyback waveform drops below this

BG

level, the feedback amplifier is disabled. This action
accommodates both continuous and discontinuous mode
operation.

Minimum Enable Time

The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time.” This prevents lockup, especially when the output
voltage is abnormally low, e.g., during start-up. The mini­mum enable time period ensures that the V

node is able

C

to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
the low load level at which output voltage regulation is lost.
See Applications Information for details.

Effects of Variable Enable Period

It should now be clear that the flyback amplifier is enabled
during only a portion of the cycle time. This can vary from
the fixed “minimum enable time” described to a maximum
of roughly the “off” switch time minus the enable delay
time. Certain parameters of flyback amp behavior will then
be directly affected by the variable enable period. These
include effective transconductance and V

node slew rate.

C

LOAD COMPENSATION THEORY

The LT1725 uses the flyback pulse to obtain information
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,

T1

10

R1

R2

FB

LOAD

COMP I

Q1 Q2

I

M

+

Q3

V

BG

I

M

Figure 1. Load Compensation Diagram

R

OCMP

A1

–

R

R3

50k

CMPC

I

SENSE

V

IN

M1

R

SENSE

1725 F01

1725fa

OPERATIO

LT1725

U

transformer secondary and output capacitor. This has
been represented previously by the expression “I

SEC

•
ESR.” However, it is generally more useful to convert this
expression to an effective output impedance. Because the
secondary current only flows during the off portion of the
duty cycle, the effective output impedance equals the
lumped secondary impedance times the inverse of the OFF
duty cycle. That is:

DC

1

OFF

⎞

where

⎟
⎠

R ESR

⎛

=

OUT

R

= effective supply output impedance

OUT

⎜
⎝

ESR = lumped secondary impedance

= OFF duty cycle

DC

OFF

Expressing this in terms of the ON duty cycle, remember­ing DC

R ESR

OFF

OUT

= 1 – DC,

⎛

=

⎜
⎝

1–

1

DC

⎞
⎟

⎠

DC = ON duty cycle

In less critical applications, or if output load current
remains relatively constant, this output impedance error
may be judged acceptable and the external FB resistor
divider adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error may be minimized by the use of the load compensa­tion function.

⎛

=

⎜
⎝

V

V EFF

IN

I

IN

OUT

•

⎞

•

I

⎟

OUT

⎠

combining the efficiency and voltage terms in a single
variable:

I

= K1 • I

IN

K

1=

⎛
⎜

⎝

V EFF

IN

V

OUT

OUT

•

, where

⎞
⎟

⎠

Switch current is converted to voltage by the external
sense resistor and averaged/lowpass filtered by R3 and
the external capacitor on R
impressed across the external R

. This voltage is then

CMPC

resistor by op amp

OCMP

A1 and transistor Q3. This produces a current at the
collector of Q3 which is then mirrored around and then
subtracted from the FB node. This action effectively in­creases the voltage required at the top of the R1/R2
feedback divider to achieve equilibrium. So the effective
change in V

VKI

∆ = ∆

OUT OUT

VV

∆

OUT

∆

I

OUT

target is:

OUT

⎛

11•••

()

⎛

R

=

SENSE

11••

K

⎜

R

⎝

OCMP

R

⎜

R

⎝
⎞

⎟
⎠

SENSE

OCMP

RN

ST

⎞

RN or

⎟
⎠

ST

Nominal output impedance cancellation is obtained by
equating this expression with R

OUT

:

To implement the load compensation function, a voltage is
developed that is proportional to average output switch
current. This voltage is then impressed across the external

resistor, and the resulting current acts to increase

R

OCMP

the V

reference used by the flyback error amplifier. As

BG

output loading increases, average switch current increases
to maintain rough output voltage regulation. This causes
an increase in R

resistor current which effects a

OCMP

corresponding increase in target output voltage.

Assuming a relatively fixed power supply efficiency, Eff,

Power Out = Eff • Power In

• I

V

OUT

= Eff • VIN • I

OUT

IN

Average primary side current may be expressed in terms
of output current as follows:

⎛

R

R

OUT

OCM

ESR

=

DC

−

1

KR

1

PP SENSE ST

R

K

=

11••

⎜

R

⎝

K1 = dimensionless variable related to VIN, V

⎞

SENSE

OCMP

1

()

RN

⎟
⎠

DC

−

ST

RN=

1•• ••

ESR

OUT

and

efficiency as above
R
R

= external sense resistor

SENSE

= uncompensated output impedance

OUT

The practical aspects of applying this equation to deter­mine an appropriate value for the R

resistor are found

OCMP

in the Applications Information section.

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TRANSFORMER DESIGN CONSIDERATIONS

Transformer specification and design is perhaps the most
critical part of applying the LT1725 successfully. In addi­tion to the usual list of caveats dealing with high frequency
isolated power supply transformer design, the following
information should prove useful.

Turns Ratios

Note that due to the use of the external feedback resistor
divider ratio to set output voltage, the user has relative
freedom in selecting transformer turns ratio to suit a given
application. In other words, “screwball” turns ratios like
“1.736:1.0” can scrupulously be avoided! In contrast,
simpler ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can
be employed which yield more freedom in setting total
turns and mutual inductance. Turns ratio can then be
chosen on the basis of desired duty cycle. However,
remember that the input supply voltage plus the second­ary-to-primary referred version of the flyback pulse (in­cluding leakage spike) must not exceed the allowed external
MOSFET breakdown rating.

Leakage Inductance

As a rough guide, total leakage inductances of several
percent (of mutual inductance) or less may require a
snubber, but exhibit little to no regulation error due to
leakage spike behavior. Inductances from several percent
up to perhaps ten percent cause increasing regulation
error.

Severe leakage inductances in the double digit percentage
range should be avoided if at all possible as there is a
potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leak­age spike becomes such a large portion of the flyback
waveform that the processing circuitry is fooled into
thinking that the leakage spike itself is the real flyback
signal! It then reverts to a potentially stable state whereby
the top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This will typically reduce the output volt­age abruptly to a fraction, perhaps between one-third to
two-thirds of its correct value. If load current is reduced
sufficiently, the system will snap back to normal opera­tion. When using transformers with considerable leakage
inductance, it is important to exercise this worst-case
check for potential bistability:

Transformer leakage inductance (on either the primary or
secondary) causes a spike after output switch turnoff. This
is increasingly prominent at higher load currents, where
more stored energy must be dissipated. In many cases a
“snubber” circuit will be required to avoid overvoltage
breakdown at the output switch node. Application Note
AN19 is a good reference on snubber design.

In situations where the flyback pulse extends beyond the
enable delay time, the output voltage regulation will be
affected to some degree. It is important to realize that the
feedback system has a deliberately limited input range,
roughly ± 50mV referred to the FB node, and this works to
the user’s advantage in rejecting large, i.e., higher voltage,
leakage spikes. In other words, once a leakage spike is
several volts in amplitude, a further increase in amplitude
has little effect on the feedback system. So the user is
generally advised to arrange the snubber circuit to clamp
at as high a voltage as comfortably possible, observing
MOSFET breakdown, such that leakage spike duration is
as short as possible.

1. Operate the prototype supply at maximum expected
load current.

2. Temporarily short circuit the output.

3. Observe that normal operation is restored.

If the output voltage is found to hang up at a abnormally
low value, the system has a problem. This will usually be
evident by simultaneously monitoring the V
on an oscilloscope to observe leakage spike behavior
firsthand. A final note—the susceptibility of the system to
bistable behavior is somewhat a function of the load I/V
characteristics. A load with resistive, i.e., I = V/R behavior
is the most susceptible to bistability. Loads which exhibit
“CMOSsy”, i.e., I = V

Secondary Leakage Inductance

In addition to the previously described effects of leakage
inductance in general, leakage inductance on the second­ary in particular exhibits an additional phenomenon. It
forms an inductive divider on the transformer secondary,

2

/R behavior are less susceptible.

waveform

SW

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LT1725

which reduces the size of the primary-referred flyback
pulse used for feedback. This will increase the output
voltage target by a similar percentage. Note that unlike
leakage spike behavior, this phenomena is load indepen­dent. To the extent that the secondary leakage inductance
is a constant percentage of mutual inductance (over
manufacturing variations), this can be accommodated by
adjusting the feedback resistor divider ratio.

Winding Resistance Effects

Resistance in either the primary or secondary will act to
reduce overall efficiency (P

OUT/PIN

). Resistance in the
secondary increases effective output impedance which
degrades load regulation, (at least before load compensa­tion is employed).

Bifilar Winding

A bifilar or similar winding technique is a good way to
minimize troublesome leakage inductances. However re­member that this will increase primary-to-secondary ca­pacitance and limit the primary-to-secondary breakdown
voltage, so bifilar winding is not always practical.

Finally, the LTC Applications group is available to assist
in the choice and/or design of the transformer. Happy
Winding!

SELECTING FEEDBACK RESISTOR DIVIDER VALUES

The expression for V

developed in the Operation sec-

OUT

tion can be rearranged to yield the following expression for
the R1/R2 ratio:

VVIESR

RR

12

+

()

R

=

2

++

()

OUT F SEC

VN

BG ST

•

•

where:

V

= desired output voltage

OUT

VF = switching diode forward voltage

• ESR = secondary resistive losses

I

SEC

VBG = data sheet reference voltage value
NST = effective secondary-to-third winding turns ratio

The above equation defines only the ratio of R1 to R2, not
their individual values. However, a “second equation for
two unknowns” is obtained from noting that the Thevenin
impedance of the resistor divider should be roughly 3k for
bias current cancellation and other reasons.

SELECTING R

RESISTOR VALUE

OCMP

The Operation section previously derived the following
expressions for R

, the external resistor value required for its nominal

R

OCMP

, i.e., effective output impedance and

OUT

compensation:

1

RESR

OUT

⎛

=

⎜

⎝
⎛

RK

OCMP

=

⎜
⎝

While the value for R

11–

R

SENSE

R

⎞
⎟

⎠

DC

⎞

RRN

1•

()

OUT

OCMP

⎟
⎠

ST

may therefore be theoretically
determined, it is usually better in practice to employ
empirical methods. This is because several of the required
input variables are difficult to estimate precisely. For
instance, the ESR term above includes that of the trans­former secondary, but its effective ESR value depends on
high frequency behavior, not simply DC winding resis­tance. Similarly, K1 appears to be a simple ratio of V

times (differential) efficiency, but theoretically esti-

V

OUT

IN

to

mating efficiency is not a simple calculation. The sug­gested empirical method is as follows:

Build a prototype of the desired supply using the eventual
secondary components. Temporarily ground the R

CMPC

pin to disable the load compensation function. Operate the
supply over the expected range of output current loading
while measuring the output voltage deviation. Approxi­mate this variation as a single value of R

(straight line

OUT

approximation). Calculate a value for the K1 constant
based on V
ciency. These are then combined with R
to yield a value for R

IN

, V

and the measured (differential) effi-

OUT

as indicated

SENSE

.

OCMP

Verify this result by connecting a resistor of roughly this
value from the R
ground short to R

pin to ground. (Disconnect the

OCMP

and connect the requisite 0.1µF

CMPC

filter capacitor to ground.) Measure the output impedance

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APPLICATIO S I FOR ATIO

with the new compensation in place. Modify the original
R

value if necessary to increase or decrease the

OCMP

effective compensation.

SELECTING OSCILLATOR CAPACITOR VALUE

The switching frequency of the LT1725 is set by an
external capacitor connected between the OSCAP pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 2 shows the nominal relationship between
external capacitance and switching frequency. To mini­mize stray capacitance and potential noise pickup, this
capacitor should be placed as close as possible to the IC
and the OSCAP node length/area minimized.

300

200

(kHz)

OSC

f

100

1000

500

TIME (ns)

100

20

Figure 3. “One Shot” Times vs Programming Resistor

100 250

RT (kΩ)

1725 F03

Minimum On Time

This time defines a period whereby the normal switch
current limit is ignored. This feature provides immunity to
the leading edge current spike often seen at the source
node of the external power MOSFET, due to rapid charging
of its gate/source capacitance. This current spike is not
indicative of actual current level in the transformer pri­mary, and may cause irregular current mode switching
action, especially at light load.

50

30

Figure 2. f

OSC

100 200

C

(pF)

OSCAP

vs OSCAP Value

1725 F02

SELECTING TIMING RESISTOR VALUES

There are three internal “one-shot” times that are pro­grammed by external application resistors: minimum on
time, enable delay time and minimum enable time. These
are all part of the isolated flyback control technique, and
their functions have been previously outlined in the Theory
of Operation section. Figures 3 shows nominal observed
time versus external resistor value for these functions.

The following information should help in selecting and/or
optimizing these timing values.

However, the user must remember that the LT1725 does
not “skip cycles” at light loads. Therefore, minimum on
time will set a limit on minimum delivered power and con­sequently a minimum load requirement to maintain regu­lation (see Minimum Load Considerations). Similarly,
minimum on time has a direct affect on short-circuit be­havior (see Maximum Load/Short-Circuit Considerations).

The user is normally tempted to set the minimum on time
to be short to minimize these load related consequences.
(After all, a smaller minimum on time approaches the ideal
case of zero, or no minimum.) However, a longer time may
be required in certain applications based on MOSFET
switching current spike considerations.

Enable Delay Time

This function provides a programmed delay between
turnoff of the gate drive node and the subsequent enabling
of the feedback amplifier. At high loads, a primary side
voltage spike after MOSFET turnoff may be observed due

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LT1725

to transformer leakage inductance. This spike is not in­dicative of actual output voltage (see Figure 4B). Delaying
the enabling of the feedback amplifier allows this system
to effectively ignore most or all of the voltage spike and
maintain proper output voltage regulation. The enable
delay time should therefore be set to the maximum ex­pected duration of the leakage spike. This may have
implications regarding output voltage regulation at mini­mum load (see Minimum Load Considerations).

A second benefit of the enable delay time function occurs
at light load. Under such conditions the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage (see Figure 4C). So
the enable delay time should also be set long enough to
ignore the “irrelevant” portion of the flyback waveform at
light load.

Additionally, there are cases wherein the gate output is
called upon to drive a large geometry MOSFET such that
the turnoff transition is slowed significantly. Under such
circumstances, the enable delay time may be increased to
accommodate for the lengthy transition.

MOSFET GATE DRIVE

A

B

C

ENABLE

DELAY

TIME

NEEDED

ENABLE DELAY

TIME NEEDED

DISCONTINUOUS

MODE

RINGING

Figure 4

IDEALIZED FLYBACK
WAVEFORM

FLYBACK WAVEFORM
WITH LARGE LEAKAGE
SPIKE AT HEAVY LOAD

“SLOW” FLYBACK
WAVEFORM AT
LIGHT LOAD

1725 F04

Minimum Enable Time

This function sets a minimum duration for the expected
flyback pulse. Its primary purpose is to provide a mini­mum source current at the VC node to avoid start-up
problems.

Average “start-up” V

MinimumEnable Time

SwitchingFrequency

current =

C

I

•

SRC

Minimum enable time can also have implications at light
load (see Minimum Load Considerations). The temptation
is to set the minimum enable time to be fairly short, as this
is the least restrictive in terms of minimum load behavior.
However, to provide a “reliable” minimum start-up current
of say, nominally 1µA, the user should set the minimum
enable time at no less that 2% of the switching period
(= 1/switching frequency).

CURRENT SENSE RESISTOR CONSIDERATIONS

The external current sense resistor allows the user to
optimize the current limit behavior for the particular appli­cation under consideration. As the current sense resistor
is varied from several ohms down to tens of milliohms,
peak switch current goes from a fraction of an ampere to
tens of amperes. Care must be taken to ensure proper
circuit operation, especially with small current sense
resistor values.

For example, a peak switch current of 10A requires a sense
resistor of 0.025Ω. Note that the instantaneous peak power
in the sense resistor is 2.5W, and it must be rated accord­ingly. The LT1725 has only a single sense line to this re­sistor. Therefore, any parasitic resistance in the ground side
connection of the sense resistor will increase its apparent
value. In the case of a 0.025Ω sense resistor,

one milliohm

of parasitic resistance will cause a 4% reduction in peak
switch current. So resistance of printed circuit copper
traces and vias cannot necessarily be ignored.

An additional consideration is parasitic inductance. Induc­tance in series with the current sense resistor will accen­tuate the high frequency components of the current
waveform. In particular, the gate switching spike and
multimegahertz ringing at the MOSFET can be considerably

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APPLICATIO S I FOR ATIO

amplified. If severe enough, this can cause erratic opera­tion. For example, assume 3nH of parasitic inductance
(equivalent to about 0.1 inch of wire in free space) is in series
with an ideal 0.025Ω sense resistor. A “zero” will be formed
at f = R/(2πL), or 1.3MHz. Above this frequency the sense
resistor will behave like an inductor.

Several techniques can be used to tame this potential
parasitic inductance problem. First, any resistor used for
current sensing purposes must be of an inherently non­inductive construction. Mounting this resistor directly
above an unbroken ground plane and minimizing its
ground side connection will serve to absolutely minimize
parasitic inductance. In the case of low valued sense
resistors, these may be implemented as a parallel combi­nation of several resistors for the thermal considerations
cited above. The parallel combination will help to lower the
parasitic inductance. Finally, it may be necessary to place
a “pole” between the current sense resistor and the
LT1725 I

pin to undo the action of the inductive zero

SENSE

(see Figure 5). A value of 51Ω is suggested for the resistor,
while the capacitor is selected empirically for the particular
application and layout. Using good high frequency mea­surement techniques, the I

pin waveform may be

SENSE

observed directly with an oscilloscope while the capacitor
value is varied.

SENSE RESISTOR ZERO AT:

R

SENSE

f =

2πL

P

COMPENSATING POLE AT:

FOR CANCELLATION:

f =

2π(51Ω)C

C

COMP

1

COMP

L

P

=

R

(51Ω)

SENSE

PGNDSGND

GATE

I

SENSE

51Ω

C

COMP

PARASITIC

INDUCTANCE

R

SENSE

L

P

1725 F05

Figure 5

SOFT-START FUNCTION

The LT1725 contains an optional soft-start function that is
enabled by connecting an explicit external capacitor be­tween the SFST pin and ground. Internal circuitry prevents
the control voltage at the V

pin from exceeding that on the

C

SFST pin.

The soft-start function is enagaged whenever VCC power
is removed, or as a result of either undervoltage lockout
or thermal (overtemperature) shutdown. The SFST node
is then discharged to roughly a VBE above ground.
(Remember that the V
old is deliberately set at a V

pin control node switching thresh-

C

plus

BE

several hundred
millivolts.) When this condition is removed, a nominal
40µA current acts to charge up the SFST node towards
roughly 3V. So, for example, a 0.1µF soft-start capacitor
will place a 0.4V/ms limit on the ramp rate at the V

node.

C

UVLO PIN FUNCTION

The UVLO pin effects an undervoltage lockout function
with at threshold of roughly 1.25V. An external resistor
divider between the input supply and ground can then be
used to achieve a user-programmable undervoltage lock­out (see Figure 6a).

An additional feature of this pin is that there is a change in
the input bias current at this pin as a function of the state
of the internal UVLO comparator. As the pin is brought
above the UVLO threshold, the bias current sourced by the
part increases. This positive feedback effects a hysteresis
band for reliable switching action. Note that the size of the
hysteresis is proportional to the Thevenin impedance of
the external UVLO resistor divider network, which makes
it user programmable. As a rough rule of thumb, each 4k
or so of impedance generates about 1% of hysteresis.
(This is based on roughly 1.25V for the threshold and 3µA
for the bias current shift.)

Even in good quality ground plane layouts, it is common
for the switching node (MOSFET drain) to couple to the
UVLO pin with a stray capacitance of several

thousandths

of a pF. To ensure proper UVLO action, a 100pF capacitor
is recommended from this pin to ground as shown in
Figure 6b. This will typically reduce the coupled noise to
a few millivolts. The UVLO filter capacitor should not be
made much larger than a few hundred pF, however, as the
hysteresis action will become too slow. In cases where
further filtering is required, e.g., to attenuate high speed
supply ripple, the topology in Figure 6c is recommended.
Resistor R1 has been split into two equal parts. This
provides a node for effecting capacitor filtering of high

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LT1725

V

IN

V

IN

R1

UVLO

R2

(6a) “Standard” UVLO
Divider Topology

(6b) Filter Capacitor
Directly On UVLO Node

C1
100pF

V

IN

R1

R2

Figure 6

speed supply ripple, while leaving the UVLO pin node
impedance relatively unchanged at high frequency.

INTERNAL WIDE HYSTERESIS
UNDERVOLTAGE LOCKOUT

The LT1725 is designed to implement isolated DC/DC
converters operating from input voltages of typically 48V
or more. The standard operating topology utilizes a third
transformer winding on the primary side that provides
both feedback information and local power for the LT1725
via its V

pin. However, this arrangement is not inherently

CC

self-starting. Start-up is effected by the use of an external
“trickle-charge” resistor and the presence of an internal
wide hysteresis undervoltage lockout circuit that monitors
V

pin voltage (see Figure 7). Operation is as follows:

CC

“Trickle charge” resistor R1 is connected to V

IN

and
supplies a small current, typically on the order of a single
mA, to charge C1. At first, the LT1725 is off and draws only
its start-up current. After some time, the voltage on C1

) reaches the VCC turn-on threshold. The LT1725 then

(V

CC

turns on abruptly and draws its normal supply current.
Switching action commences at the GATE pin and the
MOSFET begins to deliver power. The voltage on C1
begins to decline as the LT1725 draws its normal supply
current, which greatly exceeds that delivered by R1. After
some time, typically tens of milliseconds, the output
voltage approaches its desired value. By this time, the
third transformer winding is providing virtually all the
supply current required by the LT1725.

One potential design pitfall is undersizing the value of
capacitor C1. In this case, the normal supply current

R1/2

C2

R1/2

UVLO

C1
100pF

UVLO

R2

1725 F06

(6c) Recommended Topology to
Filter High Frequency Ripple

V

IN

R1

+

C1

PGND SGND

V

THRESHOLD

ON

I

VCC

V

CC

LT1725 GATE

V

VCC

I

VCC

0

V

GATE

V

IN

1725 F07

Figure 7

drawn by the LT1725 will discharge C1 too rapidly; before
the third winding drive becomes effective, the VCC turn-off
threshold will be reached. The LT1725 turns off, and the
VCC node begins to charge via R1 back up to the turn-on
threshold. Depending upon the particular situation, this
may result in either several on-off cycles before proper
operation is reached, or, permanent relaxation oscillation
at the VCC node.

Component selection is as follows:

Resistor R1 should be selected to yield a worst-case
minimum charging current greater than the maximum
rated LT1725 start-up current, and a worst-case maxi­mum charging current less than the minimum rated
LT1725 supply current.

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Capacitor C1 should then be made large enough to avoid
the relaxation oscillatory behavior described above. This
is complicated to determine theoretically as it depends on
the particulars of the secondary circuit and load behavior.
Empirical testing is recommended. (Use of the optional
soft-start function will lengthen the power-up timing and
require a correspondingly larger value for C1.)

A further note—certain users may wish to utilize the
general functionality of the LT1725, but may have an
available input voltage significantly lower than, say, 48V.
If this input voltage is within the allowable V
perhaps 20V maximum, the internal wide hysteresis range
UVLO function becomes counterproductive. In such cases
it is simply better to operate the LT1725 directly from the
available DC input supply. The LT1737 is identical to the
LT1725, with the exception that it lacks the internal wide
hysteresis UVLO function. It is therefore designed to
operate directly from DC input supplies in the range of

4.5V to 20V. See the LT1737 data sheet for further
information.

FREQUENCY COMPENSATION

Loop frequency compensation is performed by connect­ing a capacitor from the output of the error amplifier (V
pin) to ground. An additional series resistor, often re­quired in traditional current mode switcher controllers, is
usually not required and can even prove detrimental. The
phase margin improvement traditionally offered by this
extra resistor will usually be already accomplished by the
nonzero secondary circuit impedance, which adds a “zero”
to the loop response.

In further contrast to traditional current mode switchers,
VC pin ripple is generally not an issue with the LT1725. The
dynamic nature of the clamped feedback amplifier forms
an effective track/hold type response, whereby the V
voltage changes during the flyback pulse, but is then “held”
during the subsequent “switch on” portion of the next
cycle. This action naturally holds the V
during the current comparator sense action (current mode
switching).

range, i.e.,

CC

voltage stable

C

C

C

OUTPUT VOLTAGE ERROR SOURCES

Conventional nonisolated switching power supply ICs
typically have only two substantial sources of output
voltage error: the internal or external resistor divider
network that connects to V
ence. The LT1725, which senses the output voltage in both
a dynamic and an isolated manner, exhibits additional
potential error sources to contend with. Some of these
errors are proportional to output voltage, others are fixed
in an absolute millivolt sense. Here is a list of possible
error sources and their effective contribution.

Internal Voltage Reference

The internal bandgap voltage reference is, of course,
imperfect. Its error, both at 25°C and over temperature is
already included in the specifications.

User Programming Resistors

Output voltage is controlled by the user-supplied feedback
resistor divider ratio. To the extent that the resistor ratio
differs from the ideal value, the output voltage will be
proportionally affected. Highest accuracy systems will
demand 1% components.

Schottky Diode Drop

The LT1725 senses the output voltage from the trans­former primary side during the flyback portion of the cycle.
This sensed voltage therefore includes the forward drop,
VF, of the rectifier (usually a Schottky diode). The nominal

of this diode should therefore be included in feedback

V

F

resistor divider calculations. Lot to lot and ambient tem­perature variations will show up as output voltage shift/
drift.

Secondary Leakage Inductance

Leakage inductance on the transformer secondary re­duces the effective secondary-to-third winding turns ratio
(N
voltage target by a similar percentage. To the extent that
secondary leakage inductance is constant from part to
part, this can be accommodated by adjusting the feedback
resistor ratio.

) from its ideal value. This will increase the output

S/NT

and the internal IC refer-

OUT

18

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LT1725

Output Impedance Error

An additional error source is caused by transformer sec­ondary current flow through the real life nonzero imped­ances of the output rectifier, transformer secondary and
output capacitor. Because the secondary current only
flows during the off portion of the duty cycle, the effective
output impedance equals the “DC” lumped secondary
impedance times the inverse of the off duty cycle. If the
output load current remains relatively constant, or, in less
critical applications, the error may be judged acceptable
and the feedback resistor divider ratio adjusted for nomi­nal expected error. In more demanding applications, out­put impedance error may be minimized by the use of the
load compensation function (see Load Compensation).

MINIMUM LOAD CONSIDERATIONS

The LT1725 generally provides better low load perfor­mance than previous generation switcher/controllers uti­lizing indirect output voltage sensing techniques.
Specifically, it contains circuitry to detect flyback pulse
“collapse,” thereby supporting operation well into discon­tinuous mode. Nevertheless, there still remain constraints
to ultimate low load operation. These relate to the mini­mum switch on time and the minimum enable time.
Discontinuous mode operation will be assumed in the
following theoretical derivations.

f = switching frequency

= transformer primary side inductance

L

PRI

VIN = input voltage
V

= output voltage

OUT

tON = output switch minimum on time

An additional constraint has to do with the minimum
enable time. The LT1725 derives its output voltage infor­mation from the flyback pulse. If the internal minimum
enable time pulse extends beyond the flyback pulse, loss
of regulation will occur. The onset of this condition can be
determined by setting the width of the flyback pulse equal
to the sum of the flyback enable delay, t
minimum enable time, t
the load is then:

Minimum Power

Which yields a minimum output constraint:

⎛

1

fV

I

OUT MIN

f = switching frequency

=

⎜

2

⎝

. Minimum power delivered to

EN

⎞

⎛

f

1

=

⎜

L

2

⎝

VI

=

OUT OUT

OUT

SEC

⎞
⎟

⎠

•
L

Vtt

OUT EN ED

[]

⎟
⎠

SEC

•

2

+

tt

ED EN()

()

, plus the

ED

2

+

•

()

where

As outlined in the Operation section, the LT1725 utilizes a
minimum output switch on time, t
combined with expected V
yield an expression for minimum delivered power.

Minimum Power

This expression then yields a minimum output current
constraint:

I

OUT MIN

=

=

⎛

1

⎜

2

LV

⎝

PRI OUT

and switching frequency to

IN

⎛

1

f

⎜
⎝

2

L

PRI

VI

•

OUT OUT

⎞

f

•

⎟
⎠

. This value can be

ON

⎞

Vt

()

⎟

IN ON

⎠

•=

Vt

IN ON()

()

2

•

2

where

L

= transformer secondary side inductance

SEC

V

= output voltage

OUT

t

= enable delay time

ED

tEN = minimum enable time

Note that generally, depending on the particulars of input
and output voltages and transformer inductance, one of
the above constraints will prove more restrictive. In other
words, the minimum load current in a particular applica­tion will be either “output switch minimum on time”
constrained, or “minimum flyback pulse time” constrained.
(A final note—L
tance as seen from the primary or secondary side respec­tively. This general treatment allows these expressions to
be used when the transformer turns ratio is nonunity.)

PRI

and L

refer to transformer induc-

SEC

1725fa

19

LT1725

WUUU

APPLICATIO S I FOR ATIO

MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS

The LT1725 is a current mode controller. It uses the V

C

node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the V

C

node, nominally 2.5V, then acts as an output switch peak
current limit.

This 2.5V at the V
at the I

SENSE

pin corresponds to a value of 250mV

C

pin, when the (ON) switch duty cycle is less
than 40%. For a duty cycle above 40%, the internal slope
compensation mechanism lowers the effective I

SENSE

voltage limit. For example, at a duty cycle of 80%, the
nominal I

voltage limit is 220mV. This action be-

SENSE

comes the switch current limit specification. Maximum
available output power is then determined by the switch
current limit, which is somewhat duty cycle dependent
due to internal slope compensation action.

Overcurrent conditions are handled by the same mecha­nism. The output switch turns on, the peak current is
quickly reached and the switch is turned off. Because the
output switch is only on for a small fraction of the available
period, power dissipation is controlled.

Loss of current limit is possible under certain conditions.
Remember that the LT1725 normally exhibits a minimum
switch on time, irrespective of current trip point. If the duty
cycle exhibited by this minimum on time is greater than the
ratio of secondary winding voltage (referred-to-primary)
divided by input voltage, then peak current will not be
controlled at the nominal value, and will cycle-by-cycle
ratchet up to some higher level. Expressed mathemati­cally, the requirement to maintain short-circuit control is:

+

()

ON

<

•

tf

VI R

F SC SEC

•

VN

•

IN SP

where

tON = output switch minimum on time

= input voltage

V

IN

NSP = secondary-to-primary turns ratio ( N

SEC/NPRI

)

Trouble is typically only encountered in applications with
a relatively high product of input voltage times secondary­to-primary turns ratio and/or a relatively long minimum
switch on time. (Additionally, several real world effects such
as transformer leakage inductance, AC winding losses, and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate.)

THERMAL CONSIDERATIONS

Care should be taken to ensure that the worst-case input
voltage condition does not cause excessive die tempera­tures. The 16-lead SO package is rated at 100°C/W, and
the 16-lead GN at 110°C/W.

Average supply current is simply the sum of quiescent
current given in the specifications section plus gate drive
current. Gate drive current can be computed as:

I

= f • QG where

G

= total gate charge

Q

G

f = switching frequency

(Note: Total gate charge is more complicated than C

GS

• V

G

as it is frequently dominated by Miller effect of the CGD.
Furthermore, both capacitances are nonlinear in practice.
Fortunately, most MOSFET data sheets provide figures
and graphs which yield the total gate charge directly per
operating conditions.) Nearly all gate drive power is dissi­pated in the IC, except for a small amount in the external
gate series resistor, so total IC dissipation may be com­puted as:

P

D(TOTAL)

I

= quiescent current (from specifications)

Q

= VCC (IQ + • f • QG ), where

QG = total gate charge
f = switching frequency
ISC = short-circuit output current
VF = output diode forward voltage at I
R

= resistance of transformer secondary

SEC

20

f = switching frequency

VCC = LT1725 supply voltage

SC

1725fa

WUUU

APPLICATIO S I FOR ATIO

LT1725

SWITCH NODE CONSIDERATIONS

For maximum efficiency, gate drive rise and fall times are
made as short as practical. To prevent radiation and high
frequency resonance problems, proper layout of the
components connected to the IC is essential, especially
the power paths (primary and secondary). B field (mag­netic) radiation is minimized by keeping MOSFET leads,
output diode, and output bypass capacitor leads as short
as possible. E field radiation is kept low by minimizing the
length and area of all similar traces. A ground plane
should always be used under the switcher circuitry to
prevent interplane coupling.

The high speed switching current paths are shown sche­matically in Figure 8. Minimum lead length in these paths
are essential to ensure clean switching and minimal EMI.
The path containing the input capacitor, transformer pri­mary and MOSFET, and the path containing the trans­former secondary, output diode and output capacitor
contain “nanosecond” rise and fall times. Keep these
paths as short as possible.

GATE DRIVE RESISTOR CONSIDERATIONS

The gate drive circuitry internal to the LT1725 has been
designed to have as low an output impedance as practi­cally possible—only a few ohms. A strong L/C resonance
is potentially presented by the inductance of the path
leading to the gate of the power MOSFET and its overall
gate capacitance. For this reason the path from the GATE
package pin to the physical MOSFET gate should be kept
as short as possible, and good layout/ground plane prac­tice used to minimize the parasitic inductance.

An explicit series gate drive resistor may be useful in some
applications to damp out this potential L/C resonance
(typically tens of MHz). A minimum value of perhaps
several ohms is suggested, and higher values (typically a
few tens of ohms) will offer increased damping. However,
as this resistor value becomes too large, gate voltage rise
time will increase to unacceptable levels, and efficiency
will suffer due to the sluggish switching action.

V

CC

+

V

CC

GATE

PGND

Figure 8. High Speed Current Switching Paths

GATE
DISCHARGE
PATH

V

IN

+

+

SECONDARY

POWER

PATH

PRIMARY
POWER
PATH

1725 F08

1725fa

21

LT1725

TYPICAL APPLICATIO S

U

TELECOM 48V TO ISOLATED 15V APPLICATION

The design in Figure 9 accepts an input voltage in the
range of 36V to 72V and outputs an isolated 15V at up to
2A. Transformer T1 is an off-the-shelf VERSA-PAK

TM

#VP5-0155, produced by Coiltronics. As manufactured, it
consists of six ideally identical independent windings. In
this application, three windings are stacked in series on
the primary side and two are placed in parallel on the
secondary side. This arrangement provides a 3:1 primary­to-secondary turns ratio while maximizing overall effi­ciency. The remaining winding provides a primary-side

D5

34.0k
1%

BAS16

R14
820k

R1
24k

+

C10

R3

100pF

R15
33k

C1
22µF

R10
18Ω

V

IN

C2

1.5µF
×3

ground-referred version of the flyback voltage waveform
for both feedback information and providing power to the
LT1725 itself.

Capacitor C7 sets the switching frequency at approxi­mately 200kHz. Optimal load compensation for the trans­former and secondary circuit components is set by resistor
R8. Output voltage regulation and overall efficiency are
shown in the accompanying graphs. The resistor divider
formed by R14 and R15 sets the undervoltage lockout
threshold at about 32V, with a hysteresis band of about 2V.
The soft-start and 3V

VERSA-PAK is a trademark of Coiltronics, Inc

VP5-0155

7

6

R11
150Ω

C3
100pF

3

10

4

9
5

8

D3
1N5257

D4
1N5257

D2

MBRS1100

features are unused as shown.

OUT

T1

•

•

•

••

1122

D1

MBRD660

11

C5

1µF

+

C4
150µF

•

R13
750Ω
1W

V
15V

OUT

3.01k

22

1%

R

OCMP

V

R8

6.2k

15

CC

CMPC

C8

0.1µF

SGNDR

GATE

I

SENSE

PGND

11 1

R12

5.1Ω

16

51Ω

2

R9

C9
470pF

M1
IRF620

R2

0.1Ω

1725 F09a

109

UVLO3V

8

7

R4

C6
1nF

OUT

FB

V

C

6314

C7
47pF

MENAB

ENDLYSFSTOSCAP t

ON

13 12 4 5

R6

R5

51k

51k

LT1725

R7
51k

Figure 9. 48V to Isolated 15V Converter

1725fa

TYPICAL APPLICATIO S

Application Regulation Application Efficiency

LT1725

U

15.5

I

LOAD

VIN = 48V

VIN = 72V

1.5

(A)

2.0

2.5

1725 F09b

(V)

OUT

V

15.0

14.5

VIN = 36V

0.5

0

1.0

48V to Isolated 15V Application Parts List

T1: Coiltronics VP5-0155 VERSA-PAK
M1: International Rectifier IRF620. 200V, 0.8Ω N-channel

MOSFET

D1: Motorola MBRD660. 6A, 60V Schottky diode

D2: Motorola MBRS1100. 1A, 100V Schottky diode

D3, D4: 1N5257. 33V, 500mW Zener diode

D5: BAS16. 75V rectifier diode

C1: AVX TPSD226M025R0200. 22µF, 25V tantalum
capacitor

C2a, C2b, C2c: Vishay/Vitramon VJ1825Y155MXB. 1.5µF,
100V X7R ceramic capacitor

90

VIN = 48V

= 15V

V

OUT

80

70

60

50

EFFICIENCY (%)

40

30

20

0.01

0.1 1 10
I

(A)

LOAD

1725 F09c

C8: 0.1µF, 25V, Z5U ceramic capacitor

C9: 470pF, 25V, X7R ceramic capacitor

C10: 100pF, 25V, X7R ceramic capacitor

R1: 24k, 1/4W, 5% resistor
R2: IRC LR2010. 0.1Ω, 1/2W current sense resistor

R3: 34.0k, 1% resistor

R4: 3.01k, 1% resistor

R5, R6, R7: 51k, 5% resistor

R8: 6.2k, 5% resistor
R9: 51Ω, 5% resistor

C3: 100pF, 100V, X7R ceramic capacitor

C4: Sanyo 20SV150M. 150µF, 20V, OS-CON electrolytic
capacitor

C5: 1µF, 25V, Z5U ceramic capacitor

C6: 1nF, 25V, X7R ceramic capacitor

C7: 47pF, 25V NPO/COG ceramic capacitor

R10: 18Ω, 5% resistor
R11: 150Ω, 1/4W, 5% resistor
R12: 5.1Ω, 5% resistor

R13a, R13b: 1.5k, 1/2W, 5% resistor

R14: 820k, 5% resistor

R15: 33k, 5% resistor

1725fa

23

LT1725

U

TYPICAL APPLICATIO S

TELECOM 48V TO ISOLATED 5V APPLICATION

The design in Figure 10 accepts an input voltage in the
range of 36V to 72V and outputs an isolated 5V at up to 2A.
Transformer T1 is available as a Coiltronics CTX02-14989.
Capacitor C7 sets the switching frequency at approxi­mately 275kHz. Optimal load compensation for the trans­former and secondary circuit components is set by resistor

D2

BAS16

R1

+

LT1725

R7
51k

R

R10
22Ω

C1
15µF

OCMP

R8

2.7k

V

47k

C10
1µF

15

CC

CMPC

C8

0.1µF

35.7k
1%

3.01k
1%

R13
820k

C9

R3

8

FB

7

R4

V

C6
1nF

R14

100pF

33k

UVLO3V

OUT

C

ON

6314

C7
47pF

109

MENAB

ENDLYSFSTOSCAP t

13 12 4 5

R6

R5

51k

51k

R8. Output voltage regulation and overall efficiency are
shown in the accompanying graphs. Efficiency is shown
both with and without the R11 preload. The resistor divider
formed by R13 and R14 sets the undervoltage lockout
threshold at about 32V, with a hysteresis band of about 2V.
The soft-start and 3V

CTX02-14989

V

IN

SGNDR

C2

1.5µF

GATE

I

SENSE

PGND

11 1

R12
68Ω

C4
150pF

16

2

6

1

2

4

features are unused as shown.

OUT

T1

C5

R9

470pF

18Ω

9

11

10

12

M1
IRF620

R2

0.18Ω

1725 F10a

D1

12CWQ06

R11
51Ω
1W

+

C3
150µF

V

OUT

5V

24

(V)

OUT

V

5.25

5.00

4.75

Figure 10. 48V to Isolated 5V Converter

Application Regulation Application Efficiency

90

VIN = 48V

80

70

60

50

EFFICIENCY (%)

40

30

20

0.01

WITHOUT R11

PRELOAD

0.1 1 10
I

LOAD

I

LOAD

1.0

VIN = 48V

(A)

1.5

2.0

1725 F10b

VIN = 36V

VIN = 72V

0

0.5

WITH R11
PRELOAD

(A)

1725 F10c

1725fa

U

TYPICAL APPLICATIO S

48V to Isolated 5V Application Parts List

LT1725

T1: Coiltronics CTX02-14989
M1: International Rectifier IRF620. 200V, 0.8Ω N-channel

MOSFET

D1: International Rectifier 12CWQ06FN. 12A, 60V Schottky
diode

D2: BAS16. 75V switching diode

C1: AVX TPSD156M035R0300. 15µF, 35V tantalum
capacitor

C2: Vishay/Vitramon VJ1825Y155MXB. 1.5µF, 100V, X7R
ceramic capacitor

C3: Sanyo 6SA150M. 150µF, 6.3V, OS-CON electrolytic
capacitor

C4: 150pF, 100V, X7R ceramic capacitor

C5: 470pF, 50V, X7R ceramic capacitor

C6: 1nF, 25V X7R ceramic capacitor

C7: 47pF, 25V, NPO ceramic capacitor

C8: 0.1µF, 25V, Z5U ceramic capacitor

C9: 100pF, 25V, X7R ceramic capacitor

C10: 1µF, 25V, Z5U ceramic capacitor

R1: 47k, 1/4W, 5% resistor
R2: Panasonic type ERJ-14RSJ. 0.18Ω, 1/4W, 5%

resistor

R3: 35.7k, 1% resistor

R4: 3.01k, 1% resistor

R5, R6, R7: 51k, 5% resistor

R8: 2.7k, 5% resistor
R9: 18Ω, 5% resistor
R10: 22Ω, 5% resistor
R11: 51Ω, 1W, 5% resistor
R12: 68Ω, 5% resistor

R13: 820k, 5% resistor

R14: 33k, 5% resistor

1725fa

25

LT1725

PACKAGE DESCRIPTIO

U

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.045 ±.005

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.007 – .0098

(0.178 – 0.249)

.016 – .050

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

(0.406 – 1.270)

INCHES

(MILLIMETERS)

.150 – .165

.0250 BSC.0165 ± .0015

.015 ± .004

(0.38

0° – 8° TYP

± 0.10)

× 45°

.229 – .244

(5.817 – 6.198)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

16

15

12

.189 – .196*

(4.801 – 4.978)

12 11 10

14

13

5

4

3

678

.0250

(0.635)

BSC

.009

(0.229)

9

.150 – .157**
(3.810 – 3.988)

.004 – .0098

(0.102 – 0.249)

GN16 (SSOP) 0204

REF

26

1725fa

PACKAGE DESCRIPTIO

.050 BSC

N

U

S Package

16-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

.386 – .394

.045 ±.005

16

15

(9.804 – 10.008)

13

14

NOTE 3

LT1725

12

11

10

9

.245
MIN

.030 ±.005

TYP

.008 – .010

(0.203 – 0.254)

.160 ±.005

123 N/2

RECOMMENDED SOLDER PAD LAYOUT

.010 – .020

(0.254 – 0.508)

NOTE:

1. DIMENSIONS IN

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

×

°

45

.016 – .050

(0.406 – 1.270)

(MILLIMETERS)

0° – 8° TYP

INCHES

.228 – .244

(5.791 – 6.197)

.053 – .069

(1.346 – 1.752)

.014 – .019

(0.355 – 0.483)

TYP

N

.150 – .157

(3.810 – 3.988)

NOTE 3

N/2

4

5

.050

(1.270)

BSC

3

2

1

7

6

8

.004 – .010

(0.101 – 0.254)

S16 0502

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

1725fa

27

LT1725

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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Synchronization

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LTC3705 2-Switch Forward Controller and Gate Driver 2-Switch Version of LTC3725

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Forward Controller

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Forward Controller

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with Opto Driver and Second Output Synchronous Driver Controller

LTC3806 Synchronous Flyback DC/DC Controller Medium Power, High Efficiency Forced Continuous Operation, 250kHz

LTC3901 Secondary-Side Synchronous Driver for Similar Function to LTC3900, Used in Full-Bridge and Push-Pull Converter

Push-Pull and Full-Bridge Converter

LTC4440/LTC4440-5

28

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

1725fa

LT 1105 REV A • PRINTED IN THE USA

© LINEAR TECHNOLOGY CORPORATION 2000