Datasheet LT1719 Datasheet (Linear Technology)

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Page 1

FEATURES

■

UltraFast: 4.5ns at 20mV Overdrive 7ns at 5mV Overdrive

■

Low Power: 4.2mA at 3V

■

Separate Input and Output Power Supplies

■

Output Optimized for 3V and 5V Supplies

■

Input Voltage Range Extends 100mV Below Negative Rail

■

TTL/CMOS Compatible Rail-to-Rail Output

■

Low Power Shutdown Mode: 0.1µA

APPLICATIO S

■

High Speed Differential Line Receiver

■

Crystal Oscillator Circuits

■

Level Translators

■

Threshold Detectors/Discriminators

■

Zero-Crossing Detectors

■

High Speed Sampling Circuits

■

Delay Lines

LT1719

4.5ns Single/Dual Supply 3V/5V Comparator with

Rail-to-Rail Output

DESCRIPTIO

The LT®1719 is an UltraFastTM comparator optimized for low voltage operation. Separate supplies allow flexible operation to accomodate separate analog input ranges and output logic levels. The input voltage range extends from 100mV below VEE to 1.2V below VCC. Internal hysteresis makes the LT1719 easy to use even with slow moving input signals. The rail-torail outputs directly interface to TTL and CMOS. Alternatively the symmetric output drive can be harnessed for analog applications or for easy translation to other single supply logic levels.

The LT1719 is available in the 8-pin SO package; a shutdown control allows for reduced power consumption and extended battery life in portable applications.

For a dual/quad comparator with similar performance, see the LT1720/LT1721.

, LTC and LT are registered trademarks of Linear Technology Corporation. UltraFast is a trademark of Linear Technology Corporation.

TYPICAL APPLICATION

2.7V to 6V Crystal Oscillator with TTL/CMOS Output

2.7V TO 6V

620Ω

1MHz TO 10MHz

CRYSTAL (AT-CUT)

220Ω

LT1719

–

0.01µF 1.8k

GROUND

CASE

1719 TA01

OUTPUT

Propagation Delay vs Overdrive

RISING EDGE

DELAY (ns)

)

PDLH

FALLING EDGE

10 20 40

OVERDRIVE (mV)

25°C

= 100mV

STEP

= 5V

= 10pF

LOAD

)

PDHL

1719 TA02

Page 2

LT1719

TOP VIEW

OUT SHDN GND

+IN –IN

S8 PACKAGE

8-LEAD PLASTIC SO

–

ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

(Note 1)

Supply Voltage

+VS to GND .......................................................... 7V

VCC to VEE........................................................... 12V

+VS to VEE.......................................................... 12V

VEE to GND .......................................... –12V to 0.3V

Input Current (+IN, – IN or SHDN)..................... ±10mA

Output Current (Continuous) ............................ ±20mA

Operating Temperature Range

= 150°C, θJA = 200°C/ W

JMAX

C Grade .................................................. 0°C to 70°C

I Grade .............................................. –40°C to 85°C

Consult factory for Military grade parts.

Junction Temperature.......................................... 150°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

ELECTRICAL CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, +VS = 5V, VCM = 1V, C V

OVERDRIVE

= 20mV, unless otherwise specified.

The ● denotes specifications that apply over the full operating temperature

= 10pF, V

OUT

ORDER PART

NUMBER

LT1719CS8 LT1719IS8

S8 PART MARKING

1719 1719I

= 0.5V,

SHDN

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

– V

CMR

TRIP

–

TRIP

HYST

∆VOS/∆T Input Offset Voltage Drift ● 10 µV/°C I

CMRR Common Mode Rejection Ratio (Note 4) ● 55 70 dB PSRR Power Supply Rejection Ratio (Note 5) 65 80 dB A

PD20

PD5

SKEW

Input Supply Voltage ● 2.7 10.5 V

Output Supply Voltage ● 2.7 6 V Input Voltage Range (Note 2) ● VEE – 0.1 VCC – 1.2 V Input Trip Points (Note 3) ● –1.5 5.5 mV

● –5.5 1.5 mV

Input Offset Voltage (Note 3) 0.4 2.5 mV

● 3.5 mV

Input Hysteresis Voltage (Note 3) ● 2.0 3.5 7 mV

Input Bias Current ● –6 –2.5 0 µA Input Offset Current ● 0.2 0.6 µA

Voltage Gain (Note 6) ∞ Output High Voltage I Output Low Voltage I Propagation Delay V

Propagation Delay V

Propagation Delay Skew (Note 9) Between t Output Rise Time 10% to 90% 2.5 ns Output Fall Time 90% to 10% 2.2 ns

= 4mA, VIN = V

SOURCE

= 10mA, VIN = V

SINK

OVERDRIVE

= 20mV (Note 7), VEE = 0V 4.5 6.5 ns

= 20mV, VEE = –5V 4.2 ns = 5mV (Notes 7, 8), VEE = 0V 7 10 ns

+ 10mV ● +VS – 0.4 V

TRIP

–

– 10mV ● 0.4 V

TRIP

● 8.0 ns

● 13 ns

–

0.5 1.5 ns

Page 3

LT1719

ELECTRICAL CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, +VS = 5V, VCM = 1V, C V

OVERDRIVE

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

JITTER

MAX

OFF

CCS

EES

CCSO

SSO

EEO

= 20mV, unless otherwise specified.

Output Timing Jitter VIN = 1.2V

Maximum Toggle Frequency V

Turn-Off Delay Time to Z Wake-Up Delay Time to VOH or VOL, I Positive Input Stage Supply Current +VS = VCC = 5V, VEE = –5V ● 1.0 2.2 mA

Negative Input Stage Supply Current +VS = VCC = 5V, VEE = –5V ● –4.8 –2.6 mA

Positive Output Stage Supply Current +VS = VCC = 5V, VEE = –5V ● 4.2 8 mA

Disabled Supply Currents +VS = 6V, VCC = 5V, VEE = –5V ● 0.2 30 µA

The ● denotes specifications that apply over the full operating temperature

= 10pF, V

OUT

(6dBm), ZIN = 50Ω t

f = 20MHz t

+VS = VCC = 3V, VEE = 0V ● 0.9 1.8 mA

+VS = VCC = 3V, VEE = 0V ● –3.8 –2.2 mA

VS = VCC = 3V, VEE = 0V ● 3.3 6 mA

+VS = 6V, VCC = 5V, VEE = –5V ● 0.1 20 µA Shutdown Pin Open ● 0.1 20 µA

P-P

OVERDRIVE OVERDRIVE

SHDN

= 50mV, +VS = 3V 70 MHz = 50mV, +VS = 5V 62.5 MHz

≥10kΩ 75 ns

OUT

= 1mA 350 ns

LOAD

= 5.5V ● 750 µA

–

● –30 –0.2 µA

● –20 0.1 µA

= 0.5V,

SHDN

15 ps 11 ps

RMS RMS

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.

Note 2: If one input is within these common mode limits, the other input can go outside the common mode limits and the output will be valid.

Note 3: The LT1719 comparator includes internal hysteresis. The trip points are the input voltage needed to change the output state in each direction. The offset voltage is defined as the average of V

–

, while the hysteresis voltage is the difference of these two.

TRIP

Note 4: The common mode rejection ratio is measured with VCC = 5V,

= –5V and is defined as the change in offset voltage measured from

= –5.1V to VCM = 3.8V, divided by 8.9V.

Note 5: The power supply rejection ratio is measured with VCM = 1V and is defined as the worst of: the change in offset voltage from VEE = –5V to VEE = 0V divided by 5V, or the change in offset voltage

TRIP

and

UUU

PIN FUNCTIONS

VCC (Pin 1): Positive Supply Voltage for Input Stage. +IN (Pin 2): Noninverting Input of Comparator. –IN (Pin 3): Inverting Input of Comparator. VEE (Pin 4): Negative Supply Voltage for Input Stage and

Chip Substrate.

from VCC = +VS = 2.7V to VCC = +VS = 6V (with VEE = 0V) divided by

3.3V. Note 6: Because of internal hysteresis, there is no small-signal region

in which to measure gain. Proper operation of internal circuity is ensured by measuring V

Note 7: Propagation delay measurements made with 100mV steps. Overdrive is measured relative to V

Note 8: tPD cannot be measured in automatic handling equipment with low values of overdrive. The LT1719 is 100% tested with a 100mV step and 20mV overdrive. Correlation tests have shown that tPD limits can be guaranteed with this test, if additional DC tests are performed to guarantee that all internal bias conditions are correct.

Note 9: Propagation Delay Skew is defined as:

= |t

SKEW

PDLH

– t

and VOL with only 10mV of overdrive.

TRIP

PDHL

GND (Pin 5): Ground. SHDN (Pin 6): Shutdown. Pull to ground to enable

comparator.

OUT (Pin 7): Output of Comparator. +VS (Pin 8): Positive Supply Voltage for Output Stage.

Page 4

LT1719

TEMPERATURE (°C)

–50

3.6

3.8

4.2

25 75

1719 G03

–4.8

–5.0

–25 0

50 100 125

–5.2

–5.4

4.0

COMMON MODE INPUT VOLTAGE (V)

+VS = VCC = 5V V

= –5V

SUPPLY VOLTAGE, VCC = +VS (V)

–3

SUPPLY CURRENT (mA)

1719 G06

–1

–2

SUPPLY VOLTAGE, +VS = VCC (V)

2.5

4.0

3.5

PROPAGATION DELAY (ns)

5.5

5.0 t

TPLH

TPHL

4.5

4.0 5.0

1719 G09

3.0 3.5

4.5 5.5 6.0

25°C V

STEP

= 100mV OVERDRIVE = 20mV C

LOAD

= 10pF

VEE = GND

= –5V

, +VS = 5.5V

MAX

)

TYPICAL PERFORMANCE CHARACTERISTICS

Input Offset and Trip Voltages vs Supply Voltage

–1

AND TRIP POINT VOLTAGE (mV)

25°C

–2

= 1V

= GND

–3

2.5

3.0 3.5 SUPPLY VOLTAGE, VCC = +VS (V)

TRIP

4.5 5.5 6.0

4.0 5.0

Input Current vs Differential Input Voltage

25°C

–1

–2

–3

INPUT BIAS (µA)

–4

–5

–6

–7

–4 –3 –2 –1 0 5

–5

DIFFERENTIAL INPUT VOLTAGE (V)

–

1719 G01

1234

1719 G04

Input Offset and Trip Voltages vs Temperature

–1

AND TRIP POINT VOLTAGE (mV)

+VS = VCC = 5V

–2

–3

= 1V

= GND

–20 20 60 100

TRIP

TEMPERATURE (°C)

Quiescent Supply Current vs Temperature

VCC = +VS = 5V

= GND

–2

SUPPLY CURRENT (mA)

–4

–6

–25 0 50

–50

TEMPERATURE (˚C)

–

75 100 125

Input Common Mode Limits vs Temperature

140–40–60 0 40 80 120

1719 G02

Quiescent Supply Current vs Supply Voltage

1719 G05

Propagation Delay vs Load Capacitance

25°C

= 100mV

STEP

OVERDRIVE = 20mV

= VCC = 5V

= 0V

PROPAGATION DELAY (ns)

10 20 40

OUTPUT LOAD CAPACITANCE (pF)

RISING EDGE

FALLING EDGE

PDLH

PDHL

)

1719 G07

Propagation Delay vs Temperature

8.0 t

PDLH

VCM = 1V

7.5 V

= 100mV

STEP

7.0

6.5

6.0

5.5

5.0

PROPAGATION DELAY (ns)

4.5

4.0

–50

OVERDRIVE = 5mV

OVERDRIVE = 20mV

–25 0 50

TEMPERATURE (°C)

= 10pF

LOAD

= GND

= VCC = 3V

= VCC = 5V

+VS = VCC = 3V

= VCC = 5V

75 100 125

1719 G08

Propagation Delay vs Supply Voltage

Page 5

FREQUENCY (MHz)

NO LOAD

1719 G12

10 20 40

SUPPLY CURRENT (mA)

25°C +V

= 5V

LOAD

= 20pF

LOAD

= 10pF

TYPICAL PERFORMANCE CHARACTERISTICS

LT1719

Output Low Voltage vs Load Current

0.5 +VS = 5V V

= –10mV

0.4

0.3

–55°C

OUTPUT VOLTAGE (V)

0.2

0.1

OUTPUT SINK CURRENT (mA)

125°C

= 2.7V

25°C

Shutdown Currents vs Shutdown Voltage

150

100

SHDN PIN CURRENT (µA)

SUPPLY CURRENT

– 4V) (VS – 3V) (VS – 2V) (VS – 1V) V

SHDN

PIN CURRENT

SHDN PIN VOLTAGE (V)

125°C

1719 G10

1719 G13

5.0

4.5

SUPPLY CURRENT, I

4.0

3.5

3.0

2.5

2.0

+ I

1.5

(mA)

1.0

0.5 0

Output High Voltage vs Load Current

0.0

(V)

125°C

–0.2

25°C

OUTPUT SOURCE CURRENT (mA)

OUTPUT VOLTAGE RELATIVE TO +V

–0.4

–0.6

–0.8

–1.0

Shutdown Currents vs Temperature

SHUTDOWN = +V

SHUTDOWN PIN OPEN

SHUTDOWN CURRENTS (µA)

0.1

–50 25 50 75 100 125–25 0

+VS = 5V V

–55°C

= 2.7V

– 0.5V

TEMPERATURE (°C)

= 10mV

25°C

1719 G11

SHUTDOWN

CURRENT

VCC = +VS = 5V

= –5V

1719 G14

700

600

500

400

300

WAKE-UP DELAY (ns)

200

100

150

Supply Current vs Frequency

Wake-Up Delay vs Temperature

–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

1719 G15

TEST CIRCUITS

–3V

PULSE

50Ω

0.1µF

1N5711

Response Time Test Circuit

–100mV

25Ω

130Ω

2N3866

400Ω

–5V

750Ω

– V

–V

0.01µF

)

VCC – V

25Ω

50k

50Ω

V1*

*V1 = –1000 • (OVERDRIVE + V NOTE: RISING EDGE TEST SHOWN.

FOR FALLING EDGE, REVERSE LT1719 INPUTS

–

VEE – V

DUT

LT1719

TRIP

10 × SCOPE PROBE

≈ 10pF)

1719 TC02

Page 6

LT1719

TEST CIRCUITS

±V

TRIP

Test Circuit

BANDWIDTH-LIMITED TRIANGLE WAVE

1kHz, VCM ±7.5V

0.1µF

50k

50Ω

1/2 LT1638

100k

NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM ±15V.

DUT

LT1719

–

+ –

100k

200kΩ PULL-DOWN PROTECTS LTC203 LOGIC INPUTS WHEN DUT IS NOT POWERED

100k

200k

100k

+ –

1/2 LT1638

2.4k

0.15µF

LTC203

15 3 214

1000 × V

1719 TC01

1µF

–

1/2 LT1112

10k

1000 × V

10k

1000 × V

10nF

10 6 711

2 14 153

10nF

7 11 106

1000 × V

TRIP

HYST

TRIP

–

WUU

APPLICATIONS INFORMATION

Power Supply Configurations

The LT1719 has separate supply pins for the input and output stages that allow flexible operation, accommodating separate voltage ranges for the analog input and the output logic. Of course, a single 3V/5V supply may be used by tying +VS and VCC together as well as GND and VEE.

The minimum voltage requirement can be simply stated as both the output and the input stages need at least 2.7V and the VEE pin must be equal to or less than ground.

The following rules must be adhered to in any configuration:

2.7V ≤ (V

2.7V ≤ (+VS – GND) ≤ 6V (+VS – VEE) ≤ 10.5V VEE ≤ Ground

– VEE) ≤ 10.5V

Although the ground pin need not be tied to system ground, most applications will use it that way. Figure 1 shows three common configurations. The final one is uncommon, but it will work and may be useful as a level translator; the input stage is run from –5.2V and ground while the output stage is run from 3V and ground. In this case the common mode input voltage range does not include ground, so it may be helpful to tie VCC to 3V anyway. Conversely, VCC may also be tied below ground, as long as the above rules are not violated.

Input Voltage Considerations

The LT1719 is specified for a common mode range of –100mV to 3.8V when used with a single 5V supply. A more general consideration is that the common mode range is 100mV below VEE to 1.2V below VCC. The criterion for this common mode limit is that the output still

Page 7

LT1719

WUU

APPLICATIONS INFORMATION

2.7V TO 6V

–

Single Supply

10V

–

10VIN, 5V

GND

OUT

Figure 1. Variety of Power Supply Configurations

Front End Entirely Negative

responds correctly to a small differential input signal. If one input is within the common mode limit, the other input signal can go outside the common mode limits, up to the absolute maximum limits, and the output will retain the correct polarity.

When either input signal falls below the negative common mode limit, the internal PN diode formed with the substrate can turn on, resulting in significant current flow through the die. An external Schottky clamp diode between the input and the negative rail can speed up recovery from negative overdrive by preventing the substrate diode from turning on.

When both input signals are below the negative common mode limit, phase reversal protection circuitry prevents false output inversion to at least –400mV common mode. However, the offset and hysteresis in this mode will increase dramatically, to as much as 15mV each. The input bias currents will also increase.

When both input signals are above the positive common mode limit, the input stage will get debiased and the output polarity will be random. However, the internal hysteresis will hold the output to a valid logic level. When at least one of the inputs returns to within the common mode limits, recovery from this state will take as long as 1µs.

–

–5V

±5VIN, 3V

–

–5.2V

OUT

GND

1719 F01

The input stage is protected against damage from large differential signals, up to and beyond a differential voltage equal to the supply voltage, limited only by the absolute maximum currents noted. External input protection circuitry is only needed if currents would otherwise exceed these absolute maximums. The internal catch diodes can conduct current up to these rated maximums without latchup, even when the supply voltage is at the absolute maximum rating.

The propagation delay does not increase significantly when driven with large differential voltages, but with low levels of overdrive, an apparent increase may be seen with large source resistances due to an RC delay caused by the 2pF typical input capacitance.

Input Bias Current

Input bias current is measured with both inputs held at 1V. As with any PNP differential input stage, the LT1719 bias current flows out of the device. It will go to zero on the higher of the two inputs and double on the lower of the two inputs. With more than two diode drops of differential input voltage, the LT1719’s input protection circuitry activates, and current out of the lower input will increase an additional 30% and there will be a small bias current into the higher of the two input pins, of 4µA or less. See the Typical Performance curve “Input Current vs Differential Input Voltage.”

High Speed Design Considerations

Application of high speed comparators is often plagued by oscillations. The LT1719 has 4mV of internal hysteresis, which will prevent oscillations as long as parasitic output to input feedback is kept below 4mV. However, with the 2V/ns slew rate of the LT1719 outputs, a 4mV step can be created at a 100Ω input source with only 0.02pF of output to input coupling. The LT1719’s pinout has been arranged to minimize problems by placing the sensitive inputs away from the outputs, shielded by the power rails. The input and output traces of the circuit board should also be separated, and the requisite level of isolation is readily achieved if a topside ground plane runs between the output and the inputs. For multilayer boards where the ground plane is internal, a topside ground or supply trace should be run between the inputs and the output.

Page 8

LT1719

WUU

APPLICATIONS INFORMATION

Figure 2 shows a typical topside layout of the LT1719 on such a multilayer board. Shown is the topside metal etch including traces, pin escape vias, and the land pads for an SO-8 LT1719 and its adjacent X7R 10nF bypass capacitors in the 1206 case.

1719 F02

Figure 2. Typical Topside Metal for Multilayer PCB Layouts

The ground trace from Pin 5 runs under the device up to the bypass capacitor, shielding the inputs from the outputs. Note the use of a common via for the LT1719 and the bypass capacitors, which minimizes interference from high frequency energy running around the ground plane or power distribution traces.

The supply bypass should include an adjacent 10nF ceramic capacitor and a 2.2µF tantalum capacitor no farther than 5cm away; use more capacitance on +VS if driving more than 4mA loads. To prevent oscillations, it is helpful to balance the impedance at the inverting and noninverting inputs; source impedances should be kept low, preferably 1kΩ or less.

The outputs of the LT1719 are capable of very high slew rates. To prevent overshoot, ringing and other problems with transmission line effects, keep the output traces shorter than 10cm, or be sure to terminate the lines to maintain signal integrity. The LT1719 can drive DC terminations of 200Ω or more, but lower characteristic impedance traces can be used with series termination or AC termination topologies.

than +VS. Therefore, if driven by a standard TTL gate, a pull-up resistor should be used. Because shutdown is active high, this resistor adds little power drain during shutdown.

For applications that do not use the shutdown feature, it may be helpful to tie the shutdown control to ground through a 100Ω resistor rather than directly. This allows the SHDN pin to be pulled high during debug or in-circuit test (bed of nails) so that the output node can be wiggled without damaging the low impedance output driver of the LT1719.

The shutdown state is not guaranteed to be useful as a multiplexer. Digital signals can have extremely fast edge rates that may be enough to momentarily activate the LT1719 output stage via internal capacitive coupling. No damage to the LT1719 will result, but this could prove deleterious to the intended recipient of the signal.

The LT1719 includes a FET pull-up on the shutdown control pin (see Simplified Schematic) as well as other internal structures to make the shutdown state current drain <<1µA. Shutdown is guaranteed with an open circuit on the shutdown control pin. When the shutdown control pin is driven to +VS – 0.5V, the 70kΩ linear region impedance of the pull-up FET will cause a current flow of 7µA (typ) into the +VS pin and out the shutdown pin. Currents in all other power supply terminals will be <1µA.

Power Supply Sequencing

The LT1719 is designed to tolerate any power supply sequencing at system turn-on and power down. In any of the previously shown power supply configurations, the various supplies can activate in any order without excessive current drain by the LT1719.

Shutdown Control

The LT1719 features a shutdown control pin for reduced quiescent current when the comparator is not needed. During shutdown, the inputs and the outputs become high impedances. The LT1719 is enabled when the shutdown input is pulled low. A logic high disables the comparator. The logic interface is based on the output power rails, + V and GND, with a threshold roughly two diode drops less

As always, the Absolute Maximum Ratings must not be exceeded, either on the power supply terminals or the input terminals. Power supply sequencing problems can occur when input signals are powered from supplies that are independent of the LT1719’s supplies. For the comparator inputs, the signals should be powered from the same VCC and VEE supplies as the LT1719. For the shutdown input, the signal should be powered from the same +VS as the LT1719.

Page 9

LT1719

–

LT1719

INPUT

1719 F04

REF

WUU

APPLICATIONS INFORMATION

Hysteresis

The LT1719 includes internal hysteresis, which makes it easier to use than many other similar speed comparators.

The input-output transfer characteristic is illustrated in Figure 3 showing the definitions of VOS and V upon the two measurable trip points. The hysteresis band makes the LT1719 well behaved, even with slowly moving inputs.

OUT

HYST

–

– V

TRIP

–

HYST

)

TRIP

(= V

TRIP

–

TRIP

+ V

TRIP

Figure 3. Hysteresis I/O Characteristics

∆VIN = V

HYST

1719 F03

– V

based

–

Additional hysteresis may be added externally. The rail-torail outputs of the LT1719 make this more predictable than with TTL output comparators due to the LT1719’s small variability of VOH (output high voltage).

To add additional hysteresis, set up positive feedback by adding additional external resistor R3 as shown in Figure

4. Resistor R3 adds a portion of the output to the threshold set by the resistor string. The LT1719 pulls the outputs to +VS and ground to within 200mV of the rails with light loads, and to within 400mV with heavy loads. For the load of most circuits, a good model for the voltage on the right side of R3 is 300mV or +VS – 300mV, for a total voltage swing of (+VS – 300mV) – (300mV) = +VS – 600mV.

Figure 4. Additional External Hysteresis

With this in mind, calculation of the resistor values needed

The exact amount of hysteresis will vary from part to part as indicated in the specifications table. The hysteresis level will also vary slightly with changes in supply voltage and common mode voltage. A key advantage of the LT1719 is the significant reduction in these effects, which is important whenever an LT1719 is used to detect a threshold crossing in one direction only. In such a case, the relevant trip point will be all that matters, and a stable offset voltage with an unpredictable level of hysteresis, as seen in competing comparators, is useless. The LT1719 is many times better than prior comparators in these regards. In fact, the CMRR and PSRR tests are performed by checking for changes in either trip point to the limits indicated in the specifications table. Because the offset

is a two-step process. First, calculate the value of R3 based on the additional hysteresis desired, the output voltage swing and the impedance of the primary bias string:

R3 = (R1R2)(+VS – 0.6V)/(additional hysteresis)

Additional hysteresis is the desired overall hysteresis less the internal 4mV hysteresis.

The second step is to recalculate R2 to set the same average threshold as before. The average threshold before was set at VTH = (V

)(R1)/(R1 + R2). The new R2 is

REF

calculated based on the average output voltage (+VS/2) and the simplified circuit model in Figure 5. To assure that the comparator’s noninverting input is, on average, the same VTH as before:

voltage is the average of the trip points, the CMRR and PSRR of the offset voltage is therefore guaranteed to be at least as good as those limits. This more stringent test also puts a limit on the common mode and power supply dependence of the hysteresis voltage.

R2′ = (V

For additional hysteresis of 10mV or less, it is not uncommon for R2′ to be the same as R2 within 1% resistor tolerances.

– VTH)/(VTH/R1 + (VTH – VS/2)/R3)

REF

Page 10

LT1719

WUU

APPLICATIONS INFORMATION

REF

R2′

Figure 5. Model for Additional Hysteresis Calculations

This method will work for additional hysteresis of up to a few hundred millivolts. Beyond that, the impedance of R3 is low enough to effect the bias string, and adjustment of R1 may also be required. Note that the currents through the R1/R2 bias string should be many times the input currents of the LT1719. For 5% accuracy, the current must be at least 20 times the input current, more for higher accuracy.

Interfacing the LT1719 to ECL

The LT1719 comparators can be used in high speed applications where Emitter-Coupled Logic (ECL) is deployed. To interface the output of the LT1719 to ECL logic inputs, standard TTL/CMOS to ECL level translators such as the 10H124, 10H424 and 100124 can be used. These components come at a cost of a few nanoseconds additional delay as well as supply currents of 50mA or more, and are only available in quads. A faster, simpler and lower power translator can be constructed with resistors as shown in Figure 6.

Figure 6a shows the standard TTL to Positive ECL (PECL) resistive level translator. This translator cannot be used for the LT1719, or with CMOS logic, because it depends on the 820Ω resistor to limit the output swing (VOH) of the all-NPN TTL gate with its so-called totem-pole output. The LT1719 is fabricated in a complementary bipolar process and the output stage has a PNP driver that pulls the output nearly all the way to the supply rail, even when sourcing 10mA.

Figure 6b shows a three resistor level translator for interfacing the LT1719 to ECL running off the same supply rail. No pull-down on the output of the LT1719 is needed, but pull-down R3 limits the VIH seen by the PECL gate. This is needed because ECL inputs have both a minimum and maximum VIH specification for proper operation. Resistor

LT1719

–

AVERAGE

1719 F05

values are given for both ECL interface types; in both cases it is assumed that the LT1719 operates from the same supply rail.

Figure 6c shows the case of translating to PECL from an LT1719 powered by a 3V supply rail. Again, resistor values are given for both ECL interface types. This time four resistors are needed, although with 10KH/E, R3 is not needed. In that case, the circuit resembles the standard TTL translator of Figure 6a, but the function of the new resistor, R4, is much different. R4 loads the LT1719 output when high so that the current flowing through R1 doesn’t forward bias the LT1719’s internal ESD clamp diode. Although this diode can handle 20mA without damage, normal operation and performance of the output stage can be impaired above 100µA of forward current. R4 prevents this with the minimum additional power dissipation.

Finally, Figure 6d shows the case of driving standard, negative-rail, ECL with the LT1719. Resistor values are given for both ECL interface types and for both a 5V and 3V LT1719 supply rail. Again, a fourth resistor, R4 is needed to prevent the low state current from flowing out of the LT1719, turning on the internal ESD/substrate diodes. Resistor R4 again prevents this with the minimum additional power dissipation.

Of course, if the VEE of the LT1719 is the same as the ECL negative supply, the GND pin can be tied to it as well and +VS grounded. Then the output stage has the same power rails as the ECL and the circuits of Figure 6b can be used.

For all the dividers shown, the output impedance is about 110Ω. This makes these fast, less than a nanosecond, with most layouts. Avoid the temptation to use speedup capacitors. Not only can they foul up the operation of the ECL gate because of overshoots, they can damage the ECL inputs, particularly during power-up of separate supply configurations.

The level translator designs assume one gate load. Multiple gates can have significant IIH loading, and the transmission line routing and termination issues also make this case difficult.

ECL, and particularly PECL, is valuable technology for high speed system design, but it must be used with care. With less than a volt of swing, the noise margins need to be

Page 11

LT1719

WUU

APPLICATIONS INFORMATION

180Ω

LSTTL

(a) STANDARD TTL TO PECL TRANSLATOR

LT1719

(b) LT1719 OUTPUT TO PECL TRANSLATOR

LT1719

270Ω

820Ω

10KH/E

ECL

R3R4

DO NOT USE FOR LT1719 LEVEL TRANSLATION. SEE TEXT

10KH/E

100K/E

10KH/E 100K/E

5V OR 5.2V

4.5V

5V OR 5.2V

4.5V

ECL

510Ω 620Ω

300Ω 330Ω

180Ω 180Ω

750Ω 510Ω

1500Ω

OMIT

560Ω

1000Ω

SVCC

LT1719

(d) LT1719 OUTPUT TO STANDARD ECL TRANSLATOR

ECL

Figure 6

evaluated carefully. Note that there is some degradation of noise margin due to the ±5% resistor selections shown. With 10KH/E, there is no temperature compensation of the logic levels, whereas the LT1719 and the circuits shown give levels that are stable with temperature. This will lower the noise margin over temperature. In some configurations it is possible to add compensation with diode or transistor junctions in series with the resistors of these networks.

For more information on ECL design, refer to the ECLiPS data book (DL140), the 10KH system design handbook (HB205) and PECL design (AN1406), all from Motorola.

ECL FAMILY

10KH/E

100K/E –4.5V

ECL

–5.2V

5V 3V 5V 3V

560Ω 270Ω 680Ω 330Ω

270Ω 510Ω 270Ω 390Ω

330Ω 300Ω 300Ω 270Ω

1200Ω

330Ω

1500Ω

430Ω

1719 F06

Circuit Description

The block diagram of the LT1719 is shown in Figure 7. The circuit topology consists of a differential input stage, a gain stage with hysteresis and a complementary common-emitter output stage. All of the internal signal paths utilize low voltage swings for high speed at low power.

The input stage topology maximizes the input dynamic range available without requiring the power, complexity and die area of two complete input stages such as are found in rail-to-rail input comparators. With a single 2.7V supply, the LT1719 still has a respectable 1.6V of input

Page 12

LT1719

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APPLICATIONS INFORMATION

NONLINEAR STAGE

+IN

–IN

–

SHUTDOWN

common mode range. The differential input voltage range is rail-to-rail, without the large input currents found in competing devices. The input stage also features phase reversal protection to prevent false outputs when the inputs are driven below the –100mV common mode voltage limit.

The internal hysteresis is implemented by positive, nonlinear feedback around a second gain stage. Until this point, the signal path has been entirely differential. The signal path is then split into two drive signals for the upper and lower output transistors. The output transistors are connected common emitter for rail-to-rail output operation. The Schottky clamps limit the output voltages at about 300mV from the rail, not quite the 50mV or 15mV of Linear Technology’s rail-to-rail ampliﬁers and other products. But the output of a comparator is digital, and this output stage can drive TTL or CMOS directly. It can also drive ECL, as described earlier, or analog loads as demonstrated in the applications to follow.

The bias conditions and signal swings in the output stage are designed to turn their respective output transistors off faster than on. This helps minimize the surge of current from + VS to ground that occurs at transitions, to minimize the frequency-dependent increase in power consumption. The frequency dependence of the supply current is shown in the Typical Performance Characteristics.

–

BIAS CONTOL

Figure 7. LT1719 Block Diagram

–

OUT

–

GND

1719 F07

Speed Limits

The LT1719 comparator is intended for high speed applications, where it is important to understand a few limitations. These limitations can roughly be divided into three categories: input speed limits, output speed limits, and internal speed limits.

There are no signiﬁcant input speed limits except the shunt capacitance of the input nodes. If the 2pF typical input nodes are driven, the LT1719 will respond.

The output speed is constrained by two mechanisms, the first of which is the slew currents available from the output transistors. To maintain low power quiescent operation, the LT1719 output transistors are sized to deliver 35mA to 60mA typical slew currents. This is sufﬁcient to drive small capacitive loads and logic gate inputs at extremely high speeds. But the slew rate will slow dramatically with heavy capacitive loads. Because the propagation delay (tPD) deﬁnition ends at the time the output voltage is halfway between the supplies, the ﬁxed slew current makes the LT1719 faster at 3V than 5V with large capacitive loads and sufficient input overdrive.

Another manifestation of this output speed limit is skew, the difference between t

and t

–

. The slew currents of

the LT1719 vary with the process variations of the PNP and NPN transistors, for rising edges and falling edges respectively. The typical 0.5ns skew can have either polarity, rising edge or falling edge faster. Again, the skew will increase dramatically with heavy capacitive loads.

Page 13

LT1719

WUU

APPLICATIONS INFORMATION

A separate output speed limit is the clamp turnaround. The LT1719 output is optimized for fast initial response, with some loss of turnaround speed, limiting the toggle frequency. The output transistors are idled in a low power state once VOH or VOL is reached, by detecting the Schottky clamp action. It is only when the output has slewed from the old voltage to the new voltage, and the clamp circuitry has settled, that the idle state is reached and the LT1719 is fully ready to toggle again. This is typically 8ns for each direction, resulting in a maximum toggle frequency of

62.5MHz. With higher frequencies, dropout and runt pulses can result. Increases in capacitive load will increase the time needed for slewing due to the limited slew currents and the maximum toggle frequency will decrease further. For high toggle frequency applications, consider the LT1394, whose linear output stage can toggle at 100MHz typical.

The internal speed limits manifest themselves as dispersion. All comparators have some degree of dispersion, deﬁned as a change in propagation delay versus input overdrive. The propagation delay of the LT1719 will vary with overdrive, from a typical of 4.5ns at 20mV overdrive to 7ns at 5mV overdrive (typical). The LT1719’s primary source of dispersion is the hysteresis stage. As a change of polarity arrives at the gain stage, the positive feedback of the hysteresis stage subtracts from the overdrive available. Only when enough time has elapsed for a signal to propagate forward through the gain stage, backwards through the hysteresis path and forward through the gain stage again, will the output stage receive the same level of overdrive that it would have received in the absence of hysteresis.

The LT1719 is several hundred picoseconds faster when VEE = –5V, relative to single supply operation. This is due to the internal speed limit; the gain stage operates between VEE and +VS, and it is faster with higher reverse voltage bias due to reduced silicon junction capacitances.

In many applications, as shown in the following examples, there is plenty of input overdrive. Even in applications providing low levels of overdrive, the LT1719 is fast enough that the absolute dispersion of 2.5ns (= 7 – 4.5) is often small enough to ignore.

The gain and hysteresis stage of the LT1719 is simple, short and high speed to help prevent parasitic oscillations while adding minimum dispersion. This internal “self-latch” can be usefully exploited in many applications occurs early in the signal chain, in a low power, fully differential stage. It is therefore highly immune to disturbances from other parts of the circuit, such as the output, or on the supply lines. Once a high speed signal trips the hysteresis, the output will respond, after a ﬁxed propagation delay, without regard to these external inﬂuences that can cause trouble in nonhysteretic comparators.

±V

Test Circuit

TRIP

The input trip points test circuit uses a 1kHz triangle wave to repeatedly trip the comparator being tested. The LT1719 output is used to trigger switched capacitor sampling of the triangle wave, with a sampler for each direction. Because the triangle wave is attenuated 1000:1 and fed to the LT1719’s differential input, the sampled voltages are therefore 1000 times the input trip voltages. The hysteresis and offset are computed from the trip points as shown.

Crystal Oscillator

A simple crystal oscillator using an LT1719 is shown on the first page of this data sheet. The 2k-620Ω resistor pair set a bias point at the comparator’s noninverting input. The 2k-1.8k-0.1µF path sets the inverting input node at an appropriate DC average level based on the output. The crystal’s path provides resonant positive feedback and stable oscillation occurs. Although the LT1719 will give the correct logic output when one input is outside the common mode range, additional delays may occur when it is so operated, opening the possibility of spurious operating modes. Therefore, the DC bias voltages at the inputs are set near the center of the LT1719’s common mode range and the 220Ω resistor attenuates the feedback to the noninverting input. The circuit will operate with any AT-cut crystal from 1MHz to 10MHz over a 2.7V to 6V supply range. As the power is applied, the circuit remains off until the LT1719 bias circuits activate, at a typical V of 2V to 2.2V (25°C), at which point the desired frequency output is generated.

because it

Page 14

LT1719

SI PLIFIED SCHE ATIC

OUTPUT

GND

1719 SS

TO BIAS

SOURCES

15k

SHDN

150Ω

–IN

150Ω

+IN

Page 15

PACKAGE DESCRIPTION

Dimensions in inches (millimeters) unless otherwise noted.

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.189 – 0.197* (4.801 – 5.004)

LT1719

0.228 – 0.244

(5.791 – 6.197)

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0.016 – 0.050

(0.406 – 1.270)

0°– 8° TYP

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

TYP

0.150 – 0.157** (3.810 – 3.988)

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

SO8 1298

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Page 16

LT1719

TYPICAL APPLICATION

High Performance Sine Wave to Square Wave Converter

Propagation delay of comparators is typically specified for a 100mV step with some fraction of that for overdrive. But in many signal processing applications, such as in communications, the goal is to convert a sine wave, such as a carrier, to a square wave for use as a timing clock. The desired behavior is for the output timing to be dependent on the input timing only. No phase shift should occur as a function of the input amplitude, which would result in AM to FM conversion.

The circuit of Figure 8a is a simple LT1719-based sine wave to square wave converter. The ±5V supplies on the input allow very large swing inputs, while the 3V logic supply keeps the output swing small to minimize cross talk. Figure 8b shows the time delay vs input amplitude with a 10MHz sine wave. The LT1719 delay changes just

0.65ns over the 26dB amplitude range; 2.33° at 10MHz. The delay is particularly flat yielding excellent AM rejection

LT1719

–

–5V

SQUARE WAVE

OUTPUT

1719 F08a

SINE WAVE

INPUT

50Ω

Figure 8a. LT1719-Based Sine Wave to Square Wave Converter

from 0dBm to 15dBm. If a 2:1 transformer is used to drive the input differentially, this exceptionally flat zone spans –5dBm to 10dBm, a common range for RF signal levels.

Similar delay performance is achieved with input frequencies as high as 50MHz. There is, however, some additional encroachment into the central flat zone by both the small amplitude and large amplitude variations.

With small input signals, the hysteresis and dispersion make the LT1719 act like a comparator with a 12mV hysteresis span. In other words, a 12mV

sine wave at

P-P

10MHz will barely toggle the LT1719, with 90° of phase lag or 25ns additional delay.

Above 5V

at 10MHz, the LT1719 delay starts to de-

P-P

crease due to internal capacitive feed-forward in the input stage. Unlike some comparators, the LT1719 will not falsely anticipate a change in input polarity, but the feedforward is enough to make a transition propagate through the LT1719 faster once the input polarity does change.

25°C

= 5V

= –5V

= 3V

10MHz

TIME DELAY (ns)

632mV

P-P

–5

P-P

51015

INPUT AMPLITUDE (dBm)

6.32V

P-P

20 25

1719 F08b

Figure 8b. Time Delay vs Sine Wave Input Amplitude

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1016 UltraFast Precision Comparator Industry Standard 10ns Comparator LT1116 12ns Single Supply Ground-Sensing Comparator Single Supply Version of LT1016 LT1394 7ns, UltraFast, Single Supply Comparator 6mA Single Supply Comparator LT1671 60ns, Low Power, Single Supply Comparator 450µA Single Supply Comparator LT1720/LT1721 Dual/Quad 4.5ns, Single Supply 3V/5V Comparator Dual/Quad Comparator Similar to the LT1719

1719f LT/TP 0300 4K • PRINTED IN USA

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