FEATURES
Final Electrical Specifications
LT1641
Positive High Voltage
Hot Swap Controller
August 1999
U
DESCRIPTIO
■
Allows Safe Board Insertion and Removal from a
Live Backplane
■
Controls Supply Voltage from 9V to 80V
■
Programmable Analog Foldback Current Limiting
■
High Side Drive for an External N-Channel
■
Automatic Retry or Latched Operation Mode
■
User Programmable Supply Voltage Power-Up Rate
■
Undervoltage Lockout
■
Overvoltage Protection
U
APPLICATIO S
■
Hot Board Insertion
■
Electronic Circuit Breaker
■
Industrial High Side Switch/Circuit Breaker
■
24V/48V Industrial/Alarm Systems
U
TYPICAL APPLICATIO
The LT®1641 is an 8-pin Hot SwapTM controller that allows
a board to be safely inserted and removed from a live
backplane. Using an external N-channel pass transistor,
the board supply voltage can be ramped up at a programmable rate. A high side switch driver controls an N-channel
gate for supply voltages ranging from 9V to 80V.
The chip features a programmable analog foldback current limit circuit. If the chip remains in current limit for
more than a programmable time, the N-channel pass
transistor latches off and is optionally set to automatically
restart after a time-out delay.
The PWRGD output indicates when the output voltage,
sensed by the FB pin, is within tolerance. The ON pin
provides programmable undervoltage lockout.
The LT1641 is available in the 8-lead SO package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
24V Input Voltage Application
R
S
V
IN
24V
R1
49.9k
1%
R2
3.4k
1%
GND
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
0.01Ω
876
SENSE GATE
V
CC
ON
TIMER
54
C2
0.68µF
IRF530
R5
10Ω
5%
LT1641
Q1
D1
CMPZ
5248B
C1
R6,
10nF
1k, 5%
21
FB
3
PWRGD PWRGD
GND
R3
59k
1%
R4
3.57k
1%
R7
24k
5%
C
1641 TA01
V
OUT
L
1
LT1641
1
2
3
4
8
7
6
5
TOP VIEW
V
CC
SENSE
GATE
TIMER
ON
FB
PWRGD
GND
S8 PACKAGE
8-LEAD PLASTIC SO
WW
W
ABSOLUTE AXI U RATI GS
U
UUW
PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage (VCC) ...............................–0.3V to 100V
Input Voltage (SENSE).............................–0.3V to 100V
Input Voltage (TIMER) ...............................– 0.3V to 44V
Input Voltage (FB, ON)...............................–0.3V to 60V
ORDER PART
NUMBER
LT1641CS8
LT1641IS8
Output Voltage (PWRGD) ........................–0.3V to 100V
Output Voltage (GATE) ............................–0.3V to 100V
Operating Temperature Range
LT1641CS8 ............................................. 0°C to 70°C
LT1641IS8.......................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
T
= 125°C, θJA = 90°C/W
JMAX
S8 PART
MARKING
1641
1641I
Lead Temperature (Soldering, 10 sec).................. 300°C
Consult factory for Military grade parts.
DC ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. Vcc = 24V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
I
CC
V
V
V
V
I
INFB
∆V
V
I
GATEUP
I
GATEDN
∆V
I
TIMERUP
I
TIMERON
V
V
V
I
INON
V
I
OH
2
CC
LKO
FBL
FBL
FBHST
FB
SENSETRIP
GATE
ONH
ONL
ONHYST
OL
VCC Operating Range ● 980V
VCC Supply Current ON = 3V ● 2 5.5 mA
VCC Undervoltage Lockout ● 7.5 8.3 8.8 V
FB Pin High Voltage Threshold FB Low to High Transition ● 1.280 1.313 1.345 V
FB Pin Low Voltage Threshold FB High to Low Transition ● 1.221 1.233 1.245 V
FB Pin Hysteresis Voltage 80 mV
FB Pin Input Current VFB = GND –1 µA
FB Pin Threshold Line Regulation 9V ≤ VCC ≤ 80V ● 0.05 mV/V
SENSE Pin Trip Voltage (VCC – V
GATE Pin Pull-Up Current Charge Pump On, V
GATE Pin Pull-Down Current Any Fault Condition, V
External N-Channel Gate Drive V
TIMER Pin Pull-Up Current ● –40 –80 –120 µA
TIMER Pin Pull-Down Current ● 1.5 3 4.5 µA
ON Pin High Threshold ON Low to High Transition ● 1.280 1.313 1.345 V
ON Pin Low Threshold ON High to Low Transition ● 1.221 1.233 1.245 V
ON Pin Hysteresis 80 mV
ON Pin Input Current VON = GND –1 µA
PWRGD Output Low Voltage IO = 2mA ● 0.4 V
PWRGD Pin Leakage Current V
)VFB = 0V ● 51216 mV
SENSE
= 1V ● 42 47 52 mV
V
FB
GATE
V
= 20V to 80V ● 10 18 V
CC
= 5mA ● 0.8 V
I
O
PWRGD
The ● denotes the specifications which apply over the full operating
= 7V ● –5 –10 –20 µA
GATE
= 2V ● 50 70 90 mA
GATE
– VCC, VCC = 10.8V to 20V ● 4.5 18 V
= 80V ● 10 µA
LT1641
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
PHLON
t
PLHON
t
PHLFB
t
PLHFB
t
PHLSENSE
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
ON Low to GATE Low Figures 1, 2 6 µs
ON High to GATE High Figures 1, 2 1.7 µs
FB Low to PWRGD Low Figures 1, 3 3.2 µs
FB High to PWRGD High Figures 1, 3 1.5 µs
(VCC – SENSE) High to GATE Low Figures 1, 4 0.5 1 2 µs
TA = 25°C, VCC = 24V
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
UUU
PI FU CTIO S
ON (Pin 1): The ON pin is used to implement undervoltage
lockout. When the ON pin is pulled below the 1.233V Highto-Low threshold voltage, an undervoltage condition is
detected and the GATE pin is pulled low to turn the
MOSFET off. When the ON pin rises above the 1.313V
Low-to-High threshold voltage, the MOSFET is turned on
again.
Pulsing the ON pin low after a current limit fault will reset
the fault latch and allow the part to turn back on.
FB (Pin 2): “Power Good” Comparator Input. It monitors
the output voltage with an external resistive divider. When
the voltage on the FB pin is lower than the High-to-Low
threshold of 1.233V, the PWRGD pin is pulled low and
released when the FB pin is pulled above the 1.313V Lowto-High threshold.
The FB pin also effects foldback current limit (see Figure␣ 7
and related discussion).
PWRGD (Pin 3): Open Collector Output to GND. The
PWRGD pin is pulled low whenever the voltage at the FB
pin falls below the High-to-Low threshold voltage. It goes
into a high impedance state when the voltage on the FB pin
exceeds the Low-to-High threshold voltage. An external
pull-up resistor can pull the pin to a voltage higher or lower
than VCC.
GND (Pin 4): Chip Ground.
current source starts to charge the timing capacitor. When
the voltage on the TIMER pin reaches 1.233V, the GATE
pin is pulled low; the pull-up current will be turned off and
the capacitor is discharged by a 3µA pull-down current.
When the TIMER pin falls below 0.5V, the GATE pin turns
on once the ON pin is pulsed low to reset the internal fault
latch. If the ON pin is not cycled low, the GATE pin remains
latched off.
By connecting a 0.01µF capacitor from the GATE pin to the
center tap of a resistive divider at the ON pin, the part
automatically restarts after a current limit fault. With a
short at the output, the part cycles on and off with a 3.75%
on-time duty cycle.
GATE (Pin 6): The High Side Gate Drive for the External
N-Channel. An internal charge pump guarantees at least
10V of gate drive for supply voltages above 20V and 4.5V
gate drive for supply voltages between 9V and 20V. The
rising slope of the voltage at the GATE is set by an external
capacitor connected from the GATE pin to GND and an
internal 10µA pull-up current source from the charge
pump output.
When the current limit is reached, the GATE pin voltage will
be adjusted to maintain a constant voltage across the
sense resistor while the timer capacitor starts to charge.
If the TIMER pin voltage exceeds 1.233V, the GATE pin will
be pulled low.
TIMER (Pin 5): Timing Input. An external timing capacitor
at this pin programs the maximum time the part is allowed
to remain in current limit.
When the part goes into current limit, an 80µA pull-up
The GATE pin is pulled to GND whenever the ON pin is
pulled low, the VCC supply voltage drops below the 8.3V
undervoltage lockout threshold or the TIMER pin rises
above 1.233V.
3
LT1641
UUU
PI FU CTIO S
SENSE (Pin 7): The Current Limit Sense Pin. A sense
resistor must be placed in the supply path between V
CC
and SENSE. The current limit circuit will regulate the
voltage across the sense resistor (VCC – V
SENSE
) to 47mV
when VFB is 0.5V or higher. If VFB drops below 0.5V, the
voltage across the sense resistor decreases linearly and
stops at 12mV when VFB is 0V.
To defeat current limit, short the SENSE pin to the VCC pin.
W
BLOCK DIAGRA
V
CC
V
GEN
0.5V
P
+
–
+
V
P
FB
REF GEN
1.233V
SENSE
–
12mV ~ 47mV
+
VCC (Pin 8): The Positive Supply Input ranges from 9V to
80V for normal operation. ICC is typically 2mA. An internal
undervoltage lockout circuit disables the chip for inputs
less than 8.3V. Place a 0.1µF bypass capacitor next to the
VCC pin.
CHARGE
PUMP
1.233V
AND
GATE
+
–
DRIVER
GATE
PWRGD
4
V
8.3V
0.5V
ON
CC
1.233V
–
–
+
+
–
+
–
UNDERVOLTAGE LOCKOUT
LOGIC
V
GND
P
80µA
TIMER
3µA
1641 BD
TEST CIRCUIT
LT1641
WUW
TI I G DIAGRA S
ON
GATE
1.313V
5V
t
PLHON
ON
FB
+
V
5V
PWRGD
5k
GND
V
SENSE
GATE
TIMER
1641 F01
CC
10nF
+
24V
–
Figure 1
1.233V
1V
t
PHLON
1641 F02
PWRGD
FB
1.313V
1V
t
PLHFB
1.233V
1V
t
PHLFB
1641 F03
Figure 2. ON to GATE Timing
VCC – SENSE
GATE
47mV
t
PHLSENSE
V
CC
Figure 4. SENSE to GATE Timing
Figure 3. FB to PWRGD Timing
1641 F04
5
LT1641
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WUU
APPLICATIO S I FOR ATIO
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the boards draw high peak
currents from the backplane power bus as they charge up.
The transient currents can permanently damage the connector pins and glitch the system supply, causing other
boards in the system to reset.
The LT1641 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
also provides undervoltage and overcurrent protection
while a power good output signal indicates when the
output supply voltage is ready.
Power-Up Sequence
The power supply on a board is controlled by placing an
external N-channel pass transistor (Q1) in the power path
(Figure 5). Resistor RS provides current detection and
capacitor C1 provides control of the GATE slew rate.
Resistor R6 provides current control loop compensation
while R5 prevents high frequency oscillations in Q1.
Resistors R1 and R2 provide undervoltage sensing.
After the power pins first make contact, transistor Q1 is
turned off. If the voltage at the ON pin exceeds the turn-on
threshold voltage, the voltage on the VCC pin exceeds the
undervoltage lockout threshold, and the voltage on the
TIMER pin is less than 1.233V, transistor Q1 will be turned
on (Figure 6). The voltage at the GATE pin rises with a slope
equal to 10µA/C1 and the supply inrush current is set at
I
INRUSH
= CL • 10µA/C1. If the voltage across the current
sense resistor RS gets too high, the inrush current will then
be limited by the internal current limit circuitry which
adjusts the voltage on the GATE pin to maintain a constant
voltage across the sense resistor.
Once the voltage at the output has reached its final value,
as sensed by resistors R3 and R4, the PWRGD pin goes
high.
V
24V
GND
IN
49.9k
1%
3.4k
1%
R
S
0.025Ω
R1
876
V
SENSE GATE
CC
ON
R2
TIMER
54
C2
0.68µF
IRF530
R5
10Ω
5%
LT1641
Q1
D1
CMPZ
5248B
C1
R6,
10nF
1k, 5%
21
FB
3
PWRGD PWRGD
GND
R3
59k
1%
R4
3.57k
1%
+
R7
24k
5%
C
1641 F05
V
OUT
L
FIgure 5. Typical Application Figure 6. Power-Up Waveforms
6
LT1641
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WUU
APPLICATIO S I FOR ATIO
Short-Circuit Protection
The LT1641 features a programmable foldback current
limit with an electronic circuit breaker that protects against
short-circuits or excessive supply currents. The current
limit is set by placing a sense resistor between VCC (Pin 8)
and SENSE (Pin 7).
To prevent excessive power dissipation in the pass transistor and to prevent voltage spikes on the input supply
during short-circuit conditions at the output, the current
folds back as a function of the output voltage, which is
sensed at the FB pin (Figure 7).
When the voltage at the FB pin is 0V, the current limit
circuit drives the GATE pin to force a constant 12mV drop
across the sense resistor. As the output voltage at the FB
pin increases, the voltage across the sense resistor increases until the FB pin reaches 0.5V, at which point the
voltage across the sense resistor is held constant at 47mV.
The maximum current limit is calculated as:
I
= 47mV/R
LIMIT
SENSE
For a 0.025Ω sense resistor, the current limit is set at
1.88A and folds back to 480mA when the output is shorted
to ground.
The LT1641 also features a variable overcurrent response
time. The time required for the chip to regulate the GATE
pin (Pin 6) voltage is a function of the voltage across the
sense resistor connected between the VCC pin (Pin 8) and
the SENSE pin (Pin 7). The larger the voltage, the faster the
gate will be regulated. Figure 8 shows the response time
as a function of overdrive at the SENSE pin.
V
– V
CC
SENSE
47mV
12mV
0V 0.5V V
Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage
1641 F07
FB
12µs
10µs
8µs
6µs
4µs
2µs
RESPONSE TIME
50mV 100mV 150mV 200mV
Figure 8. Response Time to Overcurrent
V
– V
CC
SENSE
1641 F08
7
LT1641
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WUU
APPLICATIO S I FOR ATIO
TIMER
The TIMER pin (Pin 5) provides a method for programming the maximum time the chip is allowed to operate in
current limit. When the current limit circuitry is not active,
the TIMER pin is pulled to GND by a 3µA current source.
After the current limit circuit becomes active, an 80µA pull-
up current source is connected to the TIMER pin and the
voltage will rise with a slope equal to 77µA/C
as the current limit circuit remains active. Once the desired
maximum current limit time is set, the capacitor value is:
C(nF) = 62 • t(ms).
If the current limit circuit turns off, the TIMER pin will be
discharged to GND by the 3µA current source.
TIMER
as long
Whenever the TIMER pin reaches 1.233V, the internal fault
latch is set. The GATE pin is immediately pulled to GND and
the TIMER pin is pulled back to GND by the 3µA current
source. The part is not allowed to turn on again until the
voltage at the TIMER pin falls below 0.5V. The fault latch
is cleared by pulling the ON pin low.
The waveform in Figure 9 shows how the output latches off
following a short-circuit. The drop across the sense resistor is held at 12mV as the timer ramps up. Since the output
did not rise bringing FB above 0.5V, the circuit latches off.
Automatic Restart
To force the LT1641 to automatically restart after an
overcurrent fault, the bottom plate of capacitor C1 can be
tied back to the ON pin (Figure 10).
Figure 9. Short-Circuit Waveforms
V
24V
GND
IN
49.9k
1%
3.4k
1%
R
S
0.025Ω
R1
C1
10nF
876
SENSE GATE
V
CC
ON
R2
TIMER
54
C2
0.68µF
IRF530
R5
10Ω
5%
LT1641
Q1
PWRGD PWRGD
GND
Figure 10. Automatic Restart Application
D1
CMPZ
5248B
FB
V
OUT
C
R7
24k
5%
L
1641 F10
R3
59k
1%
21
R4
3.57k
1%
3
8
LT1641
U
WUU
APPLICATIO S I FOR ATIO
When an overcurrent condition occurs, the GATE pin is
driven to maintain a constant voltage across the sense
resistor. The capacitor C2 at the TIMER pin will begin to
charge. When the voltage at the TIMER pin reaches
1.233V, the GATE pin is immediately pulled to GND and
transistor Q1 turns off. Capacitor C1 momentarily pulses
the ON pin low and clears the internal fault latch. When the
voltage at the TIMER pin ramps back down to 0.5V, the
LT1641 turns on again. If the short-circuit condition at the
output still exists, the cycle will repeat itself indefinitely
with a 3.75% on-time duty cycle which prevents Q1 from
overheating. The waveforms are shown in Figure 11.
After the TIMER pin is pulled higher than 1.233V, the fault
latch is set and the GATE pin is pulled to GND immediately,
turning off transistor Q1. The waveforms are shown in
Figure 13. Operation is restored either by interrupting
power or by pulsing ON low.
V
24V
GND
IN
49.9k
1%
3.4k
1%
R
0.025Ω
R1
D1
30V
1N5256B
R2
876
V
CC
ON
TIMER
54
C2
0.68µF
S
IRF530
R5
10Ω
5%
SENSE GATE
LT1641
Q1
D1
CMPZ
5248B
C1
R6,
10nF
1k, 5%
21
FB
3
PWRGD PWRGD
GND
R3
59k
1%
R4
3.57k
1%
+
R7
24k
5%
C
1641 F12
V
OUT
L
Figure 11. Automatic Restart Waveforms
Undervoltage and Overvoltage Detection
The ON pin can be used to detect an undervoltage condition at the power supply input. The ON pin is internally
connected to an analog comparator with 80mV of hysteresis. If the ON pin falls below its threshold voltage (1.233V),
the GATE pin is pulled low and is held low until ON is high
again.
Figure 12 shows an overvoltage detection circuit. When
the input voltage exceeds the Zener diode’s breakdown
voltage, D1 turns on and starts to pull the TIMER pin high.
Figure 12. Overvoltage Detection
Figure 13. Overvoltage Waveforms
9
LT1641
U
WUU
APPLICATIO S I FOR ATIO
Power Good Detection
The LT1641 includes a comparator for monitoring the
output voltage. The noninverting input (FB pin) is compared against an internal 1.233V precision reference and
exhibits 80mV hysteresis. The comparator’s output
(PWRGD pin) is an open collector capable of operating
from a pull-up as high as 100V.
The PWRGD pin can be used to directly enable/disable a
power module with an active high enable input. Figure 14
shows how to use the PWRGD pin to control an active low
enable input power module. Signal inversion is accomplished by transistor Q2 and R7.
Supply Transient Protection
The LT1641 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 100V. However,
spikes above 100V may damage the part. During a shortcircuit condition, the large change in currents flowing
through the power supply traces can cause inductive
voltage spikes which could exceed 100V. To minimize the
spikes, the power trace parasitic inductance should be
minimized by using wider traces or heavier trace plating
and a 0.1µF bypass capacitor placed between VCC and
GND. A surge suppressor at the input can also prevent
damage from voltage surges.
V
IN
48V
294k
UV = 37V
10.2k
GND
1%
1%
R
S
0.01Ω
R1
876
V
SENSE GATE
CC
ON
R2
TIMER
54
C2
0.68µF
IRF530
R5
10Ω
5%
LT1641
Q1
GND
R6,
1k, 5%
10nF
PWRGD
D1
CMPZ
5248B
C1
FB
R3
143k
1%
21
R4
4.22k
1%
3
MMBT5551LT1
R7
47k
5%
Q2
ACTIVE LOW
ENABLE MODULE
+
C
220µF
VIN+
L
ON/OFF
VIN–
+
V
OUT
V
OUT
V
–
OUT
1641 F14
Figure 14. Active Low Enable Module
10
LT1641
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APPLICATIO S I FOR ATIO
GATE Pin Voltage
A curve of gate drive vs VCC is shown in Figure 15. The
GATE pin is clamped to a maximum voltage of 18V above
the input voltage. At minimum input supply voltage of 9V,
the minimum gate drive voltage is 4.5V. When the input
supply voltage is higher than 20V, the gate drive voltage is
at least 10V and a regular N-FET can be used. In applications ranges 9V to 24V range, a logic level N-FET must be
used with a proper protection Zener diode between its gate
and source (as D1 shown is Figure 5).
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is recommended. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance
of about 530µΩ/ . Small resistances add up quickly in
high current applications. To make the system immune to
noise, the resistor divider to the ON pin needs to be close
to the chip and keep traces to VCC and GND short. A 0.1µF
capacitor from the ON pin to GND also helps reject induced
noise. Figure 16 shows a layout that addresses these
issues.
18
16
14
12
(V)
CC
10
– V
8
GATE
V
6
4
2
0
8
13 18 23
VCC (V)
1641 F15
Figure 15. Gate Drive vs Supply Voltage
I
LOAD
SENSE
RESISTOR, R
CC
LT1641
R1
R2
V
ON
I
LOAD
SENSE
GND
1541 F16
Figure 16. Recommended Layout for R1, R2 and R
S
S
11
LT1641
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
8
5
6
0.228 – 0.244
(5.791 – 6.197)
0.010 – 0.020
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
× 45°
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.150 – 0.157**
(3.810 – 3.988)
1
3
2
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
SO8 1298
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1640 Negative High Voltage Hot Swap Controller Controls an N-FET at Negative Side to –80V
LTC1421 Dual Channel Hot Swap Controller Operates Two Supplies from 3V to 12V and a Third to –12V
LTC1422 High Side Drive Hot Swap Controller in SO-8 System Reset Output with Programmable Delay
LTC1643 PCI Hot Swap Controller 3.3V, 5V, 12V, –12V Supplies for PCI Bus
LTC1642 Fault Protected Hot Swap Controller Operates from 3V to 16.5V, Handles Surges to 33V
1641is sn1641 LT/TP 0899 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1999
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
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