Page 1
FEATURES
Final Electrical Specifications
LT1469
Dual 90MHz, 22V/µs
16-Bit Accurate Operational Amplifier
February 2000
U
DESCRIPTIO
■
90MHz Gain Bandwidth, f = 100kHz
■
Maximum Input Offset Voltage: 125µV
■
Settling Time: 900ns (A
■
22V/µs Slew Rate
■
Low Distortion: –96.5dB for 100kHz, 10V
■
Maximum Input Offset Voltage Drift: 3µV/°C
■
Maximum Inverting Input Bias Current: 10nA
■
Minimum DC Gain: 300V/mV
■
Minimum Output Swing into 2k: ±12.8V
■
Unity-Gain Stable
■
Input Noise Voltage: 5nV/√Hz
■
Input Noise Current: 0.6pA/√Hz
■
Total Input Noise Optimized for 1kΩ < RS < 20kΩ
■
Specified at ±5V and ±15V Supplies
= –1, 150µV, 10V Step)
V
P-P
U
APPLICATIO S
■
Precision Instrumentation
■
High Accuracy Data Acquisition Systems
■
16-Bit DAC Current-to-Voltage Converter
■
ADC Buffer
■
Low Distortion Active Filters
■
Photodiode Amplifiers
The LT®1469 is a dual, precision high speed operational
amplifier with 16-bit accuracy and 900ns settling to 150µV
for 10V signals. This unique blend of precision and AC
performance makes the LT1469 the optimum choice for
high accuracy applications such as DAC current-to-voltage conversion and ADC buffers. The initial accuracy and
drift characteristics of the input offset voltage and inverting input bias current are tailored for inverting applications.
The 90MHz gain bandwidth ensures high open-loop gain
at frequency for reducing distortion. In noninverting applications such as an ADC buffer, the low distortion and DC
accuracy allow full 16-bit AC and DC performance.
The 22V/µs slew rate of the LT1469 improves large signal
performance compared to other precision op amps in
applications such as active filters and instrumentation
amplifiers.
The LT1469 is manufactured on Linear Technology’s
complementary bipolar process and is available in 8-pin
PDIP and SO packages. A single version,the LT1468, is
also available.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
U
16-Bit Accurate Single Ended to Differential ADC Buffer
+
1/2 LT1469
–
V
IN
2k
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
10pF
2k
–
1/2 LT1469
+
200Ω
300pF
300pF
200Ω
+IN
LTC1604
–IN
1469 TA01
16 BITS
333ksps
1
Page 2
LT1469
1
2
3
4
8
7
6
5
TOP VIEW
V
+
OUT B
–IN B
+IN B
OUT A
–IN A
+IN A
V
–
S8 PACKAGE
8-LEAD PLASTIC SO
A
B
WW
W
ABSOLUTE AXI U RATI GS
U
UUW
PACKAGE/ORDER I FOR ATIO
(Note 1)
Total Supply Voltage (V+ to V–) .............................. 36V
Input Current (Note 2) ........................................ ±10mA
Output Short-Circuit Duration (Note 3)............ Indefinite
Operating Temperature Range (Note 4) .. –40°C to 85°C
Specified Temperature Range (Note 5)... –40°C to 85°C
Maximum Junction Temperature .......................... 150°C
ORDER PART
NUMBER
LT1469CS8
LT1469IS8
LT1469CN8
LT1469IN8
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
JMAX
T
= 150°C, θJA = 190°C/W (S8)
JMAX
S8 PART MARKING
T
= 150°C, θJA = 130°C/W (N8)
1469
1469I
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS V
V
OS
I
OS
IB– Inverting Input Bias Current ±5V to ±15V 3 ±10 nA
IB+ Noninverting Input Bias Current ±5V to ±15V –10 ±40 nA
e
n
i
n
R
IN
C
IN
V
CM
CMRR Common Mode Rejection Ratio VCM = ±12.5V ±15V 96 110 dB
PSRR Power Supply Rejection Ratio VS = ±4.5V to ±15V 100 112 dB
A
VOL
V
OUT
I
OUT
I
SC
2
Input Offset Voltage ±15V 30 125 µV
Input Offset Current ±5V to ±15V 13 ±50 nA
Input Noise Voltage Density f = 10kHz ±5V to ±15V 5 nV/√Hz
Input Noise Current Density f = 10kHz ±5V to ±15V 0.6 pA/√Hz
Input Resistance VCM = ±12.5V ±15V 100 240 MΩ
Differential ±15V 50 150 kΩ
Input Capacitance ±15V 4 pF
Input Voltage Range (Positive) ±15V 12.5 13.5 V
Input Voltage Range (Negative) ±15V –14.3 –12.5 V
V
= ±2.5V ±5V 96 112 dB
CM
Minimum Supply Voltage Guaranteed by PSRR ±2.5 ±4.5 V
Large-Signal Voltage Gain V
Maximum Output Swing RL = 10k, 1mV Overdrive ±15V ±13 ±13.6 V
Maximum Output Current V
Output Short-Circuit Current V
= ±12.5V, RL = 10k ±15V 300 9000 V/mV
OUT
= ±12.5V, RL = 2k ±15V 300 5000 V/mV
V
OUT
= ±2.5V, RL = 10k ±5V 200 6000 V/mV
V
OUT
V
= ±2.5V, RL = 2k ±5V 200 3000 V/mV
OUT
R
= 2k, 1mV Overdrive ±15V ±12.8 ±13.5 V
L
= 10k, 1mV Overdrive ±5V ±3 ±3.6 V
R
L
= 2k, 1mV Overdrive ±5V ±2.8 ±3.5 V
R
L
= ±12.5V, 1mV Overdrive ±15V ±15 ±22 mA
OUT
V
= ±2.5V, 1mV Overdrive ±5V ±15 ±22 mA
OUT
= 0V, 0.2V Overdrive (Note 3) ±15V ±25 ±40 mA
OUT
T
= 25°C, V
A
= 0V unless otherwise noted.
CM
SUPPLY
±5V 50 200 µV
±5V 2.5 3.5 V
±5V –4.3 –2.5 V
MIN TYP MAX UNITS
Page 3
LT1469
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS V
SR Slew Rate AV = –10, RL = 2k (Note 6) ±15V 15 22 V/µs
FPBW Full-Power Bandwidth 10V Peak, (Note 7) ±15V 350 kHz
3V Peak, (Note 7) ±5V 900 kHz
GBW Gain Bandwidth Product f = 100kHz, RL = 2k ±15V 60 90 MHz
tr, t
OS Overshoot AV = 1, 0.1V ±15V 30 %
t
PD
t
S
THD Total Harmonic Distortion AV = 1, 10V
R
OUT
I
S
∆V
∆IB– Inverting Input Bias Current Match ±5V to ±15V ±18 nA
∆IB+ Noninverting Input Bias Current Match ±5V to ±15V ±78 nA
∆CMRR Common Mode Rejection Match VCM = ±12.5V (Note 9) ±15V 93 dB
∆PSRR Power Supply Rejection Match VS = ±4.5V to ±15V (Note 9) 97 dB
Rise Time, Fall Time AV = 1, 10% to 90%, 0.1V ±15V 11 ns
f
Propagation Delay AV = 1, 50% VIN to 50% V
Settling Time 10V Step, 0.01%, AV = –1 ±15V 760 ns
10V Step, 150µV, A
5V Step, 0.01%, A
Output Resistance AV = 1, f = 100kHz ±15V 0.02 Ω
Channel Separation V
Supply Current Per Amplifier ±15V 4.1 5.2 mA
Input Offset Voltage Match ±15V 225 µV
OS
= ±12.5V, RL = 2k ±15V 100 120 dB
OUT
= ±2.5V, RL = 2k ±5V 100 120 dB
V
OUT
= ±2.5V (Note 9) ±5V 93 dB
V
CM
T
= 25°C, V
A
= –1 ±15V 900 ns
V
= –1 ±5V 770 ns
V
, 100kHz ±15V – 96.5 dB
P-P
= 0V unless otherwise noted.
CM
SUPPLY
±5V 11 17 V/µs
±5V 55 88 MHz
±5V 12 ns
±5V 35 %
, 0.1V ±15V 9 ns
OUT
±5V 10 ns
±5V 3.8 5 mA
±5V 350 µV
MIN TYP MAX UNITS
The ● denotes the specifications which apply over the temperature range 0°C ≤ TA ≤ 70°C, V
SYMBOL PARAMETER CONDITIONS V
V
OS
∆VOS/∆T Input Offset Voltage Drift (Note 8) ±5V to ±15V ● 13µV/°C
I
OS
∆IOS/∆T Input Offset Current Drift (Note 8) ±5V to ±15V ● 60 pA/°C
IB– Inverting Input Bias Current ±5V to ±15V ● ±20 nA
∆IB–/∆T Inverting Input Bias Current Drift (Note 8) ±5V to ±15V ● 40 pA/°C
IB+ Noninverting Input Bias Current ±5V to ±15V ● ±60 nA
V
CM
CMRR Common Mode Rejection Ratio VCM = ±12.5V ±15V ● 94 dB
Input Offset Voltage ±15V ● 350 µV
Input Offset Current ±5V to ±15V ● ±80 nA
Input Voltage Range (Positive) ±15V ● 12.5 V
Input Voltage Range (Negative) ±15V ● –12.5 V
= ±2.5V ±5V ● 94 dB
V
CM
SUPPLY
= 0V unless otherwise noted.
CM
MIN TYP MAX UNITS
±5V
±5V
±5V
● 350 µV
● 2.5 V
● –2.5 V
3
Page 4
LT1469
ELECTRICAL CHARACTERISTICS
0°C ≤ TA ≤ 70°C, V
SYMBOL PARAMETER CONDITIONS V
= 0V unless otherwise noted.
CM
The ● denotes the specifications which apply over the temperature range
SUPPLY
MIN TYP MAX UNITS
Minimum Supply Voltage Guaranteed by PSRR ● ±4.5 V
PSRR Power Supply Rejection Ratio VS = ±4.5V to ±15V ● 95 dB
A
V
I
I
VOL
OUT
OUT
SC
Large-Signal Voltage Gain V
= ±12.5V, RL = 10k ±15V ● 100 V/mV
OUT
V
= ±12.5V, RL = 2k ±15V ● 100 V/mV
OUT
= ±2.5V, RL = 10k ±5V ● 100 V/mV
V
OUT
= ±2.5V, RL = 2k ±5V ● 100 V/mV
V
OUT
Maximum Output Swing RL = 10k, 1mV Overdrive ±15V ● ±12.9 V
R
= 2k, 1mV Overdrive ±15V ● ±12.7 V
L
= 10k, 1mV Overdrive ±5V ● ±2.9 V
R
L
= 2k, 1mV Overdrive ±5V ● ±2.7 V
R
L
Maximum Output Current V
Output Short-Circuit Current V
= ±12.5V, 1mV Overdrive ±15V ● ±12.5 mA
OUT
= ±2.5V, 1mV Overdrive ±5V ● ±12.5 mA
V
OUT
= 0V, 0.2V Overdrive (Note 3) ±15V ● ±17 mA
OUT
SR Slew Rate AV = –10, RL = 2k (Note 6) ±15V ● 13 V/µs
±5V
● 9V/µs
GBW Gain Bandwidth Product f = 100kHz, RL = 2k ±15V ● 55 MHz
● 50 MHz
● 6.3 mA
● 600 µV
I
∆V
±5V
Channel Separation V
S
Supply Current Per Amplifier ±15V ● 6.5 mA
= ±12.5V, RL = 2k ±15V ● 98 dB
OUT
= ±2.5V, RL = 2k ±5V ● 98 dB
V
OUT
±5V
Input Offset Voltage Match ±15V ● 600 µV
OS
±5V
∆IB– Inverting Input Bias Current Match ±5V to ±15V ● ±38 nA
∆IB+ Noninverting Input Bias Current Match ±5V to ±15V ● ±118 nA
∆CMRR Common Mode Rejection Match VCM = ±12.5V (Note 9) ±15V ● 91 dB
V
= ±2.5V (Note 9) ±5V ● 91 dB
CM
∆PSRR Power Supply Rejection Match VS = ±4.5V to ±15V (Note 9) ● 92 dB
The ● denotes the specifications which apply over the temperature range – 40°C ≤ TA ≤ 85°C, V
= 0V unless otherwise noted.
CM
(Note 5)
SYMBOL PARAMETER CONDITIONS V
V
OS
Input Offset Voltage ±15V ● 500 µV
SUPPLY
±5V
∆VOS/∆T Input Offset Voltage Drift (Note 8) ±5V to ±15V ● 14µV/°C
I
OS
Input Offset Current ±5V to ±15V ● ±120 nA
∆IOS/∆T Input Offset Current Drift (Note 8) ±5V to ±15V ● 120 pA/°C
IB– Inverting Input Bias Current ±5V to ±15V ● ±40 nA
∆IB–/∆T Inverting Input Bias Current Drift (Note 8) ±5V to ±15V ● 80 pA/°C
IB+ Noninverting Input Bias Current ±5V to ±15V ● ±80 nA
V
CM
Input Voltage Range (Positive) ±15V ● 12.5 V
±5V
Input Voltage Range (Negative) ±15V ● –12.5 V
±5V
MIN TYP MAX UNITS
● 500 µV
● 2.5 V
● –2.5 V
4
Page 5
LT1469
ELECTRICAL CHARACTERISTICS
–40°C ≤ TA ≤ 85°C, V
SYMBOL PARAMETER CONDITIONS V
= 0V unless otherwise noted. (Note 5)
CM
The ● denotes the specifications which apply over the temperature range
SUPPLY
MIN TYP MAX UNITS
CMRR Common Mode Rejection Ratio VCM = ±12.5V ±15V ● 92 dB
= ±2.5V ±5V ● 92 dB
V
CM
Minimum Supply Voltage Guaranteed by PSRR ● ±4.5 V
PSRR Power Supply Rejection Ratio VS = ±4.5V to ±15V ● 93 dB
A
V
I
I
VOL
OUT
OUT
SC
Large-Signal Voltage Gain V
= ±12,5V, RL = 10k ±15V ● 75 V/mV
OUT
= ±12.5V, RL = 2k ±15V ● 75 V/mV
V
OUT
= ±2.5V, RL = 10k ±5V ● 75 V/mV
V
OUT
V
= ±2.5V, RL = 2k ±5V ● 75 V/mV
OUT
Maximum Output Swing RL = 10k, 1mV Overdrive ±15V ● ±12.8 V
= 2k, 1mV Overdrive ±15V ● ±12.6 V
R
L
= 10k, 1mV Overdrive ±5V ● ±2.8 V
R
L
R
= 2k, 1mV Overdrive ±5V ● ±2.6 V
L
Maximum Output Current V
Output Short-Circuit Current V
= ±12.5V, 1mV Overdrive ±15V ● ±7mA
OUT
= ±2.5V, 1mV Overdrive ±5V ● ±7mA
V
OUT
= 0V, 0.2V Overdrive (Note 3) ±15V ● ±12 mA
OUT
SR Slew Rate AV = –10, RL = 2k (Note 6) ±15V ● 9V/µs
±5V
● 6V/µs
GBW Gain Bandwidth Product f = 100kHz, RL = 2k ±15V ● 45 MHz
● 40 MHz
● 6.8 mA
● 800 µV
I
∆V
±5V
Channel Separation V
S
Supply Current Per Amplifier ±15V ● 7mA
= ±12.5V, RL = 2k ±15V ● 96 dB
OUT
V
= ±2.5V, RL = 2k ±5V ● 96 dB
OUT
±5V
Input Offset Voltage Match ±15V ● 800 µV
OS
±5V
∆IB– Inverting Input Bias Current Match ±5V to ±15V ● ±78 nA
∆IB+ Noninverting Input Bias Current Match ±5V to ±15V ● ±158 nA
∆CMRR Common Mode Rejection Match VCM = ±12.5V (Note 9) ±15V ● 89 dB
= ±2.5V (Note 9) ±5V ● 89 dB
V
CM
∆PSRR Power Supply Rejection Match VS = ±4.5V to ±15V (Note 9) ● 90 dB
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The inputs are protected by back-to-back diodes and two 100Ω
series resistors. If the differential input voltage exceeds 0.7V, the input
current should be limited to less than 10mA. Input voltages outside the
supplies will be clamped by ESD protection devices and input currents
should also be limited to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum when the output is shorted indefinitely.
Note 4: The LT1469C and LT1469I are guaranteed functional over the
operating temperature range of –40°C to 85°C.
Note 5: The LT1469C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet specified
performance from –40°C to 85°C but is not tested or QA sampled at these
temperatures. The LT1469I is guaranteed to meet specified performance
from –40°C to 85°C.
Note 6: Slew rate is measured between ±8V on the output with ±12V
swing for ±15V supplies and ±2V on the output with ±3V swing for ±5V
supplies.
Note 7: Full-power bandwidth is calculated from the slew rate.
FPBW = SR/2πV
.
P
Note 8: This parameter is not 100% tested.
Note 9: ∆CMRR and ∆PSRR are defined as follows: 1) CMRR and PSRR
are measured in µV/V on each amplifier; 2) the difference between the two
sides is calculated in µV/V; 3) the result is converted to dB.
5
Page 6
LT1469
U
WUU
APPLICATIO S I FOR ATIO
Layout and Passive Components
The LT1469 requires attention to detail in board layout in
order to maximize DC and AC performance. For best AC
results (for example, fast settling time) use a ground
plane, short lead lengths and RF quality bypass capacitors
(0.01µF to 0.1µF) in parallel with low ESR bypass capaci-
tors (1µF to 10µF tantalum). For best DC performance, use
“star” grounding techniques, equalize input trace lengths
and minimize leakage (i.e., 1.5GΩ of leakage between an
input and a 15V supply will generate 10nA—equal to the
maximum IB– specification).
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close to
that of the inputs: for inverting configurations tie the ring
to ground, in noninverting connections tie the ring to the
inverting input (note the input capacitance will increase
which may require a compensating capacitor as discussed
below).
Microvolt level error voltages can also be generated in the
external circuitry. Thermocouple effects caused by temperature gradients across dissimilar metals at the contacts to the inputs can exceed the inherent drift of the
amplifier. Air currents over device leads should be minimized, package leads should be short and the two input
leads should be as close together as possible and maintained at the same temperature.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with
the input capacitance to form a pole which can cause
peaking or even oscillations. For feedback resistors greater
than 2k, a feedback capacitor of value CF > RG • CIN/R
F
should be used to cancel the input pole and optimize
dynamic performance. For applications where the DC
noise gain is one, and a large feedback resistor is used, C
F
should be greater than or equal to CIN. An example would
be a DAC I-to-V converter as shown on the back page of the
data sheet where the DAC can have many tens of picofarads of output capacitance. Another example would be a
gain of –1 with 5k resistors; a 5pF to 10pF capacitor should
be added across the feedback resistor.
6
C
F
R
R
G
C
IN
V
IN
Figure 1. Nulling Input Capacitance
F
–
1/2 LT1469
+
V
OUT
1469 F01
Page 7
LT1469
U
WUU
APPLICATIO S I FOR ATIO
Input Considerations
Each input of the LT1469 is protected with a 100Ω series
resistor and back-to-back diodes across the bases of the
input devices. If large differential input voltages are anticipated, limit the input current to less than 10mA with an
external series resistor. Each input also has two ESD
clamp diodes—one to each supply. If an input is driven
beyond the supply, limit the current with an external
resistor to less than 10mA.
The LT1469 employs bias current cancellation at the
inputs. The inverting input current is trimmed at zero
common mode voltage to minimize errors in inverting
applications such as I-to-V converters. The noninverting
input current is not trimmed and has a wider variation and
therefore a larger maximum value. As the input offset
current can be greater than either input current, the use of
balanced source resistance is NOT recommended as it
actually degrades DC accuracy and also increases noise.
The input bias currents vary with common mode voltage.
The cancellation circuitry was not designed to track this
common mode voltage because the settling time would
have been adversely affected.
The LT1469 inputs can be driven to the negative supply
and to within 0.5V of the positive supply without phase
reversal. As the input moves closer than 0.5V to the
positive supply, the output reverses phase.
Total Input Noise
The total input noise of the LT1469 is optimized for a
source resistance between 1k and 20k. Within this range,
the total input noise is dominated by the noise of the
source resistance itself. When the source resistance is
below 1k, voltage noise of the amplifier dominates. When
the source resistance is above 20k, the input noise current
is the dominant contributor.
R1
100Ω
+IN
Q1
Figure 2. Input Stage Protection
R1
100Ω
Q2
–IN
1469 F02
7
Page 8
LT1469
U
WUU
APPLICATIO S I FOR ATIO
Capacitive Loading
The LT1469 drives capacitive loads of up to 100pF in unitygain and 300pF in a gain of –1. When there is a need to
drive a larger capacitive load, a small series resistor
should be inserted between the output and the load. In
addition, a capacitor should be added between the output
and the inverting input as shown in Figure 3.
Settling Time
The LT1469 is a single stage amplifier with an optimal
thermal layout that leads to outstanding settling performance. Measuring settling, even at the 12-bit level is very
challenging, and at the 16-bit level requires a great deal of
subtlety and expertise. Fortunately, there are two excellent
Linear Technology reference sources for settling measurements—Application Notes 47 and 74. Appendix B of
AN47 is a vital primer on 12-bit settling measurements
and AN74 extends the state-of-the-art while concentrating
on settling time with a 16-bit current output DAC input.
The settling of the DAC I-to-V converter on the back page
was measured using the exact methods of AN74. The
optimum nulling of the DAC output capacitance requires
20pF across the 6k feedback resistor. The theoretical limit
for 16-bit settling is 11.1 times this RC time constant or
1.33µs. The actual settling time is 1.7µs at the output of the
LT1469. The LT1469 is the fastest Linear Technology
amplifier in this application.
The RC output noise filter adds a slight settling time delay
of 100ns but reduces the noise bandwidth to 1.6MHz
which increases the output resolution for 16-bit accuracy.
8
R
F
RO ≥ (1 + RF/RG)/(2π • CL • 5MHz)
≥ 10R
R
F
O
R
O
CF = (2RO/RF)C
R
G
V
IN
C
F
–
1/2 LT1469
+
Figure 3. Driving Capacitive Loads
V
C
L
1469 F03
L
OUT
Page 9
SI PLIFIED
WW
SCHE ATIC
+
V
I4 I6
I3
–
V
LT1469
I2I1
Q8
Q5Q2
Q3
Q6Q1 –IN+IN
Q7
Q4
BIAS
C
I5
Q10
Q9
OUT
Q11
1469 SS
9
Page 10
LT1469
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
876
0.255 ± 0.015*
(6.477 ± 0.381)
5
12
0.300 – 0.325
(7.620 – 8.255)
0.065
(1.651)
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
–0.015
+0.889
8.255
()
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.100
(2.54)
BSC
3
4
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.020
(0.508)
MIN
N8 1098
10
Page 11
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
8
5
6
LT1469
0.228 – 0.244
(5.791 – 6.197)
0.010 – 0.020
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
× 45°
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.053 – 0.069
0.014 – 0.019
(0.355 – 0.483)
TYP
0.150 – 0.157**
(3.810 – 3.988)
1
3
2
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
SO8 1298
11
Page 12
LT1469
TYPICAL APPLICATIO
U
16-Bit DAC I-to-V Converter and Reference Inverter for Bipolar Output Swing (V
REF
= –10V to 10V)
OUT
+
1/2 LT1469
–
15pF
20pF
16 BITS
DAC INPUTS
LTC1597
–
1/2 LT1469
+
2k
V
OUT
50pF
1469 TA03
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1167 Precision Instrumentation Amplifier Single Resistor Gain Set, 0.04% Max Gain Error, 10ppm Max Gain Nonlinearity
LT1468 Single 90MHz, 22V/µs, 16-Bit Accurate Op Amp 75µV Max VOS, Single Version of LT1469
LTC1595/LTC1596 16-Bit Serial Multiplying I
LTC1597 16-Bit Parallel Multiplying I
LT1604 16-Bit, 333ksps Sampling ADC ±2.5V Input, SINAD = 90dB, THD = –100dB
LTC1605 Single 5V, 16-Bit, 100ksps Sampling ADC Low Power, ±10V Inputs, Parallel/Byte Interface
DAC ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
OUT
DAC ±1LSB Max INL/DNL, Low Glitch, On-Chip Bipolar Resistors
OUT
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
1469i LT/TP 0200 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2000
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