Datasheet LT1424-5 Datasheet (Linear Technology)

FEATURES

■

No Transformer “Third Winding” or Optoisolator
Required

■

Designed for Use with 1:1 Ratio Transformers

■

Fixed, Application Specific 5V Output Voltage

■

Regulation Maintained Well into Discontinuous
Mode (Light Load)

■

Load Compensation Provides Excellent
Load Regulation

■

Available in 8-Pin PDIP and SO Packages

■

Operating Frequency: 285kHz

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APPLICATIO S

■

Isolated Communication Supplies

■

Industrial Automation

■

Instrumentation Systems

LT1424-5

Isolated Flyback

Switching Regulator

with 5V Output

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DESCRIPTIO

The LT®1424-5 is a monolithic high power switching
regulator specifically designed for the isolated flyback
topology. No “third winding” or optoisolator is required;
the integrated circuit senses the isolated output voltage
directly from the primary side flyback waveform. A high
current, high efficiency switch is included on the die along
with all oscillator, control and protection circuitry.

The LT1424-5 operates with input supply voltages from
3V to 20V and draws only 7mA quiescent current. It can
deliver up to 400mA at 5V with no external power devices.
By utilizing current mode switching techniques, it pro­vides excellent AC and DC line regulation.

The LT1424-5 has a number of features not found on other
switching regulator ICs. Its unique control circuitry can
maintain regulation well into discontinuous mode. Load
compensation circuitry allows for improved load regula­tion. An externally activated shutdown mode reduces total
supply current to 20µA typical for standby operation.

TYPICAL APPLICATIO

5V Output Isolated Power Supply

5V

+

INPUT

COM

C1
100µF
10V

1000pF

0.1µF

R

CCOMP

V

PGND

8
7

V

IN

6

SW

5

1

SHDN

2

V

C

LT1424-5

3

SYNC

4

SGND

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1N5248

MBR0540T4

0.1µF

C1, C2: AVX TPS D107M010R0080
T1: DALE LPE-4841-A307

47Ω

330pF

ISOLATION

BARRIER

6

•

7

, LTC and LT are registered trademarks of Linear Technology Corporation.

5.25

5.00

OUTPUT VOLTAGE (V)

4.75
0

T1

3

•
1

47Ω

MBRS130LT3

4

•
2

330pF

5V
400mA

+

C2

1.8k

100µF
10V

OUT
COM

1424-5 TA01

Load Regulation

100 200

OUTPUT CURRENT (mA)

300 400

1424-5 TA02

1

LT1424-5

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ABSOLUTE MAXIMUM RATINGS

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PACKAGE/ORDER INFORMATION

(Note 1)

Supply Voltage (VIN)................................................ 20V

Switch Voltage (VSW) .............................................. 35V

SHDN, SYNC Pin Voltage........................................... 7V

Operating Junction Temperature Range

Commercial .......................................... 0°C to 125°C

Industrial ......................................... – 40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

TOP VIEW

1

SHDN

2

V

C

3

SYNC

4

SGND

N8 PACKAGE
8-LEAD PDIP

T

= 145°C, θJA = 130°C/ W (N)

JMAX

T

= 145°C, θJA = 110°C/ W (S)

JMAX

8

R

CCOMP

7

V

IN

6

V

SW

5

PGND

S8 PACKAGE

8-LEAD PLASTIC SO

ORDER PART

NUMBER

LT1424CN8-5
LT1424CS8-5
LT1424IN8-5
LT1424IS8-5

S8 PART MARKING

14245
14245I

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply

V

IN(MIN)

I

CC

Feedback Amplifier

V

REF

g

m

I

SOURCE

V

CL

Output Switch

BV Output Switch Breakdown Voltage IC = 5mA ● 35 50 V
V(VSW) Output Switch ON Voltage ISW = 1A ● 0.55 0.85 V
I

LIM

Current Amplifier

Minimum Operating Voltage ● 2.8 3.1 V
Supply Current ● 7.0 9.5 mA
Shutdown Mode Supply Current ● 15 40 µA
SHDN Pin Threshold ● 0.3 0.9 1.3 V

Reference Voltage Measured at VSW Pin (Note 2) 5.23 5.30 5.37 V

Feedback Amplifier Transconductance ∆IC = ±10µA (Note 3) ● 400 1000 1600 µmho

, I

Feedback Amplifier Source or Sink Current ● 30 50 80 µA

SINK

Feedback Amplifier Clamp Voltage 1.9 V
Reference Voltage/Current Line Regulation 5V ≤ VIN ≤ 18V ● 0.01 0.04 %/V
Voltage Gain (Note 4) 500 V/V

Switch Current Limit Duty Cycle = 50%, 0°C ≤ TJ ≤ 125°C ● 1.35 1.6 1.95 A

Control Pin Threshold Duty Cycle = Minimum 0.95 1.2 1.3 V

Control Voltage to Switch Transconductance 2 A/V

The ● denotes the specifications which apply over the full operating

= 25°C. V

A

Duty Cycle = 50%, –40°C ≤ T
Duty Cycle = 80% 1.3 A

= 5V, VSW Open, VC = 1.4V, unless otherwise specified.

IN

● 5.18 5.30 5.42 V

≤ 125°C ● 1.20 1.6 1.95 A

J

● 0.85 1.2 1.4 V

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2

LT1424-5

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Timing

f Switching Frequency 260 285 300 kHz

t

ON

t

ED

t

EN

Load Compensation

SYNC Function

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be imparied.
Note 2: V

from the output voltage because it accounts for output diode drop,
transformer leakage inductance, etc. Nominal output voltage is 5V in the
intended application circuit.

Minimum Switch ON Time 170 200 260 ns
Flyback Enable Delay Time 150 ns
Minimum Flyback Enable Time 180 ns
Maximum Switch Duty Cycle ● 85 90 %

∆V

/∆I

REF

SW

Minimum SYNC Amplitude ● 1.5 2.2 V
Synchronization Range ● 330 450 kHz
SYNC Pin Input Resistance 40 kΩ

is a parameter which is measured at the VSW pin. It differs

REF

The ● denotes the specifications which apply over the full operating

= 25°C. V

A

= 5V, VSW Open, VC = 1.4V, unless otherwise specified.

IN

● 240 285 320 kHz

0.9 Ω

Note 3: Feedback amplifier transconductance is R
Note 4: Voltage gain is R

referred.

REF

REF

referred.

3

LT1424-5

TEMPERATURE (°C)

–50

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75
25 75

1424-5 G06

–25 0

50 100 125

V

C

PIN VOLTAGE (V)

VC HIGH CLAMP

VC THRESHOLD

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TYPICAL PERFOR A CE CHARACTERISTICS

Switch Saturation Voltage
vs Switch Current

1.2

1.0

0.8

0.6

0.4

0.2

SWITCH SATURATION VOLTAGE (V)

0

0

0.2 0.4
SWITCH CURRENT (A)

0.8 1.2 1.4

0.6 1.0

Reference Voltage
vs Temperature

5.36

5.34

5.32

5.30

4.28

REFERENCE VOLTAGE (V)

4.26

125°C

25°C

–55°C

1424-5 G01

Switch Current Limit
vs Duty Cycle

2.0
TA = 25°C

1.5

1.0

0.5

SWITCH CURRENT LIMIT (A)

0

102030

0

40

DUTY CYCLE (%)

Feedback Amplifier Output
Current vs Flyback Voltage

60

40

20

0

–20

–40

–60

50 60 70 80 90 100

1424-5 G02

25°C
125°C
–55°C

Minimum Input Voltage
vs Temperature

3.1

3.0

2.9

2.8

2.7

INPUT VOLTAGE (V)

2.6

2.5

2.4
–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

VC Pin Threshold and High Clamp
Voltage vs Temperature

1424-5 G03

4.24

SWITCHING FREQUENCY (kHz)

4

–50

–25 0

TEMPERATURE (°C)

Switching Frequency
vs Temperature

300

295

290

285

280

275

270

265

–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

50 100 125

25 75

1424-5 G04

1424-5 G07

FEEDBACK AMPLIFIER OUTPUT CURRENT (µA)

–80

4.50

4.75 5.00
FLYBACK VOLTAGE (V)

5.50 6.00 6.25

5.25 5.75

Minimum Synchronization
Voltage vs Temperature

)

2.50

P-P

2.25

2.00

1.75

1.50

1.25

1.00

MINIMUM SYNCHRONIZATION VOLTAGE (V

0.75
–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

1424-5 G05

1424-5 G08

SHDN Pin Input Current
vs Voltage

1

TA = 25°C

0

–1

–2

–3

SHDN PIN INPUT CURRENT (µA)

–4

1

0

SHDN PIN VOLTAGE (V)

3

4

2

5

1424-5 G09

TEMPERATURE (°C)

–50

200

225

275

25 75

1424-5 G12

175

150

–25 0

50 100 125

125

100

250

ENABLE TIME (ns)

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TYPICAL PERFOR A CE CHARACTERISTICS

LT1424-5

Minimum Switch On Time
vs Temperature

275

250

225

200

175

150

SWITCH ON TIME (ns)

125

100

–50

–25 0

25 75

TEMPERATURE (°C)

50 100 125

1424-5 G10

Flyback Enable Delay Time
vs Temperature

250

225

200

175

150

125

ENABLE DELAY TIME (ns)

100

75

–50

–25 0

25 75

TEMPERATURE (°C)

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PIN FUNCTIONS

SHDN (Pin 1): Shutdown. This pin is used to turn off the
regulator and reduce VIN input current to a few tens of
microamperes. The SHDN pin can be left floating when
unused.

Minimum Flyback Enable Time
vs Temperature

50 100 125

1424-5 G11

PGND (Pin 5): Power Ground. This pin is the emitter of the
power switch device and has large currents flowing through
it. It should be connected directly to a good quality ground
plane.

VC (Pin 2): Control Voltage. This pin is the output of the
feedback amplifier and the input of the current compara­tor. Frequency compensation of the overall loop is effected
by placing a capacitor between this node and ground.

SYNC (Pin 3): Pin to synchronize internal oscillator to
external frequency reference. It is directly logic compat­ible and can be driven with any signal between 10% and
90% duty cycle. If unused, this pin should be tied to
ground.

SGND (Pin 4): Signal Ground. This pin is a clean ground.
The internal reference and feedback amplifier are referred
to it. Keep the ground path connection to the VC compen­sation capacitor free of large ground currents.

VSW (Pin 6): This is the collector node of the output switch
and has large currents flowing through it. Keep the traces
to the switching components as short as possible to
minimize electromagnetic radiation and voltage spikes.

VIN (Pin 7): Supply Voltage. Bypass input supply pin with

10µF or more. The part goes into undervoltage lockout
when VIN drops below 2.8V. Undervoltage lockout stops
switching and pulls the VC pin low.

R

(Pin 8): Pin for the External Filter Capacitor for

CCOMP

Load Compensation Function. A common 0.1µF
ceramic capacitor will suffice.

5

LT1424-5

BLOCK DIAGRAM

V

SHDN

SYNC

2.6V

REGULATOR

285kHz

OSCILLATOR

IN

W

SGND

COMP

FLYBACK

ERROR

AMPLIFIER

COMPENSATION

LOAD

R

FB

R

REF

V

SW

DRIVERLOGIC

R

CCOMP

R

OCOMP

GND IS OMITTED FOR CLARITY

WW

FLYBACK ERROR A PLIFIER DIAGRA

V

IN

V

SW

V

IN

R

D2

FB

Q1

Q2 Q3

•

Q4

V

BG

D1

T1

•

I

M

V

C

+

CURRENT

AMPLIFIER

–

R

SENSE

PGND

1424-5 BD

+

+

C1

ISOLATED

V

OUT

–

I

FXD

V

C

ENABLE

C

EXT

6

R

REF

I

I

M

1424-5 EA

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TI I G DIAGRA

V

SW

VOLTAGE

V

IN

GND

SWITCH

OFF ON

STATE

MINIMUM t

ON

FLYBACK AMP

STATE

ENABLE DELAY

MINIMUM ENABLE TIME

V

FLBK

OFF ON

ENABLEDDISABLED DISABLED

0.80×

V

FLBK

LT1424-5

COLLAPSE
DETECT

1424-5 TD

7

LT1424-5

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OPERATION

The LT1424-5 is a current mode switching regulator IC
that has been designed specifically for the isolated fly­back topology. The special problem normally encoun­tered in such circuits is that information relating to the
output voltage on the isolated secondary side of the
transformer must be communicated to the primary side
in order to maintain regulation. Historically, this has been
done with optoisolators or extra transformer windings.
Optoisolator circuits waste output power and the extra
components they require increase the cost and physical
volume of the power supply. Optoisolators can also
exhibit trouble due to limited dynamic response (tempo­ral), nonlinearity, unit-to-unit variation and aging over
life. Circuits employing extra transformer windings also
exhibit deficiencies. The extra winding adds to the
transformer’s physical size and cost. Dynamic response
is often mediocre. There is usually no method for main­taining load regulation versus load.

The LT1424-5 derives its information about the isolated
output voltage by examining the primary side flyback
pulse waveform. In this manner no optoisolator nor extra
transformer winding is required. This IC is a quantum
improvement over previous approaches because: target
output voltage is programmed by resistor ratio, regula­tion is maintained well into discontinuous mode and
optional load compensation is available.

The Block Diagram shows an overall view of the system.
Many of the blocks are similar to those found in tradi­tional designs including: internal bias regulator, oscilla­tor, logic, current amplifier and comparator, driver and
output switch. The novel sections include a special
flyback error amplifier and a load compensation mecha­nism. Also, due to the special dynamic requirements of
flyback control, the logic system contains additional
functionality not found in conventional designs.

information from the flyback pulse. Due to space con­straints, this discussion will not reiterate the basics of
current mode switcher/controllers and isolated flyback
converters. A good source of information on these topics
is LTC’s Application Note 19.

ERROR AMPLIFIER—PSEUDO DC THEORY

Please refer to the simplified diagram of the Flyback Error
Amplifier. Operation is as follows: when output switch Q4
turns off, its collector voltage rises above the VIN rail. The
amplitude of this flyback pulse, i.e., the difference between
it and VIN, is given as:

+ VF + (I

V

V

FLBK

V

= D1 forward voltage

F

I

SEC

ESR = Total impedance of secondary circuit
N

SP

turns ratio

The flyback voltage is then converted to a current by the
action of RFB and Q1. Nearly all of this current flows
through resistor R
This is then compared to the internal bandgap reference by
the differential transistor pair Q2/Q3. The collector current
from Q2 is mirrored around and subtracted from fixed
current source I
integrates this net current to provide the control voltage to
set the current mode trip point.

The relatively high gain in the overall loop will then cause
the voltage at the R
bandgap reference VBG. The relationship between V
and VBG may then be expressed as:

OUT

=

= Transformer secondary current

= Transformer effective secondary-to-primary

N

to form a ground-referred voltage.

REF

at the VC pin. An external capacitor

FXD

resistor to be nearly equal to the

REF

SP

SEC

)(ESR)

FLBK

The R
are application-specific thin-film resistors internal to the
LT1424-5. The capacitor connected to the R
external.

The LT1424-5 operates much the same as traditional
current mode switchers, the major difference being a
different type of error amplifier which derives its feedback

, RFB and R

REF

resistors in the Block Diagram

OCOMP

CCOMP

pin is

8

V

FLBK

α

R

FB

V

FLBK

α = Ratio of Q1 IC to I
VBG = Internal bandgap reference

V

BG

= or,

R

REF

= V

BG

R

)

R

FB

REF

)

)

α

1

)

E

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OPERATION

LT1424-5

Combination with the previous V
expression for V
programming resistors, transformer turns ratio and diode
forward voltage drop:

V

= V

OUT

Additionally, it includes the effect of nonzero secondary
output impedance. See Load Compensation for details.
The practical aspects of applying this equation for V
found in the Applications Information section.

So far, this has been a pseudo-DC treatment of flyback
error amplifier operation. But the flyback signal is a pulse,
not a DC level. Provision must be made to enable the
flyback amplifier only when the flyback pulse is present.
This is accomplished by the dashed line connections to the
block labeled “ENABLE”. Timing signals are then required
to enable and disable the flyback amplifier.

ERROR AMPLIFIER—DYNAMIC THEORY

There are several timing signals that are required for
proper LT1424-5 operation. Please refer to the Timing
Diagram.

Minimum Output Switch ON Time

The LT1424-5 effects output voltage regulation via flyback
pulse action. If the output switch is not turned on at all,
there will be no flyback pulse, and output voltage informa­tion is no longer available. This would cause irregular loop
response and start-up/latchup problems. The solution
chosen is to require the output switch to be on for an
absolute minimum time per each oscillator cycle. This in
turn establishes a minimum load requirement to maintain
regulation. See Applications Information section for fur­ther details.

Enable Delay

When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans­former primary side voltage waveform approximately rep-

BG

, in terms of the internal reference,

OUT

)

)

N

SP

α

)

R

R

FB

REF

expression yields an

FLBK

– VF – I

)

SEC

(ESR)

OUT

are

resents the output voltage. This is partly due to rise time
on the VSW node, but more importantly due to transformer
leakage inductance. The latter causes a voltage spike on
the primary side not directly related to output voltage.
(Some time is also required for internal settling of the
feedback amplifier circuitry.)

In order to maintain immunity to these phenomena, a fixed
delay is introduced between the switch turn-off command
and the enabling of the feedback amplifier. This is termed
“enable delay”. In certain cases where the leakage spike is
not sufficiently settled by the end of the enable delay
period, regulation error may result. See Applications
Information section for further details.

Collapse Detect

Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, that compares the flyback
voltage (R
80% of VBG. When the flyback waveform drops below this
level, the feedback amplifier is disabled. This action
accommodates both continuous and discontinuous mode
operation.

Minimum Enable Time

The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time”. This prevents lock-up, especially when the output
voltage is abnormally low, e.g., during start-up. The mini­mum enable time period ensures that the VC node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
the low load level at which output voltage regulation is lost.
See Applications Information section for details.

Effects of Variable Enable Period

It should now be clear that the flyback amplifier is enabled
only during a portion of the cycle time. This can vary from
the fixed “minimum enable time” described to a maximum
of roughly the OFF switch time minus the enable delay

referred) to a fixed reference, nominally

REF

9

LT1424-5

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OPERATION

time. Certain parameters of flyback amp behavior will then
be directly affected by the variable enable period. These
include effective transconductance and VC node slew rate.

LOAD COMPENSATION THEORY

The LT1424-5 uses the flyback pulse to obtain information
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,
transformer secondary and output capacitor. This has
been represented previously by the expression (I
However, it is generally more useful to convert this expres­sion to an effective output impedance. Because the sec­ondary current only flows during the off portion of the duty
cycle, the effective output impedance equals the lumped
secondary impedance times the inverse of the OFF duty
cycle. That is,

1

R

= ESR

OUT

= Effective supply output impedance

R

OUT

ESR = Lumped secondary impedance
DC OFF = OFF duty cycle

Expressing this in terms of the ON duty cycle, remember­ing DC OFF = 1 – DC,

R

= ESR

OUT

DC = ON duty cycle

In less critical applications, or if output load current
remains relatively constant, this output impedance error
may be judged acceptable and the external RFB resistor
value adjusted to compensate for nominal expected error.
In more demanding applications, output impedance error
may be minimized by the use of the load compensation
function.

To implement the load compensation function, a voltage
is developed that is proportional to average output switch
current. This voltage is then impressed across the inter­nal R

OCOMP

)

DC OFF

1

)

1 – DC

resistor and the resulting current is then

where,

)

)

SEC

)(ESR).

subtracted from the RFB node. As output loading in­creases, average switch current increases to maintain
rough output voltage regulation. This causes an increase
in R
through which feedback loop action causes a corre­sponding increase in target output voltage.

Assuming a relatively fixed power supply efficiency, Eff

Power Out = (Eff)(Power In)
(V

Average primary side current may be expressed in terms
of output current as follows:

I

IN

combining the efficiency and voltage terms in a single
variable,

I

IN

K1 =

Switch current is converted to voltage by a sense resistor
and amplified by the current sense amplifier with associ­ated gain G. This voltage is then impressed across the
internal R
subtracted from the RFB node. So the effective change in
V

OUT

∆V

∆V

∆I

Nominal output impedance cancellation is obtained by
equating this expression with R

For simplicity, the data sheet refers to ∆V
given as:

∆V

∆I

resistor current subtracted from the R

OCOMP

)(I

OUT

= I

= K1(I

target is:

OUT

OUT

OUT

REF

SW

) = (Eff)(VIN)(IIN)

OUT

V

OUT

)

(VIN)(Eff)

) where,

OUT

V

OUT

)

(VIN)(Eff)

resistor to form a current that is

OCOMP

= K1(∆I

= K1(R

= (R

OUT

SENSE

SENSE

)

)

OUT

)

)(G)

(R

SENSE

)

R

)(G)

)

R

)(G)

OCOMP

R

)

R

OCOMP

OUT

R

FB

OCOMP

FB

.

)

and,

R

FB

)

)

/∆ISW. This is

REF

FB

node,

10

LT1424-5

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APPLICATIONS INFORMATION

The LT1424-X is an application-specific 8-pin part which
implements an isolated flyback switcher/controller. Three
on-chip thin-film resistors are used to “program” the part
for a specific application including mainly desired output
voltage, transformer turns ratio and secondary circuit ESR
behavior. As of Initial Release, two versions of the LT1424
are available. The LT1424-5, described herein, imple­ments an isolated 5V output power supply using off-the­shelf 1:1 transformers as shown in the Typical Applica­tions. The LT1424-9, described in a separate data sheet,
implements an isolated –9V output LAN supply with
PCMCIA Type II height compatible components.

Potential users with a high volume requirement for other
applications are advised as follows: general experimenta­tion/breadboarding may be done with the LT1425. This is
a general purpose 16-pin part whose functionality is
similar to the LT1424-X, with the exception that the three
application resistors are external user-supplied compo­nents. Application information relating to the proper se­lection of these resistor values is contained within the
LT1425 data sheet. Once technical feasibility is demon­strated, the potential user may discuss the possibility of an
additional LT1424-X version with the factory.

Schottky Diode Drop

The LT1424-5 senses the output voltage from the trans­former primary side during the flyback portion of the cycle.
This sensed voltage therefore includes the forward drop,
VF, of the rectifier (usually a Schottky diode). Lot-to-lot
and ambient temperature variations will show up as output
voltage shift/drift.

Secondary Leakage Inductance

Leakage inductance on the transformer secondary reduces
the effective primary-to-secondary turns ratio (NP/NS)
from its ideal value. This increases the output voltage tar­get by a similar percentage and has been nominally taken
into account in the design of the LT1424-5. To the extent
that secondary leakage inductance varies from part-to­part, the output voltage will be affected.

Output Impedance Error

The LT1424-5 contains a load compensation function to
provide a nominal, first-order cancellation of the effects
of secondary circuit ESR. Unit-to-unit variation plus
some inherent nonlinearity in the cancellation results in
some residual V

variation with load.

OUT

OUTPUT VOLTAGE ERROR SOURCES

Conventional nonisolated switching power supply ICs
typically have only two substantial sources of output
voltage error—the internal or external resistor divider
network that connects to V
reference. The LT1424-5, which senses the output voltage
in both a dynamic and an isolated manner, exhibits addi­tional potential error sources to contend with. Some of
these errors are proportional to output voltage, others are
fixed in an absolute millivolt sense. Here is a list of possible
error sources and their effective contribution:

Internal Voltage Reference

The internal bandgap voltage reference is, of course, im­perfect. Its error, both at 25°C and over temperature is al­ready included in the specifications for Reference
Voltage.

and the internal IC

OUT

MINIMUM LOAD CONSIDERATIONS

The LT1424-5 generally provides better low load perfor­mance than previous generation switcher/controllers
utilizing indirect output voltage sensing techniques. Spe­cifically, it contains circuitry to detect flyback pulse
“collapse,” thereby supporting operation well into dis­continuous mode. In general, there are two possible
constraints to ultimate low load operation, minimum
switch ON time which sets a minimum level of delivered
power, and minimum flyback enable time, which deals
with the ability of the feedback system to derive valid
output voltage information from the flyback pulse. In the
application for which the LT1424-5 is designed, the
minimum flyback enable time is more restrictive.

The LT1424-5 derives its output voltage information from
the flyback pulse. If the internal minimum enable time

11

LT1424-5

U

WUU

APPLICATIONS INFORMATION

pulse extends beyond the flyback pulse, loss of regulation
will occur. The onset of this condition can be determined
by setting the width of the flyback pulse equal to the sum
of the flyback enable delay, tED, plus the minimum enable
time, tEN. Minimum power delivered to the load is then:

1

Min Power =

= (V

Which yields a minimum output constraint:

I

OUT(MIN)

f = Switching frequency (nominally 285kHz)
L

= Transformer secondary side inductance

SEC

V

= Output voltage

OUT

t

= Enable delay time

ED

t

= Minimum enable time

EN

=

1

)

2

)

2

)

)

OUT

f(V

)

)

L

L

f

SEC

)(I

OUT

SEC

)

OUT

• (tEN + tED)]

[V

OUT

)

)

(tED + tEN)2, where

)

2

somewhat duty cycle dependent due to internal slope
compensation action.

Short-circuit conditions are handled by the same mecha­nism. The output switch turns on, peak current is quickly
reached and the switch is turned off. Because the output
switch is only on for a small fraction of the available period,
internal power dissipation is controlled. (The LT1424-5
contains an internal overtemperature shutdown circuit,
that disables switch action, just in case.)

THERMAL CONSIDERATIONS

Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause exces­sive die temperatures. The packages are rated at 110°C/W
for SO-8 and 130°C/W for N8.

Average supply current (including driver current) is:

I

I

= 7mA + DC where,

IN

)

SW

35

)

In reality, the previously derived expression is a conserva­tive one, as it assumes perfectly “square” waveforms,
which is not the case at light load. Furthermore, the
equation was set up to yield just the
In other words, while the equation suggests a minimum
load current of perhaps 3mA, laboratory observations
suggest operation down to 1mA to 2mA before significant
output voltage rise is observed. Nevertheless, this situa­tion is addressed in the application by the use of a fixed

1.8k load resistor, which preloads the supply with a
nominal 2.8mA.

MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS

The LT1424-5 is a current mode controller. It uses the V
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the V
node, nominally 1.9V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit, which is

onset

of control error.

C

C

I

= Switch current

SW

DC = On switch duty cycle

Switch power dissipation is given by:

PSW = (ISW)2(RSW)(DC)
RSW = Output switch ON resistance

Total power dissipation of the die is the sum of supply
current times supply voltage plus switch power:

P

D(TOTAL)

FREQUENCY COMPENSATION

Loop frequency compensation is performed by connect­ing a capacitor from the output of the error amplifier (V
pin) to ground. An additional series resistor, often
required in traditional current mode switcher controllers is
usually not required; and can even prove detrimental. The
phase margin improvement traditionally offered by this
extra resistor will usually be already accomplished by the
nonzero secondary circuit impedance, which adds a “zero”
to the loop response.

= (IIN • VIN) + P

SW

C

12

LT1424-5

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WUU

APPLICATIONS INFORMATION

In further contrast to traditional current mode switchers,
VC pin ripple is generally not an issue with the LT1424-5.
The dynamic nature of the clamped feedback amplifier
forms an effective track/hold type response, whereby the
VC voltage changes during the flyback pulse, but is then
“held” during the subsequent “switch ON” portion of the
next cycle. This action naturally holds the VC voltage
stable during the current comparator sense action (cur­rent mode switching).

PCB LAYOUT CONSIDERATIONS

For maximum efficiency, switch rise and fall times are
made as short as practical. To prevent radiation and high
frequency resonance problems, proper layout of the com­ponents connected to the IC is essential, especially the

HIGH

V

IN

FREQUENCY

CIRCULATING

PATH

•

power paths (primary

and

secondary). B field (magnetic)
radiation is minimized by keeping output diode, switch pin
and output bypass capacitor leads as short as possible. E
field radiation is kept low by minimizing the length and
area of all traces connected to the switch pin. A ground
plane should always be used under the switcher circuitry
to prevent interplane coupling.

The high speed switching current paths are shown sche­matically in Figure 1. Minimum lead length in these paths
are essential to ensure clean switching and minimal EMI.
The path containing the input capacitor, transformer pri­mary, output switch, the path containing the transformer
secondary, output diode and output capacitor are the only
ones containing nanosecond rise and fall times. Keep
these paths as short as possible.

V

OUT

•

HIGH

FREQUENCY

CIRCULATING

PATH

ISOLATED

LOAD

F

1424-5 F01

Figure 1

13

LT1424-5

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

N8 Package

8-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

0.400*

(10.160)

MAX

876

0.255 ± 0.015*
(6.477 ± 0.381)

5

12

0.300 – 0.325

(7.620 – 8.255)

0.065

(1.651)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015

+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

TYP

0.100 ± 0.010

(2.540 ± 0.254)

0.045 – 0.065

(1.143 – 1.651)

3

4

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

0.020

(0.508)

MIN

N8 1197

14

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.189 – 0.197*
(4.801 – 5.004)

7

8

5

6

LT1424-5

0.228 – 0.244

(5.791 – 6.197)

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

×

45

0.016 – 0.050

0.406 – 1.270

°

0°– 8° TYP

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

0.150 – 0.157**
(3.810 – 3.988)

1

3

2

4

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

TYP

SO8 0996

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LT1424-5

TYPICAL APPLICATION

5V

+

22µF
35V

INPUT

COM

T1: COILTRONICS CTX02-13835
ER11/5 N = 1:1:1:1:1:1
LP = 27.4µH

0.1µF

1nF

U

Triple Isolated 5V Supply

MBR0530

T1

9

6

•

1

SHDN

2

V

C

LT1424-5

3

SYNC

4

SGND

R

CCOMP

V

V

SW

PGND

8
7

IN

6
5

0.1µF

•

3

12

MBR0530

7

5

•

•

2

10

MBR0530

8

4

•

•

1

11

1N752A

1N752A

1N752A

+

100µF
10V

+

100µF
10V

+

100µF
10V

1k

1k

1k

1424-5 TA03

5V

0.12A

5V

0.12A

5V

0.12A

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14245f LT/TP 0599 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1998

16

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

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