The LT®1381 is a dual RS232 driver/receiver pair with
integral charge pump to generate RS232 voltage levels
from a single 5V supply. The circuit features rugged
bipolar design to provide operating fault tolerance and
ESD protection unmatched by competing CMOS designs.
Using only 0.1µF external capacitors, the circuit con-
sumes only 40mW of power and can operate to 120kbaud
even while driving heavy capacitive loads. New ESD structures on the chip allow the LT1381 to survive multiple
±10kV strikes, eliminating the need for costly TransZorbs
on the RS232 line pins. Driver outputs are protected from
overload and can be shorted to ground or up to ±25V
without damage. During power-off conditions, driver and
receiver outputs are in a high impedance state, allowing
line sharing.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TransZorb® is a registered trademark of General Instruments, GSI
®
LOGIC
INPUTS
LOGIC
OUTPUTS
0.1µF
0.1µF
U
O
A
PPLICATITYPICAL
1
+
3
LT1381
4
+
5
11
10
12
9
16
2
+
6
+
14
7
13
5k
8
S
5k
15
0.1µF
0.1µF
5V INPUT
+
OUT
V
V– OUT
RS232 OUTPUT
RS232 OUTPUT
RS232 INPUT
RS232 INPUT
LT1381 • TA01
DRIVER
OUTPUT
R
C
= 2500pF
L
RECEIVER
OUTPUT
R
= 50pF
C
L
INPUT
= 3k
L
Output Waveforms
LT1381 • TA02
1
Page 2
LT1381
A
S
(Note 1)
W
O
LUTEXI TIS
A
WUW
U
ARB
G
Supply Voltage (VCC) ................................................ 6V
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: Testing done at V
Note 3: Supply current is measured as the average over several charge
pump cycles. C
+
= C– = C1 = C2 = 0.1µF. All outputs are open, with all
= 5V, unless otherwise specified.
CC
driver inputs tied high.
Input High Threshold (V
Output High, I
Sourcing Current, V
Output Transition t
ICS
(Note 2)
= High)0.81.3V
OUT
= Low)1.72.4V
OUT
= –1.6mA●0.20.4V
OUT
= 160µA (VCC = 5V)●3.54.2V
OUT
= V
OUT
CC
= 0V1020mA
OUT
Low-to-High350600ns
LH
–20
–10mA
Note 4: For driver delay measurements, RL = 3k and CL = 51pF. Trigger
points are set between the driver’s input logic threshold and the output
transition to the zero crossing (tHL = 1.4V to 0V and tLH = 1.4V to 0V).
Note 5: For receiver delay measurements, C
= 51pF. Trigger points are
L
set between the receiver’s input logic threshold and the output transition
to standard TTL/CMOS logic threshold (tHL = 1.3V to 2.4V and tLH = 1.7V
to 0.8V).
Note 6: Tested at V
= ±10V.
IN
WU
TYPICAL PERFOR A CE CHARACTERISTICS
Driver Maximum Output Voltage
vs Load Capacitance
9.0
2 DRIVERS LOADED
8.5
8.0
7.5
7.0
6.5
6.0
PEAK OUTPUT VOLTAGE (V)
5.5
5.0
2
1
0
3
LOAD CAPACITANCE (nF)
4
20k BAUD
60k BAUD
120k BAUD
6
5
7
8
9
LT1381 • TPC01
10
Driver Minimum Output Voltage
vs Load CapacitanceDriver Output Voltage
–4.0
2 DRIVERS LOADED
–4.5
–5.0
–5.5
–6.0
PEAK OUTPUT VOLTAGE (V)
–6.5
–7.0
0
2468
LOAD CAPACITANCE (nF)
120k BAUD
60k BAUD
20k BAUD
LT1381 • TPC02
1013579
10
RL = 3k
8
6
4
2
0
–2
–4
–6
DRIVER OUTPUT VOLTAGE (V)
–8
–10
–55
–25
VCC = 5.5V
V
CC
= 4.5V
V
CC
OUTPUT HIGH
OUTPUT LOW
VCC = 4.5V
V
CC
= 5.5V
V
CC
25
0
TEMPERATURE (°C)
= 5V
= 5V
50
75
100
LT1381 • TPC03
125
3
Page 4
LT1381
CAPACITANCE (nF)
0
SLEW RATE (V/µs)
12
16
20
4
LT1381 • TPC09
8
4
0
1
2
3
5
10
14
18
6
2
+SLEW RATE
–SLEW RATE
WU
TYPICAL PERFOR A CE CHARACTERISTICS
Receiver Input Threshold
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
THRESHOLD VOLTAGE (V)
1.00
0.75
0.50
–55
–25
INPUT HIGH
INPUT LOW
0
50
25
TEMPERATURE (°C)
Receiver Short-Circuit Current
50
–
ISC
40
30
+
ISC
20
10
SHORT-CIRCUIT CURRENT (mA)
75
100
LT1381 • TPC04
125
Supply Current vs Data Rate
50
2 DRIVERS ACTIVE
= 3k
R
L
= 2500pF
C
L
40
30
20
SUPPLY CURRENT (mA)
10
0
0
5075100
25
DATA RATE (kBaud)
125150
LT1381 • TPC05
Driver Leakage in Shutdown
100
10
1
LEAKAGE CURRENT (µA)
0.1
–550
–25
TEMPERATURE (°C)
V
V
OUT
50
25
OUT
= –30V
Driver Short-Circuit CurrentSlew Rate vs Load Capacitance
30
25
20
15
10
SHORT-CIRCUIT CURRENT (mA)
5
ISC
ISC
+
–
= 30V
75
100
LT1381 • TPC06
125
0
–55
–25
0
50
25
TEMPERATURE (°C)
75
100
LTLT1381 • TPC07
125
V+ Compliance Curve
10
+
(1µF)
V
8
V+ (0.1µF)
6
(V)
+
V
4
4
2
0
0
510
LOAD CURRENT+ (mA)
0
–55
LT1381 • TPC10
–250
15
50100 125
2575
TEMPERATURE (˚C)
LT1381 • TPC08
V– Compliance Curve
–10
–8
–6
(V)
–
V
–4
–2
0
0
LOAD CURRENT– (mA)
–
(1µF)
V
–
(0.1µF)
V
510
LT1381 • TPC11
15
Page 5
LT1381
LT1381 • ESD TC
0.1µF
RS232
LINE PINS
PROTECTED
TO ±10kV
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
0.1µF
0.1µF
0.1µF
C1
+
V
+
C1
–
C2
+
C2
–
V
–
TR2 OUT
LT1381
0.1µF
5V V
CC
GND
TR1 OUT
REC1 IN
REC1 OUT
TR1 IN
TR2 IN
RS232
LINE PINS
PROTECTED
TO ±10kV
REC2 IN
REC2 OUT
+
+
+
+
+
U
UU
PI FU CTIO S
C1+, C1–, C2+, C2– (Pins 1, 3, 4, 5): Commutating
Capacitor Inputs. These pins require two external capaci-
tors C ≥ 0.1µF: one from C1+ to C1– and another from C2
to C2–. C1 may be deleted if a separate 12V supply is
available and connected to pin C1+.
V+ (Pin 2): Positive Supply Output (RS232 Drivers).
V+ ≈ 2VCC – 2.1V. This pin requires an external charge
storage capacitor C ≥ 0.1µF, tied to ground or VCC. Larger
value capacitors may be used to reduce supply ripple. With
multiple transceivers, the V+ and V– pins may be paralleled
into common capacitors.
V– (Pin 6): Negative Supply Output (RS232 Drivers).
V– ≈ –(2VCC – 3V). This pin requires an external charge
storage capacitor C ≥ 0.1µF. Larger value capacitors may
be used to reduce supply ripple. With multiple transceivers, the V+ and V– pins may be paralleled into common
capacitors.
TR2 OUT, TR1 OUT (Pin 7, 14): Driver Outputs at RS232
Voltage Levels. Driver output swing meets RS232 levels
for loads up to 3k. Slew rates are controlled for lightly
loaded lines. Output current capability is sufficient for
load conditions up to 2500pF. Outputs are in a high
impedance state when VCC = 0V. Outputs are fully shortcircuit protected from V– + 25V to V+ – 25V. Applying
+
higher voltages will not damage the device if the overdrive is moderately current limited. Short circuits on one
output can load the power supply generator and may
disrupt the signal levels of the other outputs. The driver
outputs are protected against ESD to ±10kV for human
body model discharges.
REC2 IN, REC1 IN (Pins 8, 13): Receiver Inputs. These
pins accept RS232 level signals (±30V) into a protected 5k
terminating resistor. The receiver inputs are protected
against ESD to ±10kV for human body model discharges.
Each receiver provides 0.4V of hysteresis for noise immunity. Open receiver inputs assume a logic low state.
REC2 OUT, REC1 OUT (Pins 9, 12): Receiver Outputs with
TTL/CMOS Voltage Levels. Outputs are fully short-circuit
protected to ground or VCC with the power ON or OFF.
TR2 IN, TR1 IN (Pins 10, 11): RS232 Driver Input Pins.
These inputs are TTL/CMOS compatible. Inputs should
not be allowed to float. Tie unused inputs to VCC.
GND (Pin 15): Ground Pin.
VCC (Pin 16): 5V Input Supply Pin. This pin should be
decoupled with a 0.1µF ceramic capacitor close to the
package pin. Insufficient supply bypassing can result in
low output drive levels and erratic charge pump operation.
U
ESD PROTECTIO
The RS232 line inputs of the LT1381 have on-chip protection from ESD transients up to ±10kV. The protection
structures act to divert the static discharge safely to
system ground. In order for the ESD protection to function
effectively, the power supply and ground pins of the circuit
must be connected to ground through low impedances.
The power supply decoupling capacitors and charge pump
storage capacitors provide this low impedance in normal
application of the circuit. The only constraint is that low
ESR capacitors must be used for bypassing and charge
storage. ESD testing must be done with pins VCC, V+, V
and GND shorted to ground or connected with low ESR
capacitors.
ESD Test Circuit
–
5
Page 6
LT1381
U
TYPICAL APPLICATIO S
Isolated RS232 Driver/Receiver
= 5V
V
IN
±10% FROM
SYSTEM
+
ISOLATOR OUTPUT
(DATA TO SYSTEM)
ISOLATOR INPUT
(DATA FROM SYSTEM)
100µF
I
LIM
GND
V
V
V
CC
OUT
OS
GND2
IN
IN
GND1
ISOLATION BARRIER
47Ω
LT1111
LTC1145
LTC1145
V
IN
SW1
SW2
GND1
V
CC
OS
GND2
1:1
L1
20µH
1N5818
1N5818
1Ω
+
100µF
13.7V
10k
+
1µF
1k
1
+
0.1µF
LT1381
RS232
3
0.1µF
16
2
V
CC
LT1121-5
+
10µF
5V ±10%
CTX20-1
FB
IN
+
4
0.1µF
+
0.1µF
FLOATING GROUND
SYSTEM GROUND
5
98
1114
D
X
6
0.1µF
+
R
X
RS232 INPUT
RS232 OUTPUT
15
LT1381 • TA03
6
ISOLATOR
INPUT
RS232
OUTPUT
Data Transmission Across Isolation Barrier
RS232
INPUT
ISOLATOR
OUTPUT
1381 TA041381 TA05
Page 7
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
12
13
4
11
6
5
0.255 ± 0.015*
(6.477 ± 0.381)
14
15
16
2
1
3
LT1381
910
8
7
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
–0.015
+0.889
8.255
()
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.020
(0.508)
MIN
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
16
0.228 – 0.244
(5.791 – 6.197)
15
0.045 – 0.065
(1.143 – 1.651)
0.386 – 0.394*
(9.804 – 10.008)
13
14
0.065
(1.651)
TYP
0.018 ± 0.003
(0.457 ± 0.076)
N16 1197
12
11
10
9
0.150 – 0.157**
(3.810 – 3.988)
0.010 – 0.020
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
× 45°
0° – 8° TYP
0.016 – 0.050
0.406 – 1.270
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.