Datasheet LT1247, LT1246 Datasheet (Linear Technology)

LT1246/LT1247

1MHz Off-Line

Current Mode PWM

and DC/DC Converter

EATU

F

■

Current Mode Operation to 1MHz

■

30ns Current Sense Delay

■

< 250µA Low Start-Up Current

■

Current Sense Leading Edge Blanking

■

Pin Compatible with UC1842

■

Undervoltage Lockout with Hysteresis

■

No Cross-Conduction Current

■

Trimmed Bandgap Reference

■

1A Totem Pole Output

■

Trimmed Oscillator Frequency and Sink Current

■

Active Pull-Down on Reference and Output During

RE

S

Undervoltage Lockout

■

18V High Level Output Clamp

U

O

PPLICATI

A

■

Off-Line Converters

■

DC/DC Converters

Start-Up Operating Maximum

Device Threshold Voltage Duty Cycle Replaces

LT1246 16V 10V 100% UC1842
LT1247 8.4V 7.6V 100% UC1843

S

Minimum

DUESCRIPTIO

The LT®1246/LT1247 are 8-pin, fixed frequency, current
mode, pulse width modulators. These devices are de­signed to be improved plug compatible versions of the
industry standard UC1842 PWM circuit. The LT1246/
LT1247 are optimized for off-line and DC/DC converter
applications. They contain a temperature compensated
reference, high gain error amplifier, current sensing com­parator, and a high current totem pole output stage ideally
suited to driving power MOSFETs. Start-up current has
been reduced to less than 250µ A. Cross-conduction cur­rent spikes in the totem pole output stage have been
eliminated, making 1MHz operation practical. Several new
features have been incorporated. Leading edge blanking
has been added to the current sense comparator. This
minimizes or eliminates the filter that is normally required.
Eliminating this filter allows the current sense loop to
operate with minimum delays. Trims have been added to
the oscillator circuit for both frequency and sink current,
and both of these parameters are tightly specified. The
output stage is clamped to a maximum V
on state. The output and the reference output are actively
pulled low during under-voltage lockout.

, LTC and LT are registered trademarks of Linear Technology Corporation.

of 18V in the

OUT

BLOCK

R

COMPENSATION

FEEDBACK

I

SENSE

IDAGRA

4

T/CT

1

2

3

2.5V

W

REFERENCE ENABLE

5V REF

MAIN BIAS

OSCILLATOR

5.6V

1mA

–

+

2R

R

1V

–

+

REFERENCE PULLDOWN

S
R

BLANKING

1.5V

LOCKOUT

OUTPUT

PULLDOWN

+

–

UV

18V

8

V

REF

7V

CC

6 OUTPUT

5 GND

LT1246 • BD01

1

LT1246/LT1247

WU

U

PACKAGE

/

O

RDER I FOR ATIO

A

W

O

LUTEXI T

S

A

WUW

ARB

U
G

I

S

Supply Voltage ....................................................... 25V

Output Current...................................................... ±1A*

Output Energy (Capacitive Load per Cycle)............. 5µJ

Analog Inputs (Pins 2, 3).............................. –0.3 to 6V

Error Amplifier Output Sink Current..................... 10mA

Power Dissipation at TA ≤ 25°C ............................... 1W

Operating Junction Temperature Range

LT1246C/LT1247C ............................. 0°C to 100°C

Storage Temperature Range ................ – 65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

*The 1A rating for output current is based on transient switching

requirements.

LECTRICAL C CHARA TERIST

E

ICS

(Notes 1, 2)

ORDER PART

TOP VIEW

V

COMP

1

FB

2



I

3

SENSE

R

4

T/CT

N8 PACKAGE
8-LEAD PDIP

S8 PACKAGE

8-LEAD PLASTIC SO

T

= 100°C, θJA = 130°C/W (N8)

JMAX

T

= 100°C, θJA = 150°C/W (S8)

JMAX

Consult factory for Industrial and Military grade parts.

8
7
6
5





REF

V



CC

OUTPUT
GND

NUMBER

LT1246CN8
LT1246CS8
LT1247CN8
LT1247CS8

S8 PART MARKING

1246
1247

PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Section

Output Voltage IO = 1mA, TJ = 25°C 4.925 5.000 5.075 V
Line Regulation 12V < VCC < 25V ● 320 mV
Load Regulation 1mA < I
Temperature Stability 0.1 mV/°C
Total Output Variation Line, Load, Temperature ● 4.87 5.13 V
Output Noise Voltage 10Hz < F < 10kHz, TJ = 25°C50µV
Long-Term Stability TA = 125°C, 1000 Hrs. 5 25 mV
Output Short-Circuit Current ● –30 –90 –180 mA

Oscillator Section

Initial Accuracy RT = 10k, CT = 3.3nF, TJ = 25°C 47.5 50 52.5 kHz

RT = 6.2k, CT = 500pF, TJ = 25°C 465 500 535 kHz
Voltage Stability 12V < VCC < 25V, TJ = 25°C1%
Temperature Stability T
Amplitude Pin 4 1.7 V
Clock Ramp Reset Current V

Error Amplifier Section

Feedback Pin Input Voltage V
Input Bias Current VFB = 2.5V ● –2 µA
Open-Loop Voltage Gain 2 < VO < 4V ● 65 90 dB
Unity-Gain Bandwidth TJ = 25°C 1 2 MHz
Power Supply Rejection Ratio 12V < VCC < 25V ● 60 dB
Output Sink Current V
Output Source Current V

MIN

OSC

PIN 1

PIN 2

PIN 2

< 20mA ● –6 –25 mV

REF

< TJ < T

MAX

(Pin 4) = 2V, TJ = 25°C 7.9 8.2 8.5 mA

= 2.5V ● 2.42 2.50 2.58 V

= 2.7V, V
= 2.3V, V

= 1.1V ● 26 mA

PIN 1

= 5V ● – 0.5 –0.75 mA

PIN 1

–0.05 %/°C

2

LT1246/LT1247

LECTRICAL C CHARA TERIST

E

PARAMETER CONDITIONS MIN TYP MAX UNITS
Error Amplifier Section

Output Voltage High Level V
Output Voltage Low Level V

Current Sense Section

Gain ● 2.85 3.00 3.15 V/V
Maximum Current Sense Input Threshold V
Power Supply Rejection Ratio 70 dB
Input Bias Current ● –1 –10 µA
Delay to Output 30 ns
Blanking Time 60 ns
Blanking Override Voltage 1.5 V

Output Section

Output Low Level I

Output High Level I

Rise Time CL = 1nF, TJ = 25°C3070ns
Fall Time CL = 1nF, TJ = 25°C2060ns
Output Clamp Voltage IO = 1mA ● 18 19 V

Undervoltage Lockout

Start-Up Threshold LT1246 ● 15 16 17 V

Minimum Operating Voltage LT1246 ● 9.0 10 11 V

Hysteresis LT1246 ● 5.5 6.0 V

PWM

Maximum Duty Cycle TJ = 25°C 94 100 %
Minimum Duty Cycle TJ = 25°C0%

Total Device

Start-Up Current ● 170 250 µA
Operating Current ● 13 20 mA

PIN 2

PIN 2

PIN 3

= 20mA ● 0.25 0.4 V

OUT

= 200mA ● 0.75 2.2 V

I

OUT

= 20mA ● 12.0 V

OUT

= 200mA ● 11.75 V

I

OUT

LT1247

LT1247

LT1247

ICS

(Notes 1, 2)

= 2.3V, RL = 15k to GND ● 5 5.6 V
= 2.7V, RL = 15k to Pin 8 ● 0.2 1.1 V

< 1.1V ● 0.90 1.00 1.10 V

● 7.8 8.4 9.0 V

● 7.0 7.6 8.2 V

● 0.4 0.8 V

The ● denotes those specifications which apply over the full operating
temperature range.

Note 1: Unless otherwise specified, V

= 15V, RT = 10k, CT = 3.3nF.

CC

Note 2: Low duty cycle pulse techniques are used during test to maintain
junction temperature close to ambient.

3

LT1246/LT1247

TEMPERATURE (°C)

–50

–10

FREQUENCY CHANGE (%)

–6

–2

2

6

10

–25 25 75 125

LT1246 • TPC06

0 50 100

–8

–4

0

4

8

VCC = 15V

UW

Y

PICA

17

16

15

(V)

CC

V

11

10

9

200

150

100

LPER

F

O

R

AT

CCHARA TERIST

E

C

ICS

LT1246 Undervoltage Lockout LT1247 Undervoltage Lockout Start-Up Current

200
180
160
140
120
100

80
60

START-UP CURRENT (µA)

40
20

0

–25 25 75 125

–50

START-UP THRESHOLD

MINIMUM OPERATING VOLTAGE

–50

0 50 100

–25 25 75 125

TEMPERATURE (°C)

LT1246 • TPC01

(V)

CC

V

11

10

9

8

7

6

–50

START-UP THRESHOLD

MINIMUM OPERATING VOLTAGE

–25 25 75 125

0 50 100

TEMPERATURE (°C)

1247 TPC02

Start-Up Current Supply Current Oscillator Frequency

15

START-UP

THRESHOLD

LT1246LT1247

14

13

(mA)

CC

I

12

0 50 100

TEMPERATURE (°C)

LT1246 • TPC03

50

START-UP CURRENT (µA)

0

0

Oscillator Sink Current Reference Short-Circuit Current Reference Voltage

8.7

8.6

8.5

8.4

8.3

8.2

8.1

8.0

7.9

OSCILLATOR SINK CURRENT (mA)

7.8

7.7
–50

4

TJ = 25°C

410146 16

2 8 12 18

VCC (V)

V

= 2V

PIN 4

0 50 100

–25 25 75 125

TEMPERATURE (°C)

1246/7 TPC04

LT1246 • TPC07

11

10

–25 25 75 125

–50

140

120

100

80

60

40

REFERENCE SHORT-CIRCUIT CURRENT (mA)

20

–50

0 50 100

TEMPERATURE (°C)

0 50 100

–25 25 75 125

TEMPERATURE (°C)

VCC = 15V

= 10k

R

T

= 3300pF

C

T

LT1246 • TPC05

LT1246 • TPC08



5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

REFERENCE VOLTAGE (V)

4.97

4.96

4.95
–50

IO = 1mA

0 50 100

–25 25 75 125

TEMPERATURE (°C)

LT1246 • TPC09

LT1246/LT1247

OUTPUT SOURCE CURRENT (mA)

0

0

OUTPUT SATURATION VOLTAGE (V)

4.0

200

LT1246 • TPC12

0.5

2.0

2.5

1.0

1.5

3.0

3.5

TJ = –55°C

TJ = 25°C

TJ = 125°C

100

ERROR AMP OUTPUT VOLTAGE (V)

0

0

CURRENT SENSE INPUT THRESHOLD (V)

1.2

36

LT1246 • TPC17

0.6

0.2

0.4

0.8

1.0

12 45

TJ = –55°C

TJ = 25°C

T

J

=125°C

UW

Y

PICA

2.55

2.54

2.53

2.52

2.51

2.50

2.49

2.48

2.47

FEEDBACK PIN INPUT VOLTAGE (V)

2.46

2.45
–50

1.0

0.5

OUTPUT SATURATION VOLTAGE (V)

0

LPER

F

O

R

AT

CCHARA TERIST

E

C

ICS

High Level Output

Feedback Pin Input Voltage Current Sense Clamp Voltage Saturation Voltage

1.05

1.04

1.03

1.02

1.01

1.00

0.99

0.98

0.97

CURRENT SENSE CLAMP VOLTAGE (V)

0.96

0 50 100

–25 25 75 125

TEMPERATURE (°C)

LT1246 • TPC10

0.95
–50

0 50 100

–25 25 75 125

TEMPERATURE (°C)

LT1246 • TPC11

Low Level Output Low Level Output Saturation Voltage Supply Current vs
Saturation Voltage During Undervoltage Lockout Oscillator Frequency

TJ = 25°C

0

OUTPUT SINK CURRENT (mA)

TJ = 125°C

TJ = –55°C

100 200

LT1246 • TPC13

4.0

3.5

3.0

2.5

2.0

1.5

1.0

OUTPUT SATURATION VOLTAGE (V)

0.5

TJ = 125°C

0

0

OUTPUT SINK CURRENT (mA)

TJ = –55°C

510

TJ = 25°C

LT1246 • TPC14

14

13

12

11

SUPPLY CURRENT (mA)

10

9

10k

OSCILLATOR FREQUENCY (Hz)

100k 1M

LT1246 • TPC15

Error Amplifier Open-Loop Gain
and Phase

100

80

60

40

20

, OPEN LOOP VOLTAGE GAIN (dB)

0

VOL

A

–20

10

GAIN

100 1k 100k 1M

10k 10M

FREQUENCY (Hz)

PHASE

LT1246 • TPC16

225

180

PHASE (DEGREES)

135

90

45

0

–45

Current Sense Input Threshold

5

LT1246/LT1247

Y

PICA

LPER

F

O

R

AT

UW

CCHARA TERIST

E

C

ICS

Output Deadtime vs
Oscillator Frequency

60

50

40

30

DEADTIME (%)

20

10

0

0

OSCILLATOR FREQUENCY (kHz)

Output Rise and Fall Time Current Sense Delay Output Cross-Conduction

5nF 2nF 1nF

500pF

100pF

100 1000

LT1246 • TPC18*

OUTPUT

VOLTAGE 5V/DIV

Timing Resistor vs
Oscillator Frequency

100

10

CT =10nF

TIMING RESISTOR (kΩ)

VCC = 15V

= 25°C

T

J



1

10k

OSCILLATOR FREQUENCY (Hz)

100pF

1nF

2nF

5nF

100k 1M

5V/DIV

OUTPUT

VOLTAGE

200pF

500pF

LT1246 • TPC19

OUTPUT VOLTAGE

VCC = 15V TIME 50ns/DIV
C

= 1nF 1246/7 G20

L

PI

U

FUUC

O

TI

U
S

INPUT 1V/DIV

CURRENT SENSE

VCC = 15V TIME 50ns/DIV

= 1nF 1246/7 G21

C

L

COMP (Pin 1): Compensation Pin. This pin is the output of
the Error Amplifier and is made available for loop compen­sation. It can also be used to adjust the maximum value of
the current sense clamp voltage to less than 1V. This pin
can source a minimum of 0.5mA (0.8mA typ.) and sink a
minimum of 2mA (4mA typ.)

FB (Pin 2): Voltage Feedback. This pin is the inverting
input of the Error Amplifier. The output voltage is normally
fed back to this pin through a resistive divider. The
noninverting input of the Error Amplifier is internally
committed to a 2.5V reference point.

20mA/DIV

OUTPUT CROSS-

VCC = 15V TIME 50ns/DIV
C

= 15pF 1246/7 G22

L

CONDUCTION CURRENT

I

(Pin 3): Current Sense. This is the input to the

SENSE

current sense comparator. The trip point of the compara­tor is set by, and is proportional to, the output voltage of
the Error Amplifier.

RT/CT (Pin 4) : The oscillator frequency and the deadtime
are set by connecting a resistor (RT) from V

to RT/C

REF

T

and a capacitor (CT) from RT/CT to GND.
The rise time of the oscillator waveform is set by the RC

time constant of RT and CT. The fall time, which is equal to
the output deadtime, is set by a combination of the RC time
constant and the oscillator sink current (8.2mA typ.).

6

LT1246/LT1247

f

t

OSC

OSC

=

1

U

PI

GND (Pin 5): Ground.
OUTPUT (Pin 6): Current Output. This pin is the output of

a high current totem pole output stage. It is capable of
driving up to ±1A of current into a capacitive load such as
the gate of a MOSFET.

V

of the control IC.

A

Device Threshold Voltage Duty Cycle Replaces

LT1246 16V 10V 100% UC1842
LT1247 8.4V 7.6V 100% UC1843

Oscillator

The LT1246/LT1247 are fixed frequency current mode
pulse width modulators. The oscillator frequency and the
oscillator discharge current are both trimmed and tightly
specified to minimize the variations in frequency and
deadtime. The oscillator frequency is set by choosing a
resistor and capacitor combination, RT and CT. This RC
combination will determine both the frequency and the
maximum duty cycle. The resistor RT is connected from
V
connected from the RT/CT pin to ground. The charging
current for CT is determined by the value of RT. The
discharge current for CT is set by the difference between
the current supplied by RT and the discharge current of the
LT1246/LT1247. The discharge current of the device is
trimmed to 8.2mA. For large values of RT discharge time
will be determined by the discharge current of the device
and the value of CT. As the value of RT is reduced it will have
more effect on the discharge time of CT. During an oscil­lator cycle capacitor CT is charged to approximately 2.8V
and discharged to approximately 1.1V. The output is
enabled during the charge time of CT and disabled, in an
off state, during the discharge time of CT. The deadtime of
the circuit is equal to the discharge time of CT. The
maximum duty cycle is limited by controlling the deadtime
of the oscillator. There are many combinations of RT and
CT that will yield a given oscillator frequency, however
there is only one combination that will yield a specific

FUUC

(Pin 7): Supply Voltage. This pin is the positive supply

CC

PPLICATI

Start-Up Operating Maximum

(pin 8) to the RT/CT pin (pin 4). The capacitor CT is

REF

TI

O

U

S

U

O

S

I FOR ATIO

Minimum

WU

U

V

(Pin 8): Reference. This is the reference output of the

REF

IC. The reference output is used to supply charging current
to the external timing resistor RT. The reference provides
biasing to a large portion of the internal circuitry, and is
used to generate several internal reference levels includ­ing the VFB level and the current sense clamp voltage.

deadtime at that frequency. Curves of oscillator frequency
and deadtime for various values of RT and CT appear in the
Typical Performance Characteristics section. Frequency
and deadtime can also be calculated using the following
formulas:

Oscillator Rise Time: tr = 0.583 • RC

RC

•

346

Oscillator Discharge Time:
Oscillator Period: t
Oscillator Frequency:

Maximum Duty Cycle:

The above formulas will give values that will be accurate
to approximately ±5%, at the oscillator, over the full
operating frequency range. This is due to the fact that the
oscillator trip levels are constant versus frequency and the
discharge current and initial oscillator frequency are
trimmed. Some fine adjustment may be required to achieve
more accurate results. Once the final RT/CT combination is
selected, the oscillator characteristics will be repeatable
from device to device. Note that there will be some slight
differences between maximum duty cycle at the oscillator
and maximum duty cycle at the output due to the finite rise
and fall times of the output.

Error Amplifier

The LT1246/LT1247 contain a fully compensated error
amplifier with a DC gain of 90dB and a unity-gain fre­quency of 2MHz. Phase margin at unity-gain is 80°. The
noninverting input is internally committed to a 2.5V refer­ence point derived from the 5V reference of pin 8. The

OSC

t

=

d

= tr + t

d

D

==

MAX

.

R

0 0164 11 73

..

t

r

t

OSC

−

tt

−

OSC d

t

OSC

7

LT1246/LT1247

U

O

PPLICATI

A

inverting input (pin 2) and the output (pin 1) are made
available to the user. The output voltage in a regulator
circuit is normally fed back to the inverting input of the
error amplifier through a resistive divider. The output of
the error amplifier is made available for external loop
compensation. The output current of the error amplifier is
limited to approximately 0.8mA sourcing and approxi­mately 6mA sinking.

In a current mode PWM the peak switch current is a
function of the output voltage of the error amplifier. In the
LT1246/LT1247 the output of the error amplifier is offset
by two diodes (1.4V at 25°C), divided by a factor of three,
and fed to the inverting input of the current sense com­parator. For output voltages less than 1.4V the duty cycle
of the output stage will be zero. The maximum offset that
can appear at the current sense input is limited by a 1V
clamp. This occurs when the error amplifier output reaches

4.4V at 25°C. The output of the error amplifier can be
clamped below 4.4V in order to reduce the maximum
voltage allowed across the current sensing resistor to less
than 1V. The supply current will increase by the value of
the output source current when the output voltage of the
error amplifier is clamped.

Current Sense Comparator and PWM Latch

LT1246/LT1247 are current mode controllers. Under nor­mal operating conditions the output (pin 6) is turned on at
the start of every oscillator cycle, coincident with the rising
edge of the oscillator waveform. The output is then turned
off when the switch current reaches a threshold level
proportional to the error voltage at the output of the error
amplifier. Once the output is turned off it is latched off until
the start of the next cycle. The peak switch current is thus
proportional to the error voltage and is controlled on a
cycle by cycle basis. The peak switch current is normally
sensed by placing a sense resistor in the source lead of the
output MOSFET. This resistor converts the switch current
to a voltage that can be fed into the current sense input. For
normal operating conditions the peak inductor current,
which is equal to the peak switch current, will be equal to:

VV

−

()

1

I

PK

PIN

=

R

()

S

143.

S

I FOR ATIO

WU

U

During fault conditions the maximum threshold voltage at
the input of the current sense comparator is limited by the
internal 1V clamp at the inverting input. The peak switch
current will be equal to:

V

I

PK MAX

(

In certain applications such as high power regulators it
may be desirable to limit the maximum threshold voltage
to less than 1V in order to limit the power dissipated in the
sense resistor or to limit the short-circuit current of the
regulator circuit. This can be accomplished by clamping
the output of the error amplifier. A voltage level of
approximately 1.4V at the error amplifier output will give
a threshold voltage of 0V. A voltage level of approximately

4.4V at the output of the error amplifier will give a thresh­old level of 1V. Between 1.4V and 4.4V the threshold
voltage will change by a factor of one third of the change
in the error amplifier output voltage. The threshold voltage
will be 0.333V for an error amplifier voltage of 2.4V. To
reduce the maximum current sense threshold to less than
1V the error amplifier output should be clamped to less
than 4.4V.

Blanking

A unique feature of the LT1246/LT1247 is the built-in
blanking circuit at the output of the current sense com­parator. A common problem with current mode PWM
circuits is erratic operation due to noise at the current
sense input. The primary cause of noise problems is the
leading edge current spike due to transformer interwinding
capacitance and diode reverse recovery time. This current
spike can prematurely trip the current sense comparator
causing an instability in the regulator circuit. A filter at the
current sense input is normally required to eliminate this
instability. This filter will in turn slow down the current
sense loop. A slow current sense loop wil increase the
minimum pulse width which will increase the short-circuit
current in an overload condition. The LT1246/LT1247
blank (lock out) the signal at the output of the current
sense comparator for a fixed amount of time after the
switch is turned on. This prevents the PWM latch from
tripping due to the leading edge current spike. The blank­ing time will be a function of the voltage at the feedback pin
(pin 2). The blanking time will be 60ns for normal operat-

10.

=

)

R

S

8

LT1246/LT1247

U

O

PPLICATI

A

ing conditions (VFB = 2.5V). The blanking time goes to zero
as the feedback pin is pulled to 0V. This means that the
blanking time will be minimized during start-up and also
during an output short-circuit fault. This blanking circuit
eliminates the need for an input filter at the current sense
input except in extreme cases. Eliminating the filter allows
the current sense loop to operate with minimum delays,
reducing peak currents during fault conditions.

Undervoltage Lockout

The LT1246/LT1247 incorporate an undervoltage lockout
comparator which prevents the internal reference circuitry
and the output from starting up until the supply voltage
reaches the start-up threshold voltage. The quiescent
current, below the start-up threshold, has been reduced to
less than 250µA (170µA typ.). This minimizes the power
loss due to the start-up resistor used in off-line converters.
In undervoltage lockout both V
(pin 6) are actively pulled low by Darlington connected
PNP transistors. They are designed to sink a few milliamps
of current and will pull down to about 1V. The pull-down
transistor at the reference pin can be used to reset the
external soft start capacitor. The pull-down transistor at
the output eliminates the external pull-down resistor re­quired, with earlier devices, to hold the external MOSFET
gate low during undervoltage lockout.

Output

The LT1246/LT1247 incorporate a single high current
totem pole output stage. This output stage is capable of
driving up to ±1A of output current. Cross-conduction
current spikes in the output totem pole have been elimi­nated. These devices are primarily intended for driving
MOSFET switches. Rise time is typically 30ns and fall time
is typically 20ns when driving a 1.0nF load. A clamp is built
into the device to prevent the output from rising above 18V
in order to protect the gate of the MOSFET switch. The
output is actively pulled low during undervoltage lockout
by a Darlington PNP. This PNP is designed to sink several
milliamps and will pull the output down to approximately
1V. This active pull-down eliminates the need for the
external resistor which was required in older designs.

The output pin of the device connects directly to the
emitter of the upper NPN drive transistor and the collector
of the lower NPN drive transistor in the totem pole. The

S

I FOR ATIO

REF

WU

(pin 8) and the Output

U

collector of the lower transistor, which is n-type silicon,
forms a p-n junction with the substrate of the device. The
substate of the device is tied to ground. This junction is
reverse biased during normal operation. In some applica­tions the parasitic LC of the external MOSFET gate can ring
and pull the output pin below ground. If the output pin is
pulled negative by more than a diode drop, the parasitic
diode formed by the collector of the output NPN and the
substrate will turn on. This can cause erratic operation of
the device. In these cases a Schottky clamp diode is
recommended from output to ground.

Reference

The internal reference of the LT1246/LT1247 is a 5V
Bandgap reference, trimmed to within ±1% initial toler­ance. The reference is used to power the majority of the
internal logic and the oscillator circuitry. The oscillator
charging current is supplied from the reference. The
feedback pin voltage and the clamp level for the current
sense comparator are derived from the reference voltage.
The reference can supply up to 20mA of current to power
external circuitry. Note that using the reference in this
manner, as a voltage regulator, will significantly increase
the power dissipation in the device, which will reduce the
operating ambient temperature range.

Design/Layout Considerations

LT1246/LT1247 are high speed circuits capable of gener­ating pulsed output drive currents of up to 1A peak. The
rise and fall time for the output drive current is in the range
of 10ns to 20ns. High Speed circuit layout techniques
must be used to insure proper operation of the devices. Do

not attempt to use Proto-boards or wire-wrap tech­niques to breadboard high speed switching regulator
circuits. They will not work properly.

Printed circuit layouts should include separate ground
paths for the voltage feedback network, oscillator capaci­tor, and switch drive current. These ground paths should
be connected together directly at the ground pin (pin 5) of
the LT1246/LT1247. This will minimize noise problems
due to pulsed ground pin currents. VCC should be by­passed, with a minimum of 0.1µF, as close to the device
as possible. High current paths should be kept short and
they should be separated from the feedback voltage net­work with shield traces if possible.

9

LT1246/LT1247

PPLICATITYPICAL

U

O

SA

EXTERNAL

SYNC

INPUT

External Clock Synchronization

V

0.01µF

REF

8

R

T

RT/C

4

C

T

5V REF

T

OSCILLATOR

47Ω

D1

D1 IS REQUIRED IF THE SYNC AMPLITUDE IS
LARGE ENOUGH TO PULL THE BOTTOM OF C
MORE THAN 300mV BELOW GROUND.

T

LT1246 • TA05

Soft Start

V

REF

8

R

COMP

1

C

FEEDBACK

2

–

1mA

5.6V

5V REF

1V

2R

–

I

SENSE

+

2.5V

3

R

+

+

1.5V

–

LT1246 • TA06

Adjustable Clamp Level with Soft Start

5V REF

V

REF

8

R

T/CT

4

100k

COMP

1

FEEDBACK

2

–

+

R2

C

R1

OSCILLATOR

5.6V

1mA

MAIN BIAS

1V

2R

–

R

+

2.5V

V

≈

CLAMP

1.67

R2

+ 1

(

R1



(

I

PK (MAX)

≈

V

CLAMP



WHERE: O ≤ V

R

S

REFERENCE ENABLE

REFERENCE PULLDOWN

BLANKING

≤ 1.0V t

CLAMP

S
R

1.5V

SOFT START

= –ln 1 –

UV

LOCKOUT

OUTPUT

PULLDOWN

+

–

3 • V

18V

V

C

CLAMP

V

OUTPUT

GND

I

SENSE

R1 R2

C

R1 + R2

V

R

S

LT1246 • TA07

IN

CC

7

6

5

3



10

LT1246/LT1247

U

O

PPLICATITYPICAL

SA

R

T

C

T

V

REF

8

R

T/CT

4

COMP

1

FEEDBACK

2

–

+

2.5V

Slope Compensation at I

5V REF

MAIN BIAS

OSCILLATOR

5.6V

1mA

2R

SENSE

1V

–

R

+

Slope Compensation at Error Amp

Pin

REFERENCE ENABLE

REFERENCE PULLDOWN

S
R

BLANKING

1.5V

UV

LOCKOUT

OUTPUT

PULLDOWN

+

–

18V

V

CC

7

OUTPUT

6

GND

5

I

SENSE

3

V

LT1246 • TA08

IN

R

S

UV

V

REF

8

R

R

T

T/CT

TO

V

OUT

R

SLOPE

C

T

R

FEEDBACK

COMP

f

4

1

2

–

OSCILLATOR

5.6V

1mA

2R

+

5V REF

MAIN BIAS

1V

–

R

+

2.5V

REFERENCE ENABLE

REFERENCE PULLDOWN

S
R

BLANKING

1.5V

LOCKOUT

OUTPUT

PULLDOWN

+

–

18V

V

CC

7

OUTPUT

6

GND

5

I

SENSE

LT1246 • TA09

3

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

11

LT1246/LT1247

PACKAGEDESCRIPTI

0.300 – 0.325

(7.620 – 8.255)

O

U

Dimensions in inches (millimeters) unless otherwise noted.

N8 Package

8-Lead Plastic DIP

0.045 – 0.065

(1.143 – 1.651)

0.130 ± 0.005

(3.302 ± 0.127)

0.400*
(10.160)

MAX

876

5

0.065

(1.651)

0.009 – 0.015

(0.229 – 0.381)

+0.025

0.325
–0.015

+0.635

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTURSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).

× 45°

0.016 – 0.050

0.406 – 1.270

TYP

0.045 ± 0.015

(1.143 ± 0.381)

0.100 ± 0.010

(2.540 ± 0.254)

0.053 – 0.069

(1.346 – 1.752)

0°– 8° TYP

0.014 – 0.019

(0.355 – 0.483)

0.125

(3.175)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

S8 Package

8-Lead Plastic SOIC

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

0.255 ± 0.015*
(6.477 ± 0.381)

0.015

(0.380)



MIN

0.228 – 0.244

(5.791 – 6.197)





12

0.189 – 0.197*
(4.801 – 5.004)

7

8

1

2

6

3

3

5

4

4

N8 0694

0.150 – 0.157*
(3.810 – 3.988)

SO8 0294

RELATED PARTS

PART NUMBER DESCRIPTION

LT1105 Off-Line Switching Regulator Controller
LT1170/LT1171/LT1172 High Efficiency 100kHz Switching Regulators
LT1241-5 500kHz Low Power Current Mode Pulse Width Modulator
LT1248/LT1249 Power Factor Controllers
LT1372 High Efficiency 500kHz Boost Switching Regulator
LT1376 1.5A, 500kHz Step-Down Switching Regulator
LT1377 1MHz High Efficiency Boost Switching Regulator
LT1431 Programmable Reference

Linear Technology Corporation

12

1630 McCarthy Blvd., Milpitas, CA 95035-7487

[phone]

●

FAX

: [phone]

●

TELEX

: 499-3977

LT/GP 0395 5K REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1992