Datasheet LT1186FIS, LT1186FCS Datasheet (Linear Technology)

LT1186F

DAC Programmable

CCFL Switching Regulator

(Bits-to-Nits

TM

)

FEATURES

■

Wide Battery Input Range: 4.5V to 30V

■

Grounded Lamp or Floating Lamp Configurations

■

Open Lamp Protection

■

Precision 50µA Full-Scale DAC Programming Current

■

Standard SPI Mode or Pulse Mode

■

DAC Setting Is Retained in Shutdown

U

APPLICATIONS

■

Notebook and Palmtop Computers

■

Portable Instruments

■

Retail Terminals

U

DESCRIPTION

The LT®1186F is a fixed frequency, current mode, switch­ing regulator that provides the control function for Cold
Cathode Fluorescent Lighting (CCFL). The IC includes an
efficient high current switch, an oscillator, output drive
logic, control circuitry and a micropower 8-bit 50µA full-
scale current output DAC. The DAC provides simple “bits­to-lamp current control” and communicates in two inter-

face modes including standard SPI mode and pulse mode.
On power-up, the DAC counter resets to half-scale and the
DAC configures to SPI or pulse mode depending on the CS
signal level. In SPI mode, the system microprocessor
serially transfers the present 8-bit data and reads back the
previous 8-bit data. In pulse mode, the upper six bits of the
DAC configure as increment-only (1-wire interface) or
increment/decrement (2-wire interface) operation depend­ing on the DIN signal level.

The LT1186F control circuitry operates from a logic supply
voltage of 3.3V or 5V. The IC also has a battery supply
voltage pin that operates from 4.5V to 30V. The LT1186F
draws 6mA typical quiescent current. An active low shut­down pin reduces total supply current to 35µA for standby
operation and the DAC retains its last setting. A 200kHz
switching frequency minimizes magnetic component size.
Current mode switching techniques with cycle-by-cycle
limiting gives high reliability and simple loop frequency
compensation. The LT1186F is available in a 16-pin nar­row SO package.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Bits-to-Nits is a trademark of Linear Technology Corporation. 1 Nit = 1 Candela/meter

2

TYPICAL APPLICATION

90% Efficient Floating CCFL with 1-Wire (Increment Only) Pulse Mode Control of Lamp Current

D1

BAT85

1

CCFL

CCFL V

LT1186F

C

BULB

BAT

ROYER

V

I

OUT

D

OUT

D

SW

CC

IN

PGND

2

I

CCFL

3

C7, 1µF

SHUTDOWN

FROM MPU

ALUMINUM ELECTROLYTIC IS RECOMMENDED FOR C3A AND C3B.
MAKE 3CB ESR ≥ 0.5Ω TO PREVENT DAMAGE TO THE LT1186F HIGH-SIDE
SENSE RESISTOR DUE TO SURGE CURRENTS AT TURN-ON

C1 MUST BE A LOW LOSS CAPACITOR, C1 = WIMA MKP-20
Q1, Q2 = ZETEX ZTX849 OR ROHM 2SC5001

4

5

6

7

8

DIO

CCFL V

AGND

SHDN

CLK

CS

U

CCFL BACKLIGHT APPLICATION CIRCUITS
CONTAINED IN THIS DATA SHEET ARE COVERED
BY U.S. PATENT NUMBER 5408162
AND OTHER PATENTS PENDING

16

15

14

13

V

C4

2.2µF

IN

3.3V
OR 5V

CURRENT GIVES

CCFL

12

11

10

9

+

0µA TO 50µA I
0mA TO 6mA LAMP CURRENT
FOR A TYPICAL DISPLAY.

UP TO 6mA

LAMP

C5

1000pF

R2
220k

R3
100k

FOR ADDITIONAL CCFL/LCD CONTRAST APPLICATION CIRCUITS,
REFER TO THE LT1182/83/84/84F DATA SHEET

10

321 5

+

C1*

0.068µF

Q2* Q1*

6

C3B

2.2µF
35V

L2
100µH

C2
27pF
3kV

4

D1

1N5818

L1 = COILTRONICS CTX210605
L2 = COILTRONICS CTX100-4
*DO NOT SUBSTITUTE COMPONENTS
COILTRONICS [phone]

L1

+

C3A

2.2µF

R1
750Ω

LT1186F • TA01

35V

BAT
8V TO 28V

1

LT1186F

WW

W

ABSOLUTE MAXIMUM RATINGS

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PACKAGE/ORDER INFORMATION

VCC........................................................................... 7V

BAT, Royer, BULB .................................................. 30V

CCFL PGND

CCFL VSW............................................................... 60V

Shutdown ................................................................. 6V

I

Input Current .............................................. 10mA

CCFL

CCFL V

DIO Input Current (Peak, <100ms).................... 100mA

Digital Inputs ................................ –0.3V to VCC + 0.3V

Digital Outputs.............................. –0.3V to VCC + 0.3V

DAC Output Voltage ....................... –20V to VCC + 0.3V

Junction Temperature (Note 1)........................... 100°C

Operating Ambient Temperature Range

LT1186FC ............................................ 0°C to 100°C

LT1186FI ..........................................– 40°C to 100°C

Consult factory for Industrial and Military grade parts.

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................ 300°C

ELECTRICAL CHARACTERISTICS

TA = 25°C, VCC = SHUTDOWN = DIN = CS = 3.3V, BAT = Royer = BULB = 12V, I
= CLK = GND, CCFL VC = 0.5V, unless otherwise specified.

CCFL

TOP VIEW

1
2

I

CCFL

3

DIO

4

C

5

AGND

6

SHDN

7

CLK

8

CS

S PACKAGE

16-LEAD PLASTIC SO

T

= 100°C, θJA = 100°C/W

JMAX

= CCFL VSW = Open, D

U

W

U

ORDER PART

16

CCFL V

SW

15

BULB

14

BAT

13

ROYER

12

V

CC

11

I

OUT

10

D

OUT

9

D

IN

= Three-State, DIO = I

OUT

NUMBER

LT1186FCS
LT1186FIS

OUT

xSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

Q

I

SHDN

f Switching Frequency Measured at CCFL VSW, ISW = 50mA, 175 200 225 kHz

DC(MAX) Maximum Switch Duty Cycle Measured at CCFL V

BV Switch Breakdown Voltage Measured at CCFL V

Supply Current 3V ≤ VCC ≤ 6.5V, 1/2 Full-Scale DAC Output Current ● 6 9.5 mA
SHUTDOWN Supply Current SHUTDOWN = 0V, CCFL VC Open (Note 2) 35 70 µA
SHUTDOWN Input Bias Current SHUTDOWN = 0V, CCFL VC = Open 5 10 µA
SHUTDOWN Threshold Voltage ● 0.45 0.85 1.2 V

= 100µA, CCFL VC = Open ● 160 200 240 kHz

I

CCFL

SW

SW

Switch Leakage Current VSW = 12V, Measured at CCFL V

= 30V, Measured at CCFL V

V

SW

I

Summing Voltage 3V ≤ VCC ≤ 6.5V 0.425 0.465 0.505 V

CCFL

∆I

Summing Voltage for I

CCFL

∆Input Programming Current
CCFL VC Offset Sink Current CCFL VC = 1.5V, Positive Current Measured into Pin –5 5 15 µA

∆CCFL VC Source Current for I
∆I

Programming Current CCFL VC = 1.5V

CCFL

CCFL VC to DIO Current Servo Ratio DIO = 5mA out of Pin, Measure I(VC) at CCFL VC = 1.5V ● 94 99 104 µA/mA
CCFL VC Low Clamp Voltage V
CCFL VC High Clamp Voltage I
CCFL VC Switching Threshold CCFL VSW DC = 0% ● 0.6 0.95 1.3 V

= 0µA to 100µA515mV

CCFL

= 25µA, 50µA, 75µA, 100µA, ● 4.70 4.95 5.20 µA/µA

CCFL

< 0°C ● 4.60 4.95 5.20 µA/µA

T

J

– V

BAT

CCFL

= BULB Protect Servo Voltage ● 0.1 0.3 V

BULB

= 100µA ● 1.7 2.1 2.4 V

SW
SW

80 85 %

● 75 85 %

60 70 V

20 µA
40 µA

● 0.385 0.465 0.555 V

2

ELECTRICAL CHARACTERISTICS

LT1186F

TA = 25°C, VCC = SHUTDOWN = DIN = CS = 3.3V, BAT = Royer = BULB = 12V, I

= CCFL VSW = Open, D

CCFL

= Three-State, DIO = I

OUT

OUT

= CLK = GND, CCFL VC = 0.5V, unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

CCFL High-Side Sense Servo Current I

CCFL High-Side Sense Servo Current BAT = 5V to 30V, I
Line Regulation I(V

CCFL High-Side Sense Supply Current Current Measured into BAT and Royer Pins ● 50 100 150 µA
BULB Protect Servo Voltage I

BULB Input Bias Current I

I

LIM

V
∆I

∆I

SAT

Q

SW

CCFL Switch Current Limit Duty Cycle = 50% ● 1.25 1.9 3.0 A

CCFL Switch On Resistance CCFL ISW = 1A ● 0.6 1.0 Ω
Supply Current Increase During CCFL ISW = 1A 20 30 mA/A

CCFL Switch On Time
DAC Resolution 8 Bits
DAC Full-Scale Current V(I

DAC Zero Scale Current V(I
DAC Differential Nonlinearity ● ±2.0 LSB
DAC Supply Voltage Rejection 3V ≤ VCC ≤ 6.5V, I
Logic Input Current 0V ≤ VIN ≤ V

V

IH

V

IL

V

OH

V

OL

I

OZ

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

Low Level Output Voltage V

Three-State Output Leakage V

SERIAL INTERFACE (Notes 4, 5)

f

CLK

t

CKS

t

CSS

t

DV

t

DS

t

DH

t

DO

t

CKHI

t

CKLO

t

CSH

t

DZ

t

CKH

Clock Frequency ● 2 MHz
Setup Time, CLK↓ Before CS↓ ● 150 ns
Setup Time, CS↓ Before CLK↑ ● 400 ns
CS↓ to D

Valid See Test Circuits ● 150 ns

OUT

Data in Setup Time Before CLK↑ ● 150 ns
Data in Hold Time After CLK↑ ● 150 ns
CLK↓ to D

Valid See Test Circuits ● 150 ns

OUT

CLK High Time ● 200 ns
CLK Low Time ● 250 ns
CLK↓ Before CS↑ ● 150 ns
CS↑ to D

In Hi-Z See Test Circuits ● 400 ns

OUT

CS↑ Before CLK↑ ● 400 ns

= 100µA, I(VC) = 0µA at CCFL VC = 1.5V ● 0.93 1.00 1.07 A

CCFL

< 0°C ● 0.91 1.00 1.07 A

T

J

= 100µA, 0.1 0.16 %/V

) = 0µA at CCFL VC = 1.5V

C

= 100µA, I(VC) = 0µA at CCFL VC = 1.5V, ● 6.5 7.0 7.5 V

CCFL

CCFL

Servo Voltage Measured between BAT and BULB Pins

= 100µA, I(VC) = 0µA at CCFL VC = 1.5V 5 9 µA

CCFL

Duty Cycle = 75% (Note 3)

) = 0.465V, Measured in SPI Mode 48.5 50 51.5 µA

OUT

) = 0.465V, Measured in SPI Mode 200 nA

OUT

= Full Scale, V(I

OUT

CC

= 3.3V ● 1.9 V

CC

= 5V ● 2V

V

CC

= 3.3V ● 0.45 V

CC

= 5V ● 0.80 V

V

CC

= 3.3V, IO = 400µA ● 2.1 V

CC

V

= 5V, IO = 400µA ● 2.4 V

CC

= 3.3V, IO = 1mA ● 0.4 V

CC

V

= 5V, IO = 2mA ● 0.4 V

CC

= V

CS

CC

) = 0.465V ● 24 LSB

OUT

● 0.9 1.6 2.6 A

● 47.0 50 53.0 µA

● ±1 µA

● ±5 µA

3

LT1186F

TEMPERATURE (°C)

0

SHUTDOWN INPUT BIAS CURRENT (µA)

2

4

6

5

3

1

–25 25 75 125

LT1186F • G03

175–50–75 0 50 100 150

VCC = 5V

VCC = 3V

TEMPERATURE (°C)

–75

CCFL MAXIMUM DUTY CYCLE (%)

87

91

95
93

89

85

81

77

125 150

LT1186F • G06

83

79

75

–25 0–50

25 50

75 100

175

ELECTRICAL CHARACTERISTICS

TA = 25°C, VCC = SHUTDOWN = DIN = CS = 3.3V, BAT = Royer = BULB = 12V, I

= CCFL VSW = Open, D

CCFL

= Three-State, DIO = I

OUT

OUT

= CLK = GND, CCFL VC = 0.5V, unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
SERIAL INTERFACE (Notes 4, 5)

t

CSLO

t

CSHI

The ● denotes specifications which apply over the specified operating
temperature range.

Note 1: T
dissipation P

LT1186FCS: TJ = TA + (PD)(100°C/W)

Note 2: Does not include switch leakage.

CS Low Time f

= 2MHz ● 4550 ns

CLK

CS High Time ● 400 ns

Note 3: For duty cycles (DC) between 50% and 80%, minimum

is calculated from the ambient temperature TA and power

J

according to the following formula:

D

guaranteed switch current is given by I
LT1186F due to internal slope compensation circuitry.

Note 4: Timings for all input signals are measured at 0.8V for a High-to-

= 1.4(1.393 – DC) for the

LIM

Low transition and 2.0V for a Low-to-High transition.
Note 5: Timings are guaranteed but not tested.

W

U

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current
vs Temperature

10

9
8
7
6
5
4
3

SUPPLY CURRENT (mA)

2
1
0

–25–50 0 50 100 150

–75

TEMPERATURE (°C)

75

125

25

175

LT1186F • G01

Shutdown Current
vs Temperature

100

90
8O
70

60
50
40
30

SHUTDOWN CURRENT (µA)

20
10

0

–25–50 0 50 100 150

–75

VCC = 5V

VCC = 3V

75

25

TEMPERATURE (°C)

125

Shutdown Input Bias Current
vs Temperature

175

LT1186F • G02

Shutdown Threshold Voltage
vs Temperature

1.2

1.1

1.0

0.9

0.8

0.7

SHUTDOWN THRESHOLD VOLTAGE (V)

0.6

4

–25 25 75 125

TEMPERATURE (°C)

Maximum Duty Cycle

Frequency vs Temperature

240

230

220

210

200

190

CCFL FREQUENCY (kHz)

180

170

175–50–75 0 50 100 150

LT1186F • G04

160

–75

–50

–25

75

50

25

0

TEMPERATURE (°C)

100

125

150

LT1186F • G05

175

vs Temperature

W

TEMPERATURE (°C)

–3

CCFL V

C

SINK OFFSET CURRENT (µA)

–1

1
0

–2

10

9

6

8
7

5

3
2

4

–75 125 150

–25 0–50

25 50

75 100

175

CCFL VC = 0.5V

CCFL VC = 1.0V

CCFL VC = 1.5V

LT1186F • G09

TEMPERATURE (°C)

–75

1.7

CCFL V

C

HIGH CLAMP VOLTAGE (V)

1.8

2.0

2.1

2.2

2.4

–50

50

100

LT1186F • G15

1.9

2.3

25

150

175

–25

0

75 125

U

TYPICAL PERFORMANCE CHARACTERISTICS

I

Summing Voltage

CCFL

vs Temperature

0.53

0.52

0.51

0.50

0.49

0.48

0.47

0.46

0.45

0.44

0.43

SUMMING VOLTAGE (V)

0.42

CCFL

0.41

I

0.40

0.39

0.38
–25 25 75 125

TEMPERATURE (°C)

∆CCFL VC Source Current for
∆I

Programming Current

CCFL

vs Temperature

5.10

5.05

I

= 100µA

5.00

4.95

SOURCE CURRENT FOR

4.90

C

PROGRAMMING CURRENT (µA/µA)

4.85

∆CCFL V

CCFL

∆I

4.80

CCFL

I

= 50µA

CCFL

I

CCFL

–25 25 75 125

TEMPERATURE (°C)

175–50–75 0 50 100 150

LT1186F • G07

= 10µA

175–50–75 0 50 100 150

LT1186F • G10

I

Summing Voltage

CCFL

Load Regulation

5
4
3
2
1

0
–1
–2
–3

–4
–5

SUMMING VOLTAGE (mV)

–6

CCFL

–7

∆I

–8
–9

–10

I

T = 125°C

40 80 120 160

PROGRAMMING CURRENT (µA)

CCFL

Positive DIO Voltage
vs Temperature

1.2

1.0

0.8

0.6

0.4

POSITIVE DIO VOLTAGE (V)

0.2

0

I(DIO) = 1mA

–25 25 75 125

TEMPERATURE (°C)

T = –55°C

T = 25°C

I(DIO) = 10mA

I(DIO) = 5mA

LT1186F • G08

LT1186F • G11

LT1186F

VC Sink Offset Current
vs Temperature

20020060 100 140 180

Negative DIO Voltage
vs Temperature

1.6

1.4

1.2

1.0

0.8

0.6

0.4

NEGATIVE DIO VOLTAGE (V)

0.2

175–50–75 0 50 100 150

0

–75

–50

I(DIO) = 10mA

–25

25

0
TEMPERATURE (°C)

I(DIO) = 5mA

I(DIO) = 1mA

75

50

100

125

LT1186F • G12

150

175

VC to DIO Current Servo
Ratio vs Temperature

103

102

101

100

I(DIO) = 1mA

99

98

97

DIO CURRENT SERVO RATIO (µA/mA)

C

96

CCFL V

95

–75

–25

–50

TEMPERATURE (°C)

0

I(DIO) = 10mA

I(DIO) = 5mA

50

25

75

100

125

150

LT1186F • G13

175

VC Low Clamp Voltage
vs Temperature

0.30

0.25

0.20

0.15

0.10

LOW CLAMP VOLTAGE (V)

C

0.05

CCFL V

0

–25 25 75 125

TEMPERATURE (°C)

VC High Clamp Voltage
vs Temperature

175–50–75 0 50 100 150

LT1186F • G14

5

LT1186F

TEMPERATURE (°C)

BULB INPUT BIAS CURRENT (µA)

6

8

10

LT1186F • G18

4

2

0

–75 125 150

–25 0

–50

25 50

75 100

175

CCFL ISW (A)

0

FORCED BETA

60

80

110
100

1.6

LT1186F • G24

40

20

50

70

90

30

10

0

0.4

0.8

1.2

0.2 1.8

0.6

1.0

1.4

2.0

W

U

TYPICAL PERFORMANCE CHARACTERISTICS

VC Switching Threshold
vs Temperature

1.3

1.2

1.1

1.0

0.9

0.8

SWITCHING THRESHOLD VOLTAGE (V)

C

0.7

CCFL V

0.6
–75

–50

0

25

–25

TEMPERATURE (°C)

50

75 125

High-Side Sense Supply Current
vs Temperature

150
140
130
120

110

100

90
80

70

60

CCFL HIGH-SIDE SENSE SUPPLY CURRENT (µA)

50

–50

–75

0

–25

25 50

TEMPERATURE (°C)

75 100

100

150

LT1186F • G16

125 150

LT1186F • G19

BULB Protect Servo Voltage
vs Temperature

7.5

7.4

7.3

175

7.2

7.1

7.0

6.9

6.8

6.7

BULB PROTECT SERVO VOLTAGE (V)

6.6

6.5
–75

I

CCFL

–25 0–50

High-Side Sense Null
Current vs Temperature

1.060

1.040

1.020

1.000

0.980

0.960

CCFL HIGH-SIDE SENSE NULL CURRENT (A)

0.940
–75

175

–25 25 75 125

= 100µA

I

= 50µA

CCFL

I

= 10µA

CCFL

75 100

25 50

TEMPERATURE (°C)

0 50 100 150
TEMPERATURE (°C)

125 150

LT1186F • G17

LT1186F • G20

BULB Input Bias Current
vs Temperature

175

High-Side Sense Null Current Line
Regulation vs Temperature

0.160

0.140

0.120

0.100

0.080

0.060

0.040

0.020

CCFL HIGH-SIDE SENSE LINE REGULATI0N (%V)

175–50

0.000
–75

–50

–25

0
TEMPERATURE (°C)

75

50

100

125

175

25

150

LT1186F • G21

VSW Sat Voltage
vs Switch Current

1.0

0.9

0.8

0.7

0.6

0.5

SAT VOLTAGE (V)

0.4

SW

0.3

CCFL V

0.2

0.1
0

6

0.3

0

SWITCH CURRENT (A)

0.6

T = 25°C

0.9

T = –5°CT = 125°C

1.2

LT1186F • G22

1.5

V

Current Limit vs Duty Cycle

SW

2.5

2.0

1.5

CURRENT LIMIT (A)

1.0

SW

0.5

CCFL V

0

10 30

0

20

T = 25°C

T = 125°C

MINIMUM

50 90

40

DUTY CYCLE (%)

Forced Beta vs ISW on V

T = 0°C

70

80

60

LT1186F • G23

SW

W

OUTPUT BIAS VOLTAGE (V)

–20

OUTPUT CURRENT (µA)

–10–15 0–5

5

10

LT1186F • G27

53

52

51

50

49

48

47

46

45

TJ = 25°C

VCC = 5V

VCC = 3.3V

U

TYPICAL PERFORMANCE CHARACTERISTICS

LT1186F

vs Temperature

OUT

52

V

= 0V

OUT

51

VCC = 5V

50

OUTPUT CURRENT (µA)

49

48

–50

VCC = 3.3V

0–25 5025

TEMPERATURE (°C)

75

LT1186F • G25

100

DAC I

53

52

51

50

49

48

OUTPUT CURRENT (µA)

47

46

45

0

vs Supply VoltageDAC I

OUT

V

= 0V

OUT

= 25°C

T

J

2

SUPPLY VOLTAGE (V)

DAC I

4

6

8

LT1186F • G26

OUT

vs I

OUT

Bias Voltage

UUU

PIN FUNCTIONS

CCFL PGND (Pin 1): This pin is the emitter of an internal
NPN power switch. CCFL switch current flows through
this pin and permits internal, switch-current sensing. The
regulator provides a separate analog ground and power
ground to isolate high current ground paths from low
current signal paths. Linear Technology recommends the
use of star-ground layout techniques.

I

(Pin 2): This pin is the input to the CCFL lamp current

CCFL

programming circuit. This pin internally regulates to
465mV. The pin accepts a DC input current signal of 0µA
to 50µA full scale from the DAC. This input signal is
converted to a 0µA to 250µA source current at the CCFL V
pin. As input programming current increases, the regu­lated lamp current increases. For a typical 6mA lamp, the
range of input programming current is about 0µA to 50µA.

DIO (Pin 3): This pin is the common connection between
the cathode and anode of two internal diodes. The remain­ing terminals of the two diodes connect to ground. In a
grounded-lamp configuration, DIO connects to the low
voltage side of the lamp. Bidirectional lamp current flows
in the DIO pin and thus the diodes conduct alternately on
half cycles. Lamp current is controlled by monitoring one­half of the average lamp current. The diode conducting on
negative half cycles has one-tenth of its current diverted to
the CCFL VC pin. This current nulls against the source

current provided by the lamp-current programmer circuit.
A single capacitor on the CCFL VC pin provides both stable
loop compensation and an averaging function to the half­wave-rectified sinusoidal lamp current. Therefore, input
programming current relates to one-half of average lamp
current. This scheme reduces the number of loop com­pensation components and permits faster loop transient
response in comparison to previously published circuits.
If a floating lamp configuration is used, ground the DIO
pin.

CCFL VC (Pin 4): This pin is the output of the lamp current
programmer circuit and the input of the current compara-

C

tor for the CCFL regulator. Its uses include frequency
compensation, lamp-current averaging for grounded-lamp
circuits and current limiting. The voltage on the CCFL V
pin determines the current trip level for switch turn-off.
During normal operation this pin sits at a voltage between

0.95V (zero switch current) and 2.0V (maximum switch
current) with respect to analog ground (AGND). This pin
has a high impedance output and permits external voltage
clamping to adjust current limit. A single capacitor to
ground provides stable loop compensation. This simpli­fied loop compensation method permits the CCFL regula­tor to exhibit single-pole transient response behavior and
virtually eliminates transformer output overshoot.

C

7

LT1186F

UUU

PIN FUNCTIONS

AGND (Pin 5): This is the low current analog ground. It is
the negative sense terminal for the internal 1.24V refer­ence and the I

summing voltage in the LT1186F.

CCFL

Connect low current signal paths that terminate to ground
and frequency compensation components that terminate
to ground directly to this pin for best regulation and
performance.

SHDN (Pin 6): Pulling this pin low causes complete
regulator shutdown with quiescent current typically re­duced to 35µA. If the pin is not used, use a pull-up resistor
to force a logic high level (maximum of 6V) or tie directly
to VCC. In a shutdown condition, the DAC retains its last
output current setting and returns to this level when the
logic-low signal at the shutdown pin is removed.

CLK (Pin 7): This pin is the shift clock for the DAC. This
clock synchronizes the serial data and is a Schmitt
trigger input. In standard SPI mode, the clock shifts data
into D

and out of D

IN

on the rising and falling edges

OUT

of the clock respectively. In pulse mode, the rising edge
of the clock either increments or decrements the counter.
This action depends on the choice of a 1-wire interface
(increment only) or a 2-wire interface (increment/decre­ment).

CS (Pin 8): This pin is the chip select input for the DAC. In
SPI mode, a logic low on the CS pin enables the DAC to
receive and transfer 8-bit serial data. After the serial input
data is shifted in, a rising edge of CS transfers the data into
the counter, the DAC assumes the new I
D

pin returns to the high impedance state. On power

OUT

value and the

OUT

up, a logic high places the DAC into pulse mode. Pulling CS
low after this places the DAC into SPI mode until V

CC

resets.
DIN or UP/DN (Pin 9): This pin is the digital input for the

DAC. In SPI mode, the 8-bit serial data is shifted into the
D

input on each rising edge of the clock signal. In pulse

IN

mode, on power up, a logic high at D
function from D

to UP/DN, puts the counter into incre-

IN

transfers the pin

IN

ment-only mode and the pin function shifts to up or down
increment control of DAC output current. If UP/DN re­ceives a logic-low signal, the counter configures to incre­ment/decrement mode until VCC resets.

D

(Pin 10): This pin is the digital output for the DAC. In

OUT

SPI mode, D
D

pin then serially transfers the previous 8-bit data on

OUT

is in three-state until CS falls low. The

OUT

every falling edge of the clock. When CS rises high again,
D

returns to a three-state condition. In pulse mode,

OUT

D

is always three-stated.

OUT

I

(Pin 11): This pin is the analog current output for the

OUT

DAC and provides an output current of 50 ±3µA over
temperature. This pin can be biased from –20V to 2V for
a 3.3V V
V

supply voltage. However, this pin is tied to the I

CC

supply voltage or from –20V to 2.5V for a 5V

CC

CCFL

pin
and provides the programming current which sets operat­ing lamp current. The I
change when it is tied to the I
The programming current is sourced from the I
sunk by the I

V

(Pin 12): This is the supply pin for the LT1186F. The

CC

CCFL

pin.

pin has very little bias voltage

OUT

CCFL

pin as I

is regulated.

CCFL

OUT

pin and

IC accepts an input voltage range of 3V minimum to 6.5V
maximum with little change in quiescent current (zero
switch current). An internal, low-dropout regulator pro­vides a 2.4V supply for most of the internal circuitry.
Supply current increases as switch current increases at a
rate approximately 1/50 of switch current. This corre­sponds to a forced Beta of 50 for the power switch. The IC
incorporates undervoltage lockout by sensing regulator
dropout and locking out switching for input voltages
below 2.5V. Hysteresis is not used to maximize the useful
range of input voltage. The typical input voltage is a 3.3V
or 5V logic supply.

ROYER (Pin 13): This pin connects to the center-tapped
primary of the Royer converter and is used with the BAT
pin in a floating-lamp configuration where lamp current is
controlled by sensing Royer primary-side converter cur­rent. This pin is the inverting terminal of a high-side
current sense amplifier. The typical quiescent current is
50µA into the pin. If the CCFL regulator is not used in a
floating-lamp configuration, tie the Royer and BAT pins
together.

8

PIN FUNCTIONS

LT1186F

UUU

BAT (Pin 14): This pin connects to the battery or AC wall
adapter voltage from which the CCFL Royer converter
operates. This voltage is typically higher than the V
supply voltage but can equal V

if VCC is a 5V logic supply.

CC

CC

The BAT voltage must be at least 2.1V greater than the
internal 2.4V regulator or 4.5V. This pin provides biasing
for the lamp-current programming block, is used with the
Royer pin for floating-lamp configurations and connects
to one input for the open-lamp protection circuitry. For
floating-lamp configurations, this pin is the noninverting
terminal of a high-side current sense amplifier. The typical
quiescent current is 50µA into the pin. The BAT and Royer
pins monitor the primary-side Royer converter current
through an internal 0.1Ω topside current sense resistor. A
0A to1A primary-side, center tap converter current is
translated to an input signal range of 0mV to 100mV for the
current sense amplifier. This input range translates to a
0µA to 500µA sink current at the CCFL VC pin that nulls
against the source current provided by the programmer
circuit. The BAT pin also connects to the topside of the
internal clamp between the BAT and BULB pins that is used
for open-lamp protection.

BULB (Pin 15): This pin connects to the low side of a 7V
threshold comparator between the BAT and BULB pins.
This circuit sets the maximum voltage level across the
primary side of the Royer converter under all operating

conditions and limits the maximum secondary output
under start-up conditions or open-lamp conditions. This
eases transformer voltage rating requirements. Set the
voltage limit to ensure lamp start-up with worst-case,
lamp start voltages and cold temperature, system operat­ing conditions. The BULB pin connects to the junction of
an external divider network. The divider network connects
from the center tap of the Royer transformer or the actual
battery supply voltage to the topside of the current source
“tail inductor.” A capacitor across the top of the divider
network filters switching ripple and sets a time constant
that determines how quickly the clamp activates. When
the comparator activates, sink current is generated to pull
the CCFL VC pin down. This action transfers the entire
regulator loop from current mode operation into voltage
mode operation.

CCFL V

(Pin 16): This pin is the collector of the internal

SW

NPN power switch for the CCFL regulator. The power
switch provides a minimum of 1.25A. Maximum switch
current is a function of duty cycle as internal slope com­pensation ensures stability with duty cycles greater than
50%. Using a driver loop to automatically adapt base drive
current to the minimum required to keep the switch in a
quasi-saturation state yields fast switching times and high
efficiency operation. The ratio of switch current to driver
current is about 50:1.

TEST CIRCUITS

Load Circuit for t

D

OUT

D

DO

1.4V

3k

100pF

LT1186F • TC01

Load Circuit for tDZ, t

3k

OUT

100pF

Voltage Waveforms for t

CLK

D

OUT

0.8V

DV

5V tDZ WAVEFORM 2, t

tDZ WAVEFORM 1

t

DO

LT1186F • TC02

DO

2.4V

0.4V

LT1186F • TC03

DV

WAVEFORM 1

(SEE NOTE 1)

WAVEFORM 2

(SEE NOTE 2)

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS
DISABLED BY CS

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS
DISABLED BY CS

Voltage Waveforms for tDZ, t

CS

0.8V

D

OUT

D

OUT

2.4V

t

DV

0.4V

DV

2.0V

90%

t

DZ

10%

LT1186F • TC04

9

LT1186F

BLOCK DIAGRAM

W

LT1186F DAC Programmable CCFL Switching Regulator

SHUTDOWN

V

CC

12

Q5
1×

Q4
5×

UNDER­VOLTAGE
LOCKOUT

Q7

9×

6

SHUTDOWN

OUT

+

CCFL

2.4V

REGULATOR

200kHz

OSC

Q3

2×

–

0µA TO 50µA FROM I

V1

0.465V

THERMAL

SHUTDOWN

D2

6V

Q6
2×

Q8
1×

Q9

3×

D1

Q11

R3
1k

ROYERBAT

13

14

CCFL

V

SW

16

R4

0.1Ω

–

g

m

LOGIC

+

COMP

DRIVE

ANTI-

SAT

Q1

+

CURRENT

AMP

R1

0.125Ω

–

GAIN = 4.4

Q10
2×

25

I

CCFL

POWER-ON

RESET

CLK

7

9

D

IN

8

CS

AGND DIO

3

LATCH

AND

LOGIC

UP ONLY/
UP/DN

LATCH

AND

LOGIC

MODE SELECT
0 = PULSE
1 = SPI

CONTROL

LOGIC

15

BULB

VOLTAGE

REFERENCE

SHDN

CLK

8-BIT COUNTER/REGISTER

UP/DN

8

CLK

DO(LSB)

9-BIT SHIFT REGISTER

SHDN

4

CCFL

V

C

CURRENT

8-BIT

DAC

8

1

CCFL

PGND

I

11

OUT

50µA

FULL SCALE

8

LT1186F • BD

D

10

OUT

Q9

10

LT1186F

U

WUU

APPLICATIONS INFORMATION

Introduction

Current generation portable computers and instruments
use backlit Liquid Crystal Displays (LCDs). Cold Cathode
Fluorescent Lamps (CCFLs) provide the highest available
efficiency in back lighting the display. Providing the most
light out for the least amount of input power is the most
important goal. These lamps require high voltage AC to
operate, mandating an efficient high voltage DC/AC con­verter. The lamps operate from DC, but migration effects
damage the lamp and shorten its lifetime. Lamp drive
should contain zero DC component. In addition to good
efficiency, the converter should deliver the lamp drive in
the form of a sine wave. This minimizes EMI and RF
emissions. Such emissions can interfere with other de­vices and can also degrade overall operating efficiency.
Sinusoidal CCFL drive maximizes current-to-light conver­sion in the lamp. The circuit should also permit lamp
intensity control from zero to full brightness with no
hysteresis or “pop-on.”

The small size and battery-powered operation associated
with LCD equipped apparatus dictate low component
count and high efficiency for these circuits. Size con­straints place severe limitations on circuit architecture and
long battery life is a priority. Laptop and handheld portable
computers offer an excellent example. The CCFL and its
power supply are responsible for almost 50% of the
battery drain. Additionally, all components, including PC
board and hardware, usually must fit within the LCD
enclosure with a height restriction of 5mm to 10mm.

The CCFL regulator drives an inductor that acts as a
switched-mode current source for a current-driven Royer­class converter with efficiencies as high as 90%. The
control loop forces the CCFL PWM to modulate the aver­age inductor current to maintain constant current in the
lamp. The constant current value, and thus lamp intensity,
is programmable. This drive technique provides a wide
range of intensity control. A unique lamp-current pro­gramming block permits either grounded lamp or floating
lamp configurations. Grounded lamp circuits directly sense
one-half of average lamp current. Floating lamp circuits
directly sense the Royer’s primary-side converter current.
Floating-lamp circuits provide symmetric differential drive

to the lamp and reduce the parasitic loss from stray lamp­to-frame capacitance, extending illumination range.

Block Diagram Operation

The LT1186F is a fixed frequency, current mode switching
regulator. A fixed frequency, current mode switcher con­trols switch duty cycle directly by switch current rather
than by output voltage. Referring to the block diagram for
the LT1186F, the switch turns ON at the start of each
oscillator cycle. The switch turns OFF when switch current
reaches a predetermined level. The control of output lamp
current is obtained by using the output of a unique
programming block to set current trip level. The current
mode switching technique has several advantages. First,
it provides excellent rejection of input voltage variations.
Second, it reduces the 90° phase shift at mid-frequencies
in the energy storage inductor. This simplifies closed-loop
frequency compensation under widely varying input volt­age or output load conditions. Finally, it allows simple
pulse-by-pulse current limiting to provide maximum switch
protection under output overload or short-circuit condi­tions.

The LT1186F incorporates a low dropout internal regula­tor that provides a 2.4V supply for most of the internal
circuitry. This low dropout design allows input voltage to
vary from 3V to 6.5V with little change in quiescent
current. An active low shutdown pin typically reduces total
supply current to 35µA by shutting off the 2.4V regulator
and locks out switching action for standby operation. The
IC incorporates undervoltage lockout by sensing regulator
dropout and locking out switching below about 2.5V. The
regulator also provides thermal shutdown protection that
locks out switching in the presence of excessive junction
temperatures.

A 200kHz oscillator is the basic clock for all internal timing.
The oscillator turns on the output switch via its own logic
and driver circuitry. Adaptive anti-sat circuitry detects the
onset of saturation in the power switch and adjusts base
drive current instantaneously to limit switch saturation.
This minimizes driver dissipation and provides rapid turn­off of the switch. The CCFL power switch is guaranteed to
provide a minimum of 1.25A in the LT1186F. The anti-sat

11

LT1186F

U

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APPLICATIONS INFORMATION

circuitry provides a ratio of switch current to driver current
of about 50:1.

8-Bit Current Output DAC

The 8-bit current output DAC is guaranteed monotonic and
is digitally adjustable by the 8-bit counter in 256 equal
steps. On power up, the counter resets to 80H and the DAC
assumes its mid-range value. The current output I
drives the I

pin and sets control current for the lamp

CCFL

current programming block. The DAC has its own 1.24V
bandgap reference and a voltage to current converter that
is trimmed at wafer sort to provide the precision full-scale
current reference. Over temperature, the current output of
the DAC is 50µA ±6%.

Digital Interface

On power-up, a logic high at CS configures the DAC into
pulse mode. If CS is ever pulled low, the chip configures
into SPI mode until VCC resets. On power-up in pulse
mode, a logic high at D

puts the counter into increment-

IN

only mode. If UP/DN (DIN) is ever pulled low, the counter
configures into increment/decrement mode until VCC re­sets. These modes are illustrated in Figure 1.

SINGLE DAC

LOW

CS STAYS
HIGH

D

IN

HIGH

STAYS

CS EVER

GOES LOW

SPI MODE PULSE MODE

D

(UP/DN)

IN

EVER GOES

OUT

POWER ON

V

CC

CS ALWAYS HIGH

DIN ALWAYS HIGH

LT1186F • F01c

Figure 1c. Pulse Mode Setup (Increment Only)

POWER ON

V

CC

CS ALWAYS HIGH

UP/DN

UP/DN EVER GOES LOW

Figure 1d. Pulse Mode Setup (Increment/Decrement)

LT1186F • F01d

Standard SPI Mode

Refer to the serial interface operating sequence in Figure

2. A falling edge at CS initiates the data transfer. After the
falling CS is recognized, D

comes out of three-state.

OUT

The clock (CLK) synchronizes the data transfer. Each input
bit shifts into DIN beginning with the MSB on the rising CLK
edge and each previous data bit shifts out of D

OUT

begin­ning with the MSB on the falling CLK edge. After the 8-bit
serial input data is shifted in, a rising edge at CS transfers
the data into the counter, the DAC assumes the new value
I

= (8-bit serial input data)(50µA)/255 and the D

OUT

OUT

pin

returns to a high impedance state.

INCREMENT/
DECREMENT

Figure 1a. Tree Diagram (LT1186F DAC Operating Modes)

POWER ON

CS EVER GOES LOW

Figure 1b. SPI Mode Setup

INCREMENT-

ONLY

LT1186F • F01a

V

CS

LT1186F • F01b

CC

12

1-Wire Interface (Pulse Mode)

In increment-only pulse mode, each rising edge of CLK
increments the upper six bits of the counter by one count.
When incremented beyond 11111100B, the counter rolls
over and sets the DAC to the minimum value 00000000B.
Therefore, a single pulse applied to CLK increases the
upper 6-bit counter by one-step, and 63 pulse applied to
CLK decreases the counter by one-step. The last two LSBs
are always zero in this mode. I

= (B7B6B5B4B3B2B1B0)

OUT

(50µA)/255. The upper 6-bit counter = B7B6B5B4B3B2 and
B1 = B0 = 0. To configure the LT1186F into increment-only
mode, tie CS and DIN to VCC.

LT1186F

U

WUU

APPLICATIONS INFORMATION

CS

t

CKS

CLK

t

CSS

D

IN

Hi-Z

D

OUT

D7

t

DV

D7′ D6′ D5′ D4′ D3′

D6 D5 D4 D3 D2 D1 D0

t

DS

Figure 2. SPI Interface Timing Specification

2-Wire Interface (Pulse Mode)

In increment/decrement pulse mode, a logic high at UP/
DN programs the counter into increment mode and each
rising edge of CLK increments the upper six bits of the
counter by one. The counter stops incrementing at
11111100B. A logic low at UP/DN programs the counter
into decrement mode and each rising edge of CLK decre­ments the upper six bits of the counter by one. The counter
stops decrementing at 00000000B. The last two LSBs are
always zero in this mode. I

= (B7B6B5B4B3B2B1B0)

OUT

(50µA)/255. The upper 6-bit counter = B7B6B5B4B3B2 and
B1 = B0 = 0. To configure the LT1186F into increment/
decrement mode, tie CS to VCC and pulse the UP/DN pin
once on power-up.

Simplified Lamp Current Programming

t

DH

t

CSLO

t

CKHI

t

CKLO

t

DO

D2′

D1′ D0′

t

CSHI

t

CSH

t

CKH

t

DZ

D7

Hi-Z

LT1186F • F02

frequency compensation. This compensation scheme
meant that the loop had to be fairly slow and that output
overshoot with start-up or overload conditions had to be
carefully evaluated in terms of transformer stress and
breakdown voltage requirements.

The LT1186F eliminates the error amplifier concept en­tirely and replaces it with a lamp current programming
block. This block provides an easy-to-use interface to
program lamp current. The programmer circuit also re­duces the number of time constants in the control loop by
combining the error signal conversion scheme and fre­quency compensation into a single capacitor. The control
loop thus exhibits the response of a single pole system,
allows for faster loop transient response and virtually
eliminates overshoot under start-up or overload condi­tions.

A programming block in the LT1186F controls lamp
current, permitting either grounded lamp or floating lamp
configurations. Grounded configurations control lamp
current by directly controlling one-half of actual lamp
current and converting it to a feedback signal to close a
control loop. Floating configurations control lamp current
by directly controlling the Royer’s primary-side converter
current and generating a feedback signal to close a control
loop.

Previous backlighting solutions have used a traditional
error amplifier in the control loop to regulate lamp current.
This approach converted an RMS current into a DC voltage
for the input of the error amplifier. This approach used
several time constants in order to provide stable loop

Lamp current is programmed at the input of the program­mer block, the I

pin. This pin is the input of a shunt

CCFL

regulator and accepts a DC input current signal of 0µA to
50µA from the DAC. This input signal is converted to a 0µA
to 250µA source current at the CCFL VC pin. The program­mer circuit is simply a current-to-current converter with a
gain of five. The typical input current programming range
for 0mA to 6mA lamp current is 0µA to 50µA.

The I

pin is sensitive to capacitive loading and will

CCFL

oscillate with capacitance greater than 10pF. For example,
loading the I

pin with a 1× or 10× scope probe causes

CCFL

oscillation and erratic CCFL regulator operation because
of the probe’s respective input capacitance. A current
meter in series with the I

pin will also produce oscil-

CCFL

13

LT1186F

U

WUU

APPLICATIONS INFORMATION

lation due to its shunt capacitance. Use a decoupling
resistor of several kilohms between the I
I

pin if excessive trace stray capacitance exists. Nor-

OUT

mally, this resistor is not required.
In some applications, the maximum programming current

required at the I

pin for a maximum lamp current will be

CCFL

less than the full-scale output current of the DAC, which is
50µA. The system designer can either limit the maximum
programming current through software built into the system,
or use a current splitter which shunts a percentage of the full­scale current from the I

pin. A splitter circuit is illustrated

CCFL

in Figure 3. A divider string is used from a reference voltage
to set up a voltage level equal to the I

CCFL

or 465mV. The main current flowing in the divider string
should be chosen to swamp out the effects of the shunted
current into the divider string.

I

FULL-SCALE

OUT

50µA

V1

I

(1 – X)I

V(I

)

I = 50µA
0 < X < 1
SELECT V1 WITHIN THE DAC I
COMPLIANCE RANGE
(EX. V1 = 2V FOR V
CHOOSE I1 >> (1 – X)I

R1 = (V1 – 0.465)/(X)(50µA)

)

CCFL

R2 = (V1 – 0.465)/(1 – X)(50µA)
R3 = (V

REF

R4 = 0.465R3/[(1 – X) 50µAR3
+ (V

I1

CCFL

465mV

V

REF

R3
V(I
R4

Figure 3

R1

XI

R2

Grounded Lamp Configuration

In a grounded lamp configuration, the low voltage side of
the lamp connects directly to the LT1186F DIO pin. This
pin is the common connection between the cathode and
anode of two internal diodes. In previous grounded lamp
solutions, these diodes were discrete units and are now
integrated onto the IC, saving cost and board space.
Bidirectional lamp current flows in the DIO pin and thus,
the diodes conduct alternately on half cycles. Lamp cur­rent is controlled by monitoring one-half of the average
lamp current. The diode conducting on negative half
cycles has one-tenth of its current diverted to the CCFL pin
and nulls against the source current provided by the lamp
current programmer circuit. The compensation capacitor
on the CCFL VC pin provides stable loop compensation and
an averaging function to the rectified sinusoidal lamp
current. Therefore, input programming current relates to
one-half of average lamp current.

pin and the

CCFL

summing voltage,

OUT

= 3.3V OR 5V)

CC

– 0.465)/I1

– 0.465)]

REF

LT1186F • F03

The transfer function between lamp current and input
programming current must be empirically determined and
is dependent on the particular lamp/display housing com­bination used. The lamp and display housing are a distrib­uted loss structure due to parasitic lamp-to-frame capaci­tance. This means that the current flowing at the high­voltage side of the lamp is higher than what is flowing at
the DIO pin side of the lamp. The input programming
current is set to control lamp current at the high-voltage
side of the lamp, even though the feedback signal is the
lamp current at the bottom of the lamp. This ensures that
the lamp is not overdriven which can degrade the lamp’s
operating lifetime. Therefore, the full scale current of the
DAC does not necessarily correspond to the current re­quired to set maximum lamp current.

Floating Lamp Configuration

In a floating lamp configuration, the lamp is fully floating
with no galvanic connection to ground. This allows the
transformer to provide symmetric differential drive to the
lamp. Balanced drive eliminates the field imbalance asso­ciated with parasitic lamp-to-frame capacitance and re­duces “thermometering” (uneven lamp intensity along the
lamp length) at low lamp currents.

Carefully evaluate display designs in relation to the physi­cal layout of the lamp, its leads and the construction of the
display housing. Parasitic capacitance from any high
voltage point to DC or AC ground creates paths for
unwanted current flow. This parasitic current flow de­grades electrical efficiency and losses up to 25% have
been observed in practice. As an example, at a Royer
operating frequency of 60kHz, 1pF of stray capacitance
represents an impedance of 2.65MΩ. With an operating
lamp voltage of 400V and an operating lamp current of
6mA, the parasitic current is 150µA. This additional cur-
rent must be supplied by the transformer secondary.
Layout techniques that increase parasitic capacitance
include long high voltage lamp leads, reflective metal foil
around the lamp and displays supplied in metal enclo­sures. Losses for a good display are under 5%, whereas,
losses for a bad display range from 5% to 25%. Lossy
displays are the primary reason to use a floating lamp
configuration. Providing symmetric, differential drive to
the lamp reduces the total parasitic loss by one-half.

14

LT1186F

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APPLICATIONS INFORMATION

Maintaining closed-loop control of lamp current in a
floating lamp configuration necessitates deriving a feed­back signal from the primary side of the Royer trans­former. Previous solutions have used an external preci­sion shunt and high-side sense amplifier configuration.
This approach has been integrated onto the LT1186F for
simplicity of design and ease of use. An internal 0.1Ω
resistor monitors the Royer converter current and con­nects between the input terminals of a high-side sense
amplifier. A 0 – 1 Amp Royer primary-side, center-tap
current is translated to a 0µA to 500µA sink current at the
CCFL VC pin to null against the source current provided by
the lamp current programmer circuit. The compensation
capacitor on the CCFL VC pin provides stable loop com­pensation and an averaging function to the error sink
current. Therefore, input programming current is related
to average Royer converter current. Floating lamp circuits
operate similarly to grounded lamp circuits except for the
derivation of the feedback signal.

The transfer function between lamp current and input
programming current must be empirically determined and
is dependent upon a myriad of factors including lamp
characteristics, display construction, transformer turns
ratio and the tuning of the Royer oscillator. Once again,
lamp current will be slightly higher at one end of the lamp
and input programming current should be set for this
higher level to ensure that the lamp is not overdriven.

The internal 0.1Ω high-side sense resistor on the LT1186F
is rated for a maximum DC current of 1A. This resistor can
be damaged by extremely high surge currents at start-up.
The Royer converter typically uses a few microfarads of
bypass capacitance at the center tap of the transformer.
This capacitor charges up when the system is first pow­ered by the battery pack or an AC wall adapter. The amount
of current delivered at start-up can be very large if the total
impedance in this path is small and the voltage source has
high current capability. Linear Technology recommends
the use of an aluminum electrolytic for the transformer
center-tap bypass capacitor with an ESR greater than or
equal to 0.5Ω. This lowers the peak surge currents to an
acceptable level. In general, the wire and trace inductance
in this path also help reduce the di/dt of the surge current.
This issue only exists with floating lamp circuits as

grounded lamp circuits do not make use of the high-side
sense resistor.

Input Capacitor Type

Caution must be used in selecting the input capacitor type
for switching regulators. Aluminum electrolytics are elec­trically rugged and the lowest cost, but are physically large
to meet required ripple current ratings, and size con­straints (especially height) may preclude their use. Ce­ramic capacitors are now available in larger values and
their high ripple current and voltage rating make them
ideal for input bypassing. Cost is fairly high and footprint
can be large.

Solid tantalum capacitors would be a good choice except
for a history of occasional failure when subjected to large
current surges during start-up. The input bypass capaci­tor of regulators can see these high surges when a battery
or high capacitance source is connected. Some manufac­turers have developed tantalum capacitor lines specially
tested for surge capability (AVX TPS series for instance),
but even these units may fail if the input voltage surge
approaches the capacitor’s maximum voltage rating. AVX
recommends derating the capacitor voltage by 2:1 for high
surge applications.

Applications Support

Linear Technology invests an enormous amount of time,
resources and technical expertise in understanding, de­signing and evaluating backlight/LCD contrast solutions
for system designers. The design of an efficient and
compact LCD backlight system is a study of compromise
in a transduced electronic system. Every aspect of the
design is interrelated and any design change requires
complete re-evaluation for all other critical design param­eters. Linear Technology has engineered one of the most
complete test and evaluation setups for backlight designs
and understands the issues and tradeoffs in achieving a
compact, efficient and economical customer solution.
Linear Technology welcomes the opportunity to discuss,
design, evaluate and optimize any backlight/LCD contrast
system with a customer. For further information on back­light/LCD contrast designs, consult the References.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LT1186F

U

WUU

APPLICATIONS INFORMATION

References

1. Williams, Jim. August 1992.

Liquid Crystal Displays

. Linear Technology Corporation,

Illumination Circuitry for

Application Note 49.

2. Williams, Jim. August 1993.

cient LCD Illumination

. Linear Technology Corporation,

Techniques for 92% Effi-

Application Note 55.

3. Bonte, Anthony. March 1995.

with Dual Polarity Contrast

. Linear Technology Corpora-

LT1182 Floating CCFL

tion, Design Note 99.

U

PACKAGE DESCRIPTION

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

× 45°

0.016 – 0.050

0.406 – 1.270

0° – 8° TYP

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

Dimensions in inches (millimeters) unless otherwise noted.

16-Lead Plastic Small Outline (Narrow 0.150)

4. Williams, Jim. April 1995.

rent Probe for LCD Backlight Measurement

nology Corporation, Design Note 101.

5. LT1182/LT1183/LT1184/LT1184F Data Sheet.

LCD Contrast Switching Regulators

Technology Corporation.

S Package

(LTC DWG # 05-08-1610)

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

TYP

0.228 – 0.244

(5.791 – 6.197)

A Precision Wideband Cur-

. Linear Tech-

CCFL/

. April 1995. Linear

0.386 – 0.394*
(9.804 – 10.008)

13

16

1

14

15

3

2

12

11

10

9

0.150 – 0.157**
(3.810 – 3.988)

5

4

7

6

S16 0695

8

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1107 Micropower DC/DC Converter for LCD Contrast Control 1A, 63kHz, Hysteretic
LT1172 Current Mode Switching Regulator for CCFL or LCD Contrast Control 1.25A, 100kHz
LT1173 Micropower DC/DC Converter for LCD Contrast Control 1A, 24kHz, Hysteretic
LT1182 Dual Current Mode Switching Regulator for CCFL and LCD Contrast Control 1.25A, 0.625A, 200kHz
LT1183 Dual Current Mode Switching Regulator for CCFL and LCD Contrast Control 1.25A, 0.625A, 200kHz
LT1184 Current Mode Switching Regulator for CCFL Control 1.25A, 200kHz
LT1184F Current Mode Switching Regulator for CCFL Control 1.25A, 200kHz
LT1372 Current Mode Switching Regulator for CCFL or LCD Contrast Contol 1.5A, 500kHz

Linear Technology Corporation

16

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone]

●

FAX

: [phone]

●

TELEX

: 499-3977

 LINEAR TECHNOLOGY CORPORATION 1995

LT/GP 1096 7K REV A • PRINTED IN USA